update design
diff --git a/Makefile b/Makefile
index 3862fec..3342f8a 100644
--- a/Makefile
+++ b/Makefile
@@ -115,7 +115,7 @@
verify_command="source ~/.bashrc && cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
dv_base_dependencies=simenv
docker_run_verify=\
- docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+ docker run --memory="16g" --memory-swap="64g" -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
-e CARAVEL_ROOT=${CARAVEL_ROOT} \
@@ -287,7 +287,7 @@
.PHONY: create-spef-mapping
create-spef-mapping: ./verilog/gl/user_project_wrapper.v
docker run \
- --rm \
+ --rm --memory="16g" --memory-swap="64g" \
-u $$(id -u $$USER):$$(id -g $$USER) \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(CUP_ROOT):$(CUP_ROOT) \
@@ -306,7 +306,7 @@
.PHONY: extract-parasitics
extract-parasitics: ./verilog/gl/user_project_wrapper.v
docker run \
- --rm \
+ --rm --memory="16g" --memory-swap="64g" \
-u $$(id -u $$USER):$$(id -g $$USER) \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(CUP_ROOT):$(CUP_ROOT) \
diff --git a/openlane/Makefile b/openlane/Makefile
index df3ea04..6cfc22f 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -51,7 +51,7 @@
docker_startup_mode = $(shell test -t 0 && echo "-it" || echo "--rm" )
docker_run = \
- docker run $(docker_startup_mode) \
+ docker run --memory="16g" --memory-swap="64g" $(docker_startup_mode) \
$(docker_mounts) \
$(docker_env) \
-u $(shell id -u $(USER)):$(shell id -g $(USER))
@@ -61,7 +61,8 @@
.PHONY: $(designs)
$(designs) : export current_design=$@
-$(designs) : % : ./%/config.json
+$(designs) : % : ./%/config.tcl
+#$(designs) : % : ./%/config.json
ifneq (,$(wildcard ./$(current_design)/interactive.tcl))
$(docker_run) \
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_interactive)
diff --git a/openlane/user_proj_example/config.json b/openlane/ref/user_proj_example/config.json
similarity index 100%
rename from openlane/user_proj_example/config.json
rename to openlane/ref/user_proj_example/config.json
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/ref/user_proj_example/pin_order.cfg
similarity index 100%
rename from openlane/user_proj_example/pin_order.cfg
rename to openlane/ref/user_proj_example/pin_order.cfg
diff --git a/openlane/ref/user_project_wrapper/config.json b/openlane/ref/user_project_wrapper/config.json
new file mode 100644
index 0000000..22a00ee
--- /dev/null
+++ b/openlane/ref/user_project_wrapper/config.json
@@ -0,0 +1,85 @@
+{
+ "DESIGN_NAME": "user_project_wrapper",
+ "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
+ "CLOCK_PERIOD": 10,
+ "CLOCK_PORT": "user_clock2",
+ "CLOCK_NET": "mprj.clk",
+ "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
+ "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
+ "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
+ "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
+ "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
+ "FP_PDN_CHECK_NODES": 0,
+ "SYNTH_ELABORATE_ONLY": 1,
+ "PL_RANDOM_GLB_PLACEMENT": 1,
+ "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
+ "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
+ "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
+ "FP_PDN_ENABLE_RAILS": 0,
+ "DIODE_INSERTION_STRATEGY": 0,
+ "RUN_FILL_INSERTION": 0,
+ "RUN_TAP_DECAP_INSERTION": 0,
+ "FP_PDN_VPITCH": 180,
+ "FP_PDN_HPITCH": 180,
+ "CLOCK_TREE_SYNTH": 0,
+ "FP_PDN_VOFFSET": 5,
+ "FP_PDN_HOFFSET": 5,
+ "MAGIC_ZEROIZE_ORIGIN": 0,
+ "FP_SIZING": "absolute",
+ "RUN_CVC": 0,
+ "UNIT": "2.4",
+ "FP_IO_VEXTEND": "expr::2 * $UNIT",
+ "FP_IO_HEXTEND": "expr::2 * $UNIT",
+ "FP_IO_VLENGTH": "ref::$UNIT",
+ "FP_IO_HLENGTH": "ref::$UNIT",
+ "FP_IO_VTHICKNESS_MULT": 4,
+ "FP_IO_HTHICKNESS_MULT": 4,
+ "FP_PDN_CORE_RING": 1,
+ "FP_PDN_CORE_RING_VWIDTH": 3.1,
+ "FP_PDN_CORE_RING_HWIDTH": 3.1,
+ "FP_PDN_CORE_RING_VOFFSET": 12.45,
+ "FP_PDN_CORE_RING_HOFFSET": 12.45,
+ "FP_PDN_CORE_RING_VSPACING": 1.7,
+ "FP_PDN_CORE_RING_HSPACING": 1.7,
+ "FP_PDN_VWIDTH": 3.1,
+ "FP_PDN_HWIDTH": 3.1,
+ "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
+ "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
+ "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"],
+ "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"],
+ "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
+ "pdk::sky130*": {
+ "RT_MAX_LAYER": "met4",
+ "DIE_AREA": "0 0 2920 3520",
+ "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
+ "scl::sky130_fd_sc_hd": {
+ "CLOCK_PERIOD": 10
+ },
+ "scl::sky130_fd_sc_hdll": {
+ "CLOCK_PERIOD": 10
+ },
+ "scl::sky130_fd_sc_hs": {
+ "CLOCK_PERIOD": 8
+ },
+ "scl::sky130_fd_sc_ls": {
+ "CLOCK_PERIOD": 10,
+ "SYNTH_MAX_FANOUT": 5
+ },
+ "scl::sky130_fd_sc_ms": {
+ "CLOCK_PERIOD": 10
+ }
+ },
+ "pdk::gf180mcuC": {
+ "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+ "FP_PDN_CHECK_NODES": 0,
+ "FP_PDN_ENABLE_RAILS": 0,
+ "RT_MAX_LAYER": "Metal4",
+ "DIE_AREA": "0 0 3000 3000",
+ "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
+ "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
+ "DIODE_INSERTION_STRATEGY": 0,
+ "FP_PDN_CHECK_NODES": 0,
+ "MAGIC_WRITE_FULL_LEF": 0,
+ "FP_PDN_ENABLE_RAILS": 0
+ }
+}
diff --git a/openlane/ref/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl b/openlane/ref/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
new file mode 100644
index 0000000..4a4f8a2
--- /dev/null
+++ b/openlane/ref/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
@@ -0,0 +1,24 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# THE FOLLOWING SECTIONS CAN BE CHANGED IF NEEDED
+
+# PDN Pitch
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+
+# PDN Offset
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
\ No newline at end of file
diff --git a/openlane/ref/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl b/openlane/ref/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
new file mode 100644
index 0000000..e602da7
--- /dev/null
+++ b/openlane/ref/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
@@ -0,0 +1,57 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+set script_dir [file dirname [file normalize [info script]]]
+
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+
+set ::env(RUN_CVC) 0
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_VOFFSET) 12.45
+set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
+
+set ::env(FP_PDN_VWIDTH) 3.1
+set ::env(FP_PDN_HWIDTH) 3.1
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+
+# Pin placement template
+set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/fixed_dont_change/user_project_wrapper.def
diff --git a/openlane/ref/user_project_wrapper/fixed_dont_change/user_project_wrapper.def b/openlane/ref/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
new file mode 100644
index 0000000..0647d54
--- /dev/null
+++ b/openlane/ref/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
@@ -0,0 +1,7656 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN user_project_wrapper ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 2920000 3520000 ) ;
+ROW ROW_0 unithd 5520 10880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1 unithd 5520 13600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_2 unithd 5520 16320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_3 unithd 5520 19040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_4 unithd 5520 21760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_5 unithd 5520 24480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_6 unithd 5520 27200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_7 unithd 5520 29920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_8 unithd 5520 32640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_9 unithd 5520 35360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_10 unithd 5520 38080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_11 unithd 5520 40800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_12 unithd 5520 43520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_13 unithd 5520 46240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_14 unithd 5520 48960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_15 unithd 5520 51680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_16 unithd 5520 54400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_17 unithd 5520 57120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_18 unithd 5520 59840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_19 unithd 5520 62560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_20 unithd 5520 65280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_21 unithd 5520 68000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_22 unithd 5520 70720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_23 unithd 5520 73440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_24 unithd 5520 76160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_25 unithd 5520 78880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_26 unithd 5520 81600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_27 unithd 5520 84320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_28 unithd 5520 87040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_29 unithd 5520 89760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_30 unithd 5520 92480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_31 unithd 5520 95200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_32 unithd 5520 97920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_33 unithd 5520 100640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_34 unithd 5520 103360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_35 unithd 5520 106080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_36 unithd 5520 108800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_37 unithd 5520 111520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_38 unithd 5520 114240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_39 unithd 5520 116960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_40 unithd 5520 119680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_41 unithd 5520 122400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_42 unithd 5520 125120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_43 unithd 5520 127840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_44 unithd 5520 130560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_45 unithd 5520 133280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_46 unithd 5520 136000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_47 unithd 5520 138720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_48 unithd 5520 141440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_49 unithd 5520 144160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_50 unithd 5520 146880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_51 unithd 5520 149600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_52 unithd 5520 152320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_53 unithd 5520 155040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_54 unithd 5520 157760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_55 unithd 5520 160480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_56 unithd 5520 163200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_57 unithd 5520 165920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_58 unithd 5520 168640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_59 unithd 5520 171360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_60 unithd 5520 174080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_61 unithd 5520 176800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_62 unithd 5520 179520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_63 unithd 5520 182240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_64 unithd 5520 184960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_65 unithd 5520 187680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_66 unithd 5520 190400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_67 unithd 5520 193120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_68 unithd 5520 195840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_69 unithd 5520 198560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_70 unithd 5520 201280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_71 unithd 5520 204000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_72 unithd 5520 206720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_73 unithd 5520 209440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_74 unithd 5520 212160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_75 unithd 5520 214880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_76 unithd 5520 217600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_77 unithd 5520 220320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_78 unithd 5520 223040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_79 unithd 5520 225760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_80 unithd 5520 228480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_81 unithd 5520 231200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_82 unithd 5520 233920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_83 unithd 5520 236640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_84 unithd 5520 239360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_85 unithd 5520 242080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_86 unithd 5520 244800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_87 unithd 5520 247520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_88 unithd 5520 250240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_89 unithd 5520 252960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_90 unithd 5520 255680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_91 unithd 5520 258400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_92 unithd 5520 261120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_93 unithd 5520 263840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_94 unithd 5520 266560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_95 unithd 5520 269280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_96 unithd 5520 272000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_97 unithd 5520 274720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_98 unithd 5520 277440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_99 unithd 5520 280160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_100 unithd 5520 282880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_101 unithd 5520 285600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_102 unithd 5520 288320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_103 unithd 5520 291040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_104 unithd 5520 293760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_105 unithd 5520 296480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_106 unithd 5520 299200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_107 unithd 5520 301920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_108 unithd 5520 304640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_109 unithd 5520 307360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_110 unithd 5520 310080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_111 unithd 5520 312800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_112 unithd 5520 315520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_113 unithd 5520 318240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_114 unithd 5520 320960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_115 unithd 5520 323680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_116 unithd 5520 326400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_117 unithd 5520 329120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_118 unithd 5520 331840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_119 unithd 5520 334560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_120 unithd 5520 337280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_121 unithd 5520 340000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_122 unithd 5520 342720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_123 unithd 5520 345440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_124 unithd 5520 348160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_125 unithd 5520 350880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_126 unithd 5520 353600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_127 unithd 5520 356320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_128 unithd 5520 359040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_129 unithd 5520 361760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_130 unithd 5520 364480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_131 unithd 5520 367200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_132 unithd 5520 369920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_133 unithd 5520 372640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_134 unithd 5520 375360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_135 unithd 5520 378080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_136 unithd 5520 380800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_137 unithd 5520 383520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_138 unithd 5520 386240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_139 unithd 5520 388960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_140 unithd 5520 391680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_141 unithd 5520 394400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_142 unithd 5520 397120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_143 unithd 5520 399840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_144 unithd 5520 402560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_145 unithd 5520 405280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_146 unithd 5520 408000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_147 unithd 5520 410720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_148 unithd 5520 413440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_149 unithd 5520 416160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_150 unithd 5520 418880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_151 unithd 5520 421600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_152 unithd 5520 424320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_153 unithd 5520 427040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_154 unithd 5520 429760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_155 unithd 5520 432480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_156 unithd 5520 435200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_157 unithd 5520 437920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_158 unithd 5520 440640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_159 unithd 5520 443360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_160 unithd 5520 446080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_161 unithd 5520 448800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_162 unithd 5520 451520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_163 unithd 5520 454240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_164 unithd 5520 456960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_165 unithd 5520 459680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_166 unithd 5520 462400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_167 unithd 5520 465120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_168 unithd 5520 467840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_169 unithd 5520 470560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_170 unithd 5520 473280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_171 unithd 5520 476000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_172 unithd 5520 478720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_173 unithd 5520 481440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_174 unithd 5520 484160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_175 unithd 5520 486880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_176 unithd 5520 489600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_177 unithd 5520 492320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_178 unithd 5520 495040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_179 unithd 5520 497760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_180 unithd 5520 500480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_181 unithd 5520 503200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_182 unithd 5520 505920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_183 unithd 5520 508640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_184 unithd 5520 511360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_185 unithd 5520 514080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_186 unithd 5520 516800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_187 unithd 5520 519520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_188 unithd 5520 522240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_189 unithd 5520 524960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_190 unithd 5520 527680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_191 unithd 5520 530400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_192 unithd 5520 533120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_193 unithd 5520 535840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_194 unithd 5520 538560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_195 unithd 5520 541280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_196 unithd 5520 544000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_197 unithd 5520 546720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_198 unithd 5520 549440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_199 unithd 5520 552160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_200 unithd 5520 554880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_201 unithd 5520 557600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_202 unithd 5520 560320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_203 unithd 5520 563040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_204 unithd 5520 565760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_205 unithd 5520 568480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_206 unithd 5520 571200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_207 unithd 5520 573920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_208 unithd 5520 576640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_209 unithd 5520 579360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_210 unithd 5520 582080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_211 unithd 5520 584800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_212 unithd 5520 587520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_213 unithd 5520 590240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_214 unithd 5520 592960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_215 unithd 5520 595680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_216 unithd 5520 598400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_217 unithd 5520 601120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_218 unithd 5520 603840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_219 unithd 5520 606560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_220 unithd 5520 609280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_221 unithd 5520 612000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_222 unithd 5520 614720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_223 unithd 5520 617440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_224 unithd 5520 620160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_225 unithd 5520 622880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_226 unithd 5520 625600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_227 unithd 5520 628320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_228 unithd 5520 631040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_229 unithd 5520 633760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_230 unithd 5520 636480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_231 unithd 5520 639200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_232 unithd 5520 641920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_233 unithd 5520 644640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_234 unithd 5520 647360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_235 unithd 5520 650080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_236 unithd 5520 652800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_237 unithd 5520 655520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_238 unithd 5520 658240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_239 unithd 5520 660960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_240 unithd 5520 663680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_241 unithd 5520 666400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_242 unithd 5520 669120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_243 unithd 5520 671840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_244 unithd 5520 674560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_245 unithd 5520 677280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_246 unithd 5520 680000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_247 unithd 5520 682720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_248 unithd 5520 685440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_249 unithd 5520 688160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_250 unithd 5520 690880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_251 unithd 5520 693600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_252 unithd 5520 696320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_253 unithd 5520 699040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_254 unithd 5520 701760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_255 unithd 5520 704480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_256 unithd 5520 707200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_257 unithd 5520 709920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_258 unithd 5520 712640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_259 unithd 5520 715360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_260 unithd 5520 718080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_261 unithd 5520 720800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_262 unithd 5520 723520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_263 unithd 5520 726240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_264 unithd 5520 728960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_265 unithd 5520 731680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_266 unithd 5520 734400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_267 unithd 5520 737120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_268 unithd 5520 739840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_269 unithd 5520 742560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_270 unithd 5520 745280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_271 unithd 5520 748000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_272 unithd 5520 750720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_273 unithd 5520 753440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_274 unithd 5520 756160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_275 unithd 5520 758880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_276 unithd 5520 761600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_277 unithd 5520 764320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_278 unithd 5520 767040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_279 unithd 5520 769760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_280 unithd 5520 772480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_281 unithd 5520 775200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_282 unithd 5520 777920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_283 unithd 5520 780640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_284 unithd 5520 783360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_285 unithd 5520 786080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_286 unithd 5520 788800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_287 unithd 5520 791520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_288 unithd 5520 794240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_289 unithd 5520 796960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_290 unithd 5520 799680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_291 unithd 5520 802400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_292 unithd 5520 805120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_293 unithd 5520 807840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_294 unithd 5520 810560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_295 unithd 5520 813280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_296 unithd 5520 816000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_297 unithd 5520 818720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_298 unithd 5520 821440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_299 unithd 5520 824160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_300 unithd 5520 826880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_301 unithd 5520 829600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_302 unithd 5520 832320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_303 unithd 5520 835040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_304 unithd 5520 837760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_305 unithd 5520 840480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_306 unithd 5520 843200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_307 unithd 5520 845920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_308 unithd 5520 848640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_309 unithd 5520 851360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_310 unithd 5520 854080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_311 unithd 5520 856800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_312 unithd 5520 859520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_313 unithd 5520 862240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_314 unithd 5520 864960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_315 unithd 5520 867680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_316 unithd 5520 870400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_317 unithd 5520 873120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_318 unithd 5520 875840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_319 unithd 5520 878560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_320 unithd 5520 881280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_321 unithd 5520 884000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_322 unithd 5520 886720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_323 unithd 5520 889440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_324 unithd 5520 892160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_325 unithd 5520 894880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_326 unithd 5520 897600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_327 unithd 5520 900320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_328 unithd 5520 903040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_329 unithd 5520 905760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_330 unithd 5520 908480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_331 unithd 5520 911200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_332 unithd 5520 913920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_333 unithd 5520 916640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_334 unithd 5520 919360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_335 unithd 5520 922080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_336 unithd 5520 924800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_337 unithd 5520 927520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_338 unithd 5520 930240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_339 unithd 5520 932960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_340 unithd 5520 935680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_341 unithd 5520 938400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_342 unithd 5520 941120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_343 unithd 5520 943840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_344 unithd 5520 946560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_345 unithd 5520 949280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_346 unithd 5520 952000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_347 unithd 5520 954720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_348 unithd 5520 957440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_349 unithd 5520 960160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_350 unithd 5520 962880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_351 unithd 5520 965600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_352 unithd 5520 968320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_353 unithd 5520 971040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_354 unithd 5520 973760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_355 unithd 5520 976480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_356 unithd 5520 979200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_357 unithd 5520 981920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_358 unithd 5520 984640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_359 unithd 5520 987360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_360 unithd 5520 990080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_361 unithd 5520 992800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_362 unithd 5520 995520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_363 unithd 5520 998240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_364 unithd 5520 1000960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_365 unithd 5520 1003680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_366 unithd 5520 1006400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_367 unithd 5520 1009120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_368 unithd 5520 1011840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_369 unithd 5520 1014560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_370 unithd 5520 1017280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_371 unithd 5520 1020000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_372 unithd 5520 1022720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_373 unithd 5520 1025440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_374 unithd 5520 1028160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_375 unithd 5520 1030880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_376 unithd 5520 1033600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_377 unithd 5520 1036320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_378 unithd 5520 1039040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_379 unithd 5520 1041760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_380 unithd 5520 1044480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_381 unithd 5520 1047200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_382 unithd 5520 1049920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_383 unithd 5520 1052640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_384 unithd 5520 1055360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_385 unithd 5520 1058080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_386 unithd 5520 1060800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_387 unithd 5520 1063520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_388 unithd 5520 1066240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_389 unithd 5520 1068960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_390 unithd 5520 1071680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_391 unithd 5520 1074400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_392 unithd 5520 1077120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_393 unithd 5520 1079840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_394 unithd 5520 1082560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_395 unithd 5520 1085280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_396 unithd 5520 1088000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_397 unithd 5520 1090720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_398 unithd 5520 1093440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_399 unithd 5520 1096160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_400 unithd 5520 1098880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_401 unithd 5520 1101600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_402 unithd 5520 1104320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_403 unithd 5520 1107040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_404 unithd 5520 1109760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_405 unithd 5520 1112480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_406 unithd 5520 1115200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_407 unithd 5520 1117920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_408 unithd 5520 1120640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_409 unithd 5520 1123360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_410 unithd 5520 1126080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_411 unithd 5520 1128800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_412 unithd 5520 1131520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_413 unithd 5520 1134240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_414 unithd 5520 1136960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_415 unithd 5520 1139680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_416 unithd 5520 1142400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_417 unithd 5520 1145120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_418 unithd 5520 1147840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_419 unithd 5520 1150560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_420 unithd 5520 1153280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_421 unithd 5520 1156000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_422 unithd 5520 1158720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_423 unithd 5520 1161440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_424 unithd 5520 1164160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_425 unithd 5520 1166880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_426 unithd 5520 1169600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_427 unithd 5520 1172320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_428 unithd 5520 1175040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_429 unithd 5520 1177760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_430 unithd 5520 1180480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_431 unithd 5520 1183200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_432 unithd 5520 1185920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_433 unithd 5520 1188640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_434 unithd 5520 1191360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_435 unithd 5520 1194080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_436 unithd 5520 1196800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_437 unithd 5520 1199520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_438 unithd 5520 1202240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_439 unithd 5520 1204960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_440 unithd 5520 1207680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_441 unithd 5520 1210400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_442 unithd 5520 1213120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_443 unithd 5520 1215840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_444 unithd 5520 1218560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_445 unithd 5520 1221280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_446 unithd 5520 1224000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_447 unithd 5520 1226720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_448 unithd 5520 1229440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_449 unithd 5520 1232160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_450 unithd 5520 1234880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_451 unithd 5520 1237600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_452 unithd 5520 1240320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_453 unithd 5520 1243040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_454 unithd 5520 1245760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_455 unithd 5520 1248480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_456 unithd 5520 1251200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_457 unithd 5520 1253920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_458 unithd 5520 1256640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_459 unithd 5520 1259360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_460 unithd 5520 1262080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_461 unithd 5520 1264800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_462 unithd 5520 1267520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_463 unithd 5520 1270240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_464 unithd 5520 1272960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_465 unithd 5520 1275680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_466 unithd 5520 1278400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_467 unithd 5520 1281120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_468 unithd 5520 1283840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_469 unithd 5520 1286560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_470 unithd 5520 1289280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_471 unithd 5520 1292000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_472 unithd 5520 1294720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_473 unithd 5520 1297440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_474 unithd 5520 1300160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_475 unithd 5520 1302880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_476 unithd 5520 1305600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_477 unithd 5520 1308320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_478 unithd 5520 1311040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_479 unithd 5520 1313760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_480 unithd 5520 1316480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_481 unithd 5520 1319200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_482 unithd 5520 1321920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_483 unithd 5520 1324640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_484 unithd 5520 1327360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_485 unithd 5520 1330080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_486 unithd 5520 1332800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_487 unithd 5520 1335520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_488 unithd 5520 1338240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_489 unithd 5520 1340960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_490 unithd 5520 1343680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_491 unithd 5520 1346400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_492 unithd 5520 1349120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_493 unithd 5520 1351840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_494 unithd 5520 1354560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_495 unithd 5520 1357280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_496 unithd 5520 1360000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_497 unithd 5520 1362720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_498 unithd 5520 1365440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_499 unithd 5520 1368160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_500 unithd 5520 1370880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_501 unithd 5520 1373600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_502 unithd 5520 1376320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_503 unithd 5520 1379040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_504 unithd 5520 1381760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_505 unithd 5520 1384480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_506 unithd 5520 1387200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_507 unithd 5520 1389920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_508 unithd 5520 1392640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_509 unithd 5520 1395360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_510 unithd 5520 1398080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_511 unithd 5520 1400800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_512 unithd 5520 1403520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_513 unithd 5520 1406240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_514 unithd 5520 1408960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_515 unithd 5520 1411680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_516 unithd 5520 1414400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_517 unithd 5520 1417120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_518 unithd 5520 1419840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_519 unithd 5520 1422560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_520 unithd 5520 1425280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_521 unithd 5520 1428000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_522 unithd 5520 1430720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_523 unithd 5520 1433440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_524 unithd 5520 1436160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_525 unithd 5520 1438880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_526 unithd 5520 1441600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_527 unithd 5520 1444320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_528 unithd 5520 1447040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_529 unithd 5520 1449760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_530 unithd 5520 1452480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_531 unithd 5520 1455200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_532 unithd 5520 1457920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_533 unithd 5520 1460640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_534 unithd 5520 1463360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_535 unithd 5520 1466080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_536 unithd 5520 1468800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_537 unithd 5520 1471520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_538 unithd 5520 1474240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_539 unithd 5520 1476960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_540 unithd 5520 1479680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_541 unithd 5520 1482400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_542 unithd 5520 1485120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_543 unithd 5520 1487840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_544 unithd 5520 1490560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_545 unithd 5520 1493280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_546 unithd 5520 1496000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_547 unithd 5520 1498720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_548 unithd 5520 1501440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_549 unithd 5520 1504160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_550 unithd 5520 1506880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_551 unithd 5520 1509600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_552 unithd 5520 1512320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_553 unithd 5520 1515040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_554 unithd 5520 1517760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_555 unithd 5520 1520480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_556 unithd 5520 1523200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_557 unithd 5520 1525920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_558 unithd 5520 1528640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_559 unithd 5520 1531360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_560 unithd 5520 1534080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_561 unithd 5520 1536800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_562 unithd 5520 1539520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_563 unithd 5520 1542240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_564 unithd 5520 1544960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_565 unithd 5520 1547680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_566 unithd 5520 1550400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_567 unithd 5520 1553120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_568 unithd 5520 1555840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_569 unithd 5520 1558560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_570 unithd 5520 1561280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_571 unithd 5520 1564000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_572 unithd 5520 1566720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_573 unithd 5520 1569440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_574 unithd 5520 1572160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_575 unithd 5520 1574880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_576 unithd 5520 1577600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_577 unithd 5520 1580320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_578 unithd 5520 1583040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_579 unithd 5520 1585760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_580 unithd 5520 1588480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_581 unithd 5520 1591200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_582 unithd 5520 1593920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_583 unithd 5520 1596640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_584 unithd 5520 1599360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_585 unithd 5520 1602080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_586 unithd 5520 1604800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_587 unithd 5520 1607520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_588 unithd 5520 1610240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_589 unithd 5520 1612960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_590 unithd 5520 1615680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_591 unithd 5520 1618400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_592 unithd 5520 1621120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_593 unithd 5520 1623840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_594 unithd 5520 1626560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_595 unithd 5520 1629280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_596 unithd 5520 1632000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_597 unithd 5520 1634720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_598 unithd 5520 1637440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_599 unithd 5520 1640160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_600 unithd 5520 1642880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_601 unithd 5520 1645600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_602 unithd 5520 1648320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_603 unithd 5520 1651040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_604 unithd 5520 1653760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_605 unithd 5520 1656480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_606 unithd 5520 1659200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_607 unithd 5520 1661920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_608 unithd 5520 1664640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_609 unithd 5520 1667360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_610 unithd 5520 1670080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_611 unithd 5520 1672800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_612 unithd 5520 1675520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_613 unithd 5520 1678240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_614 unithd 5520 1680960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_615 unithd 5520 1683680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_616 unithd 5520 1686400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_617 unithd 5520 1689120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_618 unithd 5520 1691840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_619 unithd 5520 1694560 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_623 unithd 5520 1705440 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_627 unithd 5520 1716320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_628 unithd 5520 1719040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_629 unithd 5520 1721760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_630 unithd 5520 1724480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_631 unithd 5520 1727200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_632 unithd 5520 1729920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_633 unithd 5520 1732640 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_636 unithd 5520 1740800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_637 unithd 5520 1743520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_638 unithd 5520 1746240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_639 unithd 5520 1748960 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_641 unithd 5520 1754400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_642 unithd 5520 1757120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_643 unithd 5520 1759840 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_656 unithd 5520 1795200 N DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_668 unithd 5520 1827840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_669 unithd 5520 1830560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_670 unithd 5520 1833280 N DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_677 unithd 5520 1852320 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_681 unithd 5520 1863200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_682 unithd 5520 1865920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_683 unithd 5520 1868640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_684 unithd 5520 1871360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_685 unithd 5520 1874080 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_689 unithd 5520 1884960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_690 unithd 5520 1887680 N DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_693 unithd 5520 1895840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_694 unithd 5520 1898560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_695 unithd 5520 1901280 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_697 unithd 5520 1906720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_698 unithd 5520 1909440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_699 unithd 5520 1912160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_700 unithd 5520 1914880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_701 unithd 5520 1917600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_702 unithd 5520 1920320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_703 unithd 5520 1923040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_704 unithd 5520 1925760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_705 unithd 5520 1928480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_706 unithd 5520 1931200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_707 unithd 5520 1933920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_708 unithd 5520 1936640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_709 unithd 5520 1939360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_710 unithd 5520 1942080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_711 unithd 5520 1944800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_712 unithd 5520 1947520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_713 unithd 5520 1950240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_714 unithd 5520 1952960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_715 unithd 5520 1955680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_716 unithd 5520 1958400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_717 unithd 5520 1961120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_718 unithd 5520 1963840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_719 unithd 5520 1966560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_720 unithd 5520 1969280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_721 unithd 5520 1972000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_722 unithd 5520 1974720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_723 unithd 5520 1977440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_724 unithd 5520 1980160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_725 unithd 5520 1982880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_726 unithd 5520 1985600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_727 unithd 5520 1988320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_728 unithd 5520 1991040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_729 unithd 5520 1993760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_730 unithd 5520 1996480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_731 unithd 5520 1999200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_732 unithd 5520 2001920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_733 unithd 5520 2004640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_734 unithd 5520 2007360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_735 unithd 5520 2010080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_736 unithd 5520 2012800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_737 unithd 5520 2015520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_738 unithd 5520 2018240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_739 unithd 5520 2020960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_740 unithd 5520 2023680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_741 unithd 5520 2026400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_742 unithd 5520 2029120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_743 unithd 5520 2031840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_744 unithd 5520 2034560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_745 unithd 5520 2037280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_746 unithd 5520 2040000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_747 unithd 5520 2042720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_748 unithd 5520 2045440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_749 unithd 5520 2048160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_750 unithd 5520 2050880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_751 unithd 5520 2053600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_752 unithd 5520 2056320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_753 unithd 5520 2059040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_754 unithd 5520 2061760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_755 unithd 5520 2064480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_756 unithd 5520 2067200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_757 unithd 5520 2069920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_758 unithd 5520 2072640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_759 unithd 5520 2075360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_760 unithd 5520 2078080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_761 unithd 5520 2080800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_762 unithd 5520 2083520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_763 unithd 5520 2086240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_764 unithd 5520 2088960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_765 unithd 5520 2091680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_766 unithd 5520 2094400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_767 unithd 5520 2097120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_768 unithd 5520 2099840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_769 unithd 5520 2102560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_770 unithd 5520 2105280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_771 unithd 5520 2108000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_772 unithd 5520 2110720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_773 unithd 5520 2113440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_774 unithd 5520 2116160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_775 unithd 5520 2118880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_776 unithd 5520 2121600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_777 unithd 5520 2124320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_778 unithd 5520 2127040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_779 unithd 5520 2129760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_780 unithd 5520 2132480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_781 unithd 5520 2135200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_782 unithd 5520 2137920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_783 unithd 5520 2140640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_784 unithd 5520 2143360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_785 unithd 5520 2146080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_786 unithd 5520 2148800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_787 unithd 5520 2151520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_788 unithd 5520 2154240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_789 unithd 5520 2156960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_790 unithd 5520 2159680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_791 unithd 5520 2162400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_792 unithd 5520 2165120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_793 unithd 5520 2167840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_794 unithd 5520 2170560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_795 unithd 5520 2173280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_796 unithd 5520 2176000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_797 unithd 5520 2178720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_798 unithd 5520 2181440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_799 unithd 5520 2184160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_800 unithd 5520 2186880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_801 unithd 5520 2189600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_802 unithd 5520 2192320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_803 unithd 5520 2195040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_804 unithd 5520 2197760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_805 unithd 5520 2200480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_806 unithd 5520 2203200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_807 unithd 5520 2205920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_808 unithd 5520 2208640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_809 unithd 5520 2211360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_810 unithd 5520 2214080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_811 unithd 5520 2216800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_812 unithd 5520 2219520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_813 unithd 5520 2222240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_814 unithd 5520 2224960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_815 unithd 5520 2227680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_816 unithd 5520 2230400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_817 unithd 5520 2233120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_818 unithd 5520 2235840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_819 unithd 5520 2238560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_820 unithd 5520 2241280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_821 unithd 5520 2244000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_822 unithd 5520 2246720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_823 unithd 5520 2249440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_824 unithd 5520 2252160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_825 unithd 5520 2254880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_826 unithd 5520 2257600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_827 unithd 5520 2260320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_828 unithd 5520 2263040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_829 unithd 5520 2265760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_830 unithd 5520 2268480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_831 unithd 5520 2271200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_832 unithd 5520 2273920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_833 unithd 5520 2276640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_834 unithd 5520 2279360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_835 unithd 5520 2282080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_836 unithd 5520 2284800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_837 unithd 5520 2287520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_838 unithd 5520 2290240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_839 unithd 5520 2292960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_840 unithd 5520 2295680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_841 unithd 5520 2298400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_842 unithd 5520 2301120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_843 unithd 5520 2303840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_844 unithd 5520 2306560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_845 unithd 5520 2309280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_846 unithd 5520 2312000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_847 unithd 5520 2314720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_848 unithd 5520 2317440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_849 unithd 5520 2320160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_850 unithd 5520 2322880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_851 unithd 5520 2325600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_852 unithd 5520 2328320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_853 unithd 5520 2331040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_854 unithd 5520 2333760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_855 unithd 5520 2336480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_856 unithd 5520 2339200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_857 unithd 5520 2341920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_858 unithd 5520 2344640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_859 unithd 5520 2347360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_860 unithd 5520 2350080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_861 unithd 5520 2352800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_862 unithd 5520 2355520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_863 unithd 5520 2358240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_864 unithd 5520 2360960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_865 unithd 5520 2363680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_866 unithd 5520 2366400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_867 unithd 5520 2369120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_868 unithd 5520 2371840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_869 unithd 5520 2374560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_870 unithd 5520 2377280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_871 unithd 5520 2380000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_872 unithd 5520 2382720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_873 unithd 5520 2385440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_874 unithd 5520 2388160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_875 unithd 5520 2390880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_876 unithd 5520 2393600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_877 unithd 5520 2396320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_878 unithd 5520 2399040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_879 unithd 5520 2401760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_880 unithd 5520 2404480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_881 unithd 5520 2407200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_882 unithd 5520 2409920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_883 unithd 5520 2412640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_884 unithd 5520 2415360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_885 unithd 5520 2418080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_886 unithd 5520 2420800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_887 unithd 5520 2423520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_888 unithd 5520 2426240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_889 unithd 5520 2428960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_890 unithd 5520 2431680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_891 unithd 5520 2434400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_892 unithd 5520 2437120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_893 unithd 5520 2439840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_894 unithd 5520 2442560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_895 unithd 5520 2445280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_896 unithd 5520 2448000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_897 unithd 5520 2450720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_898 unithd 5520 2453440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_899 unithd 5520 2456160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_900 unithd 5520 2458880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_901 unithd 5520 2461600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_902 unithd 5520 2464320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_903 unithd 5520 2467040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_904 unithd 5520 2469760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_905 unithd 5520 2472480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_906 unithd 5520 2475200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_907 unithd 5520 2477920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_908 unithd 5520 2480640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_909 unithd 5520 2483360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_910 unithd 5520 2486080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_911 unithd 5520 2488800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_912 unithd 5520 2491520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_913 unithd 5520 2494240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_914 unithd 5520 2496960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_915 unithd 5520 2499680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_916 unithd 5520 2502400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_917 unithd 5520 2505120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_918 unithd 5520 2507840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_919 unithd 5520 2510560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_920 unithd 5520 2513280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_921 unithd 5520 2516000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_922 unithd 5520 2518720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_923 unithd 5520 2521440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_924 unithd 5520 2524160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_925 unithd 5520 2526880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_926 unithd 5520 2529600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_927 unithd 5520 2532320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_928 unithd 5520 2535040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_929 unithd 5520 2537760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_930 unithd 5520 2540480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_931 unithd 5520 2543200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_932 unithd 5520 2545920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_933 unithd 5520 2548640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_934 unithd 5520 2551360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_935 unithd 5520 2554080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_936 unithd 5520 2556800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_937 unithd 5520 2559520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_938 unithd 5520 2562240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_939 unithd 5520 2564960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_940 unithd 5520 2567680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_941 unithd 5520 2570400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_942 unithd 5520 2573120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_943 unithd 5520 2575840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_944 unithd 5520 2578560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_945 unithd 5520 2581280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_946 unithd 5520 2584000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_947 unithd 5520 2586720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_948 unithd 5520 2589440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_949 unithd 5520 2592160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_950 unithd 5520 2594880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_951 unithd 5520 2597600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_952 unithd 5520 2600320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_953 unithd 5520 2603040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_954 unithd 5520 2605760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_955 unithd 5520 2608480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_956 unithd 5520 2611200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_957 unithd 5520 2613920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_958 unithd 5520 2616640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_959 unithd 5520 2619360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_960 unithd 5520 2622080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_961 unithd 5520 2624800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_962 unithd 5520 2627520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_963 unithd 5520 2630240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_964 unithd 5520 2632960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_965 unithd 5520 2635680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_966 unithd 5520 2638400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_967 unithd 5520 2641120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_968 unithd 5520 2643840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_969 unithd 5520 2646560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_970 unithd 5520 2649280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_971 unithd 5520 2652000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_972 unithd 5520 2654720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_973 unithd 5520 2657440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_974 unithd 5520 2660160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_975 unithd 5520 2662880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_976 unithd 5520 2665600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_977 unithd 5520 2668320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_978 unithd 5520 2671040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_979 unithd 5520 2673760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_980 unithd 5520 2676480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_981 unithd 5520 2679200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_982 unithd 5520 2681920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_983 unithd 5520 2684640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_984 unithd 5520 2687360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_985 unithd 5520 2690080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_986 unithd 5520 2692800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_987 unithd 5520 2695520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_988 unithd 5520 2698240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_989 unithd 5520 2700960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_990 unithd 5520 2703680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_991 unithd 5520 2706400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_992 unithd 5520 2709120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_993 unithd 5520 2711840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_994 unithd 5520 2714560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_995 unithd 5520 2717280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_996 unithd 5520 2720000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_997 unithd 5520 2722720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_998 unithd 5520 2725440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_999 unithd 5520 2728160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1000 unithd 5520 2730880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1001 unithd 5520 2733600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1002 unithd 5520 2736320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1003 unithd 5520 2739040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1004 unithd 5520 2741760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1005 unithd 5520 2744480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1006 unithd 5520 2747200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1007 unithd 5520 2749920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1008 unithd 5520 2752640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1009 unithd 5520 2755360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1010 unithd 5520 2758080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1011 unithd 5520 2760800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1012 unithd 5520 2763520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1013 unithd 5520 2766240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1014 unithd 5520 2768960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1015 unithd 5520 2771680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1016 unithd 5520 2774400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1017 unithd 5520 2777120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1018 unithd 5520 2779840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1019 unithd 5520 2782560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1020 unithd 5520 2785280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1021 unithd 5520 2788000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1022 unithd 5520 2790720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1023 unithd 5520 2793440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1024 unithd 5520 2796160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1025 unithd 5520 2798880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1026 unithd 5520 2801600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1027 unithd 5520 2804320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1028 unithd 5520 2807040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1029 unithd 5520 2809760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1030 unithd 5520 2812480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1031 unithd 5520 2815200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1032 unithd 5520 2817920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1033 unithd 5520 2820640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1034 unithd 5520 2823360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1035 unithd 5520 2826080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1036 unithd 5520 2828800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1037 unithd 5520 2831520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1038 unithd 5520 2834240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1039 unithd 5520 2836960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1040 unithd 5520 2839680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1041 unithd 5520 2842400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1042 unithd 5520 2845120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1043 unithd 5520 2847840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1044 unithd 5520 2850560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1045 unithd 5520 2853280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1046 unithd 5520 2856000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1047 unithd 5520 2858720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1048 unithd 5520 2861440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1049 unithd 5520 2864160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1050 unithd 5520 2866880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1051 unithd 5520 2869600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1052 unithd 5520 2872320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1053 unithd 5520 2875040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1054 unithd 5520 2877760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1055 unithd 5520 2880480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1056 unithd 5520 2883200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1057 unithd 5520 2885920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1058 unithd 5520 2888640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1059 unithd 5520 2891360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1060 unithd 5520 2894080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1061 unithd 5520 2896800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1062 unithd 5520 2899520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1063 unithd 5520 2902240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1064 unithd 5520 2904960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1065 unithd 5520 2907680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1066 unithd 5520 2910400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1067 unithd 5520 2913120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1068 unithd 5520 2915840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1069 unithd 5520 2918560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1070 unithd 5520 2921280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1071 unithd 5520 2924000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1072 unithd 5520 2926720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1073 unithd 5520 2929440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1074 unithd 5520 2932160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1075 unithd 5520 2934880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1076 unithd 5520 2937600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1077 unithd 5520 2940320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1078 unithd 5520 2943040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1079 unithd 5520 2945760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1080 unithd 5520 2948480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1081 unithd 5520 2951200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1082 unithd 5520 2953920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1083 unithd 5520 2956640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1084 unithd 5520 2959360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1085 unithd 5520 2962080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1086 unithd 5520 2964800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1087 unithd 5520 2967520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1088 unithd 5520 2970240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1089 unithd 5520 2972960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1090 unithd 5520 2975680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1091 unithd 5520 2978400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1092 unithd 5520 2981120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1093 unithd 5520 2983840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1094 unithd 5520 2986560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1095 unithd 5520 2989280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1096 unithd 5520 2992000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1097 unithd 5520 2994720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1098 unithd 5520 2997440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1099 unithd 5520 3000160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1100 unithd 5520 3002880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1101 unithd 5520 3005600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1102 unithd 5520 3008320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1103 unithd 5520 3011040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1104 unithd 5520 3013760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1105 unithd 5520 3016480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1106 unithd 5520 3019200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1107 unithd 5520 3021920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1108 unithd 5520 3024640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1109 unithd 5520 3027360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1110 unithd 5520 3030080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1111 unithd 5520 3032800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1112 unithd 5520 3035520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1113 unithd 5520 3038240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1114 unithd 5520 3040960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1115 unithd 5520 3043680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1116 unithd 5520 3046400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1117 unithd 5520 3049120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1118 unithd 5520 3051840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1119 unithd 5520 3054560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1120 unithd 5520 3057280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1121 unithd 5520 3060000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1122 unithd 5520 3062720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1123 unithd 5520 3065440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1124 unithd 5520 3068160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1125 unithd 5520 3070880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1126 unithd 5520 3073600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1127 unithd 5520 3076320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1128 unithd 5520 3079040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1129 unithd 5520 3081760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1130 unithd 5520 3084480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1131 unithd 5520 3087200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1132 unithd 5520 3089920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1133 unithd 5520 3092640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1134 unithd 5520 3095360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1135 unithd 5520 3098080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1136 unithd 5520 3100800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1137 unithd 5520 3103520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1138 unithd 5520 3106240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1139 unithd 5520 3108960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1140 unithd 5520 3111680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1141 unithd 5520 3114400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1142 unithd 5520 3117120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1143 unithd 5520 3119840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1144 unithd 5520 3122560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1145 unithd 5520 3125280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1146 unithd 5520 3128000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1147 unithd 5520 3130720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1148 unithd 5520 3133440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1149 unithd 5520 3136160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1150 unithd 5520 3138880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1151 unithd 5520 3141600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1152 unithd 5520 3144320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1153 unithd 5520 3147040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1154 unithd 5520 3149760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1155 unithd 5520 3152480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1156 unithd 5520 3155200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1157 unithd 5520 3157920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1158 unithd 5520 3160640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1159 unithd 5520 3163360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1160 unithd 5520 3166080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1161 unithd 5520 3168800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1162 unithd 5520 3171520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1163 unithd 5520 3174240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1164 unithd 5520 3176960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1165 unithd 5520 3179680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1166 unithd 5520 3182400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1167 unithd 5520 3185120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1168 unithd 5520 3187840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1169 unithd 5520 3190560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1170 unithd 5520 3193280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1171 unithd 5520 3196000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1172 unithd 5520 3198720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1173 unithd 5520 3201440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1174 unithd 5520 3204160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1175 unithd 5520 3206880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1176 unithd 5520 3209600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1177 unithd 5520 3212320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1178 unithd 5520 3215040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1179 unithd 5520 3217760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1180 unithd 5520 3220480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1181 unithd 5520 3223200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1182 unithd 5520 3225920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1183 unithd 5520 3228640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1184 unithd 5520 3231360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1185 unithd 5520 3234080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1186 unithd 5520 3236800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1187 unithd 5520 3239520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1188 unithd 5520 3242240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1189 unithd 5520 3244960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1190 unithd 5520 3247680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1191 unithd 5520 3250400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1192 unithd 5520 3253120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1193 unithd 5520 3255840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1194 unithd 5520 3258560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1195 unithd 5520 3261280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1196 unithd 5520 3264000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1197 unithd 5520 3266720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1198 unithd 5520 3269440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1199 unithd 5520 3272160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1200 unithd 5520 3274880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1201 unithd 5520 3277600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1202 unithd 5520 3280320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1203 unithd 5520 3283040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1204 unithd 5520 3285760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1205 unithd 5520 3288480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1206 unithd 5520 3291200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1207 unithd 5520 3293920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1208 unithd 5520 3296640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1209 unithd 5520 3299360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1210 unithd 5520 3302080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1211 unithd 5520 3304800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1212 unithd 5520 3307520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1213 unithd 5520 3310240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1214 unithd 5520 3312960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1215 unithd 5520 3315680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1216 unithd 5520 3318400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1217 unithd 5520 3321120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1218 unithd 5520 3323840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1219 unithd 5520 3326560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1220 unithd 5520 3329280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1221 unithd 5520 3332000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1222 unithd 5520 3334720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1223 unithd 5520 3337440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1224 unithd 5520 3340160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1225 unithd 5520 3342880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1226 unithd 5520 3345600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1227 unithd 5520 3348320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1228 unithd 5520 3351040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1229 unithd 5520 3353760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1230 unithd 5520 3356480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1231 unithd 5520 3359200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1232 unithd 5520 3361920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1233 unithd 5520 3364640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1234 unithd 5520 3367360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1235 unithd 5520 3370080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1236 unithd 5520 3372800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1237 unithd 5520 3375520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1238 unithd 5520 3378240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1239 unithd 5520 3380960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1240 unithd 5520 3383680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1241 unithd 5520 3386400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1242 unithd 5520 3389120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1243 unithd 5520 3391840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1244 unithd 5520 3394560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1245 unithd 5520 3397280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1246 unithd 5520 3400000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1247 unithd 5520 3402720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1248 unithd 5520 3405440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1249 unithd 5520 3408160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1250 unithd 5520 3410880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1251 unithd 5520 3413600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1252 unithd 5520 3416320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1253 unithd 5520 3419040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1254 unithd 5520 3421760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1255 unithd 5520 3424480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1256 unithd 5520 3427200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1257 unithd 5520 3429920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1258 unithd 5520 3432640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1259 unithd 5520 3435360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1260 unithd 5520 3438080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1261 unithd 5520 3440800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1262 unithd 5520 3443520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1263 unithd 5520 3446240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1264 unithd 5520 3448960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1265 unithd 5520 3451680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1266 unithd 5520 3454400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1267 unithd 5520 3457120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1268 unithd 5520 3459840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1269 unithd 5520 3462560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1270 unithd 5520 3465280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1271 unithd 5520 3468000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1272 unithd 5520 3470720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1273 unithd 5520 3473440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1274 unithd 5520 3476160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1275 unithd 5520 3478880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1276 unithd 5520 3481600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1277 unithd 5520 3484320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1278 unithd 5520 3487040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1279 unithd 5520 3489760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1280 unithd 5520 3492480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1281 unithd 5520 3495200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1282 unithd 5520 3497920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1283 unithd 5520 3500640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1284 unithd 5520 3503360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1285 unithd 5520 3506080 FS DO 6323 BY 1 STEP 460 0 ;
+TRACKS X 230 DO 6348 STEP 460 LAYER li1 ;
+TRACKS Y 170 DO 10353 STEP 340 LAYER li1 ;
+TRACKS X 170 DO 8588 STEP 340 LAYER met1 ;
+TRACKS Y 170 DO 10353 STEP 340 LAYER met1 ;
+TRACKS X 230 DO 6348 STEP 460 LAYER met2 ;
+TRACKS Y 230 DO 7652 STEP 460 LAYER met2 ;
+TRACKS X 340 DO 4294 STEP 680 LAYER met3 ;
+TRACKS Y 340 DO 5176 STEP 680 LAYER met3 ;
+TRACKS X 460 DO 3174 STEP 920 LAYER met4 ;
+TRACKS Y 460 DO 3826 STEP 920 LAYER met4 ;
+TRACKS X 1700 DO 859 STEP 3400 LAYER met5 ;
+TRACKS Y 1700 DO 1035 STEP 3400 LAYER met5 ;
+GCELLGRID X 0 DO 423 STEP 6900 ;
+GCELLGRID Y 0 DO 510 STEP 6900 ;
+VIAS 2 ;
+ - via4_3100x3100 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 350 350 350 350 + ROWCOL 2 2 ;
+ - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 350 400 350 + ROWCOL 2 1 ;
+END VIAS
+PINS 645 ;
+ - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1426980 ) N ;
+ - analog_io[10] + NET analog_io[10] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2230770 3521200 ) N ;
+ - analog_io[11] + NET analog_io[11] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1906010 3521200 ) N ;
+ - analog_io[12] + NET analog_io[12] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1581710 3521200 ) N ;
+ - analog_io[13] + NET analog_io[13] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1257410 3521200 ) N ;
+ - analog_io[14] + NET analog_io[14] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 932650 3521200 ) N ;
+ - analog_io[15] + NET analog_io[15] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 608350 3521200 ) N ;
+ - analog_io[16] + NET analog_io[16] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 284050 3521200 ) N ;
+ - analog_io[17] + NET analog_io[17] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3486700 ) N ;
+ - analog_io[18] + NET analog_io[18] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3225580 ) N ;
+ - analog_io[19] + NET analog_io[19] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2965140 ) N ;
+ - analog_io[1] + NET analog_io[1] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1692860 ) N ;
+ - analog_io[20] + NET analog_io[20] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2704020 ) N ;
+ - analog_io[21] + NET analog_io[21] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2443580 ) N ;
+ - analog_io[22] + NET analog_io[22] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2183140 ) N ;
+ - analog_io[23] + NET analog_io[23] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1922020 ) N ;
+ - analog_io[24] + NET analog_io[24] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1661580 ) N ;
+ - analog_io[25] + NET analog_io[25] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1400460 ) N ;
+ - analog_io[26] + NET analog_io[26] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1140020 ) N ;
+ - analog_io[27] + NET analog_io[27] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 879580 ) N ;
+ - analog_io[28] + NET analog_io[28] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 618460 ) N ;
+ - analog_io[2] + NET analog_io[2] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1958740 ) N ;
+ - analog_io[3] + NET analog_io[3] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2223940 ) N ;
+ - analog_io[4] + NET analog_io[4] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2489820 ) N ;
+ - analog_io[5] + NET analog_io[5] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2755700 ) N ;
+ - analog_io[6] + NET analog_io[6] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3020900 ) N ;
+ - analog_io[7] + NET analog_io[7] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3286780 ) N ;
+ - analog_io[8] + NET analog_io[8] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2879370 3521200 ) N ;
+ - analog_io[9] + NET analog_io[9] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2555070 3521200 ) N ;
+ - io_in[0] + NET io_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 32980 ) N ;
+ - io_in[10] + NET io_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2290580 ) N ;
+ - io_in[11] + NET io_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2556460 ) N ;
+ - io_in[12] + NET io_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2821660 ) N ;
+ - io_in[13] + NET io_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3087540 ) N ;
+ - io_in[14] + NET io_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3353420 ) N ;
+ - io_in[15] + NET io_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2798410 3521200 ) N ;
+ - io_in[16] + NET io_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2474110 3521200 ) N ;
+ - io_in[17] + NET io_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2149350 3521200 ) N ;
+ - io_in[18] + NET io_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1825050 3521200 ) N ;
+ - io_in[19] + NET io_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1500750 3521200 ) N ;
+ - io_in[1] + NET io_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 231540 ) N ;
+ - io_in[20] + NET io_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1175990 3521200 ) N ;
+ - io_in[21] + NET io_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 851690 3521200 ) N ;
+ - io_in[22] + NET io_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 527390 3521200 ) N ;
+ - io_in[23] + NET io_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 202630 3521200 ) N ;
+ - io_in[24] + NET io_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3421420 ) N ;
+ - io_in[25] + NET io_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3160300 ) N ;
+ - io_in[26] + NET io_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2899860 ) N ;
+ - io_in[27] + NET io_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2639420 ) N ;
+ - io_in[28] + NET io_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2378300 ) N ;
+ - io_in[29] + NET io_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2117860 ) N ;
+ - io_in[2] + NET io_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 430780 ) N ;
+ - io_in[30] + NET io_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1856740 ) N ;
+ - io_in[31] + NET io_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1596300 ) N ;
+ - io_in[32] + NET io_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1335860 ) N ;
+ - io_in[33] + NET io_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1074740 ) N ;
+ - io_in[34] + NET io_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 814300 ) N ;
+ - io_in[35] + NET io_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 553180 ) N ;
+ - io_in[36] + NET io_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 358020 ) N ;
+ - io_in[37] + NET io_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 162180 ) N ;
+ - io_in[3] + NET io_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 630020 ) N ;
+ - io_in[4] + NET io_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 829260 ) N ;
+ - io_in[5] + NET io_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1028500 ) N ;
+ - io_in[6] + NET io_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1227740 ) N ;
+ - io_in[7] + NET io_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1493620 ) N ;
+ - io_in[8] + NET io_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1759500 ) N ;
+ - io_in[9] + NET io_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2024700 ) N ;
+ - io_oeb[0] + NET io_oeb[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 165580 ) N ;
+ - io_oeb[10] + NET io_oeb[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2423180 ) N ;
+ - io_oeb[11] + NET io_oeb[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2689060 ) N ;
+ - io_oeb[12] + NET io_oeb[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2954940 ) N ;
+ - io_oeb[13] + NET io_oeb[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3220140 ) N ;
+ - io_oeb[14] + NET io_oeb[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3486020 ) N ;
+ - io_oeb[15] + NET io_oeb[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2636030 3521200 ) N ;
+ - io_oeb[16] + NET io_oeb[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2311730 3521200 ) N ;
+ - io_oeb[17] + NET io_oeb[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1987430 3521200 ) N ;
+ - io_oeb[18] + NET io_oeb[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1662670 3521200 ) N ;
+ - io_oeb[19] + NET io_oeb[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1338370 3521200 ) N ;
+ - io_oeb[1] + NET io_oeb[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 364820 ) N ;
+ - io_oeb[20] + NET io_oeb[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1014070 3521200 ) N ;
+ - io_oeb[21] + NET io_oeb[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 689310 3521200 ) N ;
+ - io_oeb[22] + NET io_oeb[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 365010 3521200 ) N ;
+ - io_oeb[23] + NET io_oeb[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 40710 3521200 ) N ;
+ - io_oeb[24] + NET io_oeb[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3290860 ) N ;
+ - io_oeb[25] + NET io_oeb[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3030420 ) N ;
+ - io_oeb[26] + NET io_oeb[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2769300 ) N ;
+ - io_oeb[27] + NET io_oeb[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2508860 ) N ;
+ - io_oeb[28] + NET io_oeb[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2247740 ) N ;
+ - io_oeb[29] + NET io_oeb[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1987300 ) N ;
+ - io_oeb[2] + NET io_oeb[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 564060 ) N ;
+ - io_oeb[30] + NET io_oeb[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1726860 ) N ;
+ - io_oeb[31] + NET io_oeb[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1465740 ) N ;
+ - io_oeb[32] + NET io_oeb[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1205300 ) N ;
+ - io_oeb[33] + NET io_oeb[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 944180 ) N ;
+ - io_oeb[34] + NET io_oeb[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 683740 ) N ;
+ - io_oeb[35] + NET io_oeb[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 423300 ) N ;
+ - io_oeb[36] + NET io_oeb[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 227460 ) N ;
+ - io_oeb[37] + NET io_oeb[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 32300 ) N ;
+ - io_oeb[3] + NET io_oeb[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 763300 ) N ;
+ - io_oeb[4] + NET io_oeb[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 962540 ) N ;
+ - io_oeb[5] + NET io_oeb[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1161780 ) N ;
+ - io_oeb[6] + NET io_oeb[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1361020 ) N ;
+ - io_oeb[7] + NET io_oeb[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1626220 ) N ;
+ - io_oeb[8] + NET io_oeb[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1892100 ) N ;
+ - io_oeb[9] + NET io_oeb[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2157980 ) N ;
+ - io_out[0] + NET io_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 98940 ) N ;
+ - io_out[10] + NET io_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2357220 ) N ;
+ - io_out[11] + NET io_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2622420 ) N ;
+ - io_out[12] + NET io_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2888300 ) N ;
+ - io_out[13] + NET io_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3154180 ) N ;
+ - io_out[14] + NET io_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3419380 ) N ;
+ - io_out[15] + NET io_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2717450 3521200 ) N ;
+ - io_out[16] + NET io_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2392690 3521200 ) N ;
+ - io_out[17] + NET io_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2068390 3521200 ) N ;
+ - io_out[18] + NET io_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1744090 3521200 ) N ;
+ - io_out[19] + NET io_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1419330 3521200 ) N ;
+ - io_out[1] + NET io_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 298180 ) N ;
+ - io_out[20] + NET io_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1095030 3521200 ) N ;
+ - io_out[21] + NET io_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 770730 3521200 ) N ;
+ - io_out[22] + NET io_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 445970 3521200 ) N ;
+ - io_out[23] + NET io_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 121670 3521200 ) N ;
+ - io_out[24] + NET io_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3356140 ) N ;
+ - io_out[25] + NET io_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3095700 ) N ;
+ - io_out[26] + NET io_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2834580 ) N ;
+ - io_out[27] + NET io_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2574140 ) N ;
+ - io_out[28] + NET io_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2313020 ) N ;
+ - io_out[29] + NET io_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2052580 ) N ;
+ - io_out[2] + NET io_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 497420 ) N ;
+ - io_out[30] + NET io_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1792140 ) N ;
+ - io_out[31] + NET io_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1531020 ) N ;
+ - io_out[32] + NET io_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1270580 ) N ;
+ - io_out[33] + NET io_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1009460 ) N ;
+ - io_out[34] + NET io_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 749020 ) N ;
+ - io_out[35] + NET io_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 487900 ) N ;
+ - io_out[36] + NET io_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 292740 ) N ;
+ - io_out[37] + NET io_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 96900 ) N ;
+ - io_out[3] + NET io_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 696660 ) N ;
+ - io_out[4] + NET io_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 895900 ) N ;
+ - io_out[5] + NET io_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1095140 ) N ;
+ - io_out[6] + NET io_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1294380 ) N ;
+ - io_out[7] + NET io_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1560260 ) N ;
+ - io_out[8] + NET io_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1825460 ) N ;
+ - io_out[9] + NET io_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2091340 ) N ;
+ - la_data_in[0] + NET la_data_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 629510 -1200 ) N ;
+ - la_data_in[100] + NET la_data_in[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2402810 -1200 ) N ;
+ - la_data_in[101] + NET la_data_in[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2420290 -1200 ) N ;
+ - la_data_in[102] + NET la_data_in[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2438230 -1200 ) N ;
+ - la_data_in[103] + NET la_data_in[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2455710 -1200 ) N ;
+ - la_data_in[104] + NET la_data_in[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2473650 -1200 ) N ;
+ - la_data_in[105] + NET la_data_in[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2491130 -1200 ) N ;
+ - la_data_in[106] + NET la_data_in[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2509070 -1200 ) N ;
+ - la_data_in[107] + NET la_data_in[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2527010 -1200 ) N ;
+ - la_data_in[108] + NET la_data_in[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2544490 -1200 ) N ;
+ - la_data_in[109] + NET la_data_in[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2562430 -1200 ) N ;
+ - la_data_in[10] + NET la_data_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 806610 -1200 ) N ;
+ - la_data_in[110] + NET la_data_in[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2579910 -1200 ) N ;
+ - la_data_in[111] + NET la_data_in[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2597850 -1200 ) N ;
+ - la_data_in[112] + NET la_data_in[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2615330 -1200 ) N ;
+ - la_data_in[113] + NET la_data_in[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2633270 -1200 ) N ;
+ - la_data_in[114] + NET la_data_in[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2650750 -1200 ) N ;
+ - la_data_in[115] + NET la_data_in[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2668690 -1200 ) N ;
+ - la_data_in[116] + NET la_data_in[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2686170 -1200 ) N ;
+ - la_data_in[117] + NET la_data_in[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2704110 -1200 ) N ;
+ - la_data_in[118] + NET la_data_in[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2722050 -1200 ) N ;
+ - la_data_in[119] + NET la_data_in[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2739530 -1200 ) N ;
+ - la_data_in[11] + NET la_data_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 824550 -1200 ) N ;
+ - la_data_in[120] + NET la_data_in[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2757470 -1200 ) N ;
+ - la_data_in[121] + NET la_data_in[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2774950 -1200 ) N ;
+ - la_data_in[122] + NET la_data_in[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2792890 -1200 ) N ;
+ - la_data_in[123] + NET la_data_in[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2810370 -1200 ) N ;
+ - la_data_in[124] + NET la_data_in[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2828310 -1200 ) N ;
+ - la_data_in[125] + NET la_data_in[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2845790 -1200 ) N ;
+ - la_data_in[126] + NET la_data_in[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2863730 -1200 ) N ;
+ - la_data_in[127] + NET la_data_in[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2881670 -1200 ) N ;
+ - la_data_in[12] + NET la_data_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 842030 -1200 ) N ;
+ - la_data_in[13] + NET la_data_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 859970 -1200 ) N ;
+ - la_data_in[14] + NET la_data_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 877450 -1200 ) N ;
+ - la_data_in[15] + NET la_data_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 895390 -1200 ) N ;
+ - la_data_in[16] + NET la_data_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 912870 -1200 ) N ;
+ - la_data_in[17] + NET la_data_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 930810 -1200 ) N ;
+ - la_data_in[18] + NET la_data_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 948750 -1200 ) N ;
+ - la_data_in[19] + NET la_data_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 966230 -1200 ) N ;
+ - la_data_in[1] + NET la_data_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 646990 -1200 ) N ;
+ - la_data_in[20] + NET la_data_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 984170 -1200 ) N ;
+ - la_data_in[21] + NET la_data_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1001650 -1200 ) N ;
+ - la_data_in[22] + NET la_data_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1019590 -1200 ) N ;
+ - la_data_in[23] + NET la_data_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1037070 -1200 ) N ;
+ - la_data_in[24] + NET la_data_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1055010 -1200 ) N ;
+ - la_data_in[25] + NET la_data_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1072490 -1200 ) N ;
+ - la_data_in[26] + NET la_data_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1090430 -1200 ) N ;
+ - la_data_in[27] + NET la_data_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1107910 -1200 ) N ;
+ - la_data_in[28] + NET la_data_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1125850 -1200 ) N ;
+ - la_data_in[29] + NET la_data_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1143790 -1200 ) N ;
+ - la_data_in[2] + NET la_data_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 664930 -1200 ) N ;
+ - la_data_in[30] + NET la_data_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1161270 -1200 ) N ;
+ - la_data_in[31] + NET la_data_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1179210 -1200 ) N ;
+ - la_data_in[32] + NET la_data_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1196690 -1200 ) N ;
+ - la_data_in[33] + NET la_data_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1214630 -1200 ) N ;
+ - la_data_in[34] + NET la_data_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1232110 -1200 ) N ;
+ - la_data_in[35] + NET la_data_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1250050 -1200 ) N ;
+ - la_data_in[36] + NET la_data_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1267530 -1200 ) N ;
+ - la_data_in[37] + NET la_data_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1285470 -1200 ) N ;
+ - la_data_in[38] + NET la_data_in[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1303410 -1200 ) N ;
+ - la_data_in[39] + NET la_data_in[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1320890 -1200 ) N ;
+ - la_data_in[3] + NET la_data_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 682410 -1200 ) N ;
+ - la_data_in[40] + NET la_data_in[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1338830 -1200 ) N ;
+ - la_data_in[41] + NET la_data_in[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1356310 -1200 ) N ;
+ - la_data_in[42] + NET la_data_in[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1374250 -1200 ) N ;
+ - la_data_in[43] + NET la_data_in[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1391730 -1200 ) N ;
+ - la_data_in[44] + NET la_data_in[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1409670 -1200 ) N ;
+ - la_data_in[45] + NET la_data_in[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1427150 -1200 ) N ;
+ - la_data_in[46] + NET la_data_in[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1445090 -1200 ) N ;
+ - la_data_in[47] + NET la_data_in[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1463030 -1200 ) N ;
+ - la_data_in[48] + NET la_data_in[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1480510 -1200 ) N ;
+ - la_data_in[49] + NET la_data_in[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1498450 -1200 ) N ;
+ - la_data_in[4] + NET la_data_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 700350 -1200 ) N ;
+ - la_data_in[50] + NET la_data_in[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1515930 -1200 ) N ;
+ - la_data_in[51] + NET la_data_in[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1533870 -1200 ) N ;
+ - la_data_in[52] + NET la_data_in[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1551350 -1200 ) N ;
+ - la_data_in[53] + NET la_data_in[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1569290 -1200 ) N ;
+ - la_data_in[54] + NET la_data_in[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1586770 -1200 ) N ;
+ - la_data_in[55] + NET la_data_in[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1604710 -1200 ) N ;
+ - la_data_in[56] + NET la_data_in[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1622190 -1200 ) N ;
+ - la_data_in[57] + NET la_data_in[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1640130 -1200 ) N ;
+ - la_data_in[58] + NET la_data_in[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1658070 -1200 ) N ;
+ - la_data_in[59] + NET la_data_in[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1675550 -1200 ) N ;
+ - la_data_in[5] + NET la_data_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 717830 -1200 ) N ;
+ - la_data_in[60] + NET la_data_in[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1693490 -1200 ) N ;
+ - la_data_in[61] + NET la_data_in[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1710970 -1200 ) N ;
+ - la_data_in[62] + NET la_data_in[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1728910 -1200 ) N ;
+ - la_data_in[63] + NET la_data_in[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1746390 -1200 ) N ;
+ - la_data_in[64] + NET la_data_in[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1764330 -1200 ) N ;
+ - la_data_in[65] + NET la_data_in[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1781810 -1200 ) N ;
+ - la_data_in[66] + NET la_data_in[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1799750 -1200 ) N ;
+ - la_data_in[67] + NET la_data_in[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1817690 -1200 ) N ;
+ - la_data_in[68] + NET la_data_in[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1835170 -1200 ) N ;
+ - la_data_in[69] + NET la_data_in[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1853110 -1200 ) N ;
+ - la_data_in[6] + NET la_data_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 735770 -1200 ) N ;
+ - la_data_in[70] + NET la_data_in[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1870590 -1200 ) N ;
+ - la_data_in[71] + NET la_data_in[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1888530 -1200 ) N ;
+ - la_data_in[72] + NET la_data_in[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1906010 -1200 ) N ;
+ - la_data_in[73] + NET la_data_in[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1923950 -1200 ) N ;
+ - la_data_in[74] + NET la_data_in[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1941430 -1200 ) N ;
+ - la_data_in[75] + NET la_data_in[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1959370 -1200 ) N ;
+ - la_data_in[76] + NET la_data_in[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1976850 -1200 ) N ;
+ - la_data_in[77] + NET la_data_in[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1994790 -1200 ) N ;
+ - la_data_in[78] + NET la_data_in[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2012730 -1200 ) N ;
+ - la_data_in[79] + NET la_data_in[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2030210 -1200 ) N ;
+ - la_data_in[7] + NET la_data_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 753250 -1200 ) N ;
+ - la_data_in[80] + NET la_data_in[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2048150 -1200 ) N ;
+ - la_data_in[81] + NET la_data_in[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2065630 -1200 ) N ;
+ - la_data_in[82] + NET la_data_in[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2083570 -1200 ) N ;
+ - la_data_in[83] + NET la_data_in[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2101050 -1200 ) N ;
+ - la_data_in[84] + NET la_data_in[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2118990 -1200 ) N ;
+ - la_data_in[85] + NET la_data_in[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2136470 -1200 ) N ;
+ - la_data_in[86] + NET la_data_in[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2154410 -1200 ) N ;
+ - la_data_in[87] + NET la_data_in[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2172350 -1200 ) N ;
+ - la_data_in[88] + NET la_data_in[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2189830 -1200 ) N ;
+ - la_data_in[89] + NET la_data_in[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2207770 -1200 ) N ;
+ - la_data_in[8] + NET la_data_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 771190 -1200 ) N ;
+ - la_data_in[90] + NET la_data_in[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2225250 -1200 ) N ;
+ - la_data_in[91] + NET la_data_in[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2243190 -1200 ) N ;
+ - la_data_in[92] + NET la_data_in[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2260670 -1200 ) N ;
+ - la_data_in[93] + NET la_data_in[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2278610 -1200 ) N ;
+ - la_data_in[94] + NET la_data_in[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2296090 -1200 ) N ;
+ - la_data_in[95] + NET la_data_in[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2314030 -1200 ) N ;
+ - la_data_in[96] + NET la_data_in[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2331510 -1200 ) N ;
+ - la_data_in[97] + NET la_data_in[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2349450 -1200 ) N ;
+ - la_data_in[98] + NET la_data_in[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2367390 -1200 ) N ;
+ - la_data_in[99] + NET la_data_in[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2384870 -1200 ) N ;
+ - la_data_in[9] + NET la_data_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 789130 -1200 ) N ;
+ - la_data_out[0] + NET la_data_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 635030 -1200 ) N ;
+ - la_data_out[100] + NET la_data_out[100] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2408790 -1200 ) N ;
+ - la_data_out[101] + NET la_data_out[101] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2426270 -1200 ) N ;
+ - la_data_out[102] + NET la_data_out[102] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2444210 -1200 ) N ;
+ - la_data_out[103] + NET la_data_out[103] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2461690 -1200 ) N ;
+ - la_data_out[104] + NET la_data_out[104] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2479630 -1200 ) N ;
+ - la_data_out[105] + NET la_data_out[105] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2497110 -1200 ) N ;
+ - la_data_out[106] + NET la_data_out[106] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2515050 -1200 ) N ;
+ - la_data_out[107] + NET la_data_out[107] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2532530 -1200 ) N ;
+ - la_data_out[108] + NET la_data_out[108] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2550470 -1200 ) N ;
+ - la_data_out[109] + NET la_data_out[109] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2567950 -1200 ) N ;
+ - la_data_out[10] + NET la_data_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 812590 -1200 ) N ;
+ - la_data_out[110] + NET la_data_out[110] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2585890 -1200 ) N ;
+ - la_data_out[111] + NET la_data_out[111] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2603830 -1200 ) N ;
+ - la_data_out[112] + NET la_data_out[112] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2621310 -1200 ) N ;
+ - la_data_out[113] + NET la_data_out[113] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2639250 -1200 ) N ;
+ - la_data_out[114] + NET la_data_out[114] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2656730 -1200 ) N ;
+ - la_data_out[115] + NET la_data_out[115] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2674670 -1200 ) N ;
+ - la_data_out[116] + NET la_data_out[116] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2692150 -1200 ) N ;
+ - la_data_out[117] + NET la_data_out[117] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2710090 -1200 ) N ;
+ - la_data_out[118] + NET la_data_out[118] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2727570 -1200 ) N ;
+ - la_data_out[119] + NET la_data_out[119] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2745510 -1200 ) N ;
+ - la_data_out[11] + NET la_data_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 830530 -1200 ) N ;
+ - la_data_out[120] + NET la_data_out[120] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2763450 -1200 ) N ;
+ - la_data_out[121] + NET la_data_out[121] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2780930 -1200 ) N ;
+ - la_data_out[122] + NET la_data_out[122] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2798870 -1200 ) N ;
+ - la_data_out[123] + NET la_data_out[123] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2816350 -1200 ) N ;
+ - la_data_out[124] + NET la_data_out[124] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2834290 -1200 ) N ;
+ - la_data_out[125] + NET la_data_out[125] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2851770 -1200 ) N ;
+ - la_data_out[126] + NET la_data_out[126] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2869710 -1200 ) N ;
+ - la_data_out[127] + NET la_data_out[127] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2887190 -1200 ) N ;
+ - la_data_out[12] + NET la_data_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 848010 -1200 ) N ;
+ - la_data_out[13] + NET la_data_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 865950 -1200 ) N ;
+ - la_data_out[14] + NET la_data_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 883430 -1200 ) N ;
+ - la_data_out[15] + NET la_data_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 901370 -1200 ) N ;
+ - la_data_out[16] + NET la_data_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 918850 -1200 ) N ;
+ - la_data_out[17] + NET la_data_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 936790 -1200 ) N ;
+ - la_data_out[18] + NET la_data_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 954270 -1200 ) N ;
+ - la_data_out[19] + NET la_data_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 972210 -1200 ) N ;
+ - la_data_out[1] + NET la_data_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 652970 -1200 ) N ;
+ - la_data_out[20] + NET la_data_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 989690 -1200 ) N ;
+ - la_data_out[21] + NET la_data_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1007630 -1200 ) N ;
+ - la_data_out[22] + NET la_data_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1025570 -1200 ) N ;
+ - la_data_out[23] + NET la_data_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1043050 -1200 ) N ;
+ - la_data_out[24] + NET la_data_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1060990 -1200 ) N ;
+ - la_data_out[25] + NET la_data_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1078470 -1200 ) N ;
+ - la_data_out[26] + NET la_data_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1096410 -1200 ) N ;
+ - la_data_out[27] + NET la_data_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1113890 -1200 ) N ;
+ - la_data_out[28] + NET la_data_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1131830 -1200 ) N ;
+ - la_data_out[29] + NET la_data_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1149310 -1200 ) N ;
+ - la_data_out[2] + NET la_data_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 670910 -1200 ) N ;
+ - la_data_out[30] + NET la_data_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1167250 -1200 ) N ;
+ - la_data_out[31] + NET la_data_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1185190 -1200 ) N ;
+ - la_data_out[32] + NET la_data_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1202670 -1200 ) N ;
+ - la_data_out[33] + NET la_data_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1220610 -1200 ) N ;
+ - la_data_out[34] + NET la_data_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1238090 -1200 ) N ;
+ - la_data_out[35] + NET la_data_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1256030 -1200 ) N ;
+ - la_data_out[36] + NET la_data_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1273510 -1200 ) N ;
+ - la_data_out[37] + NET la_data_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1291450 -1200 ) N ;
+ - la_data_out[38] + NET la_data_out[38] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1308930 -1200 ) N ;
+ - la_data_out[39] + NET la_data_out[39] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1326870 -1200 ) N ;
+ - la_data_out[3] + NET la_data_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 688390 -1200 ) N ;
+ - la_data_out[40] + NET la_data_out[40] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1344350 -1200 ) N ;
+ - la_data_out[41] + NET la_data_out[41] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1362290 -1200 ) N ;
+ - la_data_out[42] + NET la_data_out[42] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1380230 -1200 ) N ;
+ - la_data_out[43] + NET la_data_out[43] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1397710 -1200 ) N ;
+ - la_data_out[44] + NET la_data_out[44] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1415650 -1200 ) N ;
+ - la_data_out[45] + NET la_data_out[45] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1433130 -1200 ) N ;
+ - la_data_out[46] + NET la_data_out[46] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1451070 -1200 ) N ;
+ - la_data_out[47] + NET la_data_out[47] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1468550 -1200 ) N ;
+ - la_data_out[48] + NET la_data_out[48] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1486490 -1200 ) N ;
+ - la_data_out[49] + NET la_data_out[49] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1503970 -1200 ) N ;
+ - la_data_out[4] + NET la_data_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 706330 -1200 ) N ;
+ - la_data_out[50] + NET la_data_out[50] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1521910 -1200 ) N ;
+ - la_data_out[51] + NET la_data_out[51] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1539850 -1200 ) N ;
+ - la_data_out[52] + NET la_data_out[52] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1557330 -1200 ) N ;
+ - la_data_out[53] + NET la_data_out[53] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1575270 -1200 ) N ;
+ - la_data_out[54] + NET la_data_out[54] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1592750 -1200 ) N ;
+ - la_data_out[55] + NET la_data_out[55] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1610690 -1200 ) N ;
+ - la_data_out[56] + NET la_data_out[56] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1628170 -1200 ) N ;
+ - la_data_out[57] + NET la_data_out[57] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1646110 -1200 ) N ;
+ - la_data_out[58] + NET la_data_out[58] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1663590 -1200 ) N ;
+ - la_data_out[59] + NET la_data_out[59] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1681530 -1200 ) N ;
+ - la_data_out[5] + NET la_data_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 723810 -1200 ) N ;
+ - la_data_out[60] + NET la_data_out[60] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1699470 -1200 ) N ;
+ - la_data_out[61] + NET la_data_out[61] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1716950 -1200 ) N ;
+ - la_data_out[62] + NET la_data_out[62] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1734890 -1200 ) N ;
+ - la_data_out[63] + NET la_data_out[63] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1752370 -1200 ) N ;
+ - la_data_out[64] + NET la_data_out[64] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1770310 -1200 ) N ;
+ - la_data_out[65] + NET la_data_out[65] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1787790 -1200 ) N ;
+ - la_data_out[66] + NET la_data_out[66] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1805730 -1200 ) N ;
+ - la_data_out[67] + NET la_data_out[67] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1823210 -1200 ) N ;
+ - la_data_out[68] + NET la_data_out[68] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1841150 -1200 ) N ;
+ - la_data_out[69] + NET la_data_out[69] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1858630 -1200 ) N ;
+ - la_data_out[6] + NET la_data_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 741750 -1200 ) N ;
+ - la_data_out[70] + NET la_data_out[70] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1876570 -1200 ) N ;
+ - la_data_out[71] + NET la_data_out[71] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1894510 -1200 ) N ;
+ - la_data_out[72] + NET la_data_out[72] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1911990 -1200 ) N ;
+ - la_data_out[73] + NET la_data_out[73] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1929930 -1200 ) N ;
+ - la_data_out[74] + NET la_data_out[74] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1947410 -1200 ) N ;
+ - la_data_out[75] + NET la_data_out[75] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1965350 -1200 ) N ;
+ - la_data_out[76] + NET la_data_out[76] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1982830 -1200 ) N ;
+ - la_data_out[77] + NET la_data_out[77] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2000770 -1200 ) N ;
+ - la_data_out[78] + NET la_data_out[78] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2018250 -1200 ) N ;
+ - la_data_out[79] + NET la_data_out[79] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2036190 -1200 ) N ;
+ - la_data_out[7] + NET la_data_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 759230 -1200 ) N ;
+ - la_data_out[80] + NET la_data_out[80] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2054130 -1200 ) N ;
+ - la_data_out[81] + NET la_data_out[81] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2071610 -1200 ) N ;
+ - la_data_out[82] + NET la_data_out[82] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2089550 -1200 ) N ;
+ - la_data_out[83] + NET la_data_out[83] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2107030 -1200 ) N ;
+ - la_data_out[84] + NET la_data_out[84] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2124970 -1200 ) N ;
+ - la_data_out[85] + NET la_data_out[85] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2142450 -1200 ) N ;
+ - la_data_out[86] + NET la_data_out[86] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2160390 -1200 ) N ;
+ - la_data_out[87] + NET la_data_out[87] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2177870 -1200 ) N ;
+ - la_data_out[88] + NET la_data_out[88] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2195810 -1200 ) N ;
+ - la_data_out[89] + NET la_data_out[89] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2213290 -1200 ) N ;
+ - la_data_out[8] + NET la_data_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 777170 -1200 ) N ;
+ - la_data_out[90] + NET la_data_out[90] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2231230 -1200 ) N ;
+ - la_data_out[91] + NET la_data_out[91] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2249170 -1200 ) N ;
+ - la_data_out[92] + NET la_data_out[92] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2266650 -1200 ) N ;
+ - la_data_out[93] + NET la_data_out[93] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2284590 -1200 ) N ;
+ - la_data_out[94] + NET la_data_out[94] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2302070 -1200 ) N ;
+ - la_data_out[95] + NET la_data_out[95] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2320010 -1200 ) N ;
+ - la_data_out[96] + NET la_data_out[96] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2337490 -1200 ) N ;
+ - la_data_out[97] + NET la_data_out[97] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2355430 -1200 ) N ;
+ - la_data_out[98] + NET la_data_out[98] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2372910 -1200 ) N ;
+ - la_data_out[99] + NET la_data_out[99] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2390850 -1200 ) N ;
+ - la_data_out[9] + NET la_data_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 794650 -1200 ) N ;
+ - la_oenb[0] + NET la_oenb[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 641010 -1200 ) N ;
+ - la_oenb[100] + NET la_oenb[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2414310 -1200 ) N ;
+ - la_oenb[101] + NET la_oenb[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2432250 -1200 ) N ;
+ - la_oenb[102] + NET la_oenb[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2449730 -1200 ) N ;
+ - la_oenb[103] + NET la_oenb[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2467670 -1200 ) N ;
+ - la_oenb[104] + NET la_oenb[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2485610 -1200 ) N ;
+ - la_oenb[105] + NET la_oenb[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2503090 -1200 ) N ;
+ - la_oenb[106] + NET la_oenb[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2521030 -1200 ) N ;
+ - la_oenb[107] + NET la_oenb[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2538510 -1200 ) N ;
+ - la_oenb[108] + NET la_oenb[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2556450 -1200 ) N ;
+ - la_oenb[109] + NET la_oenb[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2573930 -1200 ) N ;
+ - la_oenb[10] + NET la_oenb[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 818570 -1200 ) N ;
+ - la_oenb[110] + NET la_oenb[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2591870 -1200 ) N ;
+ - la_oenb[111] + NET la_oenb[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2609350 -1200 ) N ;
+ - la_oenb[112] + NET la_oenb[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2627290 -1200 ) N ;
+ - la_oenb[113] + NET la_oenb[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2645230 -1200 ) N ;
+ - la_oenb[114] + NET la_oenb[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2662710 -1200 ) N ;
+ - la_oenb[115] + NET la_oenb[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2680650 -1200 ) N ;
+ - la_oenb[116] + NET la_oenb[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2698130 -1200 ) N ;
+ - la_oenb[117] + NET la_oenb[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2716070 -1200 ) N ;
+ - la_oenb[118] + NET la_oenb[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2733550 -1200 ) N ;
+ - la_oenb[119] + NET la_oenb[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2751490 -1200 ) N ;
+ - la_oenb[11] + NET la_oenb[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 836050 -1200 ) N ;
+ - la_oenb[120] + NET la_oenb[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2768970 -1200 ) N ;
+ - la_oenb[121] + NET la_oenb[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2786910 -1200 ) N ;
+ - la_oenb[122] + NET la_oenb[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2804390 -1200 ) N ;
+ - la_oenb[123] + NET la_oenb[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2822330 -1200 ) N ;
+ - la_oenb[124] + NET la_oenb[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2840270 -1200 ) N ;
+ - la_oenb[125] + NET la_oenb[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2857750 -1200 ) N ;
+ - la_oenb[126] + NET la_oenb[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2875690 -1200 ) N ;
+ - la_oenb[127] + NET la_oenb[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2893170 -1200 ) N ;
+ - la_oenb[12] + NET la_oenb[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 853990 -1200 ) N ;
+ - la_oenb[13] + NET la_oenb[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 871470 -1200 ) N ;
+ - la_oenb[14] + NET la_oenb[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 889410 -1200 ) N ;
+ - la_oenb[15] + NET la_oenb[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 907350 -1200 ) N ;
+ - la_oenb[16] + NET la_oenb[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 924830 -1200 ) N ;
+ - la_oenb[17] + NET la_oenb[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 942770 -1200 ) N ;
+ - la_oenb[18] + NET la_oenb[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 960250 -1200 ) N ;
+ - la_oenb[19] + NET la_oenb[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 978190 -1200 ) N ;
+ - la_oenb[1] + NET la_oenb[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 658950 -1200 ) N ;
+ - la_oenb[20] + NET la_oenb[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 995670 -1200 ) N ;
+ - la_oenb[21] + NET la_oenb[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1013610 -1200 ) N ;
+ - la_oenb[22] + NET la_oenb[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1031090 -1200 ) N ;
+ - la_oenb[23] + NET la_oenb[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1049030 -1200 ) N ;
+ - la_oenb[24] + NET la_oenb[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1066970 -1200 ) N ;
+ - la_oenb[25] + NET la_oenb[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1084450 -1200 ) N ;
+ - la_oenb[26] + NET la_oenb[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1102390 -1200 ) N ;
+ - la_oenb[27] + NET la_oenb[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1119870 -1200 ) N ;
+ - la_oenb[28] + NET la_oenb[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1137810 -1200 ) N ;
+ - la_oenb[29] + NET la_oenb[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1155290 -1200 ) N ;
+ - la_oenb[2] + NET la_oenb[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 676430 -1200 ) N ;
+ - la_oenb[30] + NET la_oenb[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1173230 -1200 ) N ;
+ - la_oenb[31] + NET la_oenb[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1190710 -1200 ) N ;
+ - la_oenb[32] + NET la_oenb[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1208650 -1200 ) N ;
+ - la_oenb[33] + NET la_oenb[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1226130 -1200 ) N ;
+ - la_oenb[34] + NET la_oenb[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1244070 -1200 ) N ;
+ - la_oenb[35] + NET la_oenb[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1262010 -1200 ) N ;
+ - la_oenb[36] + NET la_oenb[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1279490 -1200 ) N ;
+ - la_oenb[37] + NET la_oenb[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1297430 -1200 ) N ;
+ - la_oenb[38] + NET la_oenb[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1314910 -1200 ) N ;
+ - la_oenb[39] + NET la_oenb[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1332850 -1200 ) N ;
+ - la_oenb[3] + NET la_oenb[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 694370 -1200 ) N ;
+ - la_oenb[40] + NET la_oenb[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1350330 -1200 ) N ;
+ - la_oenb[41] + NET la_oenb[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1368270 -1200 ) N ;
+ - la_oenb[42] + NET la_oenb[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1385750 -1200 ) N ;
+ - la_oenb[43] + NET la_oenb[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1403690 -1200 ) N ;
+ - la_oenb[44] + NET la_oenb[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1421630 -1200 ) N ;
+ - la_oenb[45] + NET la_oenb[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1439110 -1200 ) N ;
+ - la_oenb[46] + NET la_oenb[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1457050 -1200 ) N ;
+ - la_oenb[47] + NET la_oenb[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1474530 -1200 ) N ;
+ - la_oenb[48] + NET la_oenb[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1492470 -1200 ) N ;
+ - la_oenb[49] + NET la_oenb[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1509950 -1200 ) N ;
+ - la_oenb[4] + NET la_oenb[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 712310 -1200 ) N ;
+ - la_oenb[50] + NET la_oenb[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1527890 -1200 ) N ;
+ - la_oenb[51] + NET la_oenb[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1545370 -1200 ) N ;
+ - la_oenb[52] + NET la_oenb[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1563310 -1200 ) N ;
+ - la_oenb[53] + NET la_oenb[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1581250 -1200 ) N ;
+ - la_oenb[54] + NET la_oenb[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1598730 -1200 ) N ;
+ - la_oenb[55] + NET la_oenb[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1616670 -1200 ) N ;
+ - la_oenb[56] + NET la_oenb[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1634150 -1200 ) N ;
+ - la_oenb[57] + NET la_oenb[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1652090 -1200 ) N ;
+ - la_oenb[58] + NET la_oenb[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1669570 -1200 ) N ;
+ - la_oenb[59] + NET la_oenb[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1687510 -1200 ) N ;
+ - la_oenb[5] + NET la_oenb[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 729790 -1200 ) N ;
+ - la_oenb[60] + NET la_oenb[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1704990 -1200 ) N ;
+ - la_oenb[61] + NET la_oenb[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1722930 -1200 ) N ;
+ - la_oenb[62] + NET la_oenb[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1740410 -1200 ) N ;
+ - la_oenb[63] + NET la_oenb[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1758350 -1200 ) N ;
+ - la_oenb[64] + NET la_oenb[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1776290 -1200 ) N ;
+ - la_oenb[65] + NET la_oenb[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1793770 -1200 ) N ;
+ - la_oenb[66] + NET la_oenb[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1811710 -1200 ) N ;
+ - la_oenb[67] + NET la_oenb[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1829190 -1200 ) N ;
+ - la_oenb[68] + NET la_oenb[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1847130 -1200 ) N ;
+ - la_oenb[69] + NET la_oenb[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1864610 -1200 ) N ;
+ - la_oenb[6] + NET la_oenb[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 747730 -1200 ) N ;
+ - la_oenb[70] + NET la_oenb[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1882550 -1200 ) N ;
+ - la_oenb[71] + NET la_oenb[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1900030 -1200 ) N ;
+ - la_oenb[72] + NET la_oenb[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1917970 -1200 ) N ;
+ - la_oenb[73] + NET la_oenb[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1935910 -1200 ) N ;
+ - la_oenb[74] + NET la_oenb[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1953390 -1200 ) N ;
+ - la_oenb[75] + NET la_oenb[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1971330 -1200 ) N ;
+ - la_oenb[76] + NET la_oenb[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1988810 -1200 ) N ;
+ - la_oenb[77] + NET la_oenb[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2006750 -1200 ) N ;
+ - la_oenb[78] + NET la_oenb[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2024230 -1200 ) N ;
+ - la_oenb[79] + NET la_oenb[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2042170 -1200 ) N ;
+ - la_oenb[7] + NET la_oenb[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 765210 -1200 ) N ;
+ - la_oenb[80] + NET la_oenb[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2059650 -1200 ) N ;
+ - la_oenb[81] + NET la_oenb[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2077590 -1200 ) N ;
+ - la_oenb[82] + NET la_oenb[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2095070 -1200 ) N ;
+ - la_oenb[83] + NET la_oenb[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2113010 -1200 ) N ;
+ - la_oenb[84] + NET la_oenb[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2130950 -1200 ) N ;
+ - la_oenb[85] + NET la_oenb[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2148430 -1200 ) N ;
+ - la_oenb[86] + NET la_oenb[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2166370 -1200 ) N ;
+ - la_oenb[87] + NET la_oenb[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2183850 -1200 ) N ;
+ - la_oenb[88] + NET la_oenb[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2201790 -1200 ) N ;
+ - la_oenb[89] + NET la_oenb[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2219270 -1200 ) N ;
+ - la_oenb[8] + NET la_oenb[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 783150 -1200 ) N ;
+ - la_oenb[90] + NET la_oenb[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2237210 -1200 ) N ;
+ - la_oenb[91] + NET la_oenb[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2254690 -1200 ) N ;
+ - la_oenb[92] + NET la_oenb[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2272630 -1200 ) N ;
+ - la_oenb[93] + NET la_oenb[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2290570 -1200 ) N ;
+ - la_oenb[94] + NET la_oenb[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2308050 -1200 ) N ;
+ - la_oenb[95] + NET la_oenb[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2325990 -1200 ) N ;
+ - la_oenb[96] + NET la_oenb[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2343470 -1200 ) N ;
+ - la_oenb[97] + NET la_oenb[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2361410 -1200 ) N ;
+ - la_oenb[98] + NET la_oenb[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2378890 -1200 ) N ;
+ - la_oenb[99] + NET la_oenb[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2396830 -1200 ) N ;
+ - la_oenb[9] + NET la_oenb[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 800630 -1200 ) N ;
+ - user_clock2 + NET user_clock2 + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2899150 -1200 ) N ;
+ - user_irq[0] + NET user_irq[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2905130 -1200 ) N ;
+ - user_irq[1] + NET user_irq[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2911110 -1200 ) N ;
+ - user_irq[2] + NET user_irq[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2917090 -1200 ) N ;
+ - vccd1 + NET vccd1 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1769310 ) ( 1550 1769310 )
+ + LAYER met4 ( -181550 -1769310 ) ( -178450 1769310 )
+ + LAYER met4 ( -361550 -1769310 ) ( -358450 1769310 )
+ + LAYER met4 ( -541550 -1769310 ) ( -538450 1769310 )
+ + LAYER met4 ( -721550 -1769310 ) ( -718450 1769310 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1769310 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1769310 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1769310 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1769310 )
+ + LAYER met4 ( -1621550 540160 ) ( -1618450 1769310 )
+ + LAYER met4 ( -1801550 -1769310 ) ( -1798450 1769310 )
+ + LAYER met4 ( -1981550 -1769310 ) ( -1978450 1769310 )
+ + LAYER met4 ( -2161550 -1769310 ) ( -2158450 1769310 )
+ + LAYER met4 ( -2341550 -1769310 ) ( -2338450 1769310 )
+ + LAYER met4 ( -2521550 -1769310 ) ( -2518450 1769310 )
+ + LAYER met4 ( -2701550 -1769310 ) ( -2698450 1769310 )
+ + LAYER met4 ( -2881550 -1769310 ) ( -2878450 1769310 )
+ + LAYER met4 ( 36030 -1764510 ) ( 39130 1764510 )
+ + LAYER met4 ( -2900550 -1764510 ) ( -2897450 1764510 )
+ + LAYER met4 ( -901550 -1769310 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1769310 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1769310 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1769310 ) ( -1438450 -79840 )
+ + LAYER met4 ( -1621550 -1769310 ) ( -1618450 -79840 )
+ + LAYER met5 ( -2900550 1761410 ) ( 39130 1764510 )
+ + LAYER met5 ( -2905350 1674490 ) ( 43930 1677590 )
+ + LAYER met5 ( -2905350 1494490 ) ( 43930 1497590 )
+ + LAYER met5 ( -2905350 1314490 ) ( 43930 1317590 )
+ + LAYER met5 ( -2905350 1134490 ) ( 43930 1137590 )
+ + LAYER met5 ( -2905350 954490 ) ( 43930 957590 )
+ + LAYER met5 ( -2905350 774490 ) ( 43930 777590 )
+ + LAYER met5 ( -2905350 594490 ) ( 43930 597590 )
+ + LAYER met5 ( -2905350 414490 ) ( 43930 417590 )
+ + LAYER met5 ( -2905350 234490 ) ( 43930 237590 )
+ + LAYER met5 ( -2905350 54490 ) ( 43930 57590 )
+ + LAYER met5 ( -2905350 -125510 ) ( 43930 -122410 )
+ + LAYER met5 ( -2905350 -305510 ) ( 43930 -302410 )
+ + LAYER met5 ( -2905350 -485510 ) ( 43930 -482410 )
+ + LAYER met5 ( -2905350 -665510 ) ( 43930 -662410 )
+ + LAYER met5 ( -2905350 -845510 ) ( 43930 -842410 )
+ + LAYER met5 ( -2905350 -1025510 ) ( 43930 -1022410 )
+ + LAYER met5 ( -2905350 -1205510 ) ( 43930 -1202410 )
+ + LAYER met5 ( -2905350 -1385510 ) ( 43930 -1382410 )
+ + LAYER met5 ( -2905350 -1565510 ) ( 43930 -1562410 )
+ + LAYER met5 ( -2905350 -1745510 ) ( 43930 -1742410 )
+ + LAYER met5 ( -2900550 -1764510 ) ( 39130 -1761410 )
+ + FIXED ( 2890520 1759840 ) N ;
+ - vccd2 + NET vccd2 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1778910 ) ( 1550 1778910 )
+ + LAYER met4 ( -181550 -1778910 ) ( -178450 1778910 )
+ + LAYER met4 ( -361550 -1778910 ) ( -358450 1778910 )
+ + LAYER met4 ( -541550 -1778910 ) ( -538450 1778910 )
+ + LAYER met4 ( -721550 -1778910 ) ( -718450 1778910 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1778910 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1778910 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1778910 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1778910 )
+ + LAYER met4 ( -1621550 540160 ) ( -1618450 1778910 )
+ + LAYER met4 ( -1801550 -1778910 ) ( -1798450 1778910 )
+ + LAYER met4 ( -1981550 -1778910 ) ( -1978450 1778910 )
+ + LAYER met4 ( -2161550 -1778910 ) ( -2158450 1778910 )
+ + LAYER met4 ( -2341550 -1778910 ) ( -2338450 1778910 )
+ + LAYER met4 ( -2521550 -1778910 ) ( -2518450 1778910 )
+ + LAYER met4 ( -2701550 -1778910 ) ( -2698450 1778910 )
+ + LAYER met4 ( -2881550 -1778910 ) ( -2878450 1778910 )
+ + LAYER met4 ( 27030 -1774110 ) ( 30130 1774110 )
+ + LAYER met4 ( -2928750 -1774110 ) ( -2925650 1774110 )
+ + LAYER met4 ( -901550 -1778910 ) ( -898450 -79840 )
+ + LAYER met4 ( -1081550 -1778910 ) ( -1078450 -79840 )
+ + LAYER met4 ( -1261550 -1778910 ) ( -1258450 -79840 )
+ + LAYER met4 ( -1441550 -1778910 ) ( -1438450 -79840 )
+ + LAYER met4 ( -1621550 -1778910 ) ( -1618450 -79840 )
+ + LAYER met5 ( -2928750 1771010 ) ( 30130 1774110 )
+ + LAYER met5 ( -2933550 1693090 ) ( 34930 1696190 )
+ + LAYER met5 ( -2933550 1513090 ) ( 34930 1516190 )
+ + LAYER met5 ( -2933550 1333090 ) ( 34930 1336190 )
+ + LAYER met5 ( -2933550 1153090 ) ( 34930 1156190 )
+ + LAYER met5 ( -2933550 973090 ) ( 34930 976190 )
+ + LAYER met5 ( -2933550 793090 ) ( 34930 796190 )
+ + LAYER met5 ( -2933550 613090 ) ( 34930 616190 )
+ + LAYER met5 ( -2933550 433090 ) ( 34930 436190 )
+ + LAYER met5 ( -2933550 253090 ) ( 34930 256190 )
+ + LAYER met5 ( -2933550 73090 ) ( 34930 76190 )
+ + LAYER met5 ( -2933550 -106910 ) ( 34930 -103810 )
+ + LAYER met5 ( -2933550 -286910 ) ( 34930 -283810 )
+ + LAYER met5 ( -2933550 -466910 ) ( 34930 -463810 )
+ + LAYER met5 ( -2933550 -646910 ) ( 34930 -643810 )
+ + LAYER met5 ( -2933550 -826910 ) ( 34930 -823810 )
+ + LAYER met5 ( -2933550 -1006910 ) ( 34930 -1003810 )
+ + LAYER met5 ( -2933550 -1186910 ) ( 34930 -1183810 )
+ + LAYER met5 ( -2933550 -1366910 ) ( 34930 -1363810 )
+ + LAYER met5 ( -2933550 -1546910 ) ( 34930 -1543810 )
+ + LAYER met5 ( -2933550 -1726910 ) ( 34930 -1723810 )
+ + LAYER met5 ( -2928750 -1774110 ) ( 30130 -1771010 )
+ + FIXED ( 2909120 1759840 ) N ;
+ - vdda1 + NET vdda1 + SPECIAL + DIRECTION INPUT + USE POWER
+ + PORT
+ + LAYER met4 ( -1550 -1788510 ) ( 1550 1788510 )
+ + LAYER met4 ( -181550 -1788510 ) ( -178450 1788510 )
+ + LAYER met4 ( -361550 -1788510 ) ( -358450 1788510 )
+ + LAYER met4 ( -541550 -1788510 ) ( -538450 1788510 )
+ + LAYER met4 ( -721550 540160 ) ( -718450 1788510 )
+ + LAYER met4 ( -901550 540160 ) ( -898450 1788510 )
+ + LAYER met4 ( -1081550 540160 ) ( -1078450 1788510 )
+ + LAYER met4 ( -1261550 540160 ) ( -1258450 1788510 )
+ + LAYER met4 ( -1441550 540160 ) ( -1438450 1788510 )
+ + LAYER met4 ( -1621550 -1788510 ) ( -1618450 1788510 )
+ + LAYER met4 ( -1801550 -1788510 ) ( -1798450 1788510 )
+ + LAYER met4 ( -1981550 -1788510 ) ( -1978450 1788510 )
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+ + PORT
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+ + PORT
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+ + PORT
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+ + PORT
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+ + PORT
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+ + PORT
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+ + PORT
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+ + PORT
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+ + PLACED ( 274850 -1200 ) N ;
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+ + PORT
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+ + PORT
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+ + PORT
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+ + PORT
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+ + PORT
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+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 398590 -1200 ) N ;
+ - wbs_adr_i[1] + NET wbs_adr_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 61870 -1200 ) N ;
+ - wbs_adr_i[20] + NET wbs_adr_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 416530 -1200 ) N ;
+ - wbs_adr_i[21] + NET wbs_adr_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 434470 -1200 ) N ;
+ - wbs_adr_i[22] + NET wbs_adr_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 451950 -1200 ) N ;
+ - wbs_adr_i[23] + NET wbs_adr_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 469890 -1200 ) N ;
+ - wbs_adr_i[24] + NET wbs_adr_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 487370 -1200 ) N ;
+ - wbs_adr_i[25] + NET wbs_adr_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 505310 -1200 ) N ;
+ - wbs_adr_i[26] + NET wbs_adr_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 522790 -1200 ) N ;
+ - wbs_adr_i[27] + NET wbs_adr_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 540730 -1200 ) N ;
+ - wbs_adr_i[28] + NET wbs_adr_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 558210 -1200 ) N ;
+ - wbs_adr_i[29] + NET wbs_adr_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 576150 -1200 ) N ;
+ - wbs_adr_i[2] + NET wbs_adr_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 85330 -1200 ) N ;
+ - wbs_adr_i[30] + NET wbs_adr_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 594090 -1200 ) N ;
+ - wbs_adr_i[31] + NET wbs_adr_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 611570 -1200 ) N ;
+ - wbs_adr_i[3] + NET wbs_adr_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 109250 -1200 ) N ;
+ - wbs_adr_i[4] + NET wbs_adr_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 132710 -1200 ) N ;
+ - wbs_adr_i[5] + NET wbs_adr_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 150650 -1200 ) N ;
+ - wbs_adr_i[6] + NET wbs_adr_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 168130 -1200 ) N ;
+ - wbs_adr_i[7] + NET wbs_adr_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 186070 -1200 ) N ;
+ - wbs_adr_i[8] + NET wbs_adr_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 203550 -1200 ) N ;
+ - wbs_adr_i[9] + NET wbs_adr_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 221490 -1200 ) N ;
+ - wbs_cyc_i + NET wbs_cyc_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 20470 -1200 ) N ;
+ - wbs_dat_i[0] + NET wbs_dat_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 43930 -1200 ) N ;
+ - wbs_dat_i[10] + NET wbs_dat_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 244950 -1200 ) N ;
+ - wbs_dat_i[11] + NET wbs_dat_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 262890 -1200 ) N ;
+ - wbs_dat_i[12] + NET wbs_dat_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 280370 -1200 ) N ;
+ - wbs_dat_i[13] + NET wbs_dat_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 298310 -1200 ) N ;
+ - wbs_dat_i[14] + NET wbs_dat_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 316250 -1200 ) N ;
+ - wbs_dat_i[15] + NET wbs_dat_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 333730 -1200 ) N ;
+ - wbs_dat_i[16] + NET wbs_dat_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 351670 -1200 ) N ;
+ - wbs_dat_i[17] + NET wbs_dat_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 369150 -1200 ) N ;
+ - wbs_dat_i[18] + NET wbs_dat_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 387090 -1200 ) N ;
+ - wbs_dat_i[19] + NET wbs_dat_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 404570 -1200 ) N ;
+ - wbs_dat_i[1] + NET wbs_dat_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 67850 -1200 ) N ;
+ - wbs_dat_i[20] + NET wbs_dat_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 422510 -1200 ) N ;
+ - wbs_dat_i[21] + NET wbs_dat_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 439990 -1200 ) N ;
+ - wbs_dat_i[22] + NET wbs_dat_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 457930 -1200 ) N ;
+ - wbs_dat_i[23] + NET wbs_dat_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 475870 -1200 ) N ;
+ - wbs_dat_i[24] + NET wbs_dat_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 493350 -1200 ) N ;
+ - wbs_dat_i[25] + NET wbs_dat_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 511290 -1200 ) N ;
+ - wbs_dat_i[26] + NET wbs_dat_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 528770 -1200 ) N ;
+ - wbs_dat_i[27] + NET wbs_dat_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 546710 -1200 ) N ;
+ - wbs_dat_i[28] + NET wbs_dat_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 564190 -1200 ) N ;
+ - wbs_dat_i[29] + NET wbs_dat_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 582130 -1200 ) N ;
+ - wbs_dat_i[2] + NET wbs_dat_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 91310 -1200 ) N ;
+ - wbs_dat_i[30] + NET wbs_dat_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 599610 -1200 ) N ;
+ - wbs_dat_i[31] + NET wbs_dat_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 617550 -1200 ) N ;
+ - wbs_dat_i[3] + NET wbs_dat_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 115230 -1200 ) N ;
+ - wbs_dat_i[4] + NET wbs_dat_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 138690 -1200 ) N ;
+ - wbs_dat_i[5] + NET wbs_dat_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 156630 -1200 ) N ;
+ - wbs_dat_i[6] + NET wbs_dat_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 174110 -1200 ) N ;
+ - wbs_dat_i[7] + NET wbs_dat_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 192050 -1200 ) N ;
+ - wbs_dat_i[8] + NET wbs_dat_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 209530 -1200 ) N ;
+ - wbs_dat_i[9] + NET wbs_dat_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 227470 -1200 ) N ;
+ - wbs_dat_o[0] + NET wbs_dat_o[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 49910 -1200 ) N ;
+ - wbs_dat_o[10] + NET wbs_dat_o[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 250930 -1200 ) N ;
+ - wbs_dat_o[11] + NET wbs_dat_o[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 268870 -1200 ) N ;
+ - wbs_dat_o[12] + NET wbs_dat_o[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 286350 -1200 ) N ;
+ - wbs_dat_o[13] + NET wbs_dat_o[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 304290 -1200 ) N ;
+ - wbs_dat_o[14] + NET wbs_dat_o[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 321770 -1200 ) N ;
+ - wbs_dat_o[15] + NET wbs_dat_o[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 339710 -1200 ) N ;
+ - wbs_dat_o[16] + NET wbs_dat_o[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 357650 -1200 ) N ;
+ - wbs_dat_o[17] + NET wbs_dat_o[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 375130 -1200 ) N ;
+ - wbs_dat_o[18] + NET wbs_dat_o[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 393070 -1200 ) N ;
+ - wbs_dat_o[19] + NET wbs_dat_o[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 410550 -1200 ) N ;
+ - wbs_dat_o[1] + NET wbs_dat_o[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 73830 -1200 ) N ;
+ - wbs_dat_o[20] + NET wbs_dat_o[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 428490 -1200 ) N ;
+ - wbs_dat_o[21] + NET wbs_dat_o[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 445970 -1200 ) N ;
+ - wbs_dat_o[22] + NET wbs_dat_o[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 463910 -1200 ) N ;
+ - wbs_dat_o[23] + NET wbs_dat_o[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 481390 -1200 ) N ;
+ - wbs_dat_o[24] + NET wbs_dat_o[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 499330 -1200 ) N ;
+ - wbs_dat_o[25] + NET wbs_dat_o[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 516810 -1200 ) N ;
+ - wbs_dat_o[26] + NET wbs_dat_o[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 534750 -1200 ) N ;
+ - wbs_dat_o[27] + NET wbs_dat_o[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 552690 -1200 ) N ;
+ - wbs_dat_o[28] + NET wbs_dat_o[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 570170 -1200 ) N ;
+ - wbs_dat_o[29] + NET wbs_dat_o[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 588110 -1200 ) N ;
+ - wbs_dat_o[2] + NET wbs_dat_o[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 97290 -1200 ) N ;
+ - wbs_dat_o[30] + NET wbs_dat_o[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 605590 -1200 ) N ;
+ - wbs_dat_o[31] + NET wbs_dat_o[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 623530 -1200 ) N ;
+ - wbs_dat_o[3] + NET wbs_dat_o[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 121210 -1200 ) N ;
+ - wbs_dat_o[4] + NET wbs_dat_o[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 144670 -1200 ) N ;
+ - wbs_dat_o[5] + NET wbs_dat_o[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 162150 -1200 ) N ;
+ - wbs_dat_o[6] + NET wbs_dat_o[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 180090 -1200 ) N ;
+ - wbs_dat_o[7] + NET wbs_dat_o[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 198030 -1200 ) N ;
+ - wbs_dat_o[8] + NET wbs_dat_o[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 215510 -1200 ) N ;
+ - wbs_dat_o[9] + NET wbs_dat_o[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 233450 -1200 ) N ;
+ - wbs_sel_i[0] + NET wbs_sel_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 55890 -1200 ) N ;
+ - wbs_sel_i[1] + NET wbs_sel_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 79810 -1200 ) N ;
+ - wbs_sel_i[2] + NET wbs_sel_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 103270 -1200 ) N ;
+ - wbs_sel_i[3] + NET wbs_sel_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 126730 -1200 ) N ;
+ - wbs_stb_i + NET wbs_stb_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 26450 -1200 ) N ;
+ - wbs_we_i + NET wbs_we_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 32430 -1200 ) N ;
+END PINS
+SPECIALNETS 8 ;
+ - vccd1 ( PIN vccd1 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 1964840 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1964840 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1964840 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3435880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1810520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 555880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 375880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 195880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1630520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 195880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 550520 195880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -8480 195880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 15880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2530520 15880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1090520 15880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -8480 15880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 -3120 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2530520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 -3120 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -10030 3522800 ) ( 2929650 3522800 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3435880 ) ( 2934450 3435880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3255880 ) ( 2934450 3255880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3075880 ) ( 2934450 3075880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2895880 ) ( 2934450 2895880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2715880 ) ( 2934450 2715880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2535880 ) ( 2934450 2535880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2355880 ) ( 2934450 2355880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2175880 ) ( 2934450 2175880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1995880 ) ( 2934450 1995880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1815880 ) ( 2934450 1815880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1635880 ) ( 2934450 1635880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1455880 ) ( 2934450 1455880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1275880 ) ( 2934450 1275880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1095880 ) ( 2934450 1095880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 915880 ) ( 2934450 915880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 735880 ) ( 2934450 735880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 555880 ) ( 2934450 555880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 375880 ) ( 2934450 375880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 195880 ) ( 2934450 195880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 15880 ) ( 2934450 15880 )
+ NEW met5 3100 + SHAPE STRIPE ( -10030 -3120 ) ( 2929650 -3120 )
+ NEW met4 3100 + SHAPE STRIPE ( 2890520 -9470 ) ( 2890520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2710520 -9470 ) ( 2710520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2530520 -9470 ) ( 2530520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2350520 -9470 ) ( 2350520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2170520 -9470 ) ( 2170520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1990520 2300000 ) ( 1990520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1810520 2300000 ) ( 1810520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1630520 2300000 ) ( 1630520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1450520 2300000 ) ( 1450520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1270520 2300000 ) ( 1270520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1090520 -9470 ) ( 1090520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 910520 -9470 ) ( 910520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 730520 -9470 ) ( 730520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 550520 -9470 ) ( 550520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 370520 -9470 ) ( 370520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 190520 -9470 ) ( 190520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 10520 -9470 ) ( 10520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2928100 -4670 ) ( 2928100 3524350 )
+ NEW met4 3100 + SHAPE STRIPE ( -8480 -4670 ) ( -8480 3524350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1990520 -9470 ) ( 1990520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1810520 -9470 ) ( 1810520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1630520 -9470 ) ( 1630520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1450520 -9470 ) ( 1450520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1270520 -9470 ) ( 1270520 1680000 ) ;
+ - vccd2 ( PIN vccd2 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 2937700 3532400 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2729120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 3454480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2729120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3454480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1469120 3454480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 929120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3454480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -18080 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 3274480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2729120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 3274480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 3094480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2914480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2734480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2554480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2374480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2194480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 2014480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1834480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1654480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1474480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1294480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 1114480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 934480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 754480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 574480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 34480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2909120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 -12720 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 -12720 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -19630 3532400 ) ( 2939250 3532400 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3454480 ) ( 2944050 3454480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3274480 ) ( 2944050 3274480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3094480 ) ( 2944050 3094480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2914480 ) ( 2944050 2914480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2734480 ) ( 2944050 2734480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2554480 ) ( 2944050 2554480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2374480 ) ( 2944050 2374480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2194480 ) ( 2944050 2194480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2014480 ) ( 2944050 2014480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1834480 ) ( 2944050 1834480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1654480 ) ( 2944050 1654480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1474480 ) ( 2944050 1474480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1294480 ) ( 2944050 1294480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1114480 ) ( 2944050 1114480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 934480 ) ( 2944050 934480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 754480 ) ( 2944050 754480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 574480 ) ( 2944050 574480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 394480 ) ( 2944050 394480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 214480 ) ( 2944050 214480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 34480 ) ( 2944050 34480 )
+ NEW met5 3100 + SHAPE STRIPE ( -19630 -12720 ) ( 2939250 -12720 )
+ NEW met4 3100 + SHAPE STRIPE ( 2909120 -19070 ) ( 2909120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2729120 -19070 ) ( 2729120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2549120 -19070 ) ( 2549120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2369120 -19070 ) ( 2369120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2189120 -19070 ) ( 2189120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2009120 2300000 ) ( 2009120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1829120 2300000 ) ( 1829120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1649120 2300000 ) ( 1649120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1469120 2300000 ) ( 1469120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1289120 2300000 ) ( 1289120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1109120 -19070 ) ( 1109120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 929120 -19070 ) ( 929120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 749120 -19070 ) ( 749120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 569120 -19070 ) ( 569120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 389120 -19070 ) ( 389120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 209120 -19070 ) ( 209120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 29120 -19070 ) ( 29120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2937700 -14270 ) ( 2937700 3533950 )
+ NEW met4 3100 + SHAPE STRIPE ( -18080 -14270 ) ( -18080 3533950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2009120 -19070 ) ( 2009120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1829120 -19070 ) ( 1829120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1649120 -19070 ) ( 1649120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1469120 -19070 ) ( 1469120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1289120 -19070 ) ( 1289120 1680000 ) ;
+ - vdda1 ( PIN vdda1 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 2947300 3542000 ) via4_3100x3100
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+ NEW met5 3100 + SHAPE STRIPE ( -34030 1673080 ) ( 2953650 1673080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1493080 ) ( 2953650 1493080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1313080 ) ( 2953650 1313080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1133080 ) ( 2953650 1133080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 953080 ) ( 2953650 953080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 773080 ) ( 2953650 773080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 593080 ) ( 2953650 593080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 413080 ) ( 2953650 413080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 233080 ) ( 2953650 233080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 53080 ) ( 2953650 53080 )
+ NEW met5 3100 + SHAPE STRIPE ( -29230 -22320 ) ( 2948850 -22320 )
+ NEW met4 3100 + SHAPE STRIPE ( 2747720 -28670 ) ( 2747720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2567720 -28670 ) ( 2567720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2387720 -28670 ) ( 2387720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2207720 -28670 ) ( 2207720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2027720 2300000 ) ( 2027720 3548350 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1667720 2300000 ) ( 1667720 3548350 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1307720 2300000 ) ( 1307720 3548350 )
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+ NEW met4 3100 + SHAPE STRIPE ( 767720 -28670 ) ( 767720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 587720 -28670 ) ( 587720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 407720 -28670 ) ( 407720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 227720 -28670 ) ( 227720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 47720 -28670 ) ( 47720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2947300 -23870 ) ( 2947300 3543550 )
+ NEW met4 3100 + SHAPE STRIPE ( -27680 -23870 ) ( -27680 3543550 )
+ NEW met4 3100 + SHAPE STRIPE ( 2027720 -28670 ) ( 2027720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1847720 -28670 ) ( 1847720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1667720 -28670 ) ( 1667720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1487720 -28670 ) ( 1487720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1307720 -28670 ) ( 1307720 1680000 ) ;
+ - vdda2 ( PIN vdda2 ) + USE POWER
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+ NEW met4 0 + SHAPE STRIPE ( 966320 -31920 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -37280 -31920 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -38830 3551600 ) ( 2958450 3551600 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3491680 ) ( 2963250 3491680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3311680 ) ( 2963250 3311680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 3131680 ) ( 2963250 3131680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2951680 ) ( 2963250 2951680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2771680 ) ( 2963250 2771680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2591680 ) ( 2963250 2591680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2411680 ) ( 2963250 2411680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2231680 ) ( 2963250 2231680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2051680 ) ( 2963250 2051680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1871680 ) ( 2963250 1871680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1691680 ) ( 2963250 1691680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1511680 ) ( 2963250 1511680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1331680 ) ( 2963250 1331680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1151680 ) ( 2963250 1151680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 971680 ) ( 2963250 971680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 791680 ) ( 2963250 791680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 611680 ) ( 2963250 611680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 431680 ) ( 2963250 431680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 251680 ) ( 2963250 251680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 71680 ) ( 2963250 71680 )
+ NEW met5 3100 + SHAPE STRIPE ( -38830 -31920 ) ( 2958450 -31920 )
+ NEW met4 3100 + SHAPE STRIPE ( 2766320 -38270 ) ( 2766320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2586320 -38270 ) ( 2586320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2406320 -38270 ) ( 2406320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2226320 -38270 ) ( 2226320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2046320 2300000 ) ( 2046320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1866320 2300000 ) ( 1866320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1686320 2300000 ) ( 1686320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1506320 2300000 ) ( 1506320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1326320 2300000 ) ( 1326320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1146320 -38270 ) ( 1146320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 966320 -38270 ) ( 966320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 786320 -38270 ) ( 786320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 606320 -38270 ) ( 606320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 426320 -38270 ) ( 426320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 246320 -38270 ) ( 246320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 66320 -38270 ) ( 66320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2956900 -33470 ) ( 2956900 3553150 )
+ NEW met4 3100 + SHAPE STRIPE ( -37280 -33470 ) ( -37280 3553150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2046320 -38270 ) ( 2046320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1866320 -38270 ) ( 1866320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1686320 -38270 ) ( 1686320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1506320 -38270 ) ( 1506320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1326320 -38270 ) ( 1326320 1680000 ) ;
+ - vssa1 ( PIN vssa1 ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 2952100 3546800 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1937720 3546800 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 317720 3546800 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -32480 3546800 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2657720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2477720 3383080 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2297720 3383080 ) via4_3100x3100
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+ NEW met5 3100 + SHAPE STRIPE ( -34030 1763080 ) ( 2953650 1763080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1583080 ) ( 2953650 1583080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1403080 ) ( 2953650 1403080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1223080 ) ( 2953650 1223080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1043080 ) ( 2953650 1043080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 863080 ) ( 2953650 863080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 683080 ) ( 2953650 683080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 503080 ) ( 2953650 503080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 323080 ) ( 2953650 323080 )
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+ NEW met5 3100 + SHAPE STRIPE ( -34030 -27120 ) ( 2953650 -27120 )
+ NEW met4 3100 + SHAPE STRIPE ( 2952100 -28670 ) ( 2952100 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2837720 -28670 ) ( 2837720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2657720 -28670 ) ( 2657720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2477720 -28670 ) ( 2477720 3548350 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1937720 2300000 ) ( 1937720 3548350 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1577720 2300000 ) ( 1577720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1397720 2300000 ) ( 1397720 3548350 )
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+ NEW met4 3100 + SHAPE STRIPE ( 857720 -28670 ) ( 857720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 677720 -28670 ) ( 677720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 497720 -28670 ) ( 497720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 317720 -28670 ) ( 317720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 137720 -28670 ) ( 137720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( -32480 -28670 ) ( -32480 3548350 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1577720 -28670 ) ( 1577720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1397720 -28670 ) ( 1397720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1217720 -28670 ) ( 1217720 1680000 ) ;
+ - vssa2 ( PIN vssa2 ) + USE GROUND
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+ NEW met5 3100 + SHAPE STRIPE ( -43630 1961680 ) ( 2963250 1961680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1781680 ) ( 2963250 1781680 )
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+ NEW met5 3100 + SHAPE STRIPE ( -43630 1061680 ) ( 2963250 1061680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 881680 ) ( 2963250 881680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 701680 ) ( 2963250 701680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 521680 ) ( 2963250 521680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 341680 ) ( 2963250 341680 )
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+ NEW met5 3100 + SHAPE STRIPE ( -43630 -36720 ) ( 2963250 -36720 )
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+ NEW met4 3100 + SHAPE STRIPE ( 2856320 -38270 ) ( 2856320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2676320 -38270 ) ( 2676320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2496320 -38270 ) ( 2496320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2316320 -38270 ) ( 2316320 3557950 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1956320 2300000 ) ( 1956320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1776320 2300000 ) ( 1776320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1596320 2300000 ) ( 1596320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1416320 2300000 ) ( 1416320 3557950 )
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+ NEW met4 3100 + SHAPE STRIPE ( 876320 -38270 ) ( 876320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 696320 -38270 ) ( 696320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 516320 -38270 ) ( 516320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 336320 -38270 ) ( 336320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 156320 -38270 ) ( 156320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( -42080 -38270 ) ( -42080 3557950 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1776320 -38270 ) ( 1776320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1596320 -38270 ) ( 1596320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1416320 -38270 ) ( 1416320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1236320 -38270 ) ( 1236320 1680000 ) ;
+ - vssd1 ( PIN vssd1 ) + USE GROUND
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+ NEW met4 0 + SHAPE STRIPE ( 280520 -7920 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -13280 -7920 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3527600 ) ( 2934450 3527600 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3345880 ) ( 2934450 3345880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3165880 ) ( 2934450 3165880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2985880 ) ( 2934450 2985880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2805880 ) ( 2934450 2805880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2625880 ) ( 2934450 2625880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2445880 ) ( 2934450 2445880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2265880 ) ( 2934450 2265880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2085880 ) ( 2934450 2085880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1905880 ) ( 2934450 1905880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1725880 ) ( 2934450 1725880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1545880 ) ( 2934450 1545880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1365880 ) ( 2934450 1365880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1185880 ) ( 2934450 1185880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1005880 ) ( 2934450 1005880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 825880 ) ( 2934450 825880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 645880 ) ( 2934450 645880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 465880 ) ( 2934450 465880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 285880 ) ( 2934450 285880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 105880 ) ( 2934450 105880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 -7920 ) ( 2934450 -7920 )
+ NEW met4 3100 + SHAPE STRIPE ( 2932900 -9470 ) ( 2932900 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2800520 -9470 ) ( 2800520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2620520 -9470 ) ( 2620520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2440520 -9470 ) ( 2440520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2260520 -9470 ) ( 2260520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2080520 2300000 ) ( 2080520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1900520 2300000 ) ( 1900520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1720520 2300000 ) ( 1720520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1540520 2300000 ) ( 1540520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1360520 2300000 ) ( 1360520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1180520 2300000 ) ( 1180520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1000520 -9470 ) ( 1000520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 820520 -9470 ) ( 820520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 640520 -9470 ) ( 640520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 460520 -9470 ) ( 460520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 280520 -9470 ) ( 280520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 100520 -9470 ) ( 100520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( -13280 -9470 ) ( -13280 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2080520 -9470 ) ( 2080520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1900520 -9470 ) ( 1900520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1720520 -9470 ) ( 1720520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1540520 -9470 ) ( 1540520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1360520 -9470 ) ( 1360520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1180520 -9470 ) ( 1180520 1680000 ) ;
+ - vssd2 ( PIN vssd2 ) + USE GROUND
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+ NEW met4 0 + SHAPE STRIPE ( 1739120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 -17520 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3537200 ) ( 2944050 3537200 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3364480 ) ( 2944050 3364480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3184480 ) ( 2944050 3184480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3004480 ) ( 2944050 3004480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2824480 ) ( 2944050 2824480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2644480 ) ( 2944050 2644480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2464480 ) ( 2944050 2464480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2284480 ) ( 2944050 2284480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2104480 ) ( 2944050 2104480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1924480 ) ( 2944050 1924480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1744480 ) ( 2944050 1744480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1564480 ) ( 2944050 1564480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1384480 ) ( 2944050 1384480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1204480 ) ( 2944050 1204480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1024480 ) ( 2944050 1024480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 844480 ) ( 2944050 844480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 664480 ) ( 2944050 664480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 484480 ) ( 2944050 484480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 304480 ) ( 2944050 304480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 124480 ) ( 2944050 124480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 -17520 ) ( 2944050 -17520 )
+ NEW met4 3100 + SHAPE STRIPE ( 2942500 -19070 ) ( 2942500 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2819120 -19070 ) ( 2819120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2639120 -19070 ) ( 2639120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2459120 -19070 ) ( 2459120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2279120 -19070 ) ( 2279120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2099120 -19070 ) ( 2099120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1919120 2300000 ) ( 1919120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1739120 2300000 ) ( 1739120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1559120 2300000 ) ( 1559120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1379120 2300000 ) ( 1379120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1199120 2300000 ) ( 1199120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1019120 -19070 ) ( 1019120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 839120 -19070 ) ( 839120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 659120 -19070 ) ( 659120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 479120 -19070 ) ( 479120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 299120 -19070 ) ( 299120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 119120 -19070 ) ( 119120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( -22880 -19070 ) ( -22880 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1919120 -19070 ) ( 1919120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1739120 -19070 ) ( 1739120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1559120 -19070 ) ( 1559120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1379120 -19070 ) ( 1379120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 1680000 ) ;
+END SPECIALNETS
+END DESIGN
diff --git a/openlane/ref/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def b/openlane/ref/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def
new file mode 100644
index 0000000..0120e95
--- /dev/null
+++ b/openlane/ref/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def
@@ -0,0 +1,6837 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN user_project_wrapper ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 6000000 6000000 ) ;
+ROW ROW_0 GF018hv5v_mcu_sc7 13440 31360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_1 GF018hv5v_mcu_sc7 13440 39200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_2 GF018hv5v_mcu_sc7 13440 47040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_3 GF018hv5v_mcu_sc7 13440 54880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_4 GF018hv5v_mcu_sc7 13440 62720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_5 GF018hv5v_mcu_sc7 13440 70560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_6 GF018hv5v_mcu_sc7 13440 78400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_7 GF018hv5v_mcu_sc7 13440 86240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_8 GF018hv5v_mcu_sc7 13440 94080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_9 GF018hv5v_mcu_sc7 13440 101920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_10 GF018hv5v_mcu_sc7 13440 109760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_11 GF018hv5v_mcu_sc7 13440 117600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_12 GF018hv5v_mcu_sc7 13440 125440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_13 GF018hv5v_mcu_sc7 13440 133280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_14 GF018hv5v_mcu_sc7 13440 141120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_15 GF018hv5v_mcu_sc7 13440 148960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_16 GF018hv5v_mcu_sc7 13440 156800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_17 GF018hv5v_mcu_sc7 13440 164640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_18 GF018hv5v_mcu_sc7 13440 172480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_19 GF018hv5v_mcu_sc7 13440 180320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_20 GF018hv5v_mcu_sc7 13440 188160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_21 GF018hv5v_mcu_sc7 13440 196000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_22 GF018hv5v_mcu_sc7 13440 203840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_23 GF018hv5v_mcu_sc7 13440 211680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_24 GF018hv5v_mcu_sc7 13440 219520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_25 GF018hv5v_mcu_sc7 13440 227360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_26 GF018hv5v_mcu_sc7 13440 235200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_27 GF018hv5v_mcu_sc7 13440 243040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_28 GF018hv5v_mcu_sc7 13440 250880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_29 GF018hv5v_mcu_sc7 13440 258720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_30 GF018hv5v_mcu_sc7 13440 266560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_31 GF018hv5v_mcu_sc7 13440 274400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_32 GF018hv5v_mcu_sc7 13440 282240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_33 GF018hv5v_mcu_sc7 13440 290080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_34 GF018hv5v_mcu_sc7 13440 297920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_35 GF018hv5v_mcu_sc7 13440 305760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_36 GF018hv5v_mcu_sc7 13440 313600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_37 GF018hv5v_mcu_sc7 13440 321440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_38 GF018hv5v_mcu_sc7 13440 329280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_39 GF018hv5v_mcu_sc7 13440 337120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_40 GF018hv5v_mcu_sc7 13440 344960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_41 GF018hv5v_mcu_sc7 13440 352800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_42 GF018hv5v_mcu_sc7 13440 360640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_43 GF018hv5v_mcu_sc7 13440 368480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_44 GF018hv5v_mcu_sc7 13440 376320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_45 GF018hv5v_mcu_sc7 13440 384160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_46 GF018hv5v_mcu_sc7 13440 392000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_47 GF018hv5v_mcu_sc7 13440 399840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_48 GF018hv5v_mcu_sc7 13440 407680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_49 GF018hv5v_mcu_sc7 13440 415520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_50 GF018hv5v_mcu_sc7 13440 423360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_51 GF018hv5v_mcu_sc7 13440 431200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_52 GF018hv5v_mcu_sc7 13440 439040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_53 GF018hv5v_mcu_sc7 13440 446880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_54 GF018hv5v_mcu_sc7 13440 454720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_55 GF018hv5v_mcu_sc7 13440 462560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_56 GF018hv5v_mcu_sc7 13440 470400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_57 GF018hv5v_mcu_sc7 13440 478240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_58 GF018hv5v_mcu_sc7 13440 486080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_59 GF018hv5v_mcu_sc7 13440 493920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_60 GF018hv5v_mcu_sc7 13440 501760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_61 GF018hv5v_mcu_sc7 13440 509600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_62 GF018hv5v_mcu_sc7 13440 517440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_63 GF018hv5v_mcu_sc7 13440 525280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_64 GF018hv5v_mcu_sc7 13440 533120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_65 GF018hv5v_mcu_sc7 13440 540960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_66 GF018hv5v_mcu_sc7 13440 548800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_67 GF018hv5v_mcu_sc7 13440 556640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_68 GF018hv5v_mcu_sc7 13440 564480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_69 GF018hv5v_mcu_sc7 13440 572320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_70 GF018hv5v_mcu_sc7 13440 580160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_71 GF018hv5v_mcu_sc7 13440 588000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_72 GF018hv5v_mcu_sc7 13440 595840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_73 GF018hv5v_mcu_sc7 13440 603680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_74 GF018hv5v_mcu_sc7 13440 611520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_75 GF018hv5v_mcu_sc7 13440 619360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_76 GF018hv5v_mcu_sc7 13440 627200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_77 GF018hv5v_mcu_sc7 13440 635040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_78 GF018hv5v_mcu_sc7 13440 642880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_79 GF018hv5v_mcu_sc7 13440 650720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_80 GF018hv5v_mcu_sc7 13440 658560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_81 GF018hv5v_mcu_sc7 13440 666400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_82 GF018hv5v_mcu_sc7 13440 674240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_83 GF018hv5v_mcu_sc7 13440 682080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_84 GF018hv5v_mcu_sc7 13440 689920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_85 GF018hv5v_mcu_sc7 13440 697760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_86 GF018hv5v_mcu_sc7 13440 705600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_87 GF018hv5v_mcu_sc7 13440 713440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_88 GF018hv5v_mcu_sc7 13440 721280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_89 GF018hv5v_mcu_sc7 13440 729120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_90 GF018hv5v_mcu_sc7 13440 736960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_91 GF018hv5v_mcu_sc7 13440 744800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_92 GF018hv5v_mcu_sc7 13440 752640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_93 GF018hv5v_mcu_sc7 13440 760480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_94 GF018hv5v_mcu_sc7 13440 768320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_95 GF018hv5v_mcu_sc7 13440 776160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_96 GF018hv5v_mcu_sc7 13440 784000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_97 GF018hv5v_mcu_sc7 13440 791840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_98 GF018hv5v_mcu_sc7 13440 799680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_99 GF018hv5v_mcu_sc7 13440 807520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_100 GF018hv5v_mcu_sc7 13440 815360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_101 GF018hv5v_mcu_sc7 13440 823200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_102 GF018hv5v_mcu_sc7 13440 831040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_103 GF018hv5v_mcu_sc7 13440 838880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_104 GF018hv5v_mcu_sc7 13440 846720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_105 GF018hv5v_mcu_sc7 13440 854560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_106 GF018hv5v_mcu_sc7 13440 862400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_107 GF018hv5v_mcu_sc7 13440 870240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_108 GF018hv5v_mcu_sc7 13440 878080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_109 GF018hv5v_mcu_sc7 13440 885920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_110 GF018hv5v_mcu_sc7 13440 893760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_111 GF018hv5v_mcu_sc7 13440 901600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_112 GF018hv5v_mcu_sc7 13440 909440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_113 GF018hv5v_mcu_sc7 13440 917280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_114 GF018hv5v_mcu_sc7 13440 925120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_115 GF018hv5v_mcu_sc7 13440 932960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_116 GF018hv5v_mcu_sc7 13440 940800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_117 GF018hv5v_mcu_sc7 13440 948640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_118 GF018hv5v_mcu_sc7 13440 956480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_119 GF018hv5v_mcu_sc7 13440 964320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_120 GF018hv5v_mcu_sc7 13440 972160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_121 GF018hv5v_mcu_sc7 13440 980000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_122 GF018hv5v_mcu_sc7 13440 987840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_123 GF018hv5v_mcu_sc7 13440 995680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_124 GF018hv5v_mcu_sc7 13440 1003520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_125 GF018hv5v_mcu_sc7 13440 1011360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_126 GF018hv5v_mcu_sc7 13440 1019200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_127 GF018hv5v_mcu_sc7 13440 1027040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_128 GF018hv5v_mcu_sc7 13440 1034880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_129 GF018hv5v_mcu_sc7 13440 1042720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_130 GF018hv5v_mcu_sc7 13440 1050560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_131 GF018hv5v_mcu_sc7 13440 1058400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_132 GF018hv5v_mcu_sc7 13440 1066240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_133 GF018hv5v_mcu_sc7 13440 1074080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_134 GF018hv5v_mcu_sc7 13440 1081920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_135 GF018hv5v_mcu_sc7 13440 1089760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_136 GF018hv5v_mcu_sc7 13440 1097600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_137 GF018hv5v_mcu_sc7 13440 1105440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_138 GF018hv5v_mcu_sc7 13440 1113280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_139 GF018hv5v_mcu_sc7 13440 1121120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_140 GF018hv5v_mcu_sc7 13440 1128960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_141 GF018hv5v_mcu_sc7 13440 1136800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_142 GF018hv5v_mcu_sc7 13440 1144640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_143 GF018hv5v_mcu_sc7 13440 1152480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_144 GF018hv5v_mcu_sc7 13440 1160320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_145 GF018hv5v_mcu_sc7 13440 1168160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_146 GF018hv5v_mcu_sc7 13440 1176000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_147 GF018hv5v_mcu_sc7 13440 1183840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_148 GF018hv5v_mcu_sc7 13440 1191680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_149 GF018hv5v_mcu_sc7 13440 1199520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_150 GF018hv5v_mcu_sc7 13440 1207360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_151 GF018hv5v_mcu_sc7 13440 1215200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_152 GF018hv5v_mcu_sc7 13440 1223040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_153 GF018hv5v_mcu_sc7 13440 1230880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_154 GF018hv5v_mcu_sc7 13440 1238720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_155 GF018hv5v_mcu_sc7 13440 1246560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_156 GF018hv5v_mcu_sc7 13440 1254400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_157 GF018hv5v_mcu_sc7 13440 1262240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_158 GF018hv5v_mcu_sc7 13440 1270080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_159 GF018hv5v_mcu_sc7 13440 1277920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_160 GF018hv5v_mcu_sc7 13440 1285760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_161 GF018hv5v_mcu_sc7 13440 1293600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_162 GF018hv5v_mcu_sc7 13440 1301440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_163 GF018hv5v_mcu_sc7 13440 1309280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_164 GF018hv5v_mcu_sc7 13440 1317120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_165 GF018hv5v_mcu_sc7 13440 1324960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_166 GF018hv5v_mcu_sc7 13440 1332800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_167 GF018hv5v_mcu_sc7 13440 1340640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_168 GF018hv5v_mcu_sc7 13440 1348480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_169 GF018hv5v_mcu_sc7 13440 1356320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_170 GF018hv5v_mcu_sc7 13440 1364160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_171 GF018hv5v_mcu_sc7 13440 1372000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_172 GF018hv5v_mcu_sc7 13440 1379840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_173 GF018hv5v_mcu_sc7 13440 1387680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_174 GF018hv5v_mcu_sc7 13440 1395520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_175 GF018hv5v_mcu_sc7 13440 1403360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_176 GF018hv5v_mcu_sc7 13440 1411200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_177 GF018hv5v_mcu_sc7 13440 1419040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_178 GF018hv5v_mcu_sc7 13440 1426880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_179 GF018hv5v_mcu_sc7 13440 1434720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_180 GF018hv5v_mcu_sc7 13440 1442560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_181 GF018hv5v_mcu_sc7 13440 1450400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_182 GF018hv5v_mcu_sc7 13440 1458240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_183 GF018hv5v_mcu_sc7 13440 1466080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_184 GF018hv5v_mcu_sc7 13440 1473920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_185 GF018hv5v_mcu_sc7 13440 1481760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_186 GF018hv5v_mcu_sc7 13440 1489600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_187 GF018hv5v_mcu_sc7 13440 1497440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_188 GF018hv5v_mcu_sc7 13440 1505280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_189 GF018hv5v_mcu_sc7 13440 1513120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_190 GF018hv5v_mcu_sc7 13440 1520960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_191 GF018hv5v_mcu_sc7 13440 1528800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_192 GF018hv5v_mcu_sc7 13440 1536640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_193 GF018hv5v_mcu_sc7 13440 1544480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_194 GF018hv5v_mcu_sc7 13440 1552320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_195 GF018hv5v_mcu_sc7 13440 1560160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_196 GF018hv5v_mcu_sc7 13440 1568000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_197 GF018hv5v_mcu_sc7 13440 1575840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_198 GF018hv5v_mcu_sc7 13440 1583680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_199 GF018hv5v_mcu_sc7 13440 1591520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_200 GF018hv5v_mcu_sc7 13440 1599360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_201 GF018hv5v_mcu_sc7 13440 1607200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_202 GF018hv5v_mcu_sc7 13440 1615040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_203 GF018hv5v_mcu_sc7 13440 1622880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_204 GF018hv5v_mcu_sc7 13440 1630720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_205 GF018hv5v_mcu_sc7 13440 1638560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_206 GF018hv5v_mcu_sc7 13440 1646400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_207 GF018hv5v_mcu_sc7 13440 1654240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_208 GF018hv5v_mcu_sc7 13440 1662080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_209 GF018hv5v_mcu_sc7 13440 1669920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_210 GF018hv5v_mcu_sc7 13440 1677760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_211 GF018hv5v_mcu_sc7 13440 1685600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_212 GF018hv5v_mcu_sc7 13440 1693440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_213 GF018hv5v_mcu_sc7 13440 1701280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_214 GF018hv5v_mcu_sc7 13440 1709120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_215 GF018hv5v_mcu_sc7 13440 1716960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_216 GF018hv5v_mcu_sc7 13440 1724800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_217 GF018hv5v_mcu_sc7 13440 1732640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_218 GF018hv5v_mcu_sc7 13440 1740480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_219 GF018hv5v_mcu_sc7 13440 1748320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_220 GF018hv5v_mcu_sc7 13440 1756160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_221 GF018hv5v_mcu_sc7 13440 1764000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_222 GF018hv5v_mcu_sc7 13440 1771840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_223 GF018hv5v_mcu_sc7 13440 1779680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_224 GF018hv5v_mcu_sc7 13440 1787520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_225 GF018hv5v_mcu_sc7 13440 1795360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_226 GF018hv5v_mcu_sc7 13440 1803200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_227 GF018hv5v_mcu_sc7 13440 1811040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_228 GF018hv5v_mcu_sc7 13440 1818880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_229 GF018hv5v_mcu_sc7 13440 1826720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_230 GF018hv5v_mcu_sc7 13440 1834560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_231 GF018hv5v_mcu_sc7 13440 1842400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_232 GF018hv5v_mcu_sc7 13440 1850240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_233 GF018hv5v_mcu_sc7 13440 1858080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_234 GF018hv5v_mcu_sc7 13440 1865920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_235 GF018hv5v_mcu_sc7 13440 1873760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_236 GF018hv5v_mcu_sc7 13440 1881600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_237 GF018hv5v_mcu_sc7 13440 1889440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_238 GF018hv5v_mcu_sc7 13440 1897280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_239 GF018hv5v_mcu_sc7 13440 1905120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_240 GF018hv5v_mcu_sc7 13440 1912960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_241 GF018hv5v_mcu_sc7 13440 1920800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_242 GF018hv5v_mcu_sc7 13440 1928640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_243 GF018hv5v_mcu_sc7 13440 1936480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_244 GF018hv5v_mcu_sc7 13440 1944320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_245 GF018hv5v_mcu_sc7 13440 1952160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_246 GF018hv5v_mcu_sc7 13440 1960000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_247 GF018hv5v_mcu_sc7 13440 1967840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_248 GF018hv5v_mcu_sc7 13440 1975680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_249 GF018hv5v_mcu_sc7 13440 1983520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_250 GF018hv5v_mcu_sc7 13440 1991360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_251 GF018hv5v_mcu_sc7 13440 1999200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_252 GF018hv5v_mcu_sc7 13440 2007040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_253 GF018hv5v_mcu_sc7 13440 2014880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_254 GF018hv5v_mcu_sc7 13440 2022720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_255 GF018hv5v_mcu_sc7 13440 2030560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_256 GF018hv5v_mcu_sc7 13440 2038400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_257 GF018hv5v_mcu_sc7 13440 2046240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_258 GF018hv5v_mcu_sc7 13440 2054080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_259 GF018hv5v_mcu_sc7 13440 2061920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_260 GF018hv5v_mcu_sc7 13440 2069760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_261 GF018hv5v_mcu_sc7 13440 2077600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_262 GF018hv5v_mcu_sc7 13440 2085440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_263 GF018hv5v_mcu_sc7 13440 2093280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_264 GF018hv5v_mcu_sc7 13440 2101120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_265 GF018hv5v_mcu_sc7 13440 2108960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_266 GF018hv5v_mcu_sc7 13440 2116800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_267 GF018hv5v_mcu_sc7 13440 2124640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_268 GF018hv5v_mcu_sc7 13440 2132480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_269 GF018hv5v_mcu_sc7 13440 2140320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_270 GF018hv5v_mcu_sc7 13440 2148160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_271 GF018hv5v_mcu_sc7 13440 2156000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_272 GF018hv5v_mcu_sc7 13440 2163840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_273 GF018hv5v_mcu_sc7 13440 2171680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_274 GF018hv5v_mcu_sc7 13440 2179520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_275 GF018hv5v_mcu_sc7 13440 2187360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_276 GF018hv5v_mcu_sc7 13440 2195200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_277 GF018hv5v_mcu_sc7 13440 2203040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_278 GF018hv5v_mcu_sc7 13440 2210880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_279 GF018hv5v_mcu_sc7 13440 2218720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_280 GF018hv5v_mcu_sc7 13440 2226560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_281 GF018hv5v_mcu_sc7 13440 2234400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_282 GF018hv5v_mcu_sc7 13440 2242240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_283 GF018hv5v_mcu_sc7 13440 2250080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_284 GF018hv5v_mcu_sc7 13440 2257920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_285 GF018hv5v_mcu_sc7 13440 2265760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_286 GF018hv5v_mcu_sc7 13440 2273600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_287 GF018hv5v_mcu_sc7 13440 2281440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_288 GF018hv5v_mcu_sc7 13440 2289280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_289 GF018hv5v_mcu_sc7 13440 2297120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_290 GF018hv5v_mcu_sc7 13440 2304960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_291 GF018hv5v_mcu_sc7 13440 2312800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_292 GF018hv5v_mcu_sc7 13440 2320640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_293 GF018hv5v_mcu_sc7 13440 2328480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_294 GF018hv5v_mcu_sc7 13440 2336320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_295 GF018hv5v_mcu_sc7 13440 2344160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_296 GF018hv5v_mcu_sc7 13440 2352000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_297 GF018hv5v_mcu_sc7 13440 2359840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_298 GF018hv5v_mcu_sc7 13440 2367680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_299 GF018hv5v_mcu_sc7 13440 2375520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_300 GF018hv5v_mcu_sc7 13440 2383360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_301 GF018hv5v_mcu_sc7 13440 2391200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_302 GF018hv5v_mcu_sc7 13440 2399040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_303 GF018hv5v_mcu_sc7 13440 2406880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_304 GF018hv5v_mcu_sc7 13440 2414720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_305 GF018hv5v_mcu_sc7 13440 2422560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_306 GF018hv5v_mcu_sc7 13440 2430400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_307 GF018hv5v_mcu_sc7 13440 2438240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_308 GF018hv5v_mcu_sc7 13440 2446080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_309 GF018hv5v_mcu_sc7 13440 2453920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_310 GF018hv5v_mcu_sc7 13440 2461760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_311 GF018hv5v_mcu_sc7 13440 2469600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_312 GF018hv5v_mcu_sc7 13440 2477440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_313 GF018hv5v_mcu_sc7 13440 2485280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_314 GF018hv5v_mcu_sc7 13440 2493120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_315 GF018hv5v_mcu_sc7 13440 2500960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_316 GF018hv5v_mcu_sc7 13440 2508800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_317 GF018hv5v_mcu_sc7 13440 2516640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_318 GF018hv5v_mcu_sc7 13440 2524480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_319 GF018hv5v_mcu_sc7 13440 2532320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_320 GF018hv5v_mcu_sc7 13440 2540160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_321 GF018hv5v_mcu_sc7 13440 2548000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_322 GF018hv5v_mcu_sc7 13440 2555840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_323 GF018hv5v_mcu_sc7 13440 2563680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_324 GF018hv5v_mcu_sc7 13440 2571520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_325 GF018hv5v_mcu_sc7 13440 2579360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_326 GF018hv5v_mcu_sc7 13440 2587200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_327 GF018hv5v_mcu_sc7 13440 2595040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_328 GF018hv5v_mcu_sc7 13440 2602880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_329 GF018hv5v_mcu_sc7 13440 2610720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_330 GF018hv5v_mcu_sc7 13440 2618560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_331 GF018hv5v_mcu_sc7 13440 2626400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_332 GF018hv5v_mcu_sc7 13440 2634240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_333 GF018hv5v_mcu_sc7 13440 2642080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_334 GF018hv5v_mcu_sc7 13440 2649920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_335 GF018hv5v_mcu_sc7 13440 2657760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_336 GF018hv5v_mcu_sc7 13440 2665600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_337 GF018hv5v_mcu_sc7 13440 2673440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_338 GF018hv5v_mcu_sc7 13440 2681280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_339 GF018hv5v_mcu_sc7 13440 2689120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_340 GF018hv5v_mcu_sc7 13440 2696960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_341 GF018hv5v_mcu_sc7 13440 2704800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_342 GF018hv5v_mcu_sc7 13440 2712640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_343 GF018hv5v_mcu_sc7 13440 2720480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_344 GF018hv5v_mcu_sc7 13440 2728320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_345 GF018hv5v_mcu_sc7 13440 2736160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_346 GF018hv5v_mcu_sc7 13440 2744000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_347 GF018hv5v_mcu_sc7 13440 2751840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_348 GF018hv5v_mcu_sc7 13440 2759680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_349 GF018hv5v_mcu_sc7 13440 2767520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_350 GF018hv5v_mcu_sc7 13440 2775360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_351 GF018hv5v_mcu_sc7 13440 2783200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_352 GF018hv5v_mcu_sc7 13440 2791040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_353 GF018hv5v_mcu_sc7 13440 2798880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_354 GF018hv5v_mcu_sc7 13440 2806720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_355 GF018hv5v_mcu_sc7 13440 2814560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_356 GF018hv5v_mcu_sc7 13440 2822400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_357 GF018hv5v_mcu_sc7 13440 2830240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_358 GF018hv5v_mcu_sc7 13440 2838080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_359 GF018hv5v_mcu_sc7 13440 2845920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_360 GF018hv5v_mcu_sc7 13440 2853760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_361 GF018hv5v_mcu_sc7 13440 2861600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_362 GF018hv5v_mcu_sc7 13440 2869440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_363 GF018hv5v_mcu_sc7 13440 2877280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_364 GF018hv5v_mcu_sc7 13440 2885120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_365 GF018hv5v_mcu_sc7 13440 2892960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_366 GF018hv5v_mcu_sc7 13440 2900800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_367 GF018hv5v_mcu_sc7 13440 2908640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_368 GF018hv5v_mcu_sc7 13440 2916480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_369 GF018hv5v_mcu_sc7 13440 2924320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_370 GF018hv5v_mcu_sc7 13440 2932160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_371 GF018hv5v_mcu_sc7 13440 2940000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_372 GF018hv5v_mcu_sc7 13440 2947840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_373 GF018hv5v_mcu_sc7 13440 2955680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_374 GF018hv5v_mcu_sc7 13440 2963520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_375 GF018hv5v_mcu_sc7 13440 2971360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_376 GF018hv5v_mcu_sc7 13440 2979200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_377 GF018hv5v_mcu_sc7 13440 2987040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_378 GF018hv5v_mcu_sc7 13440 2994880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_379 GF018hv5v_mcu_sc7 13440 3002720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_380 GF018hv5v_mcu_sc7 13440 3010560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_381 GF018hv5v_mcu_sc7 13440 3018400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_382 GF018hv5v_mcu_sc7 13440 3026240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_383 GF018hv5v_mcu_sc7 13440 3034080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_384 GF018hv5v_mcu_sc7 13440 3041920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_385 GF018hv5v_mcu_sc7 13440 3049760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_386 GF018hv5v_mcu_sc7 13440 3057600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_387 GF018hv5v_mcu_sc7 13440 3065440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_388 GF018hv5v_mcu_sc7 13440 3073280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_389 GF018hv5v_mcu_sc7 13440 3081120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_390 GF018hv5v_mcu_sc7 13440 3088960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_391 GF018hv5v_mcu_sc7 13440 3096800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_392 GF018hv5v_mcu_sc7 13440 3104640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_393 GF018hv5v_mcu_sc7 13440 3112480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_394 GF018hv5v_mcu_sc7 13440 3120320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_395 GF018hv5v_mcu_sc7 13440 3128160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_396 GF018hv5v_mcu_sc7 13440 3136000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_397 GF018hv5v_mcu_sc7 13440 3143840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_398 GF018hv5v_mcu_sc7 13440 3151680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_399 GF018hv5v_mcu_sc7 13440 3159520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_400 GF018hv5v_mcu_sc7 13440 3167360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_401 GF018hv5v_mcu_sc7 13440 3175200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_402 GF018hv5v_mcu_sc7 13440 3183040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_403 GF018hv5v_mcu_sc7 13440 3190880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_404 GF018hv5v_mcu_sc7 13440 3198720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_405 GF018hv5v_mcu_sc7 13440 3206560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_406 GF018hv5v_mcu_sc7 13440 3214400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_407 GF018hv5v_mcu_sc7 13440 3222240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_408 GF018hv5v_mcu_sc7 13440 3230080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_409 GF018hv5v_mcu_sc7 13440 3237920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_410 GF018hv5v_mcu_sc7 13440 3245760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_411 GF018hv5v_mcu_sc7 13440 3253600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_412 GF018hv5v_mcu_sc7 13440 3261440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_413 GF018hv5v_mcu_sc7 13440 3269280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_414 GF018hv5v_mcu_sc7 13440 3277120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_415 GF018hv5v_mcu_sc7 13440 3284960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_416 GF018hv5v_mcu_sc7 13440 3292800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_417 GF018hv5v_mcu_sc7 13440 3300640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_418 GF018hv5v_mcu_sc7 13440 3308480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_419 GF018hv5v_mcu_sc7 13440 3316320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_420 GF018hv5v_mcu_sc7 13440 3324160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_421 GF018hv5v_mcu_sc7 13440 3332000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_422 GF018hv5v_mcu_sc7 13440 3339840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_423 GF018hv5v_mcu_sc7 13440 3347680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_424 GF018hv5v_mcu_sc7 13440 3355520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_425 GF018hv5v_mcu_sc7 13440 3363360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_426 GF018hv5v_mcu_sc7 13440 3371200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_427 GF018hv5v_mcu_sc7 13440 3379040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_428 GF018hv5v_mcu_sc7 13440 3386880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_429 GF018hv5v_mcu_sc7 13440 3394720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_430 GF018hv5v_mcu_sc7 13440 3402560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_431 GF018hv5v_mcu_sc7 13440 3410400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_432 GF018hv5v_mcu_sc7 13440 3418240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_433 GF018hv5v_mcu_sc7 13440 3426080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_434 GF018hv5v_mcu_sc7 13440 3433920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_435 GF018hv5v_mcu_sc7 13440 3441760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_436 GF018hv5v_mcu_sc7 13440 3449600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_437 GF018hv5v_mcu_sc7 13440 3457440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_438 GF018hv5v_mcu_sc7 13440 3465280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_439 GF018hv5v_mcu_sc7 13440 3473120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_440 GF018hv5v_mcu_sc7 13440 3480960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_441 GF018hv5v_mcu_sc7 13440 3488800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_442 GF018hv5v_mcu_sc7 13440 3496640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_443 GF018hv5v_mcu_sc7 13440 3504480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_444 GF018hv5v_mcu_sc7 13440 3512320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_445 GF018hv5v_mcu_sc7 13440 3520160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_446 GF018hv5v_mcu_sc7 13440 3528000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_447 GF018hv5v_mcu_sc7 13440 3535840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_448 GF018hv5v_mcu_sc7 13440 3543680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_449 GF018hv5v_mcu_sc7 13440 3551520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_450 GF018hv5v_mcu_sc7 13440 3559360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_451 GF018hv5v_mcu_sc7 13440 3567200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_452 GF018hv5v_mcu_sc7 13440 3575040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_453 GF018hv5v_mcu_sc7 13440 3582880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_454 GF018hv5v_mcu_sc7 13440 3590720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_455 GF018hv5v_mcu_sc7 13440 3598560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_456 GF018hv5v_mcu_sc7 13440 3606400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_457 GF018hv5v_mcu_sc7 13440 3614240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_458 GF018hv5v_mcu_sc7 13440 3622080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_459 GF018hv5v_mcu_sc7 13440 3629920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_460 GF018hv5v_mcu_sc7 13440 3637760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_461 GF018hv5v_mcu_sc7 13440 3645600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_462 GF018hv5v_mcu_sc7 13440 3653440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_463 GF018hv5v_mcu_sc7 13440 3661280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_464 GF018hv5v_mcu_sc7 13440 3669120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_465 GF018hv5v_mcu_sc7 13440 3676960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_466 GF018hv5v_mcu_sc7 13440 3684800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_467 GF018hv5v_mcu_sc7 13440 3692640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_468 GF018hv5v_mcu_sc7 13440 3700480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_469 GF018hv5v_mcu_sc7 13440 3708320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_470 GF018hv5v_mcu_sc7 13440 3716160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_471 GF018hv5v_mcu_sc7 13440 3724000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_472 GF018hv5v_mcu_sc7 13440 3731840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_473 GF018hv5v_mcu_sc7 13440 3739680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_474 GF018hv5v_mcu_sc7 13440 3747520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_475 GF018hv5v_mcu_sc7 13440 3755360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_476 GF018hv5v_mcu_sc7 13440 3763200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_477 GF018hv5v_mcu_sc7 13440 3771040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_478 GF018hv5v_mcu_sc7 13440 3778880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_479 GF018hv5v_mcu_sc7 13440 3786720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_480 GF018hv5v_mcu_sc7 13440 3794560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_481 GF018hv5v_mcu_sc7 13440 3802400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_482 GF018hv5v_mcu_sc7 13440 3810240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_483 GF018hv5v_mcu_sc7 13440 3818080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_484 GF018hv5v_mcu_sc7 13440 3825920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_485 GF018hv5v_mcu_sc7 13440 3833760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_486 GF018hv5v_mcu_sc7 13440 3841600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_487 GF018hv5v_mcu_sc7 13440 3849440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_488 GF018hv5v_mcu_sc7 13440 3857280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_489 GF018hv5v_mcu_sc7 13440 3865120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_490 GF018hv5v_mcu_sc7 13440 3872960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_491 GF018hv5v_mcu_sc7 13440 3880800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_492 GF018hv5v_mcu_sc7 13440 3888640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_493 GF018hv5v_mcu_sc7 13440 3896480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_494 GF018hv5v_mcu_sc7 13440 3904320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_495 GF018hv5v_mcu_sc7 13440 3912160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_496 GF018hv5v_mcu_sc7 13440 3920000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_497 GF018hv5v_mcu_sc7 13440 3927840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_498 GF018hv5v_mcu_sc7 13440 3935680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_499 GF018hv5v_mcu_sc7 13440 3943520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_500 GF018hv5v_mcu_sc7 13440 3951360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_501 GF018hv5v_mcu_sc7 13440 3959200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_502 GF018hv5v_mcu_sc7 13440 3967040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_503 GF018hv5v_mcu_sc7 13440 3974880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_504 GF018hv5v_mcu_sc7 13440 3982720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_505 GF018hv5v_mcu_sc7 13440 3990560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_506 GF018hv5v_mcu_sc7 13440 3998400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_507 GF018hv5v_mcu_sc7 13440 4006240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_508 GF018hv5v_mcu_sc7 13440 4014080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_509 GF018hv5v_mcu_sc7 13440 4021920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_510 GF018hv5v_mcu_sc7 13440 4029760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_511 GF018hv5v_mcu_sc7 13440 4037600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_512 GF018hv5v_mcu_sc7 13440 4045440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_513 GF018hv5v_mcu_sc7 13440 4053280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_514 GF018hv5v_mcu_sc7 13440 4061120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_515 GF018hv5v_mcu_sc7 13440 4068960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_516 GF018hv5v_mcu_sc7 13440 4076800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_517 GF018hv5v_mcu_sc7 13440 4084640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_518 GF018hv5v_mcu_sc7 13440 4092480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_519 GF018hv5v_mcu_sc7 13440 4100320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_520 GF018hv5v_mcu_sc7 13440 4108160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_521 GF018hv5v_mcu_sc7 13440 4116000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_522 GF018hv5v_mcu_sc7 13440 4123840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_523 GF018hv5v_mcu_sc7 13440 4131680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_524 GF018hv5v_mcu_sc7 13440 4139520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_525 GF018hv5v_mcu_sc7 13440 4147360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_526 GF018hv5v_mcu_sc7 13440 4155200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_527 GF018hv5v_mcu_sc7 13440 4163040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_528 GF018hv5v_mcu_sc7 13440 4170880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_529 GF018hv5v_mcu_sc7 13440 4178720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_530 GF018hv5v_mcu_sc7 13440 4186560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_531 GF018hv5v_mcu_sc7 13440 4194400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_532 GF018hv5v_mcu_sc7 13440 4202240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_533 GF018hv5v_mcu_sc7 13440 4210080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_534 GF018hv5v_mcu_sc7 13440 4217920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_535 GF018hv5v_mcu_sc7 13440 4225760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_536 GF018hv5v_mcu_sc7 13440 4233600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_537 GF018hv5v_mcu_sc7 13440 4241440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_538 GF018hv5v_mcu_sc7 13440 4249280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_539 GF018hv5v_mcu_sc7 13440 4257120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_540 GF018hv5v_mcu_sc7 13440 4264960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_541 GF018hv5v_mcu_sc7 13440 4272800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_542 GF018hv5v_mcu_sc7 13440 4280640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_543 GF018hv5v_mcu_sc7 13440 4288480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_544 GF018hv5v_mcu_sc7 13440 4296320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_545 GF018hv5v_mcu_sc7 13440 4304160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_546 GF018hv5v_mcu_sc7 13440 4312000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_547 GF018hv5v_mcu_sc7 13440 4319840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_548 GF018hv5v_mcu_sc7 13440 4327680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_549 GF018hv5v_mcu_sc7 13440 4335520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_550 GF018hv5v_mcu_sc7 13440 4343360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_551 GF018hv5v_mcu_sc7 13440 4351200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_552 GF018hv5v_mcu_sc7 13440 4359040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_553 GF018hv5v_mcu_sc7 13440 4366880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_554 GF018hv5v_mcu_sc7 13440 4374720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_555 GF018hv5v_mcu_sc7 13440 4382560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_556 GF018hv5v_mcu_sc7 13440 4390400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_557 GF018hv5v_mcu_sc7 13440 4398240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_558 GF018hv5v_mcu_sc7 13440 4406080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_559 GF018hv5v_mcu_sc7 13440 4413920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_560 GF018hv5v_mcu_sc7 13440 4421760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_561 GF018hv5v_mcu_sc7 13440 4429600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_562 GF018hv5v_mcu_sc7 13440 4437440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_563 GF018hv5v_mcu_sc7 13440 4445280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_564 GF018hv5v_mcu_sc7 13440 4453120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_565 GF018hv5v_mcu_sc7 13440 4460960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_566 GF018hv5v_mcu_sc7 13440 4468800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_567 GF018hv5v_mcu_sc7 13440 4476640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_568 GF018hv5v_mcu_sc7 13440 4484480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_569 GF018hv5v_mcu_sc7 13440 4492320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_570 GF018hv5v_mcu_sc7 13440 4500160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_571 GF018hv5v_mcu_sc7 13440 4508000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_572 GF018hv5v_mcu_sc7 13440 4515840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_573 GF018hv5v_mcu_sc7 13440 4523680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_574 GF018hv5v_mcu_sc7 13440 4531520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_575 GF018hv5v_mcu_sc7 13440 4539360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_576 GF018hv5v_mcu_sc7 13440 4547200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_577 GF018hv5v_mcu_sc7 13440 4555040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_578 GF018hv5v_mcu_sc7 13440 4562880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_579 GF018hv5v_mcu_sc7 13440 4570720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_580 GF018hv5v_mcu_sc7 13440 4578560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_581 GF018hv5v_mcu_sc7 13440 4586400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_582 GF018hv5v_mcu_sc7 13440 4594240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_583 GF018hv5v_mcu_sc7 13440 4602080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_584 GF018hv5v_mcu_sc7 13440 4609920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_585 GF018hv5v_mcu_sc7 13440 4617760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_586 GF018hv5v_mcu_sc7 13440 4625600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_587 GF018hv5v_mcu_sc7 13440 4633440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_588 GF018hv5v_mcu_sc7 13440 4641280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_589 GF018hv5v_mcu_sc7 13440 4649120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_590 GF018hv5v_mcu_sc7 13440 4656960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_591 GF018hv5v_mcu_sc7 13440 4664800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_592 GF018hv5v_mcu_sc7 13440 4672640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_593 GF018hv5v_mcu_sc7 13440 4680480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_594 GF018hv5v_mcu_sc7 13440 4688320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_595 GF018hv5v_mcu_sc7 13440 4696160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_596 GF018hv5v_mcu_sc7 13440 4704000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_597 GF018hv5v_mcu_sc7 13440 4711840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_598 GF018hv5v_mcu_sc7 13440 4719680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_599 GF018hv5v_mcu_sc7 13440 4727520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_600 GF018hv5v_mcu_sc7 13440 4735360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_601 GF018hv5v_mcu_sc7 13440 4743200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_602 GF018hv5v_mcu_sc7 13440 4751040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_603 GF018hv5v_mcu_sc7 13440 4758880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_604 GF018hv5v_mcu_sc7 13440 4766720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_605 GF018hv5v_mcu_sc7 13440 4774560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_606 GF018hv5v_mcu_sc7 13440 4782400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_607 GF018hv5v_mcu_sc7 13440 4790240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_608 GF018hv5v_mcu_sc7 13440 4798080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_609 GF018hv5v_mcu_sc7 13440 4805920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_610 GF018hv5v_mcu_sc7 13440 4813760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_611 GF018hv5v_mcu_sc7 13440 4821600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_612 GF018hv5v_mcu_sc7 13440 4829440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_613 GF018hv5v_mcu_sc7 13440 4837280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_614 GF018hv5v_mcu_sc7 13440 4845120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_615 GF018hv5v_mcu_sc7 13440 4852960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_616 GF018hv5v_mcu_sc7 13440 4860800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_617 GF018hv5v_mcu_sc7 13440 4868640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_618 GF018hv5v_mcu_sc7 13440 4876480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_619 GF018hv5v_mcu_sc7 13440 4884320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_620 GF018hv5v_mcu_sc7 13440 4892160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_621 GF018hv5v_mcu_sc7 13440 4900000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_622 GF018hv5v_mcu_sc7 13440 4907840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_623 GF018hv5v_mcu_sc7 13440 4915680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_624 GF018hv5v_mcu_sc7 13440 4923520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_625 GF018hv5v_mcu_sc7 13440 4931360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_626 GF018hv5v_mcu_sc7 13440 4939200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_627 GF018hv5v_mcu_sc7 13440 4947040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_628 GF018hv5v_mcu_sc7 13440 4954880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_629 GF018hv5v_mcu_sc7 13440 4962720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_630 GF018hv5v_mcu_sc7 13440 4970560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_631 GF018hv5v_mcu_sc7 13440 4978400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_632 GF018hv5v_mcu_sc7 13440 4986240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_633 GF018hv5v_mcu_sc7 13440 4994080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_634 GF018hv5v_mcu_sc7 13440 5001920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_635 GF018hv5v_mcu_sc7 13440 5009760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_636 GF018hv5v_mcu_sc7 13440 5017600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_637 GF018hv5v_mcu_sc7 13440 5025440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_638 GF018hv5v_mcu_sc7 13440 5033280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_639 GF018hv5v_mcu_sc7 13440 5041120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_640 GF018hv5v_mcu_sc7 13440 5048960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_641 GF018hv5v_mcu_sc7 13440 5056800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_642 GF018hv5v_mcu_sc7 13440 5064640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_643 GF018hv5v_mcu_sc7 13440 5072480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_644 GF018hv5v_mcu_sc7 13440 5080320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_645 GF018hv5v_mcu_sc7 13440 5088160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_646 GF018hv5v_mcu_sc7 13440 5096000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_647 GF018hv5v_mcu_sc7 13440 5103840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_648 GF018hv5v_mcu_sc7 13440 5111680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_649 GF018hv5v_mcu_sc7 13440 5119520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_650 GF018hv5v_mcu_sc7 13440 5127360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_651 GF018hv5v_mcu_sc7 13440 5135200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_652 GF018hv5v_mcu_sc7 13440 5143040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_653 GF018hv5v_mcu_sc7 13440 5150880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_654 GF018hv5v_mcu_sc7 13440 5158720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_655 GF018hv5v_mcu_sc7 13440 5166560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_656 GF018hv5v_mcu_sc7 13440 5174400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_657 GF018hv5v_mcu_sc7 13440 5182240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_658 GF018hv5v_mcu_sc7 13440 5190080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_659 GF018hv5v_mcu_sc7 13440 5197920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_660 GF018hv5v_mcu_sc7 13440 5205760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_661 GF018hv5v_mcu_sc7 13440 5213600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_662 GF018hv5v_mcu_sc7 13440 5221440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_663 GF018hv5v_mcu_sc7 13440 5229280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_664 GF018hv5v_mcu_sc7 13440 5237120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_665 GF018hv5v_mcu_sc7 13440 5244960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_666 GF018hv5v_mcu_sc7 13440 5252800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_667 GF018hv5v_mcu_sc7 13440 5260640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_668 GF018hv5v_mcu_sc7 13440 5268480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_669 GF018hv5v_mcu_sc7 13440 5276320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_670 GF018hv5v_mcu_sc7 13440 5284160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_671 GF018hv5v_mcu_sc7 13440 5292000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_672 GF018hv5v_mcu_sc7 13440 5299840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_673 GF018hv5v_mcu_sc7 13440 5307680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_674 GF018hv5v_mcu_sc7 13440 5315520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_675 GF018hv5v_mcu_sc7 13440 5323360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_676 GF018hv5v_mcu_sc7 13440 5331200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_677 GF018hv5v_mcu_sc7 13440 5339040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_678 GF018hv5v_mcu_sc7 13440 5346880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_679 GF018hv5v_mcu_sc7 13440 5354720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_680 GF018hv5v_mcu_sc7 13440 5362560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_681 GF018hv5v_mcu_sc7 13440 5370400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_682 GF018hv5v_mcu_sc7 13440 5378240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_683 GF018hv5v_mcu_sc7 13440 5386080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_684 GF018hv5v_mcu_sc7 13440 5393920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_685 GF018hv5v_mcu_sc7 13440 5401760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_686 GF018hv5v_mcu_sc7 13440 5409600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_687 GF018hv5v_mcu_sc7 13440 5417440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_688 GF018hv5v_mcu_sc7 13440 5425280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_689 GF018hv5v_mcu_sc7 13440 5433120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_690 GF018hv5v_mcu_sc7 13440 5440960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_691 GF018hv5v_mcu_sc7 13440 5448800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_692 GF018hv5v_mcu_sc7 13440 5456640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_693 GF018hv5v_mcu_sc7 13440 5464480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_694 GF018hv5v_mcu_sc7 13440 5472320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_695 GF018hv5v_mcu_sc7 13440 5480160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_696 GF018hv5v_mcu_sc7 13440 5488000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_697 GF018hv5v_mcu_sc7 13440 5495840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_698 GF018hv5v_mcu_sc7 13440 5503680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_699 GF018hv5v_mcu_sc7 13440 5511520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_700 GF018hv5v_mcu_sc7 13440 5519360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_701 GF018hv5v_mcu_sc7 13440 5527200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_702 GF018hv5v_mcu_sc7 13440 5535040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_703 GF018hv5v_mcu_sc7 13440 5542880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_704 GF018hv5v_mcu_sc7 13440 5550720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_705 GF018hv5v_mcu_sc7 13440 5558560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_706 GF018hv5v_mcu_sc7 13440 5566400 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_707 GF018hv5v_mcu_sc7 13440 5574240 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_708 GF018hv5v_mcu_sc7 13440 5582080 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_709 GF018hv5v_mcu_sc7 13440 5589920 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_710 GF018hv5v_mcu_sc7 13440 5597760 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_711 GF018hv5v_mcu_sc7 13440 5605600 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_712 GF018hv5v_mcu_sc7 13440 5613440 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_713 GF018hv5v_mcu_sc7 13440 5621280 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_714 GF018hv5v_mcu_sc7 13440 5629120 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_715 GF018hv5v_mcu_sc7 13440 5636960 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_716 GF018hv5v_mcu_sc7 13440 5644800 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_717 GF018hv5v_mcu_sc7 13440 5652640 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_718 GF018hv5v_mcu_sc7 13440 5660480 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_719 GF018hv5v_mcu_sc7 13440 5668320 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_720 GF018hv5v_mcu_sc7 13440 5676160 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_721 GF018hv5v_mcu_sc7 13440 5684000 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_722 GF018hv5v_mcu_sc7 13440 5691840 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_723 GF018hv5v_mcu_sc7 13440 5699680 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_724 GF018hv5v_mcu_sc7 13440 5707520 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_725 GF018hv5v_mcu_sc7 13440 5715360 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_726 GF018hv5v_mcu_sc7 13440 5723200 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_727 GF018hv5v_mcu_sc7 13440 5731040 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_728 GF018hv5v_mcu_sc7 13440 5738880 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_729 GF018hv5v_mcu_sc7 13440 5746720 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_730 GF018hv5v_mcu_sc7 13440 5754560 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_731 GF018hv5v_mcu_sc7 13440 5762400 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_732 GF018hv5v_mcu_sc7 13440 5770240 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_733 GF018hv5v_mcu_sc7 13440 5778080 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_734 GF018hv5v_mcu_sc7 13440 5785920 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_735 GF018hv5v_mcu_sc7 13440 5793760 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_736 GF018hv5v_mcu_sc7 13440 5801600 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_737 GF018hv5v_mcu_sc7 13440 5809440 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_738 GF018hv5v_mcu_sc7 13440 5817280 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_739 GF018hv5v_mcu_sc7 13440 5825120 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_740 GF018hv5v_mcu_sc7 13440 5832960 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_741 GF018hv5v_mcu_sc7 13440 5840800 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_742 GF018hv5v_mcu_sc7 13440 5848640 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_743 GF018hv5v_mcu_sc7 13440 5856480 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_744 GF018hv5v_mcu_sc7 13440 5864320 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_745 GF018hv5v_mcu_sc7 13440 5872160 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_746 GF018hv5v_mcu_sc7 13440 5880000 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_747 GF018hv5v_mcu_sc7 13440 5887840 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_748 GF018hv5v_mcu_sc7 13440 5895680 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_749 GF018hv5v_mcu_sc7 13440 5903520 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_750 GF018hv5v_mcu_sc7 13440 5911360 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_751 GF018hv5v_mcu_sc7 13440 5919200 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_752 GF018hv5v_mcu_sc7 13440 5927040 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_753 GF018hv5v_mcu_sc7 13440 5934880 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_754 GF018hv5v_mcu_sc7 13440 5942720 N DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_755 GF018hv5v_mcu_sc7 13440 5950560 FS DO 5333 BY 1 STEP 1120 0 ;
+ROW ROW_756 GF018hv5v_mcu_sc7 13440 5958400 N DO 5333 BY 1 STEP 1120 0 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal1 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal1 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal2 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal2 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal3 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal3 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal4 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal4 ;
+TRACKS X 560 DO 5357 STEP 1120 LAYER Metal5 ;
+TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal5 ;
+GCELLGRID X 0 DO 357 STEP 16800 ;
+GCELLGRID Y 0 DO 357 STEP 16800 ;
+VIAS 2 ;
+ - via4_5_6200_6200_6_6_1040_1040 + VIARULE Via4_GEN_HH + CUTSIZE 520 520 + LAYERS Metal4 Via4 Metal5 + CUTSPACING 520 520 + ENCLOSURE 240 120 120 240 + ROWCOL 6 6 ;
+ - via4_5_3200_6200_6_3_1040_1040 + VIARULE Via4_GEN_HH + CUTSIZE 520 520 + LAYERS Metal4 Via4 Metal5 + CUTSPACING 520 520 + ENCLOSURE 300 240 120 240 + ROWCOL 6 3 ;
+END VIAS
+COMPONENTS 1 ;
+ - mprj user_proj_example + FIXED ( 1175000 1690000 ) N ;
+END COMPONENTS
+PINS 645 ;
+ - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2434320 ) N ;
+ - analog_io[10] + NET analog_io[10] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4574640 6002400 ) N ;
+ - analog_io[11] + NET analog_io[11] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3911600 6002400 ) N ;
+ - analog_io[12] + NET analog_io[12] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3248560 6002400 ) N ;
+ - analog_io[13] + NET analog_io[13] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2585520 6002400 ) N ;
+ - analog_io[14] + NET analog_io[14] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1922480 6002400 ) N ;
+ - analog_io[15] + NET analog_io[15] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1259440 6002400 ) N ;
+ - analog_io[16] + NET analog_io[16] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 596400 6002400 ) N ;
+ - analog_io[17] + NET analog_io[17] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5937680 ) N ;
+ - analog_io[18] + NET analog_io[18] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5494160 ) N ;
+ - analog_io[19] + NET analog_io[19] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5050640 ) N ;
+ - analog_io[1] + NET analog_io[1] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2886800 ) N ;
+ - analog_io[20] + NET analog_io[20] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4607120 ) N ;
+ - analog_io[21] + NET analog_io[21] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4163600 ) N ;
+ - analog_io[22] + NET analog_io[22] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3720080 ) N ;
+ - analog_io[23] + NET analog_io[23] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3276560 ) N ;
+ - analog_io[24] + NET analog_io[24] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2833040 ) N ;
+ - analog_io[25] + NET analog_io[25] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2389520 ) N ;
+ - analog_io[26] + NET analog_io[26] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1946000 ) N ;
+ - analog_io[27] + NET analog_io[27] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1502480 ) N ;
+ - analog_io[28] + NET analog_io[28] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1058960 ) N ;
+ - analog_io[2] + NET analog_io[2] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3339280 ) N ;
+ - analog_io[3] + NET analog_io[3] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3791760 ) N ;
+ - analog_io[4] + NET analog_io[4] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4244240 ) N ;
+ - analog_io[5] + NET analog_io[5] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4696720 ) N ;
+ - analog_io[6] + NET analog_io[6] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5149200 ) N ;
+ - analog_io[7] + NET analog_io[7] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5601680 ) N ;
+ - analog_io[8] + NET analog_io[8] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5900720 6002400 ) N ;
+ - analog_io[9] + NET analog_io[9] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5237680 6002400 ) N ;
+ - io_in[0] + NET io_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 58800 ) N ;
+ - io_in[10] + NET io_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3904880 ) N ;
+ - io_in[11] + NET io_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4357360 ) N ;
+ - io_in[12] + NET io_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4809840 ) N ;
+ - io_in[13] + NET io_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5262320 ) N ;
+ - io_in[14] + NET io_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5714800 ) N ;
+ - io_in[15] + NET io_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5734960 6002400 ) N ;
+ - io_in[16] + NET io_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5071920 6002400 ) N ;
+ - io_in[17] + NET io_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4408880 6002400 ) N ;
+ - io_in[18] + NET io_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3745840 6002400 ) N ;
+ - io_in[19] + NET io_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3082800 6002400 ) N ;
+ - io_in[1] + NET io_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 398160 ) N ;
+ - io_in[20] + NET io_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2419760 6002400 ) N ;
+ - io_in[21] + NET io_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1756720 6002400 ) N ;
+ - io_in[22] + NET io_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1093680 6002400 ) N ;
+ - io_in[23] + NET io_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 430640 6002400 ) N ;
+ - io_in[24] + NET io_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5826800 ) N ;
+ - io_in[25] + NET io_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5383280 ) N ;
+ - io_in[26] + NET io_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4939760 ) N ;
+ - io_in[27] + NET io_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4496240 ) N ;
+ - io_in[28] + NET io_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4052720 ) N ;
+ - io_in[29] + NET io_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3609200 ) N ;
+ - io_in[2] + NET io_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 737520 ) N ;
+ - io_in[30] + NET io_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3165680 ) N ;
+ - io_in[31] + NET io_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2722160 ) N ;
+ - io_in[32] + NET io_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2278640 ) N ;
+ - io_in[33] + NET io_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1835120 ) N ;
+ - io_in[34] + NET io_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1391600 ) N ;
+ - io_in[35] + NET io_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 948080 ) N ;
+ - io_in[36] + NET io_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 615440 ) N ;
+ - io_in[37] + NET io_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 282800 ) N ;
+ - io_in[3] + NET io_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1076880 ) N ;
+ - io_in[4] + NET io_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1416240 ) N ;
+ - io_in[5] + NET io_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1755600 ) N ;
+ - io_in[6] + NET io_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2094960 ) N ;
+ - io_in[7] + NET io_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2547440 ) N ;
+ - io_in[8] + NET io_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2999920 ) N ;
+ - io_in[9] + NET io_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3452400 ) N ;
+ - io_oeb[0] + NET io_oeb[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 285040 ) N ;
+ - io_oeb[10] + NET io_oeb[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4131120 ) N ;
+ - io_oeb[11] + NET io_oeb[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4583600 ) N ;
+ - io_oeb[12] + NET io_oeb[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5036080 ) N ;
+ - io_oeb[13] + NET io_oeb[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5488560 ) N ;
+ - io_oeb[14] + NET io_oeb[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5941040 ) N ;
+ - io_oeb[15] + NET io_oeb[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5403440 6002400 ) N ;
+ - io_oeb[16] + NET io_oeb[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4740400 6002400 ) N ;
+ - io_oeb[17] + NET io_oeb[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4077360 6002400 ) N ;
+ - io_oeb[18] + NET io_oeb[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3414320 6002400 ) N ;
+ - io_oeb[19] + NET io_oeb[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2751280 6002400 ) N ;
+ - io_oeb[1] + NET io_oeb[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 624400 ) N ;
+ - io_oeb[20] + NET io_oeb[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2088240 6002400 ) N ;
+ - io_oeb[21] + NET io_oeb[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1425200 6002400 ) N ;
+ - io_oeb[22] + NET io_oeb[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 762160 6002400 ) N ;
+ - io_oeb[23] + NET io_oeb[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 99120 6002400 ) N ;
+ - io_oeb[24] + NET io_oeb[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5605040 ) N ;
+ - io_oeb[25] + NET io_oeb[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5161520 ) N ;
+ - io_oeb[26] + NET io_oeb[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4718000 ) N ;
+ - io_oeb[27] + NET io_oeb[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4274480 ) N ;
+ - io_oeb[28] + NET io_oeb[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3830960 ) N ;
+ - io_oeb[29] + NET io_oeb[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3387440 ) N ;
+ - io_oeb[2] + NET io_oeb[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 963760 ) N ;
+ - io_oeb[30] + NET io_oeb[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2943920 ) N ;
+ - io_oeb[31] + NET io_oeb[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2500400 ) N ;
+ - io_oeb[32] + NET io_oeb[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2056880 ) N ;
+ - io_oeb[33] + NET io_oeb[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1613360 ) N ;
+ - io_oeb[34] + NET io_oeb[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1169840 ) N ;
+ - io_oeb[35] + NET io_oeb[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 726320 ) N ;
+ - io_oeb[36] + NET io_oeb[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 393680 ) N ;
+ - io_oeb[37] + NET io_oeb[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 61040 ) N ;
+ - io_oeb[3] + NET io_oeb[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1303120 ) N ;
+ - io_oeb[4] + NET io_oeb[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1642480 ) N ;
+ - io_oeb[5] + NET io_oeb[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1981840 ) N ;
+ - io_oeb[6] + NET io_oeb[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2321200 ) N ;
+ - io_oeb[7] + NET io_oeb[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2773680 ) N ;
+ - io_oeb[8] + NET io_oeb[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3226160 ) N ;
+ - io_oeb[9] + NET io_oeb[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3678640 ) N ;
+ - io_out[0] + NET io_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 171920 ) N ;
+ - io_out[10] + NET io_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4018000 ) N ;
+ - io_out[11] + NET io_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4470480 ) N ;
+ - io_out[12] + NET io_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 4922960 ) N ;
+ - io_out[13] + NET io_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5375440 ) N ;
+ - io_out[14] + NET io_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 5827920 ) N ;
+ - io_out[15] + NET io_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5569200 6002400 ) N ;
+ - io_out[16] + NET io_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4906160 6002400 ) N ;
+ - io_out[17] + NET io_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4243120 6002400 ) N ;
+ - io_out[18] + NET io_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3580080 6002400 ) N ;
+ - io_out[19] + NET io_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2917040 6002400 ) N ;
+ - io_out[1] + NET io_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 511280 ) N ;
+ - io_out[20] + NET io_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2254000 6002400 ) N ;
+ - io_out[21] + NET io_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1590960 6002400 ) N ;
+ - io_out[22] + NET io_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 927920 6002400 ) N ;
+ - io_out[23] + NET io_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 264880 6002400 ) N ;
+ - io_out[24] + NET io_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5715920 ) N ;
+ - io_out[25] + NET io_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 5272400 ) N ;
+ - io_out[26] + NET io_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4828880 ) N ;
+ - io_out[27] + NET io_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 4385360 ) N ;
+ - io_out[28] + NET io_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3941840 ) N ;
+ - io_out[29] + NET io_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3498320 ) N ;
+ - io_out[2] + NET io_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 850640 ) N ;
+ - io_out[30] + NET io_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 3054800 ) N ;
+ - io_out[31] + NET io_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2611280 ) N ;
+ - io_out[32] + NET io_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 2167760 ) N ;
+ - io_out[33] + NET io_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1724240 ) N ;
+ - io_out[34] + NET io_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 1280720 ) N ;
+ - io_out[35] + NET io_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 837200 ) N ;
+ - io_out[36] + NET io_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 504560 ) N ;
+ - io_out[37] + NET io_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( -2400 171920 ) N ;
+ - io_out[3] + NET io_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1190000 ) N ;
+ - io_out[4] + NET io_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1529360 ) N ;
+ - io_out[5] + NET io_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 1868720 ) N ;
+ - io_out[6] + NET io_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2208080 ) N ;
+ - io_out[7] + NET io_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 2660560 ) N ;
+ - io_out[8] + NET io_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3113040 ) N ;
+ - io_out[9] + NET io_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -7200 -1120 ) ( 7200 1120 )
+ + PLACED ( 6002400 3565520 ) N ;
+ - la_data_in[0] + NET la_data_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1426320 -2400 ) N ;
+ - la_data_in[100] + NET la_data_in[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4786320 -2400 ) N ;
+ - la_data_in[101] + NET la_data_in[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4819920 -2400 ) N ;
+ - la_data_in[102] + NET la_data_in[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4853520 -2400 ) N ;
+ - la_data_in[103] + NET la_data_in[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4887120 -2400 ) N ;
+ - la_data_in[104] + NET la_data_in[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4920720 -2400 ) N ;
+ - la_data_in[105] + NET la_data_in[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4954320 -2400 ) N ;
+ - la_data_in[106] + NET la_data_in[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4987920 -2400 ) N ;
+ - la_data_in[107] + NET la_data_in[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5021520 -2400 ) N ;
+ - la_data_in[108] + NET la_data_in[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5055120 -2400 ) N ;
+ - la_data_in[109] + NET la_data_in[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5088720 -2400 ) N ;
+ - la_data_in[10] + NET la_data_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1762320 -2400 ) N ;
+ - la_data_in[110] + NET la_data_in[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5122320 -2400 ) N ;
+ - la_data_in[111] + NET la_data_in[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5155920 -2400 ) N ;
+ - la_data_in[112] + NET la_data_in[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5189520 -2400 ) N ;
+ - la_data_in[113] + NET la_data_in[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5223120 -2400 ) N ;
+ - la_data_in[114] + NET la_data_in[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5256720 -2400 ) N ;
+ - la_data_in[115] + NET la_data_in[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5290320 -2400 ) N ;
+ - la_data_in[116] + NET la_data_in[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5323920 -2400 ) N ;
+ - la_data_in[117] + NET la_data_in[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5357520 -2400 ) N ;
+ - la_data_in[118] + NET la_data_in[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5391120 -2400 ) N ;
+ - la_data_in[119] + NET la_data_in[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5424720 -2400 ) N ;
+ - la_data_in[11] + NET la_data_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1795920 -2400 ) N ;
+ - la_data_in[120] + NET la_data_in[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5458320 -2400 ) N ;
+ - la_data_in[121] + NET la_data_in[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5491920 -2400 ) N ;
+ - la_data_in[122] + NET la_data_in[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5525520 -2400 ) N ;
+ - la_data_in[123] + NET la_data_in[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5559120 -2400 ) N ;
+ - la_data_in[124] + NET la_data_in[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5592720 -2400 ) N ;
+ - la_data_in[125] + NET la_data_in[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5626320 -2400 ) N ;
+ - la_data_in[126] + NET la_data_in[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5659920 -2400 ) N ;
+ - la_data_in[127] + NET la_data_in[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5693520 -2400 ) N ;
+ - la_data_in[12] + NET la_data_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1829520 -2400 ) N ;
+ - la_data_in[13] + NET la_data_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1863120 -2400 ) N ;
+ - la_data_in[14] + NET la_data_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1896720 -2400 ) N ;
+ - la_data_in[15] + NET la_data_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1930320 -2400 ) N ;
+ - la_data_in[16] + NET la_data_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1963920 -2400 ) N ;
+ - la_data_in[17] + NET la_data_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1997520 -2400 ) N ;
+ - la_data_in[18] + NET la_data_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2031120 -2400 ) N ;
+ - la_data_in[19] + NET la_data_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2064720 -2400 ) N ;
+ - la_data_in[1] + NET la_data_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1459920 -2400 ) N ;
+ - la_data_in[20] + NET la_data_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2098320 -2400 ) N ;
+ - la_data_in[21] + NET la_data_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2131920 -2400 ) N ;
+ - la_data_in[22] + NET la_data_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2165520 -2400 ) N ;
+ - la_data_in[23] + NET la_data_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2199120 -2400 ) N ;
+ - la_data_in[24] + NET la_data_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2232720 -2400 ) N ;
+ - la_data_in[25] + NET la_data_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2266320 -2400 ) N ;
+ - la_data_in[26] + NET la_data_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2299920 -2400 ) N ;
+ - la_data_in[27] + NET la_data_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2333520 -2400 ) N ;
+ - la_data_in[28] + NET la_data_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2367120 -2400 ) N ;
+ - la_data_in[29] + NET la_data_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2400720 -2400 ) N ;
+ - la_data_in[2] + NET la_data_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1493520 -2400 ) N ;
+ - la_data_in[30] + NET la_data_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2434320 -2400 ) N ;
+ - la_data_in[31] + NET la_data_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2467920 -2400 ) N ;
+ - la_data_in[32] + NET la_data_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2501520 -2400 ) N ;
+ - la_data_in[33] + NET la_data_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2535120 -2400 ) N ;
+ - la_data_in[34] + NET la_data_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2568720 -2400 ) N ;
+ - la_data_in[35] + NET la_data_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2602320 -2400 ) N ;
+ - la_data_in[36] + NET la_data_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2635920 -2400 ) N ;
+ - la_data_in[37] + NET la_data_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2669520 -2400 ) N ;
+ - la_data_in[38] + NET la_data_in[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2703120 -2400 ) N ;
+ - la_data_in[39] + NET la_data_in[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2736720 -2400 ) N ;
+ - la_data_in[3] + NET la_data_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1527120 -2400 ) N ;
+ - la_data_in[40] + NET la_data_in[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2770320 -2400 ) N ;
+ - la_data_in[41] + NET la_data_in[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2803920 -2400 ) N ;
+ - la_data_in[42] + NET la_data_in[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2837520 -2400 ) N ;
+ - la_data_in[43] + NET la_data_in[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2871120 -2400 ) N ;
+ - la_data_in[44] + NET la_data_in[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2904720 -2400 ) N ;
+ - la_data_in[45] + NET la_data_in[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2938320 -2400 ) N ;
+ - la_data_in[46] + NET la_data_in[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2971920 -2400 ) N ;
+ - la_data_in[47] + NET la_data_in[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3005520 -2400 ) N ;
+ - la_data_in[48] + NET la_data_in[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3039120 -2400 ) N ;
+ - la_data_in[49] + NET la_data_in[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3072720 -2400 ) N ;
+ - la_data_in[4] + NET la_data_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1560720 -2400 ) N ;
+ - la_data_in[50] + NET la_data_in[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3106320 -2400 ) N ;
+ - la_data_in[51] + NET la_data_in[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3139920 -2400 ) N ;
+ - la_data_in[52] + NET la_data_in[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3173520 -2400 ) N ;
+ - la_data_in[53] + NET la_data_in[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3207120 -2400 ) N ;
+ - la_data_in[54] + NET la_data_in[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3240720 -2400 ) N ;
+ - la_data_in[55] + NET la_data_in[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3274320 -2400 ) N ;
+ - la_data_in[56] + NET la_data_in[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3307920 -2400 ) N ;
+ - la_data_in[57] + NET la_data_in[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3341520 -2400 ) N ;
+ - la_data_in[58] + NET la_data_in[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3375120 -2400 ) N ;
+ - la_data_in[59] + NET la_data_in[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3408720 -2400 ) N ;
+ - la_data_in[5] + NET la_data_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1594320 -2400 ) N ;
+ - la_data_in[60] + NET la_data_in[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3442320 -2400 ) N ;
+ - la_data_in[61] + NET la_data_in[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3475920 -2400 ) N ;
+ - la_data_in[62] + NET la_data_in[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3509520 -2400 ) N ;
+ - la_data_in[63] + NET la_data_in[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3543120 -2400 ) N ;
+ - la_data_in[64] + NET la_data_in[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3576720 -2400 ) N ;
+ - la_data_in[65] + NET la_data_in[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3610320 -2400 ) N ;
+ - la_data_in[66] + NET la_data_in[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3643920 -2400 ) N ;
+ - la_data_in[67] + NET la_data_in[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3677520 -2400 ) N ;
+ - la_data_in[68] + NET la_data_in[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3711120 -2400 ) N ;
+ - la_data_in[69] + NET la_data_in[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3744720 -2400 ) N ;
+ - la_data_in[6] + NET la_data_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1627920 -2400 ) N ;
+ - la_data_in[70] + NET la_data_in[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3778320 -2400 ) N ;
+ - la_data_in[71] + NET la_data_in[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3811920 -2400 ) N ;
+ - la_data_in[72] + NET la_data_in[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3845520 -2400 ) N ;
+ - la_data_in[73] + NET la_data_in[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3879120 -2400 ) N ;
+ - la_data_in[74] + NET la_data_in[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3912720 -2400 ) N ;
+ - la_data_in[75] + NET la_data_in[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3946320 -2400 ) N ;
+ - la_data_in[76] + NET la_data_in[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3979920 -2400 ) N ;
+ - la_data_in[77] + NET la_data_in[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4013520 -2400 ) N ;
+ - la_data_in[78] + NET la_data_in[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4047120 -2400 ) N ;
+ - la_data_in[79] + NET la_data_in[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4080720 -2400 ) N ;
+ - la_data_in[7] + NET la_data_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1661520 -2400 ) N ;
+ - la_data_in[80] + NET la_data_in[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4114320 -2400 ) N ;
+ - la_data_in[81] + NET la_data_in[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4147920 -2400 ) N ;
+ - la_data_in[82] + NET la_data_in[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4181520 -2400 ) N ;
+ - la_data_in[83] + NET la_data_in[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4215120 -2400 ) N ;
+ - la_data_in[84] + NET la_data_in[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4248720 -2400 ) N ;
+ - la_data_in[85] + NET la_data_in[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4282320 -2400 ) N ;
+ - la_data_in[86] + NET la_data_in[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4315920 -2400 ) N ;
+ - la_data_in[87] + NET la_data_in[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4349520 -2400 ) N ;
+ - la_data_in[88] + NET la_data_in[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4383120 -2400 ) N ;
+ - la_data_in[89] + NET la_data_in[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4416720 -2400 ) N ;
+ - la_data_in[8] + NET la_data_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1695120 -2400 ) N ;
+ - la_data_in[90] + NET la_data_in[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4450320 -2400 ) N ;
+ - la_data_in[91] + NET la_data_in[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4483920 -2400 ) N ;
+ - la_data_in[92] + NET la_data_in[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4517520 -2400 ) N ;
+ - la_data_in[93] + NET la_data_in[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4551120 -2400 ) N ;
+ - la_data_in[94] + NET la_data_in[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4584720 -2400 ) N ;
+ - la_data_in[95] + NET la_data_in[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4618320 -2400 ) N ;
+ - la_data_in[96] + NET la_data_in[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4651920 -2400 ) N ;
+ - la_data_in[97] + NET la_data_in[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4685520 -2400 ) N ;
+ - la_data_in[98] + NET la_data_in[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4719120 -2400 ) N ;
+ - la_data_in[99] + NET la_data_in[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4752720 -2400 ) N ;
+ - la_data_in[9] + NET la_data_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1728720 -2400 ) N ;
+ - la_data_out[0] + NET la_data_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1437520 -2400 ) N ;
+ - la_data_out[100] + NET la_data_out[100] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4797520 -2400 ) N ;
+ - la_data_out[101] + NET la_data_out[101] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4831120 -2400 ) N ;
+ - la_data_out[102] + NET la_data_out[102] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4864720 -2400 ) N ;
+ - la_data_out[103] + NET la_data_out[103] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4898320 -2400 ) N ;
+ - la_data_out[104] + NET la_data_out[104] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4931920 -2400 ) N ;
+ - la_data_out[105] + NET la_data_out[105] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4965520 -2400 ) N ;
+ - la_data_out[106] + NET la_data_out[106] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4999120 -2400 ) N ;
+ - la_data_out[107] + NET la_data_out[107] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5032720 -2400 ) N ;
+ - la_data_out[108] + NET la_data_out[108] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5066320 -2400 ) N ;
+ - la_data_out[109] + NET la_data_out[109] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5099920 -2400 ) N ;
+ - la_data_out[10] + NET la_data_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1773520 -2400 ) N ;
+ - la_data_out[110] + NET la_data_out[110] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5133520 -2400 ) N ;
+ - la_data_out[111] + NET la_data_out[111] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5167120 -2400 ) N ;
+ - la_data_out[112] + NET la_data_out[112] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5200720 -2400 ) N ;
+ - la_data_out[113] + NET la_data_out[113] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5234320 -2400 ) N ;
+ - la_data_out[114] + NET la_data_out[114] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5267920 -2400 ) N ;
+ - la_data_out[115] + NET la_data_out[115] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5301520 -2400 ) N ;
+ - la_data_out[116] + NET la_data_out[116] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5335120 -2400 ) N ;
+ - la_data_out[117] + NET la_data_out[117] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5368720 -2400 ) N ;
+ - la_data_out[118] + NET la_data_out[118] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5402320 -2400 ) N ;
+ - la_data_out[119] + NET la_data_out[119] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5435920 -2400 ) N ;
+ - la_data_out[11] + NET la_data_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1807120 -2400 ) N ;
+ - la_data_out[120] + NET la_data_out[120] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5469520 -2400 ) N ;
+ - la_data_out[121] + NET la_data_out[121] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5503120 -2400 ) N ;
+ - la_data_out[122] + NET la_data_out[122] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5536720 -2400 ) N ;
+ - la_data_out[123] + NET la_data_out[123] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5570320 -2400 ) N ;
+ - la_data_out[124] + NET la_data_out[124] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5603920 -2400 ) N ;
+ - la_data_out[125] + NET la_data_out[125] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5637520 -2400 ) N ;
+ - la_data_out[126] + NET la_data_out[126] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5671120 -2400 ) N ;
+ - la_data_out[127] + NET la_data_out[127] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5704720 -2400 ) N ;
+ - la_data_out[12] + NET la_data_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1840720 -2400 ) N ;
+ - la_data_out[13] + NET la_data_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1874320 -2400 ) N ;
+ - la_data_out[14] + NET la_data_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1907920 -2400 ) N ;
+ - la_data_out[15] + NET la_data_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1941520 -2400 ) N ;
+ - la_data_out[16] + NET la_data_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1975120 -2400 ) N ;
+ - la_data_out[17] + NET la_data_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2008720 -2400 ) N ;
+ - la_data_out[18] + NET la_data_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2042320 -2400 ) N ;
+ - la_data_out[19] + NET la_data_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2075920 -2400 ) N ;
+ - la_data_out[1] + NET la_data_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1471120 -2400 ) N ;
+ - la_data_out[20] + NET la_data_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2109520 -2400 ) N ;
+ - la_data_out[21] + NET la_data_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2143120 -2400 ) N ;
+ - la_data_out[22] + NET la_data_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2176720 -2400 ) N ;
+ - la_data_out[23] + NET la_data_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2210320 -2400 ) N ;
+ - la_data_out[24] + NET la_data_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2243920 -2400 ) N ;
+ - la_data_out[25] + NET la_data_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2277520 -2400 ) N ;
+ - la_data_out[26] + NET la_data_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2311120 -2400 ) N ;
+ - la_data_out[27] + NET la_data_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2344720 -2400 ) N ;
+ - la_data_out[28] + NET la_data_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2378320 -2400 ) N ;
+ - la_data_out[29] + NET la_data_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2411920 -2400 ) N ;
+ - la_data_out[2] + NET la_data_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1504720 -2400 ) N ;
+ - la_data_out[30] + NET la_data_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2445520 -2400 ) N ;
+ - la_data_out[31] + NET la_data_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2479120 -2400 ) N ;
+ - la_data_out[32] + NET la_data_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2512720 -2400 ) N ;
+ - la_data_out[33] + NET la_data_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2546320 -2400 ) N ;
+ - la_data_out[34] + NET la_data_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2579920 -2400 ) N ;
+ - la_data_out[35] + NET la_data_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2613520 -2400 ) N ;
+ - la_data_out[36] + NET la_data_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2647120 -2400 ) N ;
+ - la_data_out[37] + NET la_data_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2680720 -2400 ) N ;
+ - la_data_out[38] + NET la_data_out[38] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2714320 -2400 ) N ;
+ - la_data_out[39] + NET la_data_out[39] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2747920 -2400 ) N ;
+ - la_data_out[3] + NET la_data_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1538320 -2400 ) N ;
+ - la_data_out[40] + NET la_data_out[40] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2781520 -2400 ) N ;
+ - la_data_out[41] + NET la_data_out[41] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2815120 -2400 ) N ;
+ - la_data_out[42] + NET la_data_out[42] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2848720 -2400 ) N ;
+ - la_data_out[43] + NET la_data_out[43] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2882320 -2400 ) N ;
+ - la_data_out[44] + NET la_data_out[44] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2915920 -2400 ) N ;
+ - la_data_out[45] + NET la_data_out[45] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2949520 -2400 ) N ;
+ - la_data_out[46] + NET la_data_out[46] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2983120 -2400 ) N ;
+ - la_data_out[47] + NET la_data_out[47] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3016720 -2400 ) N ;
+ - la_data_out[48] + NET la_data_out[48] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3050320 -2400 ) N ;
+ - la_data_out[49] + NET la_data_out[49] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3083920 -2400 ) N ;
+ - la_data_out[4] + NET la_data_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1571920 -2400 ) N ;
+ - la_data_out[50] + NET la_data_out[50] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3117520 -2400 ) N ;
+ - la_data_out[51] + NET la_data_out[51] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3151120 -2400 ) N ;
+ - la_data_out[52] + NET la_data_out[52] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3184720 -2400 ) N ;
+ - la_data_out[53] + NET la_data_out[53] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3218320 -2400 ) N ;
+ - la_data_out[54] + NET la_data_out[54] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3251920 -2400 ) N ;
+ - la_data_out[55] + NET la_data_out[55] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3285520 -2400 ) N ;
+ - la_data_out[56] + NET la_data_out[56] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3319120 -2400 ) N ;
+ - la_data_out[57] + NET la_data_out[57] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3352720 -2400 ) N ;
+ - la_data_out[58] + NET la_data_out[58] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3386320 -2400 ) N ;
+ - la_data_out[59] + NET la_data_out[59] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3419920 -2400 ) N ;
+ - la_data_out[5] + NET la_data_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1605520 -2400 ) N ;
+ - la_data_out[60] + NET la_data_out[60] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3453520 -2400 ) N ;
+ - la_data_out[61] + NET la_data_out[61] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3487120 -2400 ) N ;
+ - la_data_out[62] + NET la_data_out[62] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3520720 -2400 ) N ;
+ - la_data_out[63] + NET la_data_out[63] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3554320 -2400 ) N ;
+ - la_data_out[64] + NET la_data_out[64] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3587920 -2400 ) N ;
+ - la_data_out[65] + NET la_data_out[65] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3621520 -2400 ) N ;
+ - la_data_out[66] + NET la_data_out[66] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3655120 -2400 ) N ;
+ - la_data_out[67] + NET la_data_out[67] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3688720 -2400 ) N ;
+ - la_data_out[68] + NET la_data_out[68] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3722320 -2400 ) N ;
+ - la_data_out[69] + NET la_data_out[69] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3755920 -2400 ) N ;
+ - la_data_out[6] + NET la_data_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1639120 -2400 ) N ;
+ - la_data_out[70] + NET la_data_out[70] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3789520 -2400 ) N ;
+ - la_data_out[71] + NET la_data_out[71] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3823120 -2400 ) N ;
+ - la_data_out[72] + NET la_data_out[72] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3856720 -2400 ) N ;
+ - la_data_out[73] + NET la_data_out[73] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3890320 -2400 ) N ;
+ - la_data_out[74] + NET la_data_out[74] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3923920 -2400 ) N ;
+ - la_data_out[75] + NET la_data_out[75] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3957520 -2400 ) N ;
+ - la_data_out[76] + NET la_data_out[76] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3991120 -2400 ) N ;
+ - la_data_out[77] + NET la_data_out[77] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4024720 -2400 ) N ;
+ - la_data_out[78] + NET la_data_out[78] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4058320 -2400 ) N ;
+ - la_data_out[79] + NET la_data_out[79] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4091920 -2400 ) N ;
+ - la_data_out[7] + NET la_data_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1672720 -2400 ) N ;
+ - la_data_out[80] + NET la_data_out[80] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4125520 -2400 ) N ;
+ - la_data_out[81] + NET la_data_out[81] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4159120 -2400 ) N ;
+ - la_data_out[82] + NET la_data_out[82] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4192720 -2400 ) N ;
+ - la_data_out[83] + NET la_data_out[83] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4226320 -2400 ) N ;
+ - la_data_out[84] + NET la_data_out[84] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4259920 -2400 ) N ;
+ - la_data_out[85] + NET la_data_out[85] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4293520 -2400 ) N ;
+ - la_data_out[86] + NET la_data_out[86] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4327120 -2400 ) N ;
+ - la_data_out[87] + NET la_data_out[87] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4360720 -2400 ) N ;
+ - la_data_out[88] + NET la_data_out[88] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4394320 -2400 ) N ;
+ - la_data_out[89] + NET la_data_out[89] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4427920 -2400 ) N ;
+ - la_data_out[8] + NET la_data_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1706320 -2400 ) N ;
+ - la_data_out[90] + NET la_data_out[90] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4461520 -2400 ) N ;
+ - la_data_out[91] + NET la_data_out[91] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4495120 -2400 ) N ;
+ - la_data_out[92] + NET la_data_out[92] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4528720 -2400 ) N ;
+ - la_data_out[93] + NET la_data_out[93] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4562320 -2400 ) N ;
+ - la_data_out[94] + NET la_data_out[94] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4595920 -2400 ) N ;
+ - la_data_out[95] + NET la_data_out[95] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4629520 -2400 ) N ;
+ - la_data_out[96] + NET la_data_out[96] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4663120 -2400 ) N ;
+ - la_data_out[97] + NET la_data_out[97] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4696720 -2400 ) N ;
+ - la_data_out[98] + NET la_data_out[98] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4730320 -2400 ) N ;
+ - la_data_out[99] + NET la_data_out[99] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4763920 -2400 ) N ;
+ - la_data_out[9] + NET la_data_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1739920 -2400 ) N ;
+ - la_oenb[0] + NET la_oenb[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1448720 -2400 ) N ;
+ - la_oenb[100] + NET la_oenb[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4808720 -2400 ) N ;
+ - la_oenb[101] + NET la_oenb[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4842320 -2400 ) N ;
+ - la_oenb[102] + NET la_oenb[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4875920 -2400 ) N ;
+ - la_oenb[103] + NET la_oenb[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4909520 -2400 ) N ;
+ - la_oenb[104] + NET la_oenb[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4943120 -2400 ) N ;
+ - la_oenb[105] + NET la_oenb[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4976720 -2400 ) N ;
+ - la_oenb[106] + NET la_oenb[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5010320 -2400 ) N ;
+ - la_oenb[107] + NET la_oenb[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5043920 -2400 ) N ;
+ - la_oenb[108] + NET la_oenb[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5077520 -2400 ) N ;
+ - la_oenb[109] + NET la_oenb[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5111120 -2400 ) N ;
+ - la_oenb[10] + NET la_oenb[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1784720 -2400 ) N ;
+ - la_oenb[110] + NET la_oenb[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5144720 -2400 ) N ;
+ - la_oenb[111] + NET la_oenb[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5178320 -2400 ) N ;
+ - la_oenb[112] + NET la_oenb[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5211920 -2400 ) N ;
+ - la_oenb[113] + NET la_oenb[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5245520 -2400 ) N ;
+ - la_oenb[114] + NET la_oenb[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5279120 -2400 ) N ;
+ - la_oenb[115] + NET la_oenb[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5312720 -2400 ) N ;
+ - la_oenb[116] + NET la_oenb[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5346320 -2400 ) N ;
+ - la_oenb[117] + NET la_oenb[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5379920 -2400 ) N ;
+ - la_oenb[118] + NET la_oenb[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5413520 -2400 ) N ;
+ - la_oenb[119] + NET la_oenb[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5447120 -2400 ) N ;
+ - la_oenb[11] + NET la_oenb[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1818320 -2400 ) N ;
+ - la_oenb[120] + NET la_oenb[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5480720 -2400 ) N ;
+ - la_oenb[121] + NET la_oenb[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5514320 -2400 ) N ;
+ - la_oenb[122] + NET la_oenb[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5547920 -2400 ) N ;
+ - la_oenb[123] + NET la_oenb[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5581520 -2400 ) N ;
+ - la_oenb[124] + NET la_oenb[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5615120 -2400 ) N ;
+ - la_oenb[125] + NET la_oenb[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5648720 -2400 ) N ;
+ - la_oenb[126] + NET la_oenb[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5682320 -2400 ) N ;
+ - la_oenb[127] + NET la_oenb[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5715920 -2400 ) N ;
+ - la_oenb[12] + NET la_oenb[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1851920 -2400 ) N ;
+ - la_oenb[13] + NET la_oenb[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1885520 -2400 ) N ;
+ - la_oenb[14] + NET la_oenb[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1919120 -2400 ) N ;
+ - la_oenb[15] + NET la_oenb[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1952720 -2400 ) N ;
+ - la_oenb[16] + NET la_oenb[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1986320 -2400 ) N ;
+ - la_oenb[17] + NET la_oenb[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2019920 -2400 ) N ;
+ - la_oenb[18] + NET la_oenb[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2053520 -2400 ) N ;
+ - la_oenb[19] + NET la_oenb[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2087120 -2400 ) N ;
+ - la_oenb[1] + NET la_oenb[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1482320 -2400 ) N ;
+ - la_oenb[20] + NET la_oenb[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2120720 -2400 ) N ;
+ - la_oenb[21] + NET la_oenb[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2154320 -2400 ) N ;
+ - la_oenb[22] + NET la_oenb[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2187920 -2400 ) N ;
+ - la_oenb[23] + NET la_oenb[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2221520 -2400 ) N ;
+ - la_oenb[24] + NET la_oenb[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2255120 -2400 ) N ;
+ - la_oenb[25] + NET la_oenb[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2288720 -2400 ) N ;
+ - la_oenb[26] + NET la_oenb[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2322320 -2400 ) N ;
+ - la_oenb[27] + NET la_oenb[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2355920 -2400 ) N ;
+ - la_oenb[28] + NET la_oenb[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2389520 -2400 ) N ;
+ - la_oenb[29] + NET la_oenb[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2423120 -2400 ) N ;
+ - la_oenb[2] + NET la_oenb[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1515920 -2400 ) N ;
+ - la_oenb[30] + NET la_oenb[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2456720 -2400 ) N ;
+ - la_oenb[31] + NET la_oenb[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2490320 -2400 ) N ;
+ - la_oenb[32] + NET la_oenb[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2523920 -2400 ) N ;
+ - la_oenb[33] + NET la_oenb[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2557520 -2400 ) N ;
+ - la_oenb[34] + NET la_oenb[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2591120 -2400 ) N ;
+ - la_oenb[35] + NET la_oenb[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2624720 -2400 ) N ;
+ - la_oenb[36] + NET la_oenb[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2658320 -2400 ) N ;
+ - la_oenb[37] + NET la_oenb[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2691920 -2400 ) N ;
+ - la_oenb[38] + NET la_oenb[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2725520 -2400 ) N ;
+ - la_oenb[39] + NET la_oenb[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2759120 -2400 ) N ;
+ - la_oenb[3] + NET la_oenb[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1549520 -2400 ) N ;
+ - la_oenb[40] + NET la_oenb[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2792720 -2400 ) N ;
+ - la_oenb[41] + NET la_oenb[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2826320 -2400 ) N ;
+ - la_oenb[42] + NET la_oenb[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2859920 -2400 ) N ;
+ - la_oenb[43] + NET la_oenb[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2893520 -2400 ) N ;
+ - la_oenb[44] + NET la_oenb[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2927120 -2400 ) N ;
+ - la_oenb[45] + NET la_oenb[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2960720 -2400 ) N ;
+ - la_oenb[46] + NET la_oenb[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 2994320 -2400 ) N ;
+ - la_oenb[47] + NET la_oenb[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3027920 -2400 ) N ;
+ - la_oenb[48] + NET la_oenb[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3061520 -2400 ) N ;
+ - la_oenb[49] + NET la_oenb[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3095120 -2400 ) N ;
+ - la_oenb[4] + NET la_oenb[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1583120 -2400 ) N ;
+ - la_oenb[50] + NET la_oenb[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3128720 -2400 ) N ;
+ - la_oenb[51] + NET la_oenb[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3162320 -2400 ) N ;
+ - la_oenb[52] + NET la_oenb[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3195920 -2400 ) N ;
+ - la_oenb[53] + NET la_oenb[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3229520 -2400 ) N ;
+ - la_oenb[54] + NET la_oenb[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3263120 -2400 ) N ;
+ - la_oenb[55] + NET la_oenb[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3296720 -2400 ) N ;
+ - la_oenb[56] + NET la_oenb[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3330320 -2400 ) N ;
+ - la_oenb[57] + NET la_oenb[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3363920 -2400 ) N ;
+ - la_oenb[58] + NET la_oenb[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3397520 -2400 ) N ;
+ - la_oenb[59] + NET la_oenb[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3431120 -2400 ) N ;
+ - la_oenb[5] + NET la_oenb[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1616720 -2400 ) N ;
+ - la_oenb[60] + NET la_oenb[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3464720 -2400 ) N ;
+ - la_oenb[61] + NET la_oenb[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3498320 -2400 ) N ;
+ - la_oenb[62] + NET la_oenb[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3531920 -2400 ) N ;
+ - la_oenb[63] + NET la_oenb[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3565520 -2400 ) N ;
+ - la_oenb[64] + NET la_oenb[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3599120 -2400 ) N ;
+ - la_oenb[65] + NET la_oenb[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3632720 -2400 ) N ;
+ - la_oenb[66] + NET la_oenb[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3666320 -2400 ) N ;
+ - la_oenb[67] + NET la_oenb[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3699920 -2400 ) N ;
+ - la_oenb[68] + NET la_oenb[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3733520 -2400 ) N ;
+ - la_oenb[69] + NET la_oenb[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3767120 -2400 ) N ;
+ - la_oenb[6] + NET la_oenb[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1650320 -2400 ) N ;
+ - la_oenb[70] + NET la_oenb[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3800720 -2400 ) N ;
+ - la_oenb[71] + NET la_oenb[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3834320 -2400 ) N ;
+ - la_oenb[72] + NET la_oenb[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3867920 -2400 ) N ;
+ - la_oenb[73] + NET la_oenb[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3901520 -2400 ) N ;
+ - la_oenb[74] + NET la_oenb[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3935120 -2400 ) N ;
+ - la_oenb[75] + NET la_oenb[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 3968720 -2400 ) N ;
+ - la_oenb[76] + NET la_oenb[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4002320 -2400 ) N ;
+ - la_oenb[77] + NET la_oenb[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4035920 -2400 ) N ;
+ - la_oenb[78] + NET la_oenb[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4069520 -2400 ) N ;
+ - la_oenb[79] + NET la_oenb[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4103120 -2400 ) N ;
+ - la_oenb[7] + NET la_oenb[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1683920 -2400 ) N ;
+ - la_oenb[80] + NET la_oenb[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4136720 -2400 ) N ;
+ - la_oenb[81] + NET la_oenb[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4170320 -2400 ) N ;
+ - la_oenb[82] + NET la_oenb[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4203920 -2400 ) N ;
+ - la_oenb[83] + NET la_oenb[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4237520 -2400 ) N ;
+ - la_oenb[84] + NET la_oenb[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4271120 -2400 ) N ;
+ - la_oenb[85] + NET la_oenb[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4304720 -2400 ) N ;
+ - la_oenb[86] + NET la_oenb[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4338320 -2400 ) N ;
+ - la_oenb[87] + NET la_oenb[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4371920 -2400 ) N ;
+ - la_oenb[88] + NET la_oenb[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4405520 -2400 ) N ;
+ - la_oenb[89] + NET la_oenb[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4439120 -2400 ) N ;
+ - la_oenb[8] + NET la_oenb[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1717520 -2400 ) N ;
+ - la_oenb[90] + NET la_oenb[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4472720 -2400 ) N ;
+ - la_oenb[91] + NET la_oenb[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4506320 -2400 ) N ;
+ - la_oenb[92] + NET la_oenb[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4539920 -2400 ) N ;
+ - la_oenb[93] + NET la_oenb[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4573520 -2400 ) N ;
+ - la_oenb[94] + NET la_oenb[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4607120 -2400 ) N ;
+ - la_oenb[95] + NET la_oenb[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4640720 -2400 ) N ;
+ - la_oenb[96] + NET la_oenb[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4674320 -2400 ) N ;
+ - la_oenb[97] + NET la_oenb[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4707920 -2400 ) N ;
+ - la_oenb[98] + NET la_oenb[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4741520 -2400 ) N ;
+ - la_oenb[99] + NET la_oenb[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 4775120 -2400 ) N ;
+ - la_oenb[9] + NET la_oenb[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1751120 -2400 ) N ;
+ - user_clock2 + NET user_clock2 + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5727120 -2400 ) N ;
+ - user_irq[0] + NET user_irq[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5738320 -2400 ) N ;
+ - user_irq[1] + NET user_irq[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5749520 -2400 ) N ;
+ - user_irq[2] + NET user_irq[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 5760720 -2400 ) N ;
+ - vccd1 + NET vccd1 + SPECIAL + DIRECTION INOUT + USE POWER
+ + PORT
+ + LAYER Metal5 ( -3235280 -3100 ) ( 3235280 3100 )
+ + LAYER Metal5 ( -3235280 -363100 ) ( 3235280 -356900 )
+ + LAYER Metal5 ( -3235280 -723100 ) ( 3235280 -716900 )
+ + LAYER Metal5 ( -3235280 -1083100 ) ( 3235280 -1076900 )
+ + LAYER Metal5 ( -3235280 -1443100 ) ( 3235280 -1436900 )
+ + LAYER Metal5 ( -3235280 -1803100 ) ( 3235280 -1796900 )
+ + LAYER Metal5 ( -3235280 -2163100 ) ( 3235280 -2156900 )
+ + LAYER Metal5 ( -3235280 -2523100 ) ( 3235280 -2516900 )
+ + LAYER Metal5 ( -3235280 -2883100 ) ( 3235280 -2876900 )
+ + LAYER Metal5 ( -3235280 -3243100 ) ( 3235280 -3236900 )
+ + LAYER Metal5 ( -3235280 -3603100 ) ( 3235280 -3596900 )
+ + LAYER Metal5 ( -3235280 -3963100 ) ( 3235280 -3956900 )
+ + LAYER Metal5 ( -3235280 -4323100 ) ( 3235280 -4316900 )
+ + LAYER Metal5 ( -3235280 -4683100 ) ( 3235280 -4676900 )
+ + LAYER Metal5 ( -3235280 -5043100 ) ( 3235280 -5036900 )
+ + LAYER Metal5 ( -3235280 -5403100 ) ( 3235280 -5396900 )
+ + LAYER Metal5 ( -3235280 -5763100 ) ( 3235280 -5756900 )
+ + LAYER Metal4 ( 2780420 -6018800 ) ( 2786620 413680 )
+ + LAYER Metal4 ( 2420420 -6018800 ) ( 2426620 413680 )
+ + LAYER Metal4 ( 2060420 -6018800 ) ( 2066620 413680 )
+ + LAYER Metal4 ( 1700420 -6018800 ) ( 1706620 413680 )
+ + LAYER Metal4 ( 1340420 -6018800 ) ( 1346620 413680 )
+ + LAYER Metal4 ( 980420 -6018800 ) ( 986620 413680 )
+ + LAYER Metal4 ( 620420 -6018800 ) ( 626620 413680 )
+ + LAYER Metal4 ( 260420 -6018800 ) ( 266620 413680 )
+ + LAYER Metal4 ( -99580 -6018800 ) ( -93380 413680 )
+ + LAYER Metal4 ( -459580 -6018800 ) ( -453380 413680 )
+ + LAYER Metal4 ( -819580 -2928420 ) ( -813380 413680 )
+ + LAYER Metal4 ( -819580 -6018800 ) ( -813380 -4119420 )
+ + LAYER Metal4 ( -1179580 -2928420 ) ( -1173380 413680 )
+ + LAYER Metal4 ( -1179580 -6018800 ) ( -1173380 -4119420 )
+ + LAYER Metal4 ( -1539580 -2928420 ) ( -1533380 413680 )
+ + LAYER Metal4 ( -1539580 -6018800 ) ( -1533380 -4119420 )
+ + LAYER Metal4 ( -1899580 -6018800 ) ( -1893380 413680 )
+ + LAYER Metal4 ( -2259580 -6018800 ) ( -2253380 413680 )
+ + LAYER Metal4 ( -2619580 -6018800 ) ( -2613380 413680 )
+ + LAYER Metal4 ( -2979580 -6018800 ) ( -2973380 413680 )
+ + LAYER Metal4 ( 3011380 -5801100 ) ( 3017580 195980 )
+ + LAYER Metal5 ( -3017580 189780 ) ( 3017580 195980 )
+ + LAYER Metal5 ( -3017580 -5801100 ) ( 3017580 -5794900 )
+ + LAYER Metal4 ( -3017580 -5801100 ) ( -3011380 195980 )
+ + FIXED ( 2999920 5801360 ) N ;
+ - vccd2 + NET vccd2 + SPECIAL + DIRECTION INOUT + USE POWER
+ + PORT
+ + LAYER Metal5 ( -3235280 -3100 ) ( 3235280 3100 )
+ + LAYER Metal5 ( -3235280 -363100 ) ( 3235280 -356900 )
+ + LAYER Metal5 ( -3235280 -723100 ) ( 3235280 -716900 )
+ + LAYER Metal5 ( -3235280 -1083100 ) ( 3235280 -1076900 )
+ + LAYER Metal5 ( -3235280 -1443100 ) ( 3235280 -1436900 )
+ + LAYER Metal5 ( -3235280 -1803100 ) ( 3235280 -1796900 )
+ + LAYER Metal5 ( -3235280 -2163100 ) ( 3235280 -2156900 )
+ + LAYER Metal5 ( -3235280 -2523100 ) ( 3235280 -2516900 )
+ + LAYER Metal5 ( -3235280 -2883100 ) ( 3235280 -2876900 )
+ + LAYER Metal5 ( -3235280 -3243100 ) ( 3235280 -3236900 )
+ + LAYER Metal5 ( -3235280 -3603100 ) ( 3235280 -3596900 )
+ + LAYER Metal5 ( -3235280 -3963100 ) ( 3235280 -3956900 )
+ + LAYER Metal5 ( -3235280 -4323100 ) ( 3235280 -4316900 )
+ + LAYER Metal5 ( -3235280 -4683100 ) ( 3235280 -4676900 )
+ + LAYER Metal5 ( -3235280 -5043100 ) ( 3235280 -5036900 )
+ + LAYER Metal5 ( -3235280 -5403100 ) ( 3235280 -5396900 )
+ + LAYER Metal5 ( -3235280 -5763100 ) ( 3235280 -5756900 )
+ + LAYER Metal4 ( 2854820 -6093200 ) ( 2861020 339280 )
+ + LAYER Metal4 ( 2494820 -6093200 ) ( 2501020 339280 )
+ + LAYER Metal4 ( 2134820 -6093200 ) ( 2141020 339280 )
+ + LAYER Metal4 ( 1774820 -6093200 ) ( 1781020 339280 )
+ + LAYER Metal4 ( 1414820 -6093200 ) ( 1421020 339280 )
+ + LAYER Metal4 ( 1054820 -6093200 ) ( 1061020 339280 )
+ + LAYER Metal4 ( 694820 -6093200 ) ( 701020 339280 )
+ + LAYER Metal4 ( 334820 -6093200 ) ( 341020 339280 )
+ + LAYER Metal4 ( -25180 -6093200 ) ( -18980 339280 )
+ + LAYER Metal4 ( -385180 -6093200 ) ( -378980 339280 )
+ + LAYER Metal4 ( -745180 -6093200 ) ( -738980 339280 )
+ + LAYER Metal4 ( -1105180 -3002820 ) ( -1098980 339280 )
+ + LAYER Metal4 ( -1105180 -6093200 ) ( -1098980 -4193820 )
+ + LAYER Metal4 ( -1465180 -3002820 ) ( -1458980 339280 )
+ + LAYER Metal4 ( -1465180 -6093200 ) ( -1458980 -4193820 )
+ + LAYER Metal4 ( -1825180 -6093200 ) ( -1818980 339280 )
+ + LAYER Metal4 ( -2185180 -6093200 ) ( -2178980 339280 )
+ + LAYER Metal4 ( -2545180 -6093200 ) ( -2538980 339280 )
+ + LAYER Metal4 ( -2905180 -6093200 ) ( -2898980 339280 )
+ + LAYER Metal4 ( 3073580 -5937700 ) ( 3079780 183780 )
+ + LAYER Metal5 ( -3079780 177580 ) ( 3079780 183780 )
+ + LAYER Metal5 ( -3079780 -5937700 ) ( 3079780 -5931500 )
+ + LAYER Metal4 ( -3079780 -5937700 ) ( -3073580 183780 )
+ + FIXED ( 2999920 5875760 ) N ;
+ - vdda1 + NET vdda1 + SPECIAL + DIRECTION INOUT + USE POWER
+ + PORT
+ + LAYER Metal5 ( -3235280 -3100 ) ( 3235280 3100 )
+ + LAYER Metal5 ( -3235280 -363100 ) ( 3235280 -356900 )
+ + LAYER Metal5 ( -3235280 -723100 ) ( 3235280 -716900 )
+ + LAYER Metal5 ( -3235280 -1083100 ) ( 3235280 -1076900 )
+ + LAYER Metal5 ( -3235280 -1443100 ) ( 3235280 -1436900 )
+ + LAYER Metal5 ( -3235280 -1803100 ) ( 3235280 -1796900 )
+ + LAYER Metal5 ( -3235280 -2163100 ) ( 3235280 -2156900 )
+ + LAYER Metal5 ( -3235280 -2523100 ) ( 3235280 -2516900 )
+ + LAYER Metal5 ( -3235280 -2883100 ) ( 3235280 -2876900 )
+ + LAYER Metal5 ( -3235280 -3243100 ) ( 3235280 -3236900 )
+ + LAYER Metal5 ( -3235280 -3603100 ) ( 3235280 -3596900 )
+ + LAYER Metal5 ( -3235280 -3963100 ) ( 3235280 -3956900 )
+ + LAYER Metal5 ( -3235280 -4323100 ) ( 3235280 -4316900 )
+ + LAYER Metal5 ( -3235280 -4683100 ) ( 3235280 -4676900 )
+ + LAYER Metal5 ( -3235280 -5043100 ) ( 3235280 -5036900 )
+ + LAYER Metal5 ( -3235280 -5403100 ) ( 3235280 -5396900 )
+ + LAYER Metal5 ( -3235280 -5763100 ) ( 3235280 -5756900 )
+ + LAYER Metal4 ( 2929220 -6167600 ) ( 2935420 264880 )
+ + LAYER Metal4 ( 2569220 -6167600 ) ( 2575420 264880 )
+ + LAYER Metal4 ( 2209220 -6167600 ) ( 2215420 264880 )
+ + LAYER Metal4 ( 1849220 -6167600 ) ( 1855420 264880 )
+ + LAYER Metal4 ( 1489220 -6167600 ) ( 1495420 264880 )
+ + LAYER Metal4 ( 1129220 -6167600 ) ( 1135420 264880 )
+ + LAYER Metal4 ( 769220 -6167600 ) ( 775420 264880 )
+ + LAYER Metal4 ( 409220 -6167600 ) ( 415420 264880 )
+ + LAYER Metal4 ( 49220 -6167600 ) ( 55420 264880 )
+ + LAYER Metal4 ( -310780 -6167600 ) ( -304580 264880 )
+ + LAYER Metal4 ( -670780 -6167600 ) ( -664580 264880 )
+ + LAYER Metal4 ( -1030780 -3077220 ) ( -1024580 264880 )
+ + LAYER Metal4 ( -1030780 -6167600 ) ( -1024580 -4268220 )
+ + LAYER Metal4 ( -1390780 -3077220 ) ( -1384580 264880 )
+ + LAYER Metal4 ( -1390780 -6167600 ) ( -1384580 -4268220 )
+ + LAYER Metal4 ( -1750780 -6167600 ) ( -1744580 264880 )
+ + LAYER Metal4 ( -2110780 -6167600 ) ( -2104580 264880 )
+ + LAYER Metal4 ( -2470780 -6167600 ) ( -2464580 264880 )
+ + LAYER Metal4 ( -2830780 -6167600 ) ( -2824580 264880 )
+ + LAYER Metal4 ( 3135780 -6074300 ) ( 3141980 171580 )
+ + LAYER Metal5 ( -3141980 165380 ) ( 3141980 171580 )
+ + LAYER Metal5 ( -3141980 -6074300 ) ( 3141980 -6068100 )
+ + LAYER Metal4 ( -3141980 -6074300 ) ( -3135780 171580 )
+ + FIXED ( 2999920 5950160 ) N ;
+ - vdda2 + NET vdda2 + SPECIAL + DIRECTION INOUT + USE POWER
+ + PORT
+ + LAYER Metal5 ( -3235280 -3100 ) ( 3235280 3100 )
+ + LAYER Metal5 ( -3235280 -363100 ) ( 3235280 -356900 )
+ + LAYER Metal5 ( -3235280 -723100 ) ( 3235280 -716900 )
+ + LAYER Metal5 ( -3235280 -1083100 ) ( 3235280 -1076900 )
+ + LAYER Metal5 ( -3235280 -1443100 ) ( 3235280 -1436900 )
+ + LAYER Metal5 ( -3235280 -1803100 ) ( 3235280 -1796900 )
+ + LAYER Metal5 ( -3235280 -2163100 ) ( 3235280 -2156900 )
+ + LAYER Metal5 ( -3235280 -2523100 ) ( 3235280 -2516900 )
+ + LAYER Metal5 ( -3235280 -2883100 ) ( 3235280 -2876900 )
+ + LAYER Metal5 ( -3235280 -3243100 ) ( 3235280 -3236900 )
+ + LAYER Metal5 ( -3235280 -3603100 ) ( 3235280 -3596900 )
+ + LAYER Metal5 ( -3235280 -3963100 ) ( 3235280 -3956900 )
+ + LAYER Metal5 ( -3235280 -4323100 ) ( 3235280 -4316900 )
+ + LAYER Metal5 ( -3235280 -4683100 ) ( 3235280 -4676900 )
+ + LAYER Metal5 ( -3235280 -5043100 ) ( 3235280 -5036900 )
+ + LAYER Metal5 ( -3235280 -5403100 ) ( 3235280 -5396900 )
+ + LAYER Metal4 ( 2643620 -5882000 ) ( 2649820 550480 )
+ + LAYER Metal4 ( 2283620 -5882000 ) ( 2289820 550480 )
+ + LAYER Metal4 ( 1923620 -5882000 ) ( 1929820 550480 )
+ + LAYER Metal4 ( 1563620 -5882000 ) ( 1569820 550480 )
+ + LAYER Metal4 ( 1203620 -5882000 ) ( 1209820 550480 )
+ + LAYER Metal4 ( 843620 -5882000 ) ( 849820 550480 )
+ + LAYER Metal4 ( 483620 -5882000 ) ( 489820 550480 )
+ + LAYER Metal4 ( 123620 -5882000 ) ( 129820 550480 )
+ + LAYER Metal4 ( -236380 -5882000 ) ( -230180 550480 )
+ + LAYER Metal4 ( -596380 -5882000 ) ( -590180 550480 )
+ + LAYER Metal4 ( -956380 -2791620 ) ( -950180 550480 )
+ + LAYER Metal4 ( -956380 -5882000 ) ( -950180 -3982620 )
+ + LAYER Metal4 ( -1316380 -2785240 ) ( -1310180 550480 )
+ + LAYER Metal4 ( -1316380 -5882000 ) ( -1310180 -3982620 )
+ + LAYER Metal4 ( -1676380 -2791620 ) ( -1670180 550480 )
+ + LAYER Metal4 ( -1676380 -5882000 ) ( -1670180 -3982620 )
+ + LAYER Metal4 ( -2036380 -5882000 ) ( -2030180 550480 )
+ + LAYER Metal4 ( -2396380 -5882000 ) ( -2390180 550480 )
+ + LAYER Metal4 ( -2756380 -5882000 ) ( -2750180 550480 )
+ + LAYER Metal4 ( 3197980 -5850900 ) ( 3204180 519380 )
+ + LAYER Metal5 ( -3204180 513180 ) ( 3204180 519380 )
+ + LAYER Metal5 ( -3204180 -5850900 ) ( 3204180 -5844700 )
+ + LAYER Metal4 ( -3204180 -5850900 ) ( -3197980 519380 )
+ + FIXED ( 2999920 5664560 ) N ;
+ - vssa1 + NET vssa1 + SPECIAL + DIRECTION INOUT + USE GROUND
+ + PORT
+ + LAYER Metal5 ( -3235280 -3100 ) ( 3235280 3100 )
+ + LAYER Metal5 ( -3235280 -363100 ) ( 3235280 -356900 )
+ + LAYER Metal5 ( -3235280 -723100 ) ( 3235280 -716900 )
+ + LAYER Metal5 ( -3235280 -1083100 ) ( 3235280 -1076900 )
+ + LAYER Metal5 ( -3235280 -1443100 ) ( 3235280 -1436900 )
+ + LAYER Metal5 ( -3235280 -1803100 ) ( 3235280 -1796900 )
+ + LAYER Metal5 ( -3235280 -2163100 ) ( 3235280 -2156900 )
+ + LAYER Metal5 ( -3235280 -2523100 ) ( 3235280 -2516900 )
+ + LAYER Metal5 ( -3235280 -2883100 ) ( 3235280 -2876900 )
+ + LAYER Metal5 ( -3235280 -3243100 ) ( 3235280 -3236900 )
+ + LAYER Metal5 ( -3235280 -3603100 ) ( 3235280 -3596900 )
+ + LAYER Metal5 ( -3235280 -3963100 ) ( 3235280 -3956900 )
+ + LAYER Metal5 ( -3235280 -4323100 ) ( 3235280 -4316900 )
+ + LAYER Metal5 ( -3235280 -4683100 ) ( 3235280 -4676900 )
+ + LAYER Metal5 ( -3235280 -5043100 ) ( 3235280 -5036900 )
+ + LAYER Metal5 ( -3235280 -5403100 ) ( 3235280 -5396900 )
+ + LAYER Metal4 ( 2966420 -5844800 ) ( 2972620 587680 )
+ + LAYER Metal4 ( 2606420 -5844800 ) ( 2612620 587680 )
+ + LAYER Metal4 ( 2246420 -5844800 ) ( 2252620 587680 )
+ + LAYER Metal4 ( 1886420 -5844800 ) ( 1892620 587680 )
+ + LAYER Metal4 ( 1526420 -5844800 ) ( 1532620 587680 )
+ + LAYER Metal4 ( 1166420 -5844800 ) ( 1172620 587680 )
+ + LAYER Metal4 ( 806420 -5844800 ) ( 812620 587680 )
+ + LAYER Metal4 ( 446420 -5844800 ) ( 452620 587680 )
+ + LAYER Metal4 ( 86420 -5844800 ) ( 92620 587680 )
+ + LAYER Metal4 ( -273580 -5844800 ) ( -267380 587680 )
+ + LAYER Metal4 ( -633580 -5844800 ) ( -627380 587680 )
+ + LAYER Metal4 ( -993580 -2754420 ) ( -987380 587680 )
+ + LAYER Metal4 ( -993580 -5844800 ) ( -987380 -3945420 )
+ + LAYER Metal4 ( -1353580 -2754420 ) ( -1347380 587680 )
+ + LAYER Metal4 ( -1353580 -5844800 ) ( -1347380 -3945420 )
+ + LAYER Metal4 ( -1713580 -5844800 ) ( -1707380 587680 )
+ + LAYER Metal4 ( -2073580 -5844800 ) ( -2067380 587680 )
+ + LAYER Metal4 ( -2433580 -5844800 ) ( -2427380 587680 )
+ + LAYER Metal4 ( -2793580 -5844800 ) ( -2787380 587680 )
+ + LAYER Metal4 ( 3166880 -5782600 ) ( 3173080 525480 )
+ + LAYER Metal5 ( -3173080 519280 ) ( 3173080 525480 )
+ + LAYER Metal5 ( -3173080 -5782600 ) ( 3173080 -5776400 )
+ + LAYER Metal4 ( -3173080 -5782600 ) ( -3166880 525480 )
+ + FIXED ( 2999920 5627360 ) N ;
+ - vssa2 + NET vssa2 + SPECIAL + DIRECTION INOUT + USE GROUND
+ + PORT
+ + LAYER Metal5 ( -3235280 -3100 ) ( 3235280 3100 )
+ + LAYER Metal5 ( -3235280 -363100 ) ( 3235280 -356900 )
+ + LAYER Metal5 ( -3235280 -723100 ) ( 3235280 -716900 )
+ + LAYER Metal5 ( -3235280 -1083100 ) ( 3235280 -1076900 )
+ + LAYER Metal5 ( -3235280 -1443100 ) ( 3235280 -1436900 )
+ + LAYER Metal5 ( -3235280 -1803100 ) ( 3235280 -1796900 )
+ + LAYER Metal5 ( -3235280 -2163100 ) ( 3235280 -2156900 )
+ + LAYER Metal5 ( -3235280 -2523100 ) ( 3235280 -2516900 )
+ + LAYER Metal5 ( -3235280 -2883100 ) ( 3235280 -2876900 )
+ + LAYER Metal5 ( -3235280 -3243100 ) ( 3235280 -3236900 )
+ + LAYER Metal5 ( -3235280 -3603100 ) ( 3235280 -3596900 )
+ + LAYER Metal5 ( -3235280 -3963100 ) ( 3235280 -3956900 )
+ + LAYER Metal5 ( -3235280 -4323100 ) ( 3235280 -4316900 )
+ + LAYER Metal5 ( -3235280 -4683100 ) ( 3235280 -4676900 )
+ + LAYER Metal5 ( -3235280 -5043100 ) ( 3235280 -5036900 )
+ + LAYER Metal5 ( -3235280 -5403100 ) ( 3235280 -5396900 )
+ + LAYER Metal4 ( 2680820 -5919200 ) ( 2687020 513280 )
+ + LAYER Metal4 ( 2320820 -5919200 ) ( 2327020 513280 )
+ + LAYER Metal4 ( 1960820 -5919200 ) ( 1967020 513280 )
+ + LAYER Metal4 ( 1600820 -5919200 ) ( 1607020 513280 )
+ + LAYER Metal4 ( 1240820 -5919200 ) ( 1247020 513280 )
+ + LAYER Metal4 ( 880820 -5919200 ) ( 887020 513280 )
+ + LAYER Metal4 ( 520820 -5919200 ) ( 527020 513280 )
+ + LAYER Metal4 ( 160820 -5919200 ) ( 167020 513280 )
+ + LAYER Metal4 ( -199180 -5919200 ) ( -192980 513280 )
+ + LAYER Metal4 ( -559180 -5919200 ) ( -552980 513280 )
+ + LAYER Metal4 ( -919180 -2828820 ) ( -912980 513280 )
+ + LAYER Metal4 ( -919180 -5919200 ) ( -912980 -4019820 )
+ + LAYER Metal4 ( -1279180 -2828820 ) ( -1272980 513280 )
+ + LAYER Metal4 ( -1279180 -5919200 ) ( -1272980 -4019820 )
+ + LAYER Metal4 ( -1639180 -2828820 ) ( -1632980 513280 )
+ + LAYER Metal4 ( -1639180 -5919200 ) ( -1632980 -4019820 )
+ + LAYER Metal4 ( -1999180 -5919200 ) ( -1992980 513280 )
+ + LAYER Metal4 ( -2359180 -5919200 ) ( -2352980 513280 )
+ + LAYER Metal4 ( -2719180 -5919200 ) ( -2712980 513280 )
+ + LAYER Metal4 ( 3229080 -5919200 ) ( 3235280 513280 )
+ + LAYER Metal5 ( -3235280 507080 ) ( 3235280 513280 )
+ + LAYER Metal5 ( -3235280 -5919200 ) ( 3235280 -5913000 )
+ + LAYER Metal4 ( -3235280 -5919200 ) ( -3229080 513280 )
+ + FIXED ( 2999920 5701760 ) N ;
+ - vssd1 + NET vssd1 + SPECIAL + DIRECTION INOUT + USE GROUND
+ + PORT
+ + LAYER Metal5 ( -3235280 -3100 ) ( 3235280 3100 )
+ + LAYER Metal5 ( -3235280 -363100 ) ( 3235280 -356900 )
+ + LAYER Metal5 ( -3235280 -723100 ) ( 3235280 -716900 )
+ + LAYER Metal5 ( -3235280 -1083100 ) ( 3235280 -1076900 )
+ + LAYER Metal5 ( -3235280 -1443100 ) ( 3235280 -1436900 )
+ + LAYER Metal5 ( -3235280 -1803100 ) ( 3235280 -1796900 )
+ + LAYER Metal5 ( -3235280 -2163100 ) ( 3235280 -2156900 )
+ + LAYER Metal5 ( -3235280 -2523100 ) ( 3235280 -2516900 )
+ + LAYER Metal5 ( -3235280 -2883100 ) ( 3235280 -2876900 )
+ + LAYER Metal5 ( -3235280 -3243100 ) ( 3235280 -3236900 )
+ + LAYER Metal5 ( -3235280 -3603100 ) ( 3235280 -3596900 )
+ + LAYER Metal5 ( -3235280 -3963100 ) ( 3235280 -3956900 )
+ + LAYER Metal5 ( -3235280 -4323100 ) ( 3235280 -4316900 )
+ + LAYER Metal5 ( -3235280 -4683100 ) ( 3235280 -4676900 )
+ + LAYER Metal5 ( -3235280 -5043100 ) ( 3235280 -5036900 )
+ + LAYER Metal5 ( -3235280 -5403100 ) ( 3235280 -5396900 )
+ + LAYER Metal5 ( -3235280 -5763100 ) ( 3235280 -5756900 )
+ + LAYER Metal4 ( 2817620 -6056000 ) ( 2823820 376480 )
+ + LAYER Metal4 ( 2457620 -6056000 ) ( 2463820 376480 )
+ + LAYER Metal4 ( 2097620 -6056000 ) ( 2103820 376480 )
+ + LAYER Metal4 ( 1737620 -6056000 ) ( 1743820 376480 )
+ + LAYER Metal4 ( 1377620 -6056000 ) ( 1383820 376480 )
+ + LAYER Metal4 ( 1017620 -6056000 ) ( 1023820 376480 )
+ + LAYER Metal4 ( 657620 -6056000 ) ( 663820 376480 )
+ + LAYER Metal4 ( 297620 -6056000 ) ( 303820 376480 )
+ + LAYER Metal4 ( -62380 -6056000 ) ( -56180 376480 )
+ + LAYER Metal4 ( -422380 -6056000 ) ( -416180 376480 )
+ + LAYER Metal4 ( -782380 -6056000 ) ( -776180 376480 )
+ + LAYER Metal4 ( -1142380 -2965620 ) ( -1136180 376480 )
+ + LAYER Metal4 ( -1142380 -6056000 ) ( -1136180 -4156620 )
+ + LAYER Metal4 ( -1502380 -2965620 ) ( -1496180 376480 )
+ + LAYER Metal4 ( -1502380 -6056000 ) ( -1496180 -4156620 )
+ + LAYER Metal4 ( -1862380 -6056000 ) ( -1856180 376480 )
+ + LAYER Metal4 ( -2222380 -6056000 ) ( -2216180 376480 )
+ + LAYER Metal4 ( -2582380 -6056000 ) ( -2576180 376480 )
+ + LAYER Metal4 ( -2942380 -6056000 ) ( -2936180 376480 )
+ + LAYER Metal4 ( 3042480 -5869400 ) ( 3048680 189880 )
+ + LAYER Metal5 ( -3048680 183680 ) ( 3048680 189880 )
+ + LAYER Metal5 ( -3048680 -5869400 ) ( 3048680 -5863200 )
+ + LAYER Metal4 ( -3048680 -5869400 ) ( -3042480 189880 )
+ + FIXED ( 2999920 5838560 ) N ;
+ - vssd2 + NET vssd2 + SPECIAL + DIRECTION INOUT + USE GROUND
+ + PORT
+ + LAYER Metal5 ( -3235280 -3100 ) ( 3235280 3100 )
+ + LAYER Metal5 ( -3235280 -363100 ) ( 3235280 -356900 )
+ + LAYER Metal5 ( -3235280 -723100 ) ( 3235280 -716900 )
+ + LAYER Metal5 ( -3235280 -1083100 ) ( 3235280 -1076900 )
+ + LAYER Metal5 ( -3235280 -1443100 ) ( 3235280 -1436900 )
+ + LAYER Metal5 ( -3235280 -1803100 ) ( 3235280 -1796900 )
+ + LAYER Metal5 ( -3235280 -2163100 ) ( 3235280 -2156900 )
+ + LAYER Metal5 ( -3235280 -2523100 ) ( 3235280 -2516900 )
+ + LAYER Metal5 ( -3235280 -2883100 ) ( 3235280 -2876900 )
+ + LAYER Metal5 ( -3235280 -3243100 ) ( 3235280 -3236900 )
+ + LAYER Metal5 ( -3235280 -3603100 ) ( 3235280 -3596900 )
+ + LAYER Metal5 ( -3235280 -3963100 ) ( 3235280 -3956900 )
+ + LAYER Metal5 ( -3235280 -4323100 ) ( 3235280 -4316900 )
+ + LAYER Metal5 ( -3235280 -4683100 ) ( 3235280 -4676900 )
+ + LAYER Metal5 ( -3235280 -5043100 ) ( 3235280 -5036900 )
+ + LAYER Metal5 ( -3235280 -5403100 ) ( 3235280 -5396900 )
+ + LAYER Metal5 ( -3235280 -5763100 ) ( 3235280 -5756900 )
+ + LAYER Metal4 ( 2892020 -6130400 ) ( 2898220 302080 )
+ + LAYER Metal4 ( 2532020 -6130400 ) ( 2538220 302080 )
+ + LAYER Metal4 ( 2172020 -6130400 ) ( 2178220 302080 )
+ + LAYER Metal4 ( 1812020 -6130400 ) ( 1818220 302080 )
+ + LAYER Metal4 ( 1452020 -6130400 ) ( 1458220 302080 )
+ + LAYER Metal4 ( 1092020 -6130400 ) ( 1098220 302080 )
+ + LAYER Metal4 ( 732020 -6130400 ) ( 738220 302080 )
+ + LAYER Metal4 ( 372020 -6130400 ) ( 378220 302080 )
+ + LAYER Metal4 ( 12020 -6130400 ) ( 18220 302080 )
+ + LAYER Metal4 ( -347980 -6130400 ) ( -341780 302080 )
+ + LAYER Metal4 ( -707980 -3033640 ) ( -701780 302080 )
+ + LAYER Metal4 ( -707980 -6130400 ) ( -701780 -4212760 )
+ + LAYER Metal4 ( -1067980 -3040020 ) ( -1061780 302080 )
+ + LAYER Metal4 ( -1067980 -6130400 ) ( -1061780 -4231020 )
+ + LAYER Metal4 ( -1427980 -3040020 ) ( -1421780 302080 )
+ + LAYER Metal4 ( -1427980 -6130400 ) ( -1421780 -4231020 )
+ + LAYER Metal4 ( -1787980 -6130400 ) ( -1781780 302080 )
+ + LAYER Metal4 ( -2147980 -6130400 ) ( -2141780 302080 )
+ + LAYER Metal4 ( -2507980 -6130400 ) ( -2501780 302080 )
+ + LAYER Metal4 ( -2867980 -6130400 ) ( -2861780 302080 )
+ + LAYER Metal4 ( 3104680 -6006000 ) ( 3110880 177680 )
+ + LAYER Metal5 ( -3110880 171480 ) ( 3110880 177680 )
+ + LAYER Metal5 ( -3110880 -6006000 ) ( 3110880 -5999800 )
+ + LAYER Metal4 ( -3110880 -6006000 ) ( -3104680 177680 )
+ + FIXED ( 2999920 5912960 ) N ;
+ - wb_clk_i + NET wb_clk_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 239120 -2400 ) N ;
+ - wb_rst_i + NET wb_rst_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 250320 -2400 ) N ;
+ - wbs_ack_o + NET wbs_ack_o + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 261520 -2400 ) N ;
+ - wbs_adr_i[0] + NET wbs_adr_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 306320 -2400 ) N ;
+ - wbs_adr_i[10] + NET wbs_adr_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 687120 -2400 ) N ;
+ - wbs_adr_i[11] + NET wbs_adr_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 720720 -2400 ) N ;
+ - wbs_adr_i[12] + NET wbs_adr_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 754320 -2400 ) N ;
+ - wbs_adr_i[13] + NET wbs_adr_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 787920 -2400 ) N ;
+ - wbs_adr_i[14] + NET wbs_adr_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 821520 -2400 ) N ;
+ - wbs_adr_i[15] + NET wbs_adr_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 855120 -2400 ) N ;
+ - wbs_adr_i[16] + NET wbs_adr_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 888720 -2400 ) N ;
+ - wbs_adr_i[17] + NET wbs_adr_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 922320 -2400 ) N ;
+ - wbs_adr_i[18] + NET wbs_adr_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 955920 -2400 ) N ;
+ - wbs_adr_i[19] + NET wbs_adr_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 989520 -2400 ) N ;
+ - wbs_adr_i[1] + NET wbs_adr_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 351120 -2400 ) N ;
+ - wbs_adr_i[20] + NET wbs_adr_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1023120 -2400 ) N ;
+ - wbs_adr_i[21] + NET wbs_adr_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1056720 -2400 ) N ;
+ - wbs_adr_i[22] + NET wbs_adr_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1090320 -2400 ) N ;
+ - wbs_adr_i[23] + NET wbs_adr_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1123920 -2400 ) N ;
+ - wbs_adr_i[24] + NET wbs_adr_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1157520 -2400 ) N ;
+ - wbs_adr_i[25] + NET wbs_adr_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1191120 -2400 ) N ;
+ - wbs_adr_i[26] + NET wbs_adr_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1224720 -2400 ) N ;
+ - wbs_adr_i[27] + NET wbs_adr_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1258320 -2400 ) N ;
+ - wbs_adr_i[28] + NET wbs_adr_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1291920 -2400 ) N ;
+ - wbs_adr_i[29] + NET wbs_adr_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1325520 -2400 ) N ;
+ - wbs_adr_i[2] + NET wbs_adr_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 395920 -2400 ) N ;
+ - wbs_adr_i[30] + NET wbs_adr_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1359120 -2400 ) N ;
+ - wbs_adr_i[31] + NET wbs_adr_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1392720 -2400 ) N ;
+ - wbs_adr_i[3] + NET wbs_adr_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 440720 -2400 ) N ;
+ - wbs_adr_i[4] + NET wbs_adr_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 485520 -2400 ) N ;
+ - wbs_adr_i[5] + NET wbs_adr_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 519120 -2400 ) N ;
+ - wbs_adr_i[6] + NET wbs_adr_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 552720 -2400 ) N ;
+ - wbs_adr_i[7] + NET wbs_adr_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 586320 -2400 ) N ;
+ - wbs_adr_i[8] + NET wbs_adr_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 619920 -2400 ) N ;
+ - wbs_adr_i[9] + NET wbs_adr_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 653520 -2400 ) N ;
+ - wbs_cyc_i + NET wbs_cyc_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 272720 -2400 ) N ;
+ - wbs_dat_i[0] + NET wbs_dat_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 317520 -2400 ) N ;
+ - wbs_dat_i[10] + NET wbs_dat_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 698320 -2400 ) N ;
+ - wbs_dat_i[11] + NET wbs_dat_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 731920 -2400 ) N ;
+ - wbs_dat_i[12] + NET wbs_dat_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 765520 -2400 ) N ;
+ - wbs_dat_i[13] + NET wbs_dat_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 799120 -2400 ) N ;
+ - wbs_dat_i[14] + NET wbs_dat_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 832720 -2400 ) N ;
+ - wbs_dat_i[15] + NET wbs_dat_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 866320 -2400 ) N ;
+ - wbs_dat_i[16] + NET wbs_dat_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 899920 -2400 ) N ;
+ - wbs_dat_i[17] + NET wbs_dat_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 933520 -2400 ) N ;
+ - wbs_dat_i[18] + NET wbs_dat_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 967120 -2400 ) N ;
+ - wbs_dat_i[19] + NET wbs_dat_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1000720 -2400 ) N ;
+ - wbs_dat_i[1] + NET wbs_dat_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 362320 -2400 ) N ;
+ - wbs_dat_i[20] + NET wbs_dat_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1034320 -2400 ) N ;
+ - wbs_dat_i[21] + NET wbs_dat_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1067920 -2400 ) N ;
+ - wbs_dat_i[22] + NET wbs_dat_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1101520 -2400 ) N ;
+ - wbs_dat_i[23] + NET wbs_dat_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1135120 -2400 ) N ;
+ - wbs_dat_i[24] + NET wbs_dat_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1168720 -2400 ) N ;
+ - wbs_dat_i[25] + NET wbs_dat_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1202320 -2400 ) N ;
+ - wbs_dat_i[26] + NET wbs_dat_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1235920 -2400 ) N ;
+ - wbs_dat_i[27] + NET wbs_dat_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1269520 -2400 ) N ;
+ - wbs_dat_i[28] + NET wbs_dat_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1303120 -2400 ) N ;
+ - wbs_dat_i[29] + NET wbs_dat_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1336720 -2400 ) N ;
+ - wbs_dat_i[2] + NET wbs_dat_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 407120 -2400 ) N ;
+ - wbs_dat_i[30] + NET wbs_dat_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1370320 -2400 ) N ;
+ - wbs_dat_i[31] + NET wbs_dat_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1403920 -2400 ) N ;
+ - wbs_dat_i[3] + NET wbs_dat_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 451920 -2400 ) N ;
+ - wbs_dat_i[4] + NET wbs_dat_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 496720 -2400 ) N ;
+ - wbs_dat_i[5] + NET wbs_dat_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 530320 -2400 ) N ;
+ - wbs_dat_i[6] + NET wbs_dat_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 563920 -2400 ) N ;
+ - wbs_dat_i[7] + NET wbs_dat_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 597520 -2400 ) N ;
+ - wbs_dat_i[8] + NET wbs_dat_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 631120 -2400 ) N ;
+ - wbs_dat_i[9] + NET wbs_dat_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 664720 -2400 ) N ;
+ - wbs_dat_o[0] + NET wbs_dat_o[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 328720 -2400 ) N ;
+ - wbs_dat_o[10] + NET wbs_dat_o[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 709520 -2400 ) N ;
+ - wbs_dat_o[11] + NET wbs_dat_o[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 743120 -2400 ) N ;
+ - wbs_dat_o[12] + NET wbs_dat_o[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 776720 -2400 ) N ;
+ - wbs_dat_o[13] + NET wbs_dat_o[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 810320 -2400 ) N ;
+ - wbs_dat_o[14] + NET wbs_dat_o[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 843920 -2400 ) N ;
+ - wbs_dat_o[15] + NET wbs_dat_o[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 877520 -2400 ) N ;
+ - wbs_dat_o[16] + NET wbs_dat_o[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 911120 -2400 ) N ;
+ - wbs_dat_o[17] + NET wbs_dat_o[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 944720 -2400 ) N ;
+ - wbs_dat_o[18] + NET wbs_dat_o[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 978320 -2400 ) N ;
+ - wbs_dat_o[19] + NET wbs_dat_o[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1011920 -2400 ) N ;
+ - wbs_dat_o[1] + NET wbs_dat_o[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 373520 -2400 ) N ;
+ - wbs_dat_o[20] + NET wbs_dat_o[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1045520 -2400 ) N ;
+ - wbs_dat_o[21] + NET wbs_dat_o[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1079120 -2400 ) N ;
+ - wbs_dat_o[22] + NET wbs_dat_o[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1112720 -2400 ) N ;
+ - wbs_dat_o[23] + NET wbs_dat_o[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1146320 -2400 ) N ;
+ - wbs_dat_o[24] + NET wbs_dat_o[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1179920 -2400 ) N ;
+ - wbs_dat_o[25] + NET wbs_dat_o[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1213520 -2400 ) N ;
+ - wbs_dat_o[26] + NET wbs_dat_o[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1247120 -2400 ) N ;
+ - wbs_dat_o[27] + NET wbs_dat_o[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1280720 -2400 ) N ;
+ - wbs_dat_o[28] + NET wbs_dat_o[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1314320 -2400 ) N ;
+ - wbs_dat_o[29] + NET wbs_dat_o[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1347920 -2400 ) N ;
+ - wbs_dat_o[2] + NET wbs_dat_o[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 418320 -2400 ) N ;
+ - wbs_dat_o[30] + NET wbs_dat_o[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1381520 -2400 ) N ;
+ - wbs_dat_o[31] + NET wbs_dat_o[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 1415120 -2400 ) N ;
+ - wbs_dat_o[3] + NET wbs_dat_o[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 463120 -2400 ) N ;
+ - wbs_dat_o[4] + NET wbs_dat_o[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 507920 -2400 ) N ;
+ - wbs_dat_o[5] + NET wbs_dat_o[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 541520 -2400 ) N ;
+ - wbs_dat_o[6] + NET wbs_dat_o[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 575120 -2400 ) N ;
+ - wbs_dat_o[7] + NET wbs_dat_o[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 608720 -2400 ) N ;
+ - wbs_dat_o[8] + NET wbs_dat_o[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 642320 -2400 ) N ;
+ - wbs_dat_o[9] + NET wbs_dat_o[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 675920 -2400 ) N ;
+ - wbs_sel_i[0] + NET wbs_sel_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 339920 -2400 ) N ;
+ - wbs_sel_i[1] + NET wbs_sel_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 384720 -2400 ) N ;
+ - wbs_sel_i[2] + NET wbs_sel_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 429520 -2400 ) N ;
+ - wbs_sel_i[3] + NET wbs_sel_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 474320 -2400 ) N ;
+ - wbs_stb_i + NET wbs_stb_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 283920 -2400 ) N ;
+ - wbs_we_i + NET wbs_we_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -7200 ) ( 1120 7200 )
+ + PLACED ( 295120 -2400 ) N ;
+END PINS
+SPECIALNETS 8 ;
+ - vccd1 ( PIN vccd1 ) ( * vccd1 ) + USE POWER
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 2903440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2757080 2561360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2757080 2201360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2757080 1841360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2449880 2561360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2449880 2201360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2449880 1841360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2142680 2561360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2142680 2201360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2142680 1841360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1835480 2561360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1835480 2201360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1835480 1841360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1528280 2561360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1528280 2201360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1528280 1841360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1221080 2561360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1221080 2201360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1221080 1841360 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5801360 ) ( 6235200 5801360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5441360 ) ( 6235200 5441360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5081360 ) ( 6235200 5081360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4721360 ) ( 6235200 4721360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4361360 ) ( 6235200 4361360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4001360 ) ( 6235200 4001360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3641360 ) ( 6235200 3641360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3281360 ) ( 6235200 3281360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2921360 ) ( 6235200 2921360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2561360 ) ( 6235200 2561360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2201360 ) ( 6235200 2201360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1841360 ) ( 6235200 1841360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1481360 ) ( 6235200 1481360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1121360 ) ( 6235200 1121360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 761360 ) ( 6235200 761360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 401360 ) ( 6235200 401360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 41360 ) ( 6235200 41360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5783440 -217440 ) ( 5783440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5423440 -217440 ) ( 5423440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5063440 -217440 ) ( 5063440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4703440 -217440 ) ( 4703440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4343440 -217440 ) ( 4343440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3983440 -217440 ) ( 3983440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3623440 -217440 ) ( 3623440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3263440 -217440 ) ( 3263440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2903440 -217440 ) ( 2903440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2543440 -217440 ) ( 2543440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2183440 2872940 ) ( 2183440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2183440 -217440 ) ( 2183440 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1823440 2872940 ) ( 1823440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1823440 -217440 ) ( 1823440 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1463440 2872940 ) ( 1463440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1463440 -217440 ) ( 1463440 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1103440 -217440 ) ( 1103440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 743440 -217440 ) ( 743440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 383440 -217440 ) ( 383440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 23440 -217440 ) ( 23440 6215040 )
+ NEW Metal4 6200 + SHAPE RING ( 6014400 260 ) ( 6014400 5997340 )
+ NEW Metal5 6200 + SHAPE RING ( -17660 5994240 ) ( 6017500 5994240 )
+ NEW Metal5 6200 + SHAPE RING ( -17660 3360 ) ( 6017500 3360 )
+ NEW Metal4 6200 + SHAPE RING ( -14560 260 ) ( -14560 5997340 )
+ NEW Metal4 0 + SHAPE RING ( 6014400 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6014400 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 6014400 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5783440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5423440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5063440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4703440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4343440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3983440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3623440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3263440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2903440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2543440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2183440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1823440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1463440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1103440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 743440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 383440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 23440 3360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -14560 5994240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 5801360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 5441360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 5081360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 4721360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 4361360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 4001360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 3641360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 3281360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 2921360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 2561360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 2201360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 1841360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 1481360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 1121360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 761360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 401360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -14560 41360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -14560 3360 ) via4_5_6200_6200_6_6_1040_1040 ;
+ - vccd2 ( PIN vccd2 ) + USE POWER
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 2977840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5875760 ) ( 6235200 5875760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5515760 ) ( 6235200 5515760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5155760 ) ( 6235200 5155760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4795760 ) ( 6235200 4795760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4435760 ) ( 6235200 4435760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4075760 ) ( 6235200 4075760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3715760 ) ( 6235200 3715760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3355760 ) ( 6235200 3355760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2995760 ) ( 6235200 2995760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2635760 ) ( 6235200 2635760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2275760 ) ( 6235200 2275760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1915760 ) ( 6235200 1915760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1555760 ) ( 6235200 1555760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1195760 ) ( 6235200 1195760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 835760 ) ( 6235200 835760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 475760 ) ( 6235200 475760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 115760 ) ( 6235200 115760 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5857840 -217440 ) ( 5857840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5497840 -217440 ) ( 5497840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5137840 -217440 ) ( 5137840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4777840 -217440 ) ( 4777840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4417840 -217440 ) ( 4417840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4057840 -217440 ) ( 4057840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3697840 -217440 ) ( 3697840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3337840 -217440 ) ( 3337840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2977840 -217440 ) ( 2977840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2617840 -217440 ) ( 2617840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2257840 -217440 ) ( 2257840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1897840 2872940 ) ( 1897840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1897840 -217440 ) ( 1897840 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1537840 2872940 ) ( 1537840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1537840 -217440 ) ( 1537840 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1177840 -217440 ) ( 1177840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 817840 -217440 ) ( 817840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 457840 -217440 ) ( 457840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 97840 -217440 ) ( 97840 6215040 )
+ NEW Metal4 6200 + SHAPE RING ( 6076600 -61940 ) ( 6076600 6059540 )
+ NEW Metal5 6200 + SHAPE RING ( -79860 6056440 ) ( 6079700 6056440 )
+ NEW Metal5 6200 + SHAPE RING ( -79860 -58840 ) ( 6079700 -58840 )
+ NEW Metal4 6200 + SHAPE RING ( -76760 -61940 ) ( -76760 6059540 )
+ NEW Metal4 0 + SHAPE RING ( 6076600 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6076600 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 6076600 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5857840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5497840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5137840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4777840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4417840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4057840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 1915760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3697840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3337840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2977840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 2275760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2617840 475760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 6056440 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 5155760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 835760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 2257840 -58840 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 5155760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1897840 -58840 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1537840 475760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1177840 115760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 817840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 817840 835760 ) via4_5_6200_6200_6_6_1040_1040
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+ NEW Metal4 0 + SHAPE STRIPE ( 457840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 457840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 97840 -58840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -76760 6056440 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 5875760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 5515760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 5155760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 4795760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 4435760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 4075760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 3715760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 3355760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 2995760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 2635760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 2275760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 1915760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 1555760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 1195760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 835760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 475760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -76760 115760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -76760 -58840 ) via4_5_6200_6200_6_6_1040_1040 ;
+ - vdda1 ( PIN vdda1 ) + USE POWER
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 2692240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5950160 ) ( 6235200 5950160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5590160 ) ( 6235200 5590160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5230160 ) ( 6235200 5230160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4870160 ) ( 6235200 4870160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4510160 ) ( 6235200 4510160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4150160 ) ( 6235200 4150160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3790160 ) ( 6235200 3790160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3430160 ) ( 6235200 3430160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3070160 ) ( 6235200 3070160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2710160 ) ( 6235200 2710160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2350160 ) ( 6235200 2350160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1990160 ) ( 6235200 1990160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1630160 ) ( 6235200 1630160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1270160 ) ( 6235200 1270160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 910160 ) ( 6235200 910160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 550160 ) ( 6235200 550160 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 190160 ) ( 6235200 190160 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5932240 -217440 ) ( 5932240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5572240 -217440 ) ( 5572240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5212240 -217440 ) ( 5212240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4852240 -217440 ) ( 4852240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4492240 -217440 ) ( 4492240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4132240 -217440 ) ( 4132240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3772240 -217440 ) ( 3772240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3412240 -217440 ) ( 3412240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3052240 -217440 ) ( 3052240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2692240 -217440 ) ( 2692240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2332240 -217440 ) ( 2332240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1972240 2872940 ) ( 1972240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1972240 -217440 ) ( 1972240 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1612240 2872940 ) ( 1612240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1612240 -217440 ) ( 1612240 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1252240 -217440 ) ( 1252240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 892240 -217440 ) ( 892240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 532240 -217440 ) ( 532240 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 172240 -217440 ) ( 172240 6215040 )
+ NEW Metal4 6200 + SHAPE RING ( 6138800 -124140 ) ( 6138800 6121740 )
+ NEW Metal5 6200 + SHAPE RING ( -142060 6118640 ) ( 6141900 6118640 )
+ NEW Metal5 6200 + SHAPE RING ( -142060 -121040 ) ( 6141900 -121040 )
+ NEW Metal4 6200 + SHAPE RING ( -138960 -124140 ) ( -138960 6121740 )
+ NEW Metal4 0 + SHAPE RING ( 6138800 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6138800 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 6138800 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5932240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5572240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5212240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4852240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4492240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4132240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3772240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3412240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3052240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2692240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2332240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1972240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1612240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1252240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 892240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 532240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 172240 -121040 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -138960 6118640 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 5950160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 5590160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 5230160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 4870160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 4510160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 4150160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 3790160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 3430160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 3070160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 2710160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 2350160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 1990160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 1630160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 1270160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 910160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 550160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -138960 190160 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -138960 -121040 ) via4_5_6200_6200_6_6_1040_1040 ;
+ - vdda2 ( PIN vdda2 ) + USE POWER
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 2766640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5664560 ) ( 6235200 5664560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5304560 ) ( 6235200 5304560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4944560 ) ( 6235200 4944560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4584560 ) ( 6235200 4584560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4224560 ) ( 6235200 4224560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3864560 ) ( 6235200 3864560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3504560 ) ( 6235200 3504560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3144560 ) ( 6235200 3144560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2784560 ) ( 6235200 2784560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2424560 ) ( 6235200 2424560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2064560 ) ( 6235200 2064560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1704560 ) ( 6235200 1704560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1344560 ) ( 6235200 1344560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 984560 ) ( 6235200 984560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 624560 ) ( 6235200 624560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 264560 ) ( 6235200 264560 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5646640 -217440 ) ( 5646640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5286640 -217440 ) ( 5286640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4926640 -217440 ) ( 4926640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4566640 -217440 ) ( 4566640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4206640 -217440 ) ( 4206640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3846640 -217440 ) ( 3846640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3486640 -217440 ) ( 3486640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3126640 -217440 ) ( 3126640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2766640 -217440 ) ( 2766640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2406640 -217440 ) ( 2406640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2046640 2872940 ) ( 2046640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2046640 -217440 ) ( 2046640 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1686640 2879320 ) ( 1686640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1686640 -217440 ) ( 1686640 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1326640 2872940 ) ( 1326640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1326640 -217440 ) ( 1326640 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 966640 -217440 ) ( 966640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 606640 -217440 ) ( 606640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 246640 -217440 ) ( 246640 6215040 )
+ NEW Metal4 6200 + SHAPE RING ( 6201000 -186340 ) ( 6201000 6183940 )
+ NEW Metal5 6200 + SHAPE RING ( -204260 6180840 ) ( 6204100 6180840 )
+ NEW Metal5 6200 + SHAPE RING ( -204260 -183240 ) ( 6204100 -183240 )
+ NEW Metal4 6200 + SHAPE RING ( -201160 -186340 ) ( -201160 6183940 )
+ NEW Metal4 0 + SHAPE RING ( 6201000 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6201000 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 6201000 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5646640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5286640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4926640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4566640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4206640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3846640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3486640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3126640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2766640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2406640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2046640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1686640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1326640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 966640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 606640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 246640 -183240 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -201160 6180840 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 5664560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 5304560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 4944560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 4584560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 4224560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 3864560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 3504560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 3144560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 2784560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 2424560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 2064560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 1704560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 1344560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 984560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 624560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -201160 264560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -201160 -183240 ) via4_5_6200_6200_6_6_1040_1040 ;
+ - vssa1 ( PIN vssa1 ) + USE GROUND
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 2729440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5627360 ) ( 6235200 5627360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5267360 ) ( 6235200 5267360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4907360 ) ( 6235200 4907360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4547360 ) ( 6235200 4547360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4187360 ) ( 6235200 4187360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3827360 ) ( 6235200 3827360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3467360 ) ( 6235200 3467360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3107360 ) ( 6235200 3107360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2747360 ) ( 6235200 2747360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2387360 ) ( 6235200 2387360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2027360 ) ( 6235200 2027360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1667360 ) ( 6235200 1667360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1307360 ) ( 6235200 1307360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 947360 ) ( 6235200 947360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 587360 ) ( 6235200 587360 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 227360 ) ( 6235200 227360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5969440 -217440 ) ( 5969440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5609440 -217440 ) ( 5609440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5249440 -217440 ) ( 5249440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4889440 -217440 ) ( 4889440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4529440 -217440 ) ( 4529440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4169440 -217440 ) ( 4169440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3809440 -217440 ) ( 3809440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3449440 -217440 ) ( 3449440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3089440 -217440 ) ( 3089440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2729440 -217440 ) ( 2729440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2369440 -217440 ) ( 2369440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2009440 2872940 ) ( 2009440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2009440 -217440 ) ( 2009440 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1649440 2872940 ) ( 1649440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1649440 -217440 ) ( 1649440 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1289440 -217440 ) ( 1289440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 929440 -217440 ) ( 929440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 569440 -217440 ) ( 569440 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 209440 -217440 ) ( 209440 6215040 )
+ NEW Metal4 6200 + SHAPE RING ( 6169900 -155240 ) ( 6169900 6152840 )
+ NEW Metal5 6200 + SHAPE RING ( -173160 6149740 ) ( 6173000 6149740 )
+ NEW Metal5 6200 + SHAPE RING ( -173160 -152140 ) ( 6173000 -152140 )
+ NEW Metal4 6200 + SHAPE RING ( -170060 -155240 ) ( -170060 6152840 )
+ NEW Metal4 0 + SHAPE RING ( 6169900 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6169900 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 6169900 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5969440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5609440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5249440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4889440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4529440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4169440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3809440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3449440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3089440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2729440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2369440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2009440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1649440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1289440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 929440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 569440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 209440 -152140 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -170060 6149740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 5627360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 5267360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 4907360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 4547360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 4187360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 3827360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 3467360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 3107360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 2747360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 2387360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 2027360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 1667360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 1307360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 947360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 587360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -170060 227360 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -170060 -152140 ) via4_5_6200_6200_6_6_1040_1040 ;
+ - vssa2 ( PIN vssa2 ) + USE GROUND
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 2803840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5701760 ) ( 6235200 5701760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5341760 ) ( 6235200 5341760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4981760 ) ( 6235200 4981760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4621760 ) ( 6235200 4621760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4261760 ) ( 6235200 4261760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3901760 ) ( 6235200 3901760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3541760 ) ( 6235200 3541760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3181760 ) ( 6235200 3181760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2821760 ) ( 6235200 2821760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2461760 ) ( 6235200 2461760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2101760 ) ( 6235200 2101760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1741760 ) ( 6235200 1741760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1381760 ) ( 6235200 1381760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1021760 ) ( 6235200 1021760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 661760 ) ( 6235200 661760 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 301760 ) ( 6235200 301760 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5683840 -217440 ) ( 5683840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5323840 -217440 ) ( 5323840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4963840 -217440 ) ( 4963840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4603840 -217440 ) ( 4603840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4243840 -217440 ) ( 4243840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3883840 -217440 ) ( 3883840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3523840 -217440 ) ( 3523840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3163840 -217440 ) ( 3163840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2803840 -217440 ) ( 2803840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2443840 -217440 ) ( 2443840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2083840 2872940 ) ( 2083840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2083840 -217440 ) ( 2083840 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1723840 2872940 ) ( 1723840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1723840 -217440 ) ( 1723840 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1363840 2872940 ) ( 1363840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1363840 -217440 ) ( 1363840 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1003840 -217440 ) ( 1003840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 643840 -217440 ) ( 643840 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 283840 -217440 ) ( 283840 6215040 )
+ NEW Metal4 6200 + SHAPE RING ( 6232100 -217440 ) ( 6232100 6215040 )
+ NEW Metal5 6200 + SHAPE RING ( -235360 6211940 ) ( 6235200 6211940 )
+ NEW Metal5 6200 + SHAPE RING ( -235360 -214340 ) ( 6235200 -214340 )
+ NEW Metal4 6200 + SHAPE RING ( -232260 -217440 ) ( -232260 6215040 )
+ NEW Metal4 0 + SHAPE RING ( 6232100 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6232100 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 6232100 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5683840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5323840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4963840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4603840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4243840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3883840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3523840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3163840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2803840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2443840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2083840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1723840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1363840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1003840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 643840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 283840 -214340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -232260 6211940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 5701760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 5341760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 4981760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 4621760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 4261760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 3901760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 3541760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 3181760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 2821760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 2461760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 2101760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 1741760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 1381760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 1021760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 661760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -232260 301760 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -232260 -214340 ) via4_5_6200_6200_6_6_1040_1040 ;
+ - vssd1 ( PIN vssd1 ) ( * vssd1 ) + USE GROUND
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 2940640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2910680 2598560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2910680 2238560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2910680 1878560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2603480 2598560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2603480 2238560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2603480 1878560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2296280 2598560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2296280 2238560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2296280 1878560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1989080 2598560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1989080 2238560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1989080 1878560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1681880 2598560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1681880 2238560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1681880 1878560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1374680 2598560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1374680 2238560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1374680 1878560 ) via4_5_3200_6200_6_3_1040_1040
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5838560 ) ( 6235200 5838560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5478560 ) ( 6235200 5478560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5118560 ) ( 6235200 5118560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4758560 ) ( 6235200 4758560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4398560 ) ( 6235200 4398560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4038560 ) ( 6235200 4038560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3678560 ) ( 6235200 3678560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3318560 ) ( 6235200 3318560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2958560 ) ( 6235200 2958560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2598560 ) ( 6235200 2598560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2238560 ) ( 6235200 2238560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1878560 ) ( 6235200 1878560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1518560 ) ( 6235200 1518560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1158560 ) ( 6235200 1158560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 798560 ) ( 6235200 798560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 438560 ) ( 6235200 438560 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 78560 ) ( 6235200 78560 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5820640 -217440 ) ( 5820640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5460640 -217440 ) ( 5460640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5100640 -217440 ) ( 5100640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4740640 -217440 ) ( 4740640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4380640 -217440 ) ( 4380640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4020640 -217440 ) ( 4020640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3660640 -217440 ) ( 3660640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3300640 -217440 ) ( 3300640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2940640 -217440 ) ( 2940640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2580640 -217440 ) ( 2580640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2220640 -217440 ) ( 2220640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1860640 2872940 ) ( 1860640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1860640 -217440 ) ( 1860640 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1500640 2872940 ) ( 1500640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1500640 -217440 ) ( 1500640 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1140640 -217440 ) ( 1140640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 780640 -217440 ) ( 780640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 420640 -217440 ) ( 420640 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 60640 -217440 ) ( 60640 6215040 )
+ NEW Metal4 6200 + SHAPE RING ( 6045500 -30840 ) ( 6045500 6028440 )
+ NEW Metal5 6200 + SHAPE RING ( -48760 6025340 ) ( 6048600 6025340 )
+ NEW Metal5 6200 + SHAPE RING ( -48760 -27740 ) ( 6048600 -27740 )
+ NEW Metal4 6200 + SHAPE RING ( -45660 -30840 ) ( -45660 6028440 )
+ NEW Metal4 0 + SHAPE RING ( 6045500 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6045500 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 6045500 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5820640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5460640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5100640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4740640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4380640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4020640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3660640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3300640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2940640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2580640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2220640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1860640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1500640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1140640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 780640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 420640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 60640 -27740 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -45660 6025340 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 5838560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 5478560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 5118560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 4758560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 4398560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 4038560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 3678560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 3318560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 2958560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 2598560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 2238560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 1878560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 1518560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 1158560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 798560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 438560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -45660 78560 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -45660 -27740 ) via4_5_6200_6200_6_6_1040_1040 ;
+ - vssd2 ( PIN vssd2 ) + USE GROUND
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 2655040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5912960 ) ( 6235200 5912960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5552960 ) ( 6235200 5552960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 5192960 ) ( 6235200 5192960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4832960 ) ( 6235200 4832960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4472960 ) ( 6235200 4472960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 4112960 ) ( 6235200 4112960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3752960 ) ( 6235200 3752960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3392960 ) ( 6235200 3392960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 3032960 ) ( 6235200 3032960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2672960 ) ( 6235200 2672960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 2312960 ) ( 6235200 2312960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1952960 ) ( 6235200 1952960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1592960 ) ( 6235200 1592960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 1232960 ) ( 6235200 1232960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 872960 ) ( 6235200 872960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 512960 ) ( 6235200 512960 )
+ NEW Metal5 6200 + SHAPE STRIPE ( -235360 152960 ) ( 6235200 152960 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5895040 -217440 ) ( 5895040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5535040 -217440 ) ( 5535040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 5175040 -217440 ) ( 5175040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4815040 -217440 ) ( 4815040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4455040 -217440 ) ( 4455040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 4095040 -217440 ) ( 4095040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3735040 -217440 ) ( 3735040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3375040 -217440 ) ( 3375040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 3015040 -217440 ) ( 3015040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2655040 -217440 ) ( 2655040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2295040 2879320 ) ( 2295040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2295040 -217440 ) ( 2295040 1700200 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1935040 2872940 ) ( 1935040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1935040 -217440 ) ( 1935040 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1575040 2872940 ) ( 1575040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1575040 -217440 ) ( 1575040 1681940 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1215040 -217440 ) ( 1215040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 855040 -217440 ) ( 855040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 495040 -217440 ) ( 495040 6215040 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 135040 -217440 ) ( 135040 6215040 )
+ NEW Metal4 6200 + SHAPE RING ( 6107700 -93040 ) ( 6107700 6090640 )
+ NEW Metal5 6200 + SHAPE RING ( -110960 6087540 ) ( 6110800 6087540 )
+ NEW Metal5 6200 + SHAPE RING ( -110960 -89940 ) ( 6110800 -89940 )
+ NEW Metal4 6200 + SHAPE RING ( -107860 -93040 ) ( -107860 6090640 )
+ NEW Metal4 0 + SHAPE RING ( 6107700 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 6107700 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( 6107700 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5895040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5535040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 5175040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4815040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4455040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 4095040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3735040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3375040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 3015040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2655040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 2295040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1935040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1575040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 1215040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 855040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 495040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( 135040 -89940 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -107860 6087540 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 5912960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 5552960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 5192960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 4832960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 4472960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 4112960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 3752960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 3392960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 3032960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 2672960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 2312960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 1952960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 1592960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 1232960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 872960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 512960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE STRIPE ( -107860 152960 ) via4_5_6200_6200_6_6_1040_1040
+ NEW Metal4 0 + SHAPE RING ( -107860 -89940 ) via4_5_6200_6200_6_6_1040_1040 ;
+END SPECIALNETS
+END DESIGN
diff --git a/openlane/ref/user_project_wrapper/macro.cfg b/openlane/ref/user_project_wrapper/macro.cfg
new file mode 100644
index 0000000..a7365ab
--- /dev/null
+++ b/openlane/ref/user_project_wrapper/macro.cfg
@@ -0,0 +1 @@
+mprj 1175 1690 N
diff --git a/openlane/ref/user_project_wrapper/pin_order.cfg b/openlane/ref/user_project_wrapper/pin_order.cfg
new file mode 100644
index 0000000..c9632da
--- /dev/null
+++ b/openlane/ref/user_project_wrapper/pin_order.cfg
@@ -0,0 +1,156 @@
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 22a00ee..d83d5bb 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -1,85 +1,58 @@
{
- "DESIGN_NAME": "user_project_wrapper",
- "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
- "CLOCK_PERIOD": 10,
- "CLOCK_PORT": "user_clock2",
- "CLOCK_NET": "mprj.clk",
- "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
- "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
- "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
- "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
- "FP_PDN_CHECK_NODES": 0,
- "SYNTH_ELABORATE_ONLY": 1,
- "PL_RANDOM_GLB_PLACEMENT": 1,
- "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
- "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
- "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
- "FP_PDN_ENABLE_RAILS": 0,
- "DIODE_INSERTION_STRATEGY": 0,
- "RUN_FILL_INSERTION": 0,
- "RUN_TAP_DECAP_INSERTION": 0,
- "FP_PDN_VPITCH": 180,
- "FP_PDN_HPITCH": 180,
- "CLOCK_TREE_SYNTH": 0,
- "FP_PDN_VOFFSET": 5,
- "FP_PDN_HOFFSET": 5,
- "MAGIC_ZEROIZE_ORIGIN": 0,
- "FP_SIZING": "absolute",
- "RUN_CVC": 0,
- "UNIT": "2.4",
- "FP_IO_VEXTEND": "expr::2 * $UNIT",
- "FP_IO_HEXTEND": "expr::2 * $UNIT",
- "FP_IO_VLENGTH": "ref::$UNIT",
- "FP_IO_HLENGTH": "ref::$UNIT",
- "FP_IO_VTHICKNESS_MULT": 4,
- "FP_IO_HTHICKNESS_MULT": 4,
- "FP_PDN_CORE_RING": 1,
- "FP_PDN_CORE_RING_VWIDTH": 3.1,
- "FP_PDN_CORE_RING_HWIDTH": 3.1,
- "FP_PDN_CORE_RING_VOFFSET": 12.45,
- "FP_PDN_CORE_RING_HOFFSET": 12.45,
- "FP_PDN_CORE_RING_VSPACING": 1.7,
- "FP_PDN_CORE_RING_HSPACING": 1.7,
- "FP_PDN_VWIDTH": 3.1,
- "FP_PDN_HWIDTH": 3.1,
- "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
- "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
- "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"],
- "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"],
- "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
- "pdk::sky130*": {
- "RT_MAX_LAYER": "met4",
- "DIE_AREA": "0 0 2920 3520",
- "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
- "scl::sky130_fd_sc_hd": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hdll": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hs": {
- "CLOCK_PERIOD": 8
- },
- "scl::sky130_fd_sc_ls": {
- "CLOCK_PERIOD": 10,
- "SYNTH_MAX_FANOUT": 5
- },
- "scl::sky130_fd_sc_ms": {
- "CLOCK_PERIOD": 10
- }
- },
- "pdk::gf180mcuC": {
- "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
- "FP_PDN_CHECK_NODES": 0,
- "FP_PDN_ENABLE_RAILS": 0,
- "RT_MAX_LAYER": "Metal4",
- "DIE_AREA": "0 0 3000 3000",
- "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
- "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
- "DIODE_INSERTION_STRATEGY": 0,
- "FP_PDN_CHECK_NODES": 0,
- "MAGIC_WRITE_FULL_LEF": 0,
- "FP_PDN_ENABLE_RAILS": 0
- }
+ "PDK" : "sky130A",
+ "STD_CELL_LIBRARY" : "sky130_fd_sc_hd",
+ "CARAVEL_ROOT" : "../../caravel",
+ "CLOCK_NET" : "mprj.clk",
+ "CLOCK_PERIOD" : "10",
+ "CLOCK_PORT" : "user_clock2",
+ "CLOCK_TREE_SYNTH" : "0",
+ "DESIGN_NAME" : "user_project_wrapper",
+ "DIE_AREA" : "0 0 2920 3520",
+ "DIODE_INSERTION_STRATEGY" : "0",
+ "EXTRA_GDS_FILES" : "../../gds/user_proj_example.gds",
+ "EXTRA_LEFS" : "../../lef/user_proj_example.lef",
+ "FILL_INSERTION" : "0",
+ "FP_IO_HEXTEND" : "4.8",
+ "FP_IO_HLENGTH" : "2.4",
+ "FP_IO_HTHICKNESS_MULT" : "4",
+ "FP_IO_VEXTEND" : "4.8",
+ "FP_IO_VLENGTH" : "2.4",
+ "FP_IO_VTHICKNESS_MULT" : "4",
+ "FP_PDN_CHECK_NODES" : "0",
+ "FP_PDN_CORE_RING" : "1",
+ "FP_PDN_CORE_RING_HOFFSET" : "14",
+ "FP_PDN_CORE_RING_HSPACING" : "1.7",
+ "FP_PDN_CORE_RING_HWIDTH" : "3.1",
+ "FP_PDN_CORE_RING_VOFFSET" : "14",
+ "FP_PDN_CORE_RING_VSPACING" : "1.7",
+ "FP_PDN_CORE_RING_VWIDTH" : "3.1",
+ "FP_PDN_ENABLE_RAILS" : "0",
+ "FP_PDN_HOFFSET" : "5",
+ "FP_PDN_HPITCH" : "180",
+ "FP_PDN_HSPACING" : "15.5",
+ "FP_PDN_HWIDTH" : "3.1",
+ "FP_PDN_MACRO_HOOKS" : "mprj vccd1 vssd1",
+ "FP_PDN_VOFFSET" : "5",
+ "FP_PDN_VPITCH" : "180",
+ "FP_PDN_VSPACING" : "15.5",
+ "FP_PDN_VWIDTH" : "3.1",
+ "FP_PIN_ORDER_CFG" : "../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg",
+ "FP_SIZING" : "absolute",
+ "GLB_RT_MAXLAYER" : "5",
+ "GND_NETS" : "vssd1 vssd2 vssa1 vssa2",
+ "MACRO_PLACEMENT_CFG" : "macro.cfg",
+ "MAGIC_ZEROIZE_ORIGIN" : "0",
+ "PL_RANDOM_GLB_PLACEMENT" : "1",
+ "PL_RESIZER_BUFFER_INPUT_PORTS" : "0",
+ "PL_RESIZER_BUFFER_OUTPUT_PORTS" : "0",
+ "PL_RESIZER_DESIGN_OPTIMIZATIONS" : "0",
+ "PL_RESIZER_TIMING_OPTIMIZATIONS" : "0",
+ "RUN_CVC" : "0",
+ "SYNTH_TOP_LEVEL" : "1",
+ "SYNTH_USE_PG_PINS_DEFINES" : "USE_POWER_PINS",
+ "TAP_DECAP_INSERTION" : "0",
+ "VDD_NETS" : "vccd1 vccd2 vdda1 vdda2",
+ "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"],
+ "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_proj_example.v"]
}
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
new file mode 100644
index 0000000..45c3772
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Base Configurations. Don't Touch
+# section begin
+
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
+
+# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) user_project_wrapper
+#section end
+
+# User Configurations
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/user_project_wrapper.v"
+
+## Clock configurations
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "Inst_user_project_wrapper1.wb_clk_i"
+
+set ::env(CLOCK_PERIOD) "10"
+
+## Internal Macros
+### Macro PDN Connections
+set ::env(FP_PDN_MACRO_HOOKS) "\
+ Inst_user_project_wrapper1 vccd1 vssd1"
+
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/user_project_wrapper1.v"
+
+set ::env(EXTRA_LEFS) "\
+ $script_dir/../../lef/user_project_wrapper1.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $script_dir/../../gds/user_project_wrapper1.gds"
+
+# set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+# disable pdn check nodes becuase it hangs with multiple power domains.
+# any issue with pdn connections will be flagged with LVS so it is not a critical check.
+set ::env(FP_PDN_CHECK_NODES) 0
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 0
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
+set ::env(PL_MACRO_HALO) {20 20}
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+set ::env(FP_PDN_ENABLE_RAILS) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(FILL_INSERTION) 0
+set ::env(TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..7199272 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+Inst_user_project_wrapper1 20 20 N
diff --git a/openlane/user_project_wrapper1/config.tcl b/openlane/user_project_wrapper1/config.tcl
new file mode 100644
index 0000000..391e137
--- /dev/null
+++ b/openlane/user_project_wrapper1/config.tcl
@@ -0,0 +1,145 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+
+set ::env(DESIGN_NAME) user_project_wrapper1
+
+set ::env(FP_PDN_CHECK_NODES) 0
+set ::env(FP_PDN_ENABLE_RAILS) 1
+
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "Inst_ChipTop.clock_clock"
+
+set ::env(CLOCK_PERIOD) "40"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2880 3480"
+
+#set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(DIODE_INSERTION_STRATEGY) 5
+
+set ::env(MAGIC_WRITE_FULL_LEF) 0
+
+set ::env(SYNTH_FLAT_TOP) 1
+#set ::env(SYNTH_NO_FLAT) 1
+set ::env(CLOCK_TREE_SYNTH) 1
+set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(STA_REPORT_POWER) 0
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+set ::env(VDD_NETS) {vccd1 }
+set ::env(GND_NETS) {vssd1 }
+set ::env(VDD_PIN) "vccd1"
+set ::env(GND_PIN) "vssd1"
+set ::env(PL_TARGET_DENSITY) 0.25
+set ::env(PL_SKIP_INITIAL_PLACEMENT) 1
+set ::env(DECAP_CELL) {sky130_ef_sc_hd__decap_* sky130_fd_sc_hd__decap_*}
+#set ::env(FILL_CELL) {sky130_fd_sc_hd__fill_}
+#set ::env(CTS_TARGET_SKEW) 200
+#set ::env(CTS_SINK_CLUSTERING_SIZE) 100
+#set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) 1000
+set ::env(FP_IO_VLENGTH) 1
+set ::env(FP_IO_HLENGTH) 1
+set ::env(ROUTING_CORES) 16
+set ::env(GRT_ALLOW_CONGESTION) 1
+#set ::env(GLB_RT_ALLOW_CONGESTION) 1
+#set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(RT_MAX_LAYER) {met4}
+set ::env(FP_PDN_CHECK_NODES) 0
+set ::env(RUN_KLAYOUT_XOR) 0
+set ::env(KLAYOUT_XOR_GDS) 0
+set ::env(KLAYOUT_XOR_XML) 0
+set ::env(FP_PDN_IRDROP) 0
+set ::env(RUN_CVC) 0
+set ::env(RUN_MAGIC_DRC) 0
+#set ::env(TAKE_LAYOUT_SCROT) 1
+
+#set ::env(PL_MAX_DISPLACEMENT_X) 800
+#set ::env(PL_MAX_DISPLACEMENT_Y) 600
+#set ::env(FP_TAP_HORIZONTAL_HALO) 20
+#set ::env(FP_TAP_VERTICAL_HALO) 20
+#set ::env(FP_PDN_HORIZONTAL_HALO) 30
+#set ::env(FP_PDN_VERTICAL_HALO) 30
+#set ::env(FP_PDN_VOFFSET) 5
+#set ::env(FP_PDN_HOFFSET) 235
+#set ::env(FP_PDN_VWIDTH) 1.6
+#set ::env(FP_PDN_HSPACING) 15.5
+#set ::env(FP_PDN_HSPACING) 3
+#set ::env(FP_PDN_VPITCH) 2800
+#set ::env(FP_PDN_HPITCH) {2800}
+#set ::env(PL_MACRO_CHANNEL) {5 30}
+#set ::env(PL_MACRO_HALO) {5 30}
+#set ::env(FP_PDN_HPITCH) {180}
+#set ::env(FP_PDN_VPITCH) {2800}
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+## Source Verilog Files
+#set ::env(VERILOG_FILES) [glob $script_dir/../../verilog/rtl/defines.v $script_dir/../../../verilog/rtl/*.v ]
+set ::env(VERILOG_FILES) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $script_dir/../../../verilog/rtl/user_project_wrapper1.v \
+ $script_dir/../../../verilog/rtl/rocketAlpha/*v "
+
+
+## Internal Macros
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) "$script_dir/../../../openlane/user_project_wrapper1/macro.cfg"
+
+### Black-box verilog and views
+set ::env(VERILOG_FILES_BLACKBOX) "\
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_8x1024_8.v \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+
+set ::env(EXTRA_LEFS) "\
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_8x1024_8.lef \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
+
+set ::env(EXTRA_GDS_FILES) "\
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_8x1024_8.gds \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
+
+set ::env(EXTRA_LIBS) "\
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_8x1024_8_TT_1p8V_25C.lib \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib \
+ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib"
+
+### Macro PDN Connections
+set ::env(FP_PDN_MACRO_HOOKS) "\
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_1 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_1 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_1 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0 vccd1 vssd1 \
+ Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_1 vccd1 vssd1 "
+
+#set ::env(GLB_RT_OBS) "met1 0 0 $::env(DIE_AREA),\
+# met2 0 0 $::env(DIE_AREA),\
+# met3 0 0 $::env(DIE_AREA),\
+# met4 0 0 $::env(DIE_AREA),\
+# met5 0 0 $::env(DIE_AREA)"
+
diff --git a/openlane/user_project_wrapper1/macro.cfg b/openlane/user_project_wrapper1/macro.cfg
new file mode 100644
index 0000000..f74fb8c
--- /dev/null
+++ b/openlane/user_project_wrapper1/macro.cfg
@@ -0,0 +1,25 @@
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.ptw.l2_tlb_ram.l2_tlb_ram_ext.mem_0_0 100 100 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0 2100 3000 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0 150 3000 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_1.data_arrays_0_0_ext.mem_0_0 1100 3000 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0 150 200 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_1 150 850 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0 150 1500 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_1 150 2150 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0 2050 200 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_1 2050 850 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0 2050 1500 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_1 2050 2150 N
+
+##Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.ptw.l2_tlb_ram.l2_tlb_ram_ext.mem_0_0 100 100 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0 2000 3000 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0 150 3000 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_1.data_arrays_0_0_ext.mem_0_0 1100 3000 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0 150 150 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_1 150 700 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0 150 1250 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_1 150 1800 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0 2030 150 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_1 2030 700 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0 2030 1250 N
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_1 2030 1800 N
diff --git a/openlane/user_project_wrapper1/macro.cfg.old b/openlane/user_project_wrapper1/macro.cfg.old
new file mode 100644
index 0000000..a5ed4da
--- /dev/null
+++ b/openlane/user_project_wrapper1/macro.cfg.old
@@ -0,0 +1,12 @@
+#Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.ptw.l2_tlb_ram.l2_tlb_ram_ext.mem_0_0 100 100 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0 1700 2950 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0 100 2950 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_1.data_arrays_0_0_ext.mem_0_0 900 2950 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0 100 250 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_1 100 800 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0 100 1350 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_1 100 1900 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0 2080 250 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_1 2080 800 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0 2080 1350 N
+Inst_ChipTop.system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_1 2080 1900 N
diff --git a/openlane/user_project_wrapper1/pin_order.cfg b/openlane/user_project_wrapper1/pin_order.cfg
new file mode 100644
index 0000000..90cde69
--- /dev/null
+++ b/openlane/user_project_wrapper1/pin_order.cfg
@@ -0,0 +1,156 @@
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/verilog/rtl/rocketAlpha/ClockDividerN.sv b/verilog/rtl/rocketAlpha/ClockDividerN.sv
new file mode 100644
index 0000000..1e09a07
--- /dev/null
+++ b/verilog/rtl/rocketAlpha/ClockDividerN.sv
@@ -0,0 +1,42 @@
+// See LICENSE for license details.
+
+/**
+ * An unsynthesizable divide-by-N clock divider.
+ * Duty cycle is 100 * (ceil(DIV / 2)) / DIV.
+ */
+
+module ClockDividerN #(parameter DIV = 1)(output logic clk_out = 1'b0, input clk_in);
+
+ localparam CWIDTH = $clog2(DIV);
+ localparam LOW_CYCLES = DIV / 2;
+ localparam HIGH_TRANSITION = LOW_CYCLES - 1;
+ localparam LOW_TRANSITION = DIV - 1;
+
+ generate
+ if (DIV == 1) begin
+ // This needs to be procedural because of the assignment on declaration
+ always @(clk_in) begin
+ clk_out = clk_in;
+ end
+ end else begin
+ reg [CWIDTH - 1: 0] count = HIGH_TRANSITION[CWIDTH-1:0];
+ // The blocking assignment to clock out is used to conform what was done
+ // in RC's clock dividers.
+ // It should have the effect of preventing registers in the divided clock
+ // domain latching register updates launched by the fast clock-domain edge
+ // that occurs at the same simulated time (as the divided clock edge).
+ always @(posedge clk_in) begin
+ if (count == LOW_TRANSITION[CWIDTH-1:0]) begin
+ clk_out = 1'b0;
+ count <= '0;
+ end
+ else begin
+ if (count == HIGH_TRANSITION[CWIDTH-1:0]) begin
+ clk_out = 1'b1;
+ end
+ count <= count + 1'b1;
+ end
+ end
+ end
+ endgenerate
+endmodule // ClockDividerN
diff --git a/verilog/rtl/rocketAlpha/EICG_wrapper.v b/verilog/rtl/rocketAlpha/EICG_wrapper.v
new file mode 100644
index 0000000..76ee093
--- /dev/null
+++ b/verilog/rtl/rocketAlpha/EICG_wrapper.v
@@ -0,0 +1,20 @@
+/* verilator lint_off UNOPTFLAT */
+
+module EICG_wrapper(
+ output out,
+ input en,
+ input test_en,
+ input in
+);
+
+ reg en_latched /*verilator clock_enable*/;
+
+ always @(*) begin
+ if (!in) begin
+ en_latched = en || test_en;
+ end
+ end
+
+ assign out = en_latched && in;
+
+endmodule
diff --git a/verilog/rtl/rocketAlpha/IOCell.v b/verilog/rtl/rocketAlpha/IOCell.v
new file mode 100644
index 0000000..a266cec
--- /dev/null
+++ b/verilog/rtl/rocketAlpha/IOCell.v
@@ -0,0 +1,62 @@
+// See LICENSE for license details
+
+`timescale 1ns/1ps
+
+module GenericAnalogIOCell(
+ inout pad,
+ inout core
+);
+
+ assign core = 1'bz;
+ assign pad = core;
+
+endmodule
+
+module GenericDigitalGPIOCell_1(
+ inout pad,
+ output i,
+ input ie,
+ input o,
+ input oe,
+ output io_oeb // caravel GPIO enable (enable output @ active LOW)
+);
+
+ assign pad = oe ? o : 1'bz;
+ assign i = ie ? pad : 1'b0;
+ assign io_oeb = !oe;
+ //assign io_oeb = oe ? 1'b0 : ie ? 1'b1 : 1'bz;
+
+endmodule
+
+module GenericDigitalGPIOCell(
+ inout pad,
+ output i,
+ input ie,
+ input o,
+ input oe
+);
+
+ assign pad = oe ? o : 1'bz;
+ assign i = ie ? pad : 1'b0;
+
+endmodule
+
+module GenericDigitalInIOCell(
+ input pad,
+ output i,
+ input ie
+);
+
+ assign i = ie ? pad : 1'b0;
+
+endmodule
+
+module GenericDigitalOutIOCell(
+ output pad,
+ input o,
+ input oe
+);
+
+ assign pad = oe ? o : 1'bz;
+
+endmodule
diff --git a/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v b/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v
new file mode 100644
index 0000000..568af54
--- /dev/null
+++ b/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v
@@ -0,0 +1,571 @@
+module data_arrays_0_ext(
+ input [10:0] RW0_addr,
+ input RW0_clk,
+ input [63:0] RW0_wdata,
+ output [63:0] RW0_rdata,
+ input RW0_en,
+ input RW0_wmode,
+ input [7:0] RW0_wmask
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ wire [8:0] mem_0_0_addr0;
+ wire mem_0_0_clk0;
+ wire [31:0] mem_0_0_din0;
+ wire [31:0] mem_0_0_dout0;
+ wire mem_0_0_csb0;
+ wire mem_0_0_web0;
+ wire [7:0] mem_0_0_wmask0;
+ wire mem_0_0_clk1;
+ wire mem_0_0_csb1;
+ wire [8:0] mem_0_0_addr1;
+ wire [8:0] mem_0_1_addr0;
+ wire mem_0_1_clk0;
+ wire [31:0] mem_0_1_din0;
+ wire [31:0] mem_0_1_dout0;
+ wire mem_0_1_csb0;
+ wire mem_0_1_web0;
+ wire [7:0] mem_0_1_wmask0;
+ wire mem_0_1_clk1;
+ wire mem_0_1_csb1;
+ wire [8:0] mem_0_1_addr1;
+ wire [8:0] mem_1_0_addr0;
+ wire mem_1_0_clk0;
+ wire [31:0] mem_1_0_din0;
+ wire [31:0] mem_1_0_dout0;
+ wire mem_1_0_csb0;
+ wire mem_1_0_web0;
+ wire [7:0] mem_1_0_wmask0;
+ wire mem_1_0_clk1;
+ wire mem_1_0_csb1;
+ wire [8:0] mem_1_0_addr1;
+ wire [8:0] mem_1_1_addr0;
+ wire mem_1_1_clk0;
+ wire [31:0] mem_1_1_din0;
+ wire [31:0] mem_1_1_dout0;
+ wire mem_1_1_csb0;
+ wire mem_1_1_web0;
+ wire [7:0] mem_1_1_wmask0;
+ wire mem_1_1_clk1;
+ wire mem_1_1_csb1;
+ wire [8:0] mem_1_1_addr1;
+ wire [8:0] mem_2_0_addr0;
+ wire mem_2_0_clk0;
+ wire [31:0] mem_2_0_din0;
+ wire [31:0] mem_2_0_dout0;
+ wire mem_2_0_csb0;
+ wire mem_2_0_web0;
+ wire [7:0] mem_2_0_wmask0;
+ wire mem_2_0_clk1;
+ wire mem_2_0_csb1;
+ wire [8:0] mem_2_0_addr1;
+ wire [8:0] mem_2_1_addr0;
+ wire mem_2_1_clk0;
+ wire [31:0] mem_2_1_din0;
+ wire [31:0] mem_2_1_dout0;
+ wire mem_2_1_csb0;
+ wire mem_2_1_web0;
+ wire [7:0] mem_2_1_wmask0;
+ wire mem_2_1_clk1;
+ wire mem_2_1_csb1;
+ wire [8:0] mem_2_1_addr1;
+ wire [8:0] mem_3_0_addr0;
+ wire mem_3_0_clk0;
+ wire [31:0] mem_3_0_din0;
+ wire [31:0] mem_3_0_dout0;
+ wire mem_3_0_csb0;
+ wire mem_3_0_web0;
+ wire [7:0] mem_3_0_wmask0;
+ wire mem_3_0_clk1;
+ wire mem_3_0_csb1;
+ wire [8:0] mem_3_0_addr1;
+ wire [8:0] mem_3_1_addr0;
+ wire mem_3_1_clk0;
+ wire [31:0] mem_3_1_din0;
+ wire [31:0] mem_3_1_dout0;
+ wire mem_3_1_csb0;
+ wire mem_3_1_web0;
+ wire [7:0] mem_3_1_wmask0;
+ wire mem_3_1_clk1;
+ wire mem_3_1_csb1;
+ wire [8:0] mem_3_1_addr1;
+ wire [1:0] RW0_addr_sel = RW0_addr[10:9];
+ reg [1:0] RW0_addr_sel_reg;
+ wire [31:0] RW0_rdata_0_0 = mem_0_0_dout0;
+ wire [31:0] RW0_rdata_0_1 = mem_0_1_dout0;
+ wire [63:0] RW0_rdata_0 = {RW0_rdata_0_1,RW0_rdata_0_0};
+ wire [31:0] RW0_rdata_1_0 = mem_1_0_dout0;
+ wire [31:0] RW0_rdata_1_1 = mem_1_1_dout0;
+ wire [63:0] RW0_rdata_1 = {RW0_rdata_1_1,RW0_rdata_1_0};
+ wire [31:0] RW0_rdata_2_0 = mem_2_0_dout0;
+ wire [31:0] RW0_rdata_2_1 = mem_2_1_dout0;
+ wire [63:0] RW0_rdata_2 = {RW0_rdata_2_1,RW0_rdata_2_0};
+ wire [31:0] RW0_rdata_3_0 = mem_3_0_dout0;
+ wire [31:0] RW0_rdata_3_1 = mem_3_1_dout0;
+ wire [63:0] RW0_rdata_3 = {RW0_rdata_3_1,RW0_rdata_3_0};
+ wire _GEN_0 = RW0_addr_sel == 2'h0;
+ wire _GEN_1 = RW0_en & RW0_addr_sel == 2'h0;
+ wire _GEN_2 = RW0_addr_sel == 2'h0;
+ wire _GEN_3 = RW0_wmode & RW0_addr_sel == 2'h0;
+ wire _GEN_4 = RW0_wmask[0];
+ wire _GEN_5 = RW0_wmask[0];
+ wire _GEN_6 = RW0_wmask[1];
+ wire [1:0] _GEN_7 = {RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_8 = RW0_wmask[1];
+ wire [2:0] _GEN_9 = {RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_10 = RW0_wmask[2];
+ wire [3:0] _GEN_11 = {RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_12 = RW0_wmask[2];
+ wire [4:0] _GEN_13 = {RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_14 = RW0_wmask[3];
+ wire [5:0] _GEN_15 = {RW0_wmask[2],RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_16 = RW0_wmask[3];
+ wire [6:0] _GEN_17 = {RW0_wmask[3],RW0_wmask[2],RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_18 = RW0_addr_sel == 2'h0;
+ wire _GEN_19 = RW0_en & RW0_addr_sel == 2'h0;
+ wire _GEN_20 = RW0_addr_sel == 2'h0;
+ wire _GEN_21 = RW0_wmode & RW0_addr_sel == 2'h0;
+ wire _GEN_22 = RW0_wmask[4];
+ wire _GEN_23 = RW0_wmask[4];
+ wire _GEN_24 = RW0_wmask[5];
+ wire [1:0] _GEN_25 = {RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_26 = RW0_wmask[5];
+ wire [2:0] _GEN_27 = {RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_28 = RW0_wmask[6];
+ wire [3:0] _GEN_29 = {RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_30 = RW0_wmask[6];
+ wire [4:0] _GEN_31 = {RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_32 = RW0_wmask[7];
+ wire [5:0] _GEN_33 = {RW0_wmask[6],RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_34 = RW0_wmask[7];
+ wire [6:0] _GEN_35 = {RW0_wmask[7],RW0_wmask[6],RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_36 = RW0_addr_sel == 2'h1;
+ wire _GEN_37 = RW0_en & RW0_addr_sel == 2'h1;
+ wire _GEN_38 = RW0_addr_sel == 2'h1;
+ wire _GEN_39 = RW0_wmode & RW0_addr_sel == 2'h1;
+ wire _GEN_40 = RW0_wmask[0];
+ wire _GEN_41 = RW0_wmask[0];
+ wire _GEN_42 = RW0_wmask[1];
+ wire [1:0] _GEN_43 = {RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_44 = RW0_wmask[1];
+ wire [2:0] _GEN_45 = {RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_46 = RW0_wmask[2];
+ wire [3:0] _GEN_47 = {RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_48 = RW0_wmask[2];
+ wire [4:0] _GEN_49 = {RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_50 = RW0_wmask[3];
+ wire [5:0] _GEN_51 = {RW0_wmask[2],RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_52 = RW0_wmask[3];
+ wire [6:0] _GEN_53 = {RW0_wmask[3],RW0_wmask[2],RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_54 = RW0_addr_sel == 2'h1;
+ wire _GEN_55 = RW0_en & RW0_addr_sel == 2'h1;
+ wire _GEN_56 = RW0_addr_sel == 2'h1;
+ wire _GEN_57 = RW0_wmode & RW0_addr_sel == 2'h1;
+ wire _GEN_58 = RW0_wmask[4];
+ wire _GEN_59 = RW0_wmask[4];
+ wire _GEN_60 = RW0_wmask[5];
+ wire [1:0] _GEN_61 = {RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_62 = RW0_wmask[5];
+ wire [2:0] _GEN_63 = {RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_64 = RW0_wmask[6];
+ wire [3:0] _GEN_65 = {RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_66 = RW0_wmask[6];
+ wire [4:0] _GEN_67 = {RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_68 = RW0_wmask[7];
+ wire [5:0] _GEN_69 = {RW0_wmask[6],RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_70 = RW0_wmask[7];
+ wire [6:0] _GEN_71 = {RW0_wmask[7],RW0_wmask[6],RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_72 = RW0_addr_sel == 2'h2;
+ wire _GEN_73 = RW0_en & RW0_addr_sel == 2'h2;
+ wire _GEN_74 = RW0_addr_sel == 2'h2;
+ wire _GEN_75 = RW0_wmode & RW0_addr_sel == 2'h2;
+ wire _GEN_76 = RW0_wmask[0];
+ wire _GEN_77 = RW0_wmask[0];
+ wire _GEN_78 = RW0_wmask[1];
+ wire [1:0] _GEN_79 = {RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_80 = RW0_wmask[1];
+ wire [2:0] _GEN_81 = {RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_82 = RW0_wmask[2];
+ wire [3:0] _GEN_83 = {RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_84 = RW0_wmask[2];
+ wire [4:0] _GEN_85 = {RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_86 = RW0_wmask[3];
+ wire [5:0] _GEN_87 = {RW0_wmask[2],RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_88 = RW0_wmask[3];
+ wire [6:0] _GEN_89 = {RW0_wmask[3],RW0_wmask[2],RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_90 = RW0_addr_sel == 2'h2;
+ wire _GEN_91 = RW0_en & RW0_addr_sel == 2'h2;
+ wire _GEN_92 = RW0_addr_sel == 2'h2;
+ wire _GEN_93 = RW0_wmode & RW0_addr_sel == 2'h2;
+ wire _GEN_94 = RW0_wmask[4];
+ wire _GEN_95 = RW0_wmask[4];
+ wire _GEN_96 = RW0_wmask[5];
+ wire [1:0] _GEN_97 = {RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_98 = RW0_wmask[5];
+ wire [2:0] _GEN_99 = {RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_100 = RW0_wmask[6];
+ wire [3:0] _GEN_101 = {RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_102 = RW0_wmask[6];
+ wire [4:0] _GEN_103 = {RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_104 = RW0_wmask[7];
+ wire [5:0] _GEN_105 = {RW0_wmask[6],RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_106 = RW0_wmask[7];
+ wire [6:0] _GEN_107 = {RW0_wmask[7],RW0_wmask[6],RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_108 = RW0_addr_sel == 2'h3;
+ wire _GEN_109 = RW0_en & RW0_addr_sel == 2'h3;
+ wire _GEN_110 = RW0_addr_sel == 2'h3;
+ wire _GEN_111 = RW0_wmode & RW0_addr_sel == 2'h3;
+ wire _GEN_112 = RW0_wmask[0];
+ wire _GEN_113 = RW0_wmask[0];
+ wire _GEN_114 = RW0_wmask[1];
+ wire [1:0] _GEN_115 = {RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_116 = RW0_wmask[1];
+ wire [2:0] _GEN_117 = {RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_118 = RW0_wmask[2];
+ wire [3:0] _GEN_119 = {RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_120 = RW0_wmask[2];
+ wire [4:0] _GEN_121 = {RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_122 = RW0_wmask[3];
+ wire [5:0] _GEN_123 = {RW0_wmask[2],RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_124 = RW0_wmask[3];
+ wire [6:0] _GEN_125 = {RW0_wmask[3],RW0_wmask[2],RW0_wmask[2],RW0_wmask[1],RW0_wmask[1],RW0_wmask[0],RW0_wmask[0]};
+ wire _GEN_126 = RW0_addr_sel == 2'h3;
+ wire _GEN_127 = RW0_en & RW0_addr_sel == 2'h3;
+ wire _GEN_128 = RW0_addr_sel == 2'h3;
+ wire _GEN_129 = RW0_wmode & RW0_addr_sel == 2'h3;
+ wire _GEN_130 = RW0_wmask[4];
+ wire _GEN_131 = RW0_wmask[4];
+ wire _GEN_132 = RW0_wmask[5];
+ wire [1:0] _GEN_133 = {RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_134 = RW0_wmask[5];
+ wire [2:0] _GEN_135 = {RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_136 = RW0_wmask[6];
+ wire [3:0] _GEN_137 = {RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_138 = RW0_wmask[6];
+ wire [4:0] _GEN_139 = {RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_140 = RW0_wmask[7];
+ wire [5:0] _GEN_141 = {RW0_wmask[6],RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ wire _GEN_142 = RW0_wmask[7];
+ wire [6:0] _GEN_143 = {RW0_wmask[7],RW0_wmask[6],RW0_wmask[6],RW0_wmask[5],RW0_wmask[5],RW0_wmask[4],RW0_wmask[4]};
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_0_0 (
+ .addr0(mem_0_0_addr0),
+ .clk0(mem_0_0_clk0),
+ .din0(mem_0_0_din0),
+ .dout0(mem_0_0_dout0),
+ .csb0(mem_0_0_csb0),
+ .web0(mem_0_0_web0),
+ .wmask0(mem_0_0_wmask0),
+ .clk1(mem_0_0_clk1),
+ .csb1(mem_0_0_csb1),
+ .addr1(mem_0_0_addr1)
+ );
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_0_1 (
+ .addr0(mem_0_1_addr0),
+ .clk0(mem_0_1_clk0),
+ .din0(mem_0_1_din0),
+ .dout0(mem_0_1_dout0),
+ .csb0(mem_0_1_csb0),
+ .web0(mem_0_1_web0),
+ .wmask0(mem_0_1_wmask0),
+ .clk1(mem_0_1_clk1),
+ .csb1(mem_0_1_csb1),
+ .addr1(mem_0_1_addr1)
+ );
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_1_0 (
+ .addr0(mem_1_0_addr0),
+ .clk0(mem_1_0_clk0),
+ .din0(mem_1_0_din0),
+ .dout0(mem_1_0_dout0),
+ .csb0(mem_1_0_csb0),
+ .web0(mem_1_0_web0),
+ .wmask0(mem_1_0_wmask0),
+ .clk1(mem_1_0_clk1),
+ .csb1(mem_1_0_csb1),
+ .addr1(mem_1_0_addr1)
+ );
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_1_1 (
+ .addr0(mem_1_1_addr0),
+ .clk0(mem_1_1_clk0),
+ .din0(mem_1_1_din0),
+ .dout0(mem_1_1_dout0),
+ .csb0(mem_1_1_csb0),
+ .web0(mem_1_1_web0),
+ .wmask0(mem_1_1_wmask0),
+ .clk1(mem_1_1_clk1),
+ .csb1(mem_1_1_csb1),
+ .addr1(mem_1_1_addr1)
+ );
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_2_0 (
+ .addr0(mem_2_0_addr0),
+ .clk0(mem_2_0_clk0),
+ .din0(mem_2_0_din0),
+ .dout0(mem_2_0_dout0),
+ .csb0(mem_2_0_csb0),
+ .web0(mem_2_0_web0),
+ .wmask0(mem_2_0_wmask0),
+ .clk1(mem_2_0_clk1),
+ .csb1(mem_2_0_csb1),
+ .addr1(mem_2_0_addr1)
+ );
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_2_1 (
+ .addr0(mem_2_1_addr0),
+ .clk0(mem_2_1_clk0),
+ .din0(mem_2_1_din0),
+ .dout0(mem_2_1_dout0),
+ .csb0(mem_2_1_csb0),
+ .web0(mem_2_1_web0),
+ .wmask0(mem_2_1_wmask0),
+ .clk1(mem_2_1_clk1),
+ .csb1(mem_2_1_csb1),
+ .addr1(mem_2_1_addr1)
+ );
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_3_0 (
+ .addr0(mem_3_0_addr0),
+ .clk0(mem_3_0_clk0),
+ .din0(mem_3_0_din0),
+ .dout0(mem_3_0_dout0),
+ .csb0(mem_3_0_csb0),
+ .web0(mem_3_0_web0),
+ .wmask0(mem_3_0_wmask0),
+ .clk1(mem_3_0_clk1),
+ .csb1(mem_3_0_csb1),
+ .addr1(mem_3_0_addr1)
+ );
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_3_1 (
+ .addr0(mem_3_1_addr0),
+ .clk0(mem_3_1_clk0),
+ .din0(mem_3_1_din0),
+ .dout0(mem_3_1_dout0),
+ .csb0(mem_3_1_csb0),
+ .web0(mem_3_1_web0),
+ .wmask0(mem_3_1_wmask0),
+ .clk1(mem_3_1_clk1),
+ .csb1(mem_3_1_csb1),
+ .addr1(mem_3_1_addr1)
+ );
+ assign RW0_rdata = RW0_addr_sel_reg == 2'h0 ? RW0_rdata_0 : RW0_addr_sel_reg == 2'h1 ? RW0_rdata_1 : RW0_addr_sel_reg
+ == 2'h2 ? RW0_rdata_2 : RW0_addr_sel_reg == 2'h3 ? RW0_rdata_3 : 64'h0;
+ assign mem_0_0_addr0 = RW0_addr[8:0];
+ assign mem_0_0_clk0 = RW0_clk;
+ assign mem_0_0_din0 = RW0_wdata[31:0];
+ assign mem_0_0_csb0 = ~(RW0_en & RW0_addr_sel == 2'h0);
+ assign mem_0_0_web0 = ~(RW0_wmode & RW0_addr_sel == 2'h0);
+ assign mem_0_0_wmask0 = {RW0_wmask[3],_GEN_17};
+ assign mem_0_0_clk1 = 1'h0;
+ assign mem_0_0_csb1 = 1'h0;
+ assign mem_0_0_addr1 = 9'h0;
+ assign mem_0_1_addr0 = RW0_addr[8:0];
+ assign mem_0_1_clk0 = RW0_clk;
+ assign mem_0_1_din0 = RW0_wdata[63:32];
+ assign mem_0_1_csb0 = ~(RW0_en & RW0_addr_sel == 2'h0);
+ assign mem_0_1_web0 = ~(RW0_wmode & RW0_addr_sel == 2'h0);
+ assign mem_0_1_wmask0 = {RW0_wmask[7],_GEN_35};
+ assign mem_0_1_clk1 = 1'h0;
+ assign mem_0_1_csb1 = 1'h0;
+ assign mem_0_1_addr1 = 9'h0;
+ assign mem_1_0_addr0 = RW0_addr[8:0];
+ assign mem_1_0_clk0 = RW0_clk;
+ assign mem_1_0_din0 = RW0_wdata[31:0];
+ assign mem_1_0_csb0 = ~(RW0_en & RW0_addr_sel == 2'h1);
+ assign mem_1_0_web0 = ~(RW0_wmode & RW0_addr_sel == 2'h1);
+ assign mem_1_0_wmask0 = {RW0_wmask[3],_GEN_17};
+ assign mem_1_0_clk1 = 1'h0;
+ assign mem_1_0_csb1 = 1'h0;
+ assign mem_1_0_addr1 = 9'h0;
+ assign mem_1_1_addr0 = RW0_addr[8:0];
+ assign mem_1_1_clk0 = RW0_clk;
+ assign mem_1_1_din0 = RW0_wdata[63:32];
+ assign mem_1_1_csb0 = ~(RW0_en & RW0_addr_sel == 2'h1);
+ assign mem_1_1_web0 = ~(RW0_wmode & RW0_addr_sel == 2'h1);
+ assign mem_1_1_wmask0 = {RW0_wmask[7],_GEN_35};
+ assign mem_1_1_clk1 = 1'h0;
+ assign mem_1_1_csb1 = 1'h0;
+ assign mem_1_1_addr1 = 9'h0;
+ assign mem_2_0_addr0 = RW0_addr[8:0];
+ assign mem_2_0_clk0 = RW0_clk;
+ assign mem_2_0_din0 = RW0_wdata[31:0];
+ assign mem_2_0_csb0 = ~(RW0_en & RW0_addr_sel == 2'h2);
+ assign mem_2_0_web0 = ~(RW0_wmode & RW0_addr_sel == 2'h2);
+ assign mem_2_0_wmask0 = {RW0_wmask[3],_GEN_17};
+ assign mem_2_0_clk1 = 1'h0;
+ assign mem_2_0_csb1 = 1'h0;
+ assign mem_2_0_addr1 = 9'h0;
+ assign mem_2_1_addr0 = RW0_addr[8:0];
+ assign mem_2_1_clk0 = RW0_clk;
+ assign mem_2_1_din0 = RW0_wdata[63:32];
+ assign mem_2_1_csb0 = ~(RW0_en & RW0_addr_sel == 2'h2);
+ assign mem_2_1_web0 = ~(RW0_wmode & RW0_addr_sel == 2'h2);
+ assign mem_2_1_wmask0 = {RW0_wmask[7],_GEN_35};
+ assign mem_2_1_clk1 = 1'h0;
+ assign mem_2_1_csb1 = 1'h0;
+ assign mem_2_1_addr1 = 9'h0;
+ assign mem_3_0_addr0 = RW0_addr[8:0];
+ assign mem_3_0_clk0 = RW0_clk;
+ assign mem_3_0_din0 = RW0_wdata[31:0];
+ assign mem_3_0_csb0 = ~(RW0_en & RW0_addr_sel == 2'h3);
+ assign mem_3_0_web0 = ~(RW0_wmode & RW0_addr_sel == 2'h3);
+ assign mem_3_0_wmask0 = {RW0_wmask[3],_GEN_17};
+ assign mem_3_0_clk1 = 1'h0;
+ assign mem_3_0_csb1 = 1'h0;
+ assign mem_3_0_addr1 = 9'h0;
+ assign mem_3_1_addr0 = RW0_addr[8:0];
+ assign mem_3_1_clk0 = RW0_clk;
+ assign mem_3_1_din0 = RW0_wdata[63:32];
+ assign mem_3_1_csb0 = ~(RW0_en & RW0_addr_sel == 2'h3);
+ assign mem_3_1_web0 = ~(RW0_wmode & RW0_addr_sel == 2'h3);
+ assign mem_3_1_wmask0 = {RW0_wmask[7],_GEN_35};
+ assign mem_3_1_clk1 = 1'h0;
+ assign mem_3_1_csb1 = 1'h0;
+ assign mem_3_1_addr1 = 9'h0;
+ always @(posedge RW0_clk) begin
+ if (RW0_en) begin
+ RW0_addr_sel_reg <= RW0_addr_sel;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ RW0_addr_sel_reg = _RAND_0[1:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module tag_array_ext(
+ input [5:0] RW0_addr,
+ input RW0_clk,
+ input [20:0] RW0_wdata,
+ output [20:0] RW0_rdata,
+ input RW0_en,
+ input RW0_wmode,
+ input RW0_wmask
+);
+ wire [7:0] mem_0_0_addr0;
+ wire mem_0_0_clk0;
+ wire [31:0] mem_0_0_din0;
+ wire [31:0] mem_0_0_dout0;
+ wire mem_0_0_csb0;
+ wire mem_0_0_web0;
+ wire [7:0] mem_0_0_wmask0;
+ wire mem_0_0_clk1;
+ wire mem_0_0_csb1;
+ wire [7:0] mem_0_0_addr1;
+ wire [20:0] RW0_rdata_0_0 = mem_0_0_dout0[20:0];
+ wire [20:0] RW0_rdata_0 = RW0_rdata_0_0;
+ wire [1:0] _GEN_0 = {RW0_wmask,RW0_wmask};
+ wire [2:0] _GEN_1 = {RW0_wmask,RW0_wmask,RW0_wmask};
+ wire [3:0] _GEN_2 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
+ wire [4:0] _GEN_3 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
+ wire [5:0] _GEN_4 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
+ wire [6:0] _GEN_5 = {1'h0,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
+ sky130_sram_1kbyte_1rw1r_32x256_8 mem_0_0 (
+ .addr0(mem_0_0_addr0),
+ .clk0(mem_0_0_clk0),
+ .din0(mem_0_0_din0),
+ .dout0(mem_0_0_dout0),
+ .csb0(mem_0_0_csb0),
+ .web0(mem_0_0_web0),
+ .wmask0(mem_0_0_wmask0),
+ .clk1(mem_0_0_clk1),
+ .csb1(mem_0_0_csb1),
+ .addr1(mem_0_0_addr1)
+ );
+ assign RW0_rdata = mem_0_0_dout0[20:0];
+ assign mem_0_0_addr0 = {{2'd0}, RW0_addr};
+ assign mem_0_0_clk0 = RW0_clk;
+ assign mem_0_0_din0 = {{11'd0}, RW0_wdata};
+ assign mem_0_0_csb0 = ~RW0_en;
+ assign mem_0_0_web0 = ~RW0_wmode;
+ assign mem_0_0_wmask0 = {1'h0,_GEN_5};
+ assign mem_0_0_clk1 = 1'h0;
+ assign mem_0_0_csb1 = 1'h0;
+ assign mem_0_0_addr1 = 8'h0;
+endmodule
+module data_arrays_0_0_ext(
+ input [8:0] RW0_addr,
+ input RW0_clk,
+ input [31:0] RW0_wdata,
+ output [31:0] RW0_rdata,
+ input RW0_en,
+ input RW0_wmode,
+ input RW0_wmask
+);
+ wire [8:0] mem_0_0_addr0;
+ wire mem_0_0_clk0;
+ wire [31:0] mem_0_0_din0;
+ wire [31:0] mem_0_0_dout0;
+ wire mem_0_0_csb0;
+ wire mem_0_0_web0;
+ wire [7:0] mem_0_0_wmask0;
+ wire mem_0_0_clk1;
+ wire mem_0_0_csb1;
+ wire [8:0] mem_0_0_addr1;
+ wire [31:0] RW0_rdata_0_0 = mem_0_0_dout0;
+ wire [31:0] RW0_rdata_0 = RW0_rdata_0_0;
+ wire [1:0] _GEN_0 = {RW0_wmask,RW0_wmask};
+ wire [2:0] _GEN_1 = {RW0_wmask,RW0_wmask,RW0_wmask};
+ wire [3:0] _GEN_2 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
+ wire [4:0] _GEN_3 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
+ wire [5:0] _GEN_4 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
+ wire [6:0] _GEN_5 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
+ sky130_sram_2kbyte_1rw1r_32x512_8 mem_0_0 (
+ .addr0(mem_0_0_addr0),
+ .clk0(mem_0_0_clk0),
+ .din0(mem_0_0_din0),
+ .dout0(mem_0_0_dout0),
+ .csb0(mem_0_0_csb0),
+ .web0(mem_0_0_web0),
+ .wmask0(mem_0_0_wmask0),
+ .clk1(mem_0_0_clk1),
+ .csb1(mem_0_0_csb1),
+ .addr1(mem_0_0_addr1)
+ );
+ assign RW0_rdata = mem_0_0_dout0;
+ assign mem_0_0_addr0 = RW0_addr;
+ assign mem_0_0_clk0 = RW0_clk;
+ assign mem_0_0_din0 = RW0_wdata;
+ assign mem_0_0_csb0 = ~RW0_en;
+ assign mem_0_0_web0 = ~RW0_wmode;
+ assign mem_0_0_wmask0 = {RW0_wmask,_GEN_5};
+ assign mem_0_0_clk1 = 1'h0;
+ assign mem_0_0_csb1 = 1'h0;
+ assign mem_0_0_addr1 = 9'h0;
+endmodule
diff --git a/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.v b/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.v
new file mode 100644
index 0000000..b4e0864
--- /dev/null
+++ b/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.v
@@ -0,0 +1,226163 @@
+module IntXbar(
+ input auto_int_in_4_0,
+ input auto_int_in_3_0,
+ input auto_int_in_2_0,
+ input auto_int_in_2_1,
+ input auto_int_in_2_2,
+ input auto_int_in_2_3,
+ input auto_int_in_1_0,
+ input auto_int_in_0_0,
+ output auto_int_out_0,
+ output auto_int_out_1,
+ output auto_int_out_2,
+ output auto_int_out_3,
+ output auto_int_out_4,
+ output auto_int_out_5,
+ output auto_int_out_6,
+ output auto_int_out_7
+);
+ assign auto_int_out_0 = auto_int_in_0_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_1 = auto_int_in_1_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_2 = auto_int_in_2_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_3 = auto_int_in_2_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_4 = auto_int_in_2_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_5 = auto_int_in_2_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_6 = auto_int_in_3_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_7 = auto_int_in_4_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module InterruptBusWrapper(
+ input auto_int_bus_int_in_4_0,
+ input auto_int_bus_int_in_3_0,
+ input auto_int_bus_int_in_2_0,
+ input auto_int_bus_int_in_2_1,
+ input auto_int_bus_int_in_2_2,
+ input auto_int_bus_int_in_2_3,
+ input auto_int_bus_int_in_1_0,
+ input auto_int_bus_int_in_0_0,
+ output auto_int_bus_int_out_0,
+ output auto_int_bus_int_out_1,
+ output auto_int_bus_int_out_2,
+ output auto_int_bus_int_out_3,
+ output auto_int_bus_int_out_4,
+ output auto_int_bus_int_out_5,
+ output auto_int_bus_int_out_6,
+ output auto_int_bus_int_out_7
+);
+ wire int_bus_auto_int_in_4_0; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_in_3_0; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_in_2_0; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_in_2_1; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_in_2_2; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_in_2_3; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_in_1_0; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_in_0_0; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_out_0; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_out_1; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_out_2; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_out_3; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_out_4; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_out_5; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_out_6; // @[InterruptBus.scala 14:27]
+ wire int_bus_auto_int_out_7; // @[InterruptBus.scala 14:27]
+ IntXbar int_bus ( // @[InterruptBus.scala 14:27]
+ .auto_int_in_4_0(int_bus_auto_int_in_4_0),
+ .auto_int_in_3_0(int_bus_auto_int_in_3_0),
+ .auto_int_in_2_0(int_bus_auto_int_in_2_0),
+ .auto_int_in_2_1(int_bus_auto_int_in_2_1),
+ .auto_int_in_2_2(int_bus_auto_int_in_2_2),
+ .auto_int_in_2_3(int_bus_auto_int_in_2_3),
+ .auto_int_in_1_0(int_bus_auto_int_in_1_0),
+ .auto_int_in_0_0(int_bus_auto_int_in_0_0),
+ .auto_int_out_0(int_bus_auto_int_out_0),
+ .auto_int_out_1(int_bus_auto_int_out_1),
+ .auto_int_out_2(int_bus_auto_int_out_2),
+ .auto_int_out_3(int_bus_auto_int_out_3),
+ .auto_int_out_4(int_bus_auto_int_out_4),
+ .auto_int_out_5(int_bus_auto_int_out_5),
+ .auto_int_out_6(int_bus_auto_int_out_6),
+ .auto_int_out_7(int_bus_auto_int_out_7)
+ );
+ assign auto_int_bus_int_out_0 = int_bus_auto_int_out_0; // @[LazyModule.scala 311:12]
+ assign auto_int_bus_int_out_1 = int_bus_auto_int_out_1; // @[LazyModule.scala 311:12]
+ assign auto_int_bus_int_out_2 = int_bus_auto_int_out_2; // @[LazyModule.scala 311:12]
+ assign auto_int_bus_int_out_3 = int_bus_auto_int_out_3; // @[LazyModule.scala 311:12]
+ assign auto_int_bus_int_out_4 = int_bus_auto_int_out_4; // @[LazyModule.scala 311:12]
+ assign auto_int_bus_int_out_5 = int_bus_auto_int_out_5; // @[LazyModule.scala 311:12]
+ assign auto_int_bus_int_out_6 = int_bus_auto_int_out_6; // @[LazyModule.scala 311:12]
+ assign auto_int_bus_int_out_7 = int_bus_auto_int_out_7; // @[LazyModule.scala 311:12]
+ assign int_bus_auto_int_in_4_0 = auto_int_bus_int_in_4_0; // @[LazyModule.scala 309:16]
+ assign int_bus_auto_int_in_3_0 = auto_int_bus_int_in_3_0; // @[LazyModule.scala 309:16]
+ assign int_bus_auto_int_in_2_0 = auto_int_bus_int_in_2_0; // @[LazyModule.scala 309:16]
+ assign int_bus_auto_int_in_2_1 = auto_int_bus_int_in_2_1; // @[LazyModule.scala 309:16]
+ assign int_bus_auto_int_in_2_2 = auto_int_bus_int_in_2_2; // @[LazyModule.scala 309:16]
+ assign int_bus_auto_int_in_2_3 = auto_int_bus_int_in_2_3; // @[LazyModule.scala 309:16]
+ assign int_bus_auto_int_in_1_0 = auto_int_bus_int_in_1_0; // @[LazyModule.scala 309:16]
+ assign int_bus_auto_int_in_0_0 = auto_int_bus_int_in_0_0; // @[LazyModule.scala 309:16]
+endmodule
+module ClockGroupAggregator(
+ input auto_in_member_subsystem_sbus_0_clock,
+ input auto_in_member_subsystem_sbus_0_reset,
+ output auto_out_member_subsystem_sbus_0_clock,
+ output auto_out_member_subsystem_sbus_0_reset
+);
+ assign auto_out_member_subsystem_sbus_0_clock = auto_in_member_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_subsystem_sbus_0_reset = auto_in_member_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockGroup(
+ input auto_in_member_subsystem_sbus_0_clock,
+ input auto_in_member_subsystem_sbus_0_reset,
+ output auto_out_clock,
+ output auto_out_reset
+);
+ assign auto_out_clock = auto_in_member_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_reset = auto_in_member_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module FixedClockBroadcast(
+ input auto_in_clock,
+ input auto_in_reset,
+ output auto_out_2_clock,
+ output auto_out_2_reset,
+ output auto_out_0_clock,
+ output auto_out_0_reset
+);
+ assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_17 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_20 = _T_17 & _source_ok_T; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_26 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_28 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_29 = {1'b0,$signed(_T_28)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_31 = $signed(_T_29) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_32 = $signed(_T_31) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_33 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_36 = $signed(_T_34) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_38 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_39 = {1'b0,$signed(_T_38)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_41 = $signed(_T_39) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_42 = $signed(_T_41) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_43 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_44 = {1'b0,$signed(_T_43)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_46 = $signed(_T_44) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_47 = $signed(_T_46) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_48 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_51 = $signed(_T_49) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_52 = $signed(_T_51) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_53 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_54 = {1'b0,$signed(_T_53)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_56 = $signed(_T_54) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_57 = $signed(_T_56) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_58 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_59 = {1'b0,$signed(_T_58)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_61 = $signed(_T_59) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_62 = $signed(_T_61) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_63 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_66 = $signed(_T_64) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_67 = $signed(_T_66) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_68 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_71 = $signed(_T_69) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_72 = $signed(_T_71) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_73 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_76 = $signed(_T_74) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_77 = $signed(_T_76) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_78 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_79 = {1'b0,$signed(_T_78)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_81 = $signed(_T_79) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_82 = $signed(_T_81) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_191 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_195 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_196 = _T_195 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_200 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_204 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_384 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_397 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_416 = _T_17 & _T_32; // @[Parameters.scala 670:56]
+ wire _T_418 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_485 = _T_27 | _T_37 | _T_42 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_77 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_486 = _T_418 & _T_485; // @[Parameters.scala 670:56]
+ wire _T_488 = _T_416 | _T_486; // @[Parameters.scala 672:30]
+ wire _T_498 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_502 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_510 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_577 = _T_27 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_578 = _T_418 & _T_577; // @[Parameters.scala 670:56]
+ wire _T_599 = _T_416 | _T_578; // @[Parameters.scala 672:30]
+ wire _T_601 = _T_20 & _T_599; // @[Monitor.scala 115:71]
+ wire _T_619 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_724 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_725 = io_in_a_bits_mask & _T_724; // @[Monitor.scala 127:31]
+ wire _T_726 = _T_725 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_730 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_738 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_793 = _T_27 | _T_32 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_794 = _T_738 & _T_793; // @[Parameters.scala 670:56]
+ wire _T_816 = _T_20 & _T_794; // @[Monitor.scala 131:74]
+ wire _T_826 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_834 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_930 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_938 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1024 = _T_20 & _T_416; // @[Monitor.scala 147:68]
+ wire _T_1034 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1046 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _T_1050 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1054 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1058 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1062 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1066 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1070 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1081 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1085 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1098 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1118 = _T_1066 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1127 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1144 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1162 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1192 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1193 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1197 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1201 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1205 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1209 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1216 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1217 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1221 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1225 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1233 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1237 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_72 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_74 = {{8'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_74 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1243 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1246 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [2:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [19:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire _T_1250 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1254 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1256 = ~_T_1050; // @[Monitor.scala 671:74]
+ wire _T_1257 = io_in_d_valid & d_first_1 & ~_T_1050; // @[Monitor.scala 671:71]
+ wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1050 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_sizes_clr_T_5 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_1256 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1256 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1256 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire same_cycle_resp = _T_1243 & _source_ok_T; // @[Monitor.scala 681:88]
+ wire _T_1269 = inflight | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1274 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1275 = io_in_d_bits_opcode == _GEN_32 | _T_1274; // @[Monitor.scala 685:77]
+ wire _T_1279 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1286 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1287 = io_in_d_bits_opcode == _GEN_48 | _T_1286; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_77 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1291 = _GEN_77 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1301 = _T_1254 & a_first_1 & io_in_a_valid & _source_ok_T & _T_1256; // @[Monitor.scala 694:116]
+ wire _T_1303 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set_wo_ready = _GEN_15[0];
+ wire d_clr_wo_ready = _GEN_21[0];
+ wire _T_1310 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [7:0] a_sizes_set = _GEN_20[7:0];
+ wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [7:0] d_sizes_clr = _GEN_24[7:0];
+ wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1319 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _GEN_80 = {{8'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_80 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1345 = io_in_d_valid & d_first_2 & _T_1050; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1050 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1363 = _GEN_77 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
+ wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_384 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_384) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_20 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_20) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_488 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_488) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_726 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_726) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_826 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_826) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_930 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_930) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1024 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1024) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1034 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1034) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1046 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1046) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1066 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1066) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1193 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1193) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1197 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1201 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1201) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1205 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1205) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1209 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1209) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1217 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1217) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1221 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1221) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1225 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1225) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1233 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1237 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1237) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1246 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1246 & ~reset & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1269 & (_T_1257 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_2 & ~_T_1269) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1257 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & same_cycle_resp & _T_2 & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1279 & (_T_1257 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & same_cycle_resp & _T_2 & ~_T_1279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1287 & (_T_1257 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~same_cycle_resp & _T_2 & ~_T_1287) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1291 & (_T_1257 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~same_cycle_resp & _T_2 & ~_T_1291) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1303 & (_T_1301 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1301 & _T_2 & ~_T_1303) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1310 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1310) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1319 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1319) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1363 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1363) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ sink = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ denied = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_13[3:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_sizes = _RAND_14[7:0];
+ _RAND_15 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_15[8:0];
+ _RAND_16 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ watchdog = _RAND_17[31:0];
+ _RAND_18 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_18[7:0];
+ _RAND_19 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_19[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_1(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_1 = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
+ wire source_ok = io_in_a_bits_source | _source_ok_T_1; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_24 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_26 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_31 = _T_26 & source_ok; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_37 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_38 = $signed(_T_37) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_39 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_40 = {1'b0,$signed(_T_39)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_42 = $signed(_T_40) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_43 = $signed(_T_42) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_44 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_45 = {1'b0,$signed(_T_44)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_47 = $signed(_T_45) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_48 = $signed(_T_47) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_49 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_50 = {1'b0,$signed(_T_49)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_52 = $signed(_T_50) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_53 = $signed(_T_52) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_54 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_55 = {1'b0,$signed(_T_54)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_57 = $signed(_T_55) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_58 = $signed(_T_57) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_59 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_60 = {1'b0,$signed(_T_59)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_62 = $signed(_T_60) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_63 = $signed(_T_62) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_64 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_67 = $signed(_T_65) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_68 = $signed(_T_67) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_69 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_72 = $signed(_T_70) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_73 = $signed(_T_72) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_74 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_75 = {1'b0,$signed(_T_74)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_77 = $signed(_T_75) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_78 = $signed(_T_77) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_79 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_80 = {1'b0,$signed(_T_79)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_82 = $signed(_T_80) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_83 = $signed(_T_82) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_84 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_85 = {1'b0,$signed(_T_84)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_87 = $signed(_T_85) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_88 = $signed(_T_87) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_89 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_90 = {1'b0,$signed(_T_89)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_92 = $signed(_T_90) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_93 = $signed(_T_92) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_202 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_206 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_207 = _T_206 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_211 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_215 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_397 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_410 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_431 = _T_26 & _T_43; // @[Parameters.scala 670:56]
+ wire _T_433 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_500 = _T_38 | _T_48 | _T_53 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_88 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_501 = _T_433 & _T_500; // @[Parameters.scala 670:56]
+ wire _T_503 = _T_431 | _T_501; // @[Parameters.scala 672:30]
+ wire _T_513 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_517 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_525 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_594 = _T_38 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_595 = _T_433 & _T_594; // @[Parameters.scala 670:56]
+ wire _T_616 = _T_431 | _T_595; // @[Parameters.scala 672:30]
+ wire _T_618 = _T_31 & _T_616; // @[Monitor.scala 115:71]
+ wire _T_636 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_743 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_744 = io_in_a_bits_mask & _T_743; // @[Monitor.scala 127:31]
+ wire _T_745 = _T_744 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_749 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_759 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_814 = _T_38 | _T_43 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_815 = _T_759 & _T_814; // @[Parameters.scala 670:56]
+ wire _T_837 = _T_31 & _T_815; // @[Monitor.scala 131:74]
+ wire _T_847 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_855 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_953 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_961 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1049 = _T_31 & _T_431; // @[Monitor.scala 147:68]
+ wire _T_1059 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1071 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_3 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
+ wire source_ok_1 = io_in_d_bits_source | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire _T_1075 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1079 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1083 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1087 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1091 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1095 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1106 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1110 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1123 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1143 = _T_1091 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1152 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1169 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1187 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1217 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1218 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1222 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1226 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1230 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1234 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1241 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1242 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1246 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1250 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1254 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1258 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1262 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [1:0] inflight; // @[Monitor.scala 611:27]
+ reg [7:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [15:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [2:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{8'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [3:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1268 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1271 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [2:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [19:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [1:0] _T_1273 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_1275 = ~_T_1273[0]; // @[Monitor.scala 658:17]
+ wire [1:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1279 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1281 = ~_T_1075; // @[Monitor.scala 671:74]
+ wire _T_1282 = io_in_d_valid & d_first_1 & ~_T_1075; // @[Monitor.scala 671:71]
+ wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_1075 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _GEN_3 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [30:0] _GEN_4 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [30:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [1:0] d_clr = _d_first_T & d_first_1 & _T_1281 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1281 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1281 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1268 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [1:0] _T_1292 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_1294 = _T_1292[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1299 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1300 = io_in_d_bits_opcode == _GEN_32 | _T_1299; // @[Monitor.scala 685:77]
+ wire _T_1304 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1311 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1312 = io_in_d_bits_opcode == _GEN_48 | _T_1311; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_78 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1316 = _GEN_78 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1326 = _T_1279 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1281; // @[Monitor.scala 694:116]
+ wire _T_1328 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire _T_1335 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [7:0] a_opcodes_set = _GEN_19[7:0];
+ wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [7:0] d_opcodes_clr = _GEN_23[7:0];
+ wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [15:0] a_sizes_set = _GEN_20[15:0];
+ wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [15:0] d_sizes_clr = _GEN_24[15:0];
+ wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1344 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [1:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [15:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1370 = io_in_d_valid & d_first_2 & _T_1075; // @[Monitor.scala 779:71]
+ wire [1:0] d_clr_1 = _d_first_T & d_first_2 & _T_1075 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 783:90 784:21]
+ wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1075 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire [1:0] _T_1378 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1388 = _GEN_78 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [1:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [15:0] d_sizes_clr_1 = _GEN_69[15:0];
+ wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [15:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1413 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 2'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 8'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 16'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 2'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 16'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_202 & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_T_202) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_207 & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_T_207) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_211 & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_T_211) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_202 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_202) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_207 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_207) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_211 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_211) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_31 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_31) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_211 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_211) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_745 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_745) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_837 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_837) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_847 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_847) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_837 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_837) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_953 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_953) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1049 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_1049) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1059 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_1059) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_211 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_211) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1071 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1071) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1091 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1091) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1106 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1106) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1110 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1110) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1106 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1106) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1110 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1110) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1218 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1222 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1222) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1226 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1226) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1230 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1230) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1234 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1234) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1242 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1246 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1246) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1254 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1254) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1258 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1258) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1262 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1262) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1271 & ~reset & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1294 & (_T_1282 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & _T_2 & ~_T_1294) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1300 & (_T_1282 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & same_cycle_resp & _T_2 & ~_T_1300) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1304 & (_T_1282 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & same_cycle_resp & _T_2 & ~_T_1304) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1312 & (_T_1282 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & ~same_cycle_resp & _T_2 & ~_T_1312) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1316 & (_T_1282 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & ~same_cycle_resp & _T_2 & ~_T_1316) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1328 & (_T_1326 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1326 & _T_2 & ~_T_1328) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1335 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1335) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1344 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1344) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1378[0] & (_T_1370 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1370 & _T_2 & ~_T_1378[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1388 & (_T_1370 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1370 & _T_2 & ~_T_1388) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1413 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:55)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[1:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[7:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[15:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[1:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[15:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLXbar(
+ input clock,
+ input reset,
+ output auto_in_1_a_ready,
+ input auto_in_1_a_valid,
+ input [2:0] auto_in_1_a_bits_opcode,
+ input [2:0] auto_in_1_a_bits_param,
+ input [3:0] auto_in_1_a_bits_size,
+ input auto_in_1_a_bits_source,
+ input [31:0] auto_in_1_a_bits_address,
+ input [7:0] auto_in_1_a_bits_mask,
+ input [63:0] auto_in_1_a_bits_data,
+ input auto_in_1_a_bits_corrupt,
+ input auto_in_1_d_ready,
+ output auto_in_1_d_valid,
+ output [2:0] auto_in_1_d_bits_opcode,
+ output [1:0] auto_in_1_d_bits_param,
+ output [3:0] auto_in_1_d_bits_size,
+ output auto_in_1_d_bits_source,
+ output auto_in_1_d_bits_sink,
+ output auto_in_1_d_bits_denied,
+ output [63:0] auto_in_1_d_bits_data,
+ output auto_in_1_d_bits_corrupt,
+ output auto_in_0_a_ready,
+ input auto_in_0_a_valid,
+ input [2:0] auto_in_0_a_bits_opcode,
+ input [2:0] auto_in_0_a_bits_param,
+ input [3:0] auto_in_0_a_bits_size,
+ input auto_in_0_a_bits_source,
+ input [31:0] auto_in_0_a_bits_address,
+ input [7:0] auto_in_0_a_bits_mask,
+ input [63:0] auto_in_0_a_bits_data,
+ input auto_in_0_a_bits_corrupt,
+ input auto_in_0_d_ready,
+ output auto_in_0_d_valid,
+ output [2:0] auto_in_0_d_bits_opcode,
+ output [1:0] auto_in_0_d_bits_param,
+ output [3:0] auto_in_0_d_bits_size,
+ output auto_in_0_d_bits_sink,
+ output auto_in_0_d_bits_denied,
+ output [63:0] auto_in_0_d_bits_data,
+ output auto_in_0_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [1:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input [1:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_clock; // @[Nodes.scala 24:25]
+ wire monitor_1_reset; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire [1:0] _GEN_1 = {{1'd0}, auto_in_0_a_bits_source}; // @[Xbar.scala 237:55]
+ wire [1:0] in_0_a_bits_source = _GEN_1 | 2'h2; // @[Xbar.scala 237:55]
+ wire requestDOI_0_0 = auto_out_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
+ wire requestDOI_0_1 = ~auto_out_d_bits_source[1]; // @[Parameters.scala 54:32]
+ wire [26:0] _beatsAI_decode_T_1 = 27'hfff << auto_in_0_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] _beatsAI_decode_T_3 = ~_beatsAI_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] beatsAI_decode = _beatsAI_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire beatsAI_opdata = ~auto_in_0_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala 220:14]
+ wire [26:0] _beatsAI_decode_T_5 = 27'hfff << auto_in_1_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] _beatsAI_decode_T_7 = ~_beatsAI_decode_T_5[11:0]; // @[package.scala 234:46]
+ wire [8:0] beatsAI_decode_1 = _beatsAI_decode_T_7[11:3]; // @[Edges.scala 219:59]
+ wire beatsAI_opdata_1 = ~auto_in_1_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ wire [8:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 9'h0; // @[Edges.scala 220:14]
+ reg [8:0] beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle = beatsLeft == 9'h0; // @[Arbiter.scala 88:28]
+ wire latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
+ wire [1:0] readys_valid = {auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 31:58]
+ wire _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
+ reg [1:0] readys_mask; // @[Arbiter.scala 23:23]
+ wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
+ wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
+ wire [3:0] readys_filter = {_readys_filter_T_1,auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 31:58]
+ wire [3:0] _GEN_2 = {{1'd0}, readys_filter[3:1]}; // @[package.scala 253:43]
+ wire [3:0] _readys_unready_T_1 = readys_filter | _GEN_2; // @[package.scala 253:43]
+ wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
+ wire [3:0] _GEN_3 = {{1'd0}, _readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
+ wire [3:0] readys_unready = _GEN_3 | _readys_unready_T_4; // @[Arbiter.scala 25:58]
+ wire [1:0] _readys_readys_T_2 = readys_unready[3:2] & readys_unready[1:0]; // @[Arbiter.scala 26:39]
+ wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
+ wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
+ wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
+ wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[1:0]; // @[package.scala 244:43]
+ wire readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
+ wire readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_0 = readys_0 & auto_in_0_a_valid; // @[Arbiter.scala 97:79]
+ wire earlyWinner_1 = readys_1 & auto_in_1_a_valid; // @[Arbiter.scala 97:79]
+ wire _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
+ wire _T_10 = auto_in_0_a_valid | auto_in_1_a_valid; // @[Arbiter.scala 107:36]
+ wire _T_11 = ~(auto_in_0_a_valid | auto_in_1_a_valid); // @[Arbiter.scala 107:15]
+ wire [8:0] maskedBeats_0 = earlyWinner_0 ? beatsAI_0 : 9'h0; // @[Arbiter.scala 111:73]
+ wire [8:0] maskedBeats_1 = earlyWinner_1 ? beatsAI_1 : 9'h0; // @[Arbiter.scala 111:73]
+ wire [8:0] initBeats = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala 112:44]
+ reg state_0; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire _out_0_a_earlyValid_T_3 = state_0 & auto_in_0_a_valid | state_1 & auto_in_1_a_valid; // @[Mux.scala 27:73]
+ wire out_2_0_a_earlyValid = idle ? _T_10 : _out_0_a_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_out_a_ready & out_2_0_a_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ wire [8:0] _GEN_4 = {{8'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
+ wire [8:0] _beatsLeft_T_4 = beatsLeft - _GEN_4; // @[Arbiter.scala 113:52]
+ wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
+ wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire [63:0] _T_27 = muxStateEarly_0 ? auto_in_0_a_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_28 = muxStateEarly_1 ? auto_in_1_a_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_30 = muxStateEarly_0 ? auto_in_0_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_31 = muxStateEarly_1 ? auto_in_1_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_33 = muxStateEarly_0 ? auto_in_0_a_bits_address : 32'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_34 = muxStateEarly_1 ? auto_in_1_a_bits_address : 32'h0; // @[Mux.scala 27:73]
+ wire [1:0] _T_36 = muxStateEarly_0 ? in_0_a_bits_source : 2'h0; // @[Mux.scala 27:73]
+ wire [1:0] in_1_a_bits_source = {{1'd0}, auto_in_1_a_bits_source}; // @[Xbar.scala 231:18 237:29]
+ wire [1:0] _T_37 = muxStateEarly_1 ? in_1_a_bits_source : 2'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_39 = muxStateEarly_0 ? auto_in_0_a_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_40 = muxStateEarly_1 ? auto_in_1_a_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_42 = muxStateEarly_0 ? auto_in_0_a_bits_param : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_43 = muxStateEarly_1 ? auto_in_1_a_bits_param : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_45 = muxStateEarly_0 ? auto_in_0_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_46 = muxStateEarly_1 ? auto_in_1_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ TLMonitor monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ TLMonitor_1 monitor_1 ( // @[Nodes.scala 24:25]
+ .clock(monitor_1_clock),
+ .reset(monitor_1_reset),
+ .io_in_a_ready(monitor_1_io_in_a_ready),
+ .io_in_a_valid(monitor_1_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_1_io_in_d_ready),
+ .io_in_d_valid(monitor_1_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_1_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_1_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_1_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_1_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_1_io_in_d_bits_corrupt)
+ );
+ assign auto_in_1_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign auto_in_1_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
+ assign auto_in_1_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_source = auto_out_d_bits_source[0]; // @[Xbar.scala 228:69]
+ assign auto_in_1_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign auto_in_1_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign auto_in_0_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
+ assign auto_in_0_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign auto_in_0_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = idle ? _T_10 : _out_0_a_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ assign auto_out_a_bits_opcode = _T_45 | _T_46; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_param = _T_42 | _T_43; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_size = _T_39 | _T_40; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_source = _T_36 | _T_37; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_address = _T_33 | _T_34; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_mask = _T_30 | _T_31; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_data = _T_27 | _T_28; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_corrupt = muxStateEarly_0 & auto_in_0_a_bits_corrupt | muxStateEarly_1 &
+ auto_in_1_a_bits_corrupt; // @[Mux.scala 27:73]
+ assign auto_out_d_ready = requestDOI_0_0 & auto_in_0_d_ready | requestDOI_0_1 & auto_in_1_d_ready; // @[Mux.scala 27:73]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign monitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_clock = clock;
+ assign monitor_1_reset = reset;
+ assign monitor_1_io_in_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign monitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_opcode = auto_in_1_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_param = auto_in_1_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_size = auto_in_1_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_source = auto_in_1_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_mask = auto_in_1_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_ready = auto_in_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
+ assign monitor_1_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_source = auto_out_d_bits_source[0]; // @[Xbar.scala 228:69]
+ assign monitor_1_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign monitor_1_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 9'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ beatsLeft <= initBeats;
+ end else begin
+ beatsLeft <= _beatsLeft_T_4;
+ end
+ if (reset) begin // @[Arbiter.scala 23:23]
+ readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
+ end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
+ readys_mask <= _readys_mask_T_3; // @[Arbiter.scala 28:12]
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_0 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_0 <= earlyWinner_0;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~earlyWinner_0 | ~earlyWinner_1) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 105:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
+ ); // @[Arbiter.scala 105:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(auto_in_0_a_valid | auto_in_1_a_valid) | _prefixOR_T) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~(auto_in_0_a_valid | auto_in_1_a_valid) | _prefixOR_T)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_11 | _T_10) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(_T_11 | _T_10)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ beatsLeft = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ readys_mask = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ state_0 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ state_1 = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_2(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_17 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_20 = _T_17 & _source_ok_T; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_26 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_28 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_29 = {1'b0,$signed(_T_28)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_31 = $signed(_T_29) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_32 = $signed(_T_31) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_33 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_36 = $signed(_T_34) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_38 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_39 = {1'b0,$signed(_T_38)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_41 = $signed(_T_39) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_42 = $signed(_T_41) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_43 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_44 = {1'b0,$signed(_T_43)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_46 = $signed(_T_44) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_47 = $signed(_T_46) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_48 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_51 = $signed(_T_49) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_52 = $signed(_T_51) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_53 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_54 = {1'b0,$signed(_T_53)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_56 = $signed(_T_54) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_57 = $signed(_T_56) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_58 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_59 = {1'b0,$signed(_T_58)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_61 = $signed(_T_59) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_62 = $signed(_T_61) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_63 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_66 = $signed(_T_64) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_67 = $signed(_T_66) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_68 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_71 = $signed(_T_69) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_72 = $signed(_T_71) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_73 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_76 = $signed(_T_74) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_77 = $signed(_T_76) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_78 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_79 = {1'b0,$signed(_T_78)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_81 = $signed(_T_79) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_82 = $signed(_T_81) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_191 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_195 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_196 = _T_195 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_200 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_204 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_384 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_397 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_416 = _T_17 & _T_32; // @[Parameters.scala 670:56]
+ wire _T_418 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_485 = _T_27 | _T_37 | _T_42 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_77 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_486 = _T_418 & _T_485; // @[Parameters.scala 670:56]
+ wire _T_488 = _T_416 | _T_486; // @[Parameters.scala 672:30]
+ wire _T_498 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_502 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_510 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_577 = _T_27 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_578 = _T_418 & _T_577; // @[Parameters.scala 670:56]
+ wire _T_599 = _T_416 | _T_578; // @[Parameters.scala 672:30]
+ wire _T_601 = _T_20 & _T_599; // @[Monitor.scala 115:71]
+ wire _T_619 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_724 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_725 = io_in_a_bits_mask & _T_724; // @[Monitor.scala 127:31]
+ wire _T_726 = _T_725 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_730 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_738 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_793 = _T_27 | _T_32 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_794 = _T_738 & _T_793; // @[Parameters.scala 670:56]
+ wire _T_816 = _T_20 & _T_794; // @[Monitor.scala 131:74]
+ wire _T_826 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_834 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_930 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_938 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1024 = _T_20 & _T_416; // @[Monitor.scala 147:68]
+ wire _T_1034 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1046 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _T_1050 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1054 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1058 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1062 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1066 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1070 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1081 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1085 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1098 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1118 = _T_1066 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1127 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1144 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1162 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1192 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1193 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1197 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1201 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1205 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1209 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1216 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1217 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1221 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1225 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1233 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1237 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_72 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_74 = {{8'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_74 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1243 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1246 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [2:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [19:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire _T_1250 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1254 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1256 = ~_T_1050; // @[Monitor.scala 671:74]
+ wire _T_1257 = io_in_d_valid & d_first_1 & ~_T_1050; // @[Monitor.scala 671:71]
+ wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1050 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_sizes_clr_T_5 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_1256 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1256 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1256 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire same_cycle_resp = _T_1243 & _source_ok_T; // @[Monitor.scala 681:88]
+ wire _T_1269 = inflight | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1274 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1275 = io_in_d_bits_opcode == _GEN_32 | _T_1274; // @[Monitor.scala 685:77]
+ wire _T_1279 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1286 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1287 = io_in_d_bits_opcode == _GEN_48 | _T_1286; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_77 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1291 = _GEN_77 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1301 = _T_1254 & a_first_1 & io_in_a_valid & _source_ok_T & _T_1256; // @[Monitor.scala 694:116]
+ wire _T_1303 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set_wo_ready = _GEN_15[0];
+ wire d_clr_wo_ready = _GEN_21[0];
+ wire _T_1310 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [7:0] a_sizes_set = _GEN_20[7:0];
+ wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [7:0] d_sizes_clr = _GEN_24[7:0];
+ wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1319 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _GEN_80 = {{8'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_80 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1345 = io_in_d_valid & d_first_2 & _T_1050; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1050 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1363 = _GEN_77 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
+ wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_384 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_384) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_20 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_20) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_488 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_488) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_726 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_726) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_826 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_826) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_930 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_930) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1024 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1024) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1034 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1034) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1046 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1046) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1066 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1066) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1193 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1193) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1197 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1201 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1201) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1205 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1205) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1209 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1209) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1217 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1217) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1221 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1221) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1225 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1225) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1233 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1237 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1237) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1246 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1246 & ~reset & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1269 & (_T_1257 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_2 & ~_T_1269) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1257 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & same_cycle_resp & _T_2 & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1279 & (_T_1257 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & same_cycle_resp & _T_2 & ~_T_1279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1287 & (_T_1257 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~same_cycle_resp & _T_2 & ~_T_1287) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1291 & (_T_1257 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~same_cycle_resp & _T_2 & ~_T_1291) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1303 & (_T_1301 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1301 & _T_2 & ~_T_1303) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1310 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1310) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1319 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1319) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1363 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1363) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ sink = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ denied = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_13[3:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_sizes = _RAND_14[7:0];
+ _RAND_15 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_15[8:0];
+ _RAND_16 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ watchdog = _RAND_17[31:0];
+ _RAND_18 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_18[7:0];
+ _RAND_19 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_19[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_3(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_1 = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
+ wire source_ok = io_in_a_bits_source | _source_ok_T_1; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_24 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_26 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_31 = _T_26 & source_ok; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_37 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_38 = $signed(_T_37) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_39 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_40 = {1'b0,$signed(_T_39)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_42 = $signed(_T_40) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_43 = $signed(_T_42) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_44 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_45 = {1'b0,$signed(_T_44)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_47 = $signed(_T_45) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_48 = $signed(_T_47) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_49 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_50 = {1'b0,$signed(_T_49)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_52 = $signed(_T_50) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_53 = $signed(_T_52) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_54 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_55 = {1'b0,$signed(_T_54)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_57 = $signed(_T_55) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_58 = $signed(_T_57) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_59 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_60 = {1'b0,$signed(_T_59)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_62 = $signed(_T_60) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_63 = $signed(_T_62) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_64 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_67 = $signed(_T_65) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_68 = $signed(_T_67) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_69 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_72 = $signed(_T_70) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_73 = $signed(_T_72) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_74 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_75 = {1'b0,$signed(_T_74)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_77 = $signed(_T_75) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_78 = $signed(_T_77) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_79 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_80 = {1'b0,$signed(_T_79)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_82 = $signed(_T_80) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_83 = $signed(_T_82) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_84 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_85 = {1'b0,$signed(_T_84)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_87 = $signed(_T_85) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_88 = $signed(_T_87) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_89 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_90 = {1'b0,$signed(_T_89)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_92 = $signed(_T_90) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_93 = $signed(_T_92) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_202 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_206 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_207 = _T_206 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_211 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_215 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_397 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_410 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_431 = _T_26 & _T_43; // @[Parameters.scala 670:56]
+ wire _T_433 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_500 = _T_38 | _T_48 | _T_53 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_88 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_501 = _T_433 & _T_500; // @[Parameters.scala 670:56]
+ wire _T_503 = _T_431 | _T_501; // @[Parameters.scala 672:30]
+ wire _T_513 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_517 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_525 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_594 = _T_38 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_595 = _T_433 & _T_594; // @[Parameters.scala 670:56]
+ wire _T_616 = _T_431 | _T_595; // @[Parameters.scala 672:30]
+ wire _T_618 = _T_31 & _T_616; // @[Monitor.scala 115:71]
+ wire _T_636 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_743 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_744 = io_in_a_bits_mask & _T_743; // @[Monitor.scala 127:31]
+ wire _T_745 = _T_744 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_749 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_759 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_814 = _T_38 | _T_43 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_815 = _T_759 & _T_814; // @[Parameters.scala 670:56]
+ wire _T_837 = _T_31 & _T_815; // @[Monitor.scala 131:74]
+ wire _T_847 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_855 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_953 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_961 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1049 = _T_31 & _T_431; // @[Monitor.scala 147:68]
+ wire _T_1059 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1071 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_3 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
+ wire source_ok_1 = io_in_d_bits_source | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire _T_1075 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1079 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1083 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1087 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1091 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1095 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1106 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1110 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1123 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1143 = _T_1091 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1152 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1169 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1187 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1217 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1218 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1222 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1226 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1230 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1234 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1241 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1242 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1246 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1250 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1254 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1258 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1262 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [1:0] inflight; // @[Monitor.scala 611:27]
+ reg [7:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [15:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [2:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{8'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [3:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1268 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1271 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [2:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [19:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [1:0] _T_1273 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_1275 = ~_T_1273[0]; // @[Monitor.scala 658:17]
+ wire [1:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1279 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1281 = ~_T_1075; // @[Monitor.scala 671:74]
+ wire _T_1282 = io_in_d_valid & d_first_1 & ~_T_1075; // @[Monitor.scala 671:71]
+ wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_1075 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _GEN_3 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [30:0] _GEN_4 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [30:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [1:0] d_clr = _d_first_T & d_first_1 & _T_1281 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1281 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1281 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1268 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [1:0] _T_1292 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_1294 = _T_1292[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1299 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1300 = io_in_d_bits_opcode == _GEN_32 | _T_1299; // @[Monitor.scala 685:77]
+ wire _T_1304 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1311 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1312 = io_in_d_bits_opcode == _GEN_48 | _T_1311; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_78 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1316 = _GEN_78 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1326 = _T_1279 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1281; // @[Monitor.scala 694:116]
+ wire _T_1328 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire _T_1335 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [7:0] a_opcodes_set = _GEN_19[7:0];
+ wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [7:0] d_opcodes_clr = _GEN_23[7:0];
+ wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [15:0] a_sizes_set = _GEN_20[15:0];
+ wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [15:0] d_sizes_clr = _GEN_24[15:0];
+ wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1344 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [1:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [15:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1370 = io_in_d_valid & d_first_2 & _T_1075; // @[Monitor.scala 779:71]
+ wire [1:0] d_clr_1 = _d_first_T & d_first_2 & _T_1075 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 783:90 784:21]
+ wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1075 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire [1:0] _T_1378 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1388 = _GEN_78 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [1:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [15:0] d_sizes_clr_1 = _GEN_69[15:0];
+ wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [15:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1413 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 2'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 8'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 16'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 2'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 16'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_202 & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_T_202) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_207 & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_T_207) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_211 & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_T_211) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_202 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_202) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_207 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_207) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_211 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_211) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_31 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_31) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_211 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_211) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_745 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_745) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_837 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_837) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_847 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_847) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_837 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_837) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_953 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_953) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1049 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_1049) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1059 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_1059) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_211 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_211) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1071 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1071) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1091 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1091) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1106 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1106) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1110 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1110) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1106 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1106) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1110 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1110) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1218 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1222 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1222) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1226 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1226) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1230 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1230) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1234 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1234) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1242 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1246 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1246) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1254 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1254) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1258 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1258) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1262 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1262) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1271 & ~reset & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1294 & (_T_1282 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & _T_2 & ~_T_1294) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1300 & (_T_1282 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & same_cycle_resp & _T_2 & ~_T_1300) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1304 & (_T_1282 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & same_cycle_resp & _T_2 & ~_T_1304) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1312 & (_T_1282 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & ~same_cycle_resp & _T_2 & ~_T_1312) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1316 & (_T_1282 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & ~same_cycle_resp & _T_2 & ~_T_1316) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1328 & (_T_1326 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1326 & _T_2 & ~_T_1328) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1335 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1335) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1344 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1344) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1378[0] & (_T_1370 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1370 & _T_2 & ~_T_1378[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1388 & (_T_1370 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1370 & _T_2 & ~_T_1388) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1413 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:96)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[1:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[7:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[15:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[1:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[15:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFIFOFixer(
+ input clock,
+ input reset,
+ output auto_in_1_a_ready,
+ input auto_in_1_a_valid,
+ input [2:0] auto_in_1_a_bits_opcode,
+ input [2:0] auto_in_1_a_bits_param,
+ input [3:0] auto_in_1_a_bits_size,
+ input auto_in_1_a_bits_source,
+ input [31:0] auto_in_1_a_bits_address,
+ input [7:0] auto_in_1_a_bits_mask,
+ input [63:0] auto_in_1_a_bits_data,
+ input auto_in_1_a_bits_corrupt,
+ input auto_in_1_d_ready,
+ output auto_in_1_d_valid,
+ output [2:0] auto_in_1_d_bits_opcode,
+ output [1:0] auto_in_1_d_bits_param,
+ output [3:0] auto_in_1_d_bits_size,
+ output auto_in_1_d_bits_source,
+ output auto_in_1_d_bits_sink,
+ output auto_in_1_d_bits_denied,
+ output [63:0] auto_in_1_d_bits_data,
+ output auto_in_1_d_bits_corrupt,
+ output auto_in_0_a_ready,
+ input auto_in_0_a_valid,
+ input [2:0] auto_in_0_a_bits_opcode,
+ input [2:0] auto_in_0_a_bits_param,
+ input [3:0] auto_in_0_a_bits_size,
+ input auto_in_0_a_bits_source,
+ input [31:0] auto_in_0_a_bits_address,
+ input [7:0] auto_in_0_a_bits_mask,
+ input [63:0] auto_in_0_a_bits_data,
+ input auto_in_0_a_bits_corrupt,
+ input auto_in_0_d_ready,
+ output auto_in_0_d_valid,
+ output [2:0] auto_in_0_d_bits_opcode,
+ output [1:0] auto_in_0_d_bits_param,
+ output [3:0] auto_in_0_d_bits_size,
+ output auto_in_0_d_bits_sink,
+ output auto_in_0_d_bits_denied,
+ output [63:0] auto_in_0_d_bits_data,
+ output auto_in_0_d_bits_corrupt,
+ input auto_out_1_a_ready,
+ output auto_out_1_a_valid,
+ output [2:0] auto_out_1_a_bits_opcode,
+ output [2:0] auto_out_1_a_bits_param,
+ output [3:0] auto_out_1_a_bits_size,
+ output auto_out_1_a_bits_source,
+ output [31:0] auto_out_1_a_bits_address,
+ output [7:0] auto_out_1_a_bits_mask,
+ output [63:0] auto_out_1_a_bits_data,
+ output auto_out_1_a_bits_corrupt,
+ output auto_out_1_d_ready,
+ input auto_out_1_d_valid,
+ input [2:0] auto_out_1_d_bits_opcode,
+ input [1:0] auto_out_1_d_bits_param,
+ input [3:0] auto_out_1_d_bits_size,
+ input auto_out_1_d_bits_source,
+ input auto_out_1_d_bits_sink,
+ input auto_out_1_d_bits_denied,
+ input [63:0] auto_out_1_d_bits_data,
+ input auto_out_1_d_bits_corrupt,
+ input auto_out_0_a_ready,
+ output auto_out_0_a_valid,
+ output [2:0] auto_out_0_a_bits_opcode,
+ output [2:0] auto_out_0_a_bits_param,
+ output [3:0] auto_out_0_a_bits_size,
+ output auto_out_0_a_bits_source,
+ output [31:0] auto_out_0_a_bits_address,
+ output [7:0] auto_out_0_a_bits_mask,
+ output [63:0] auto_out_0_a_bits_data,
+ output auto_out_0_a_bits_corrupt,
+ output auto_out_0_d_ready,
+ input auto_out_0_d_valid,
+ input [2:0] auto_out_0_d_bits_opcode,
+ input [1:0] auto_out_0_d_bits_param,
+ input [3:0] auto_out_0_d_bits_size,
+ input auto_out_0_d_bits_sink,
+ input auto_out_0_d_bits_denied,
+ input [63:0] auto_out_0_d_bits_data,
+ input auto_out_0_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_clock; // @[Nodes.scala 24:25]
+ wire monitor_1_reset; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ TLMonitor_2 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ TLMonitor_3 monitor_1 ( // @[Nodes.scala 24:25]
+ .clock(monitor_1_clock),
+ .reset(monitor_1_reset),
+ .io_in_a_ready(monitor_1_io_in_a_ready),
+ .io_in_a_valid(monitor_1_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_1_io_in_d_ready),
+ .io_in_d_valid(monitor_1_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_1_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_1_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_1_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_1_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_1_io_in_d_bits_corrupt)
+ );
+ assign auto_in_1_a_ready = auto_out_1_a_ready; // @[FIFOFixer.scala 88:33]
+ assign auto_in_1_d_valid = auto_out_1_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_opcode = auto_out_1_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_param = auto_out_1_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_size = auto_out_1_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_source = auto_out_1_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_sink = auto_out_1_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_denied = auto_out_1_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_data = auto_out_1_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_a_ready = auto_out_0_a_ready; // @[FIFOFixer.scala 88:33]
+ assign auto_in_0_d_valid = auto_out_0_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_opcode = auto_out_0_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_param = auto_out_0_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_size = auto_out_0_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_sink = auto_out_0_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_denied = auto_out_0_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_data = auto_out_0_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_1_a_valid = auto_in_1_a_valid; // @[FIFOFixer.scala 87:33]
+ assign auto_out_1_a_bits_opcode = auto_in_1_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_param = auto_in_1_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_size = auto_in_1_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_source = auto_in_1_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_mask = auto_in_1_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_data = auto_in_1_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_d_ready = auto_in_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_valid = auto_in_0_a_valid; // @[FIFOFixer.scala 87:33]
+ assign auto_out_0_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_data = auto_in_0_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_d_ready = auto_in_0_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_out_0_a_ready; // @[FIFOFixer.scala 88:33]
+ assign monitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_0_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_opcode = auto_out_0_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_param = auto_out_0_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_0_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_sink = auto_out_0_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_denied = auto_out_0_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_clock = clock;
+ assign monitor_1_reset = reset;
+ assign monitor_1_io_in_a_ready = auto_out_1_a_ready; // @[FIFOFixer.scala 88:33]
+ assign monitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_opcode = auto_in_1_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_param = auto_in_1_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_size = auto_in_1_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_source = auto_in_1_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_mask = auto_in_1_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_ready = auto_in_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_valid = auto_out_1_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_opcode = auto_out_1_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_param = auto_out_1_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_size = auto_out_1_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_source = auto_out_1_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_sink = auto_out_1_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_denied = auto_out_1_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLWidthWidget(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input [1:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output [1:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [1:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input [1:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLInterconnectCoupler(
+ output auto_widget_in_a_ready,
+ input auto_widget_in_a_valid,
+ input [2:0] auto_widget_in_a_bits_opcode,
+ input [2:0] auto_widget_in_a_bits_param,
+ input [3:0] auto_widget_in_a_bits_size,
+ input [1:0] auto_widget_in_a_bits_source,
+ input [31:0] auto_widget_in_a_bits_address,
+ input [7:0] auto_widget_in_a_bits_mask,
+ input [63:0] auto_widget_in_a_bits_data,
+ input auto_widget_in_a_bits_corrupt,
+ input auto_widget_in_d_ready,
+ output auto_widget_in_d_valid,
+ output [2:0] auto_widget_in_d_bits_opcode,
+ output [1:0] auto_widget_in_d_bits_param,
+ output [3:0] auto_widget_in_d_bits_size,
+ output [1:0] auto_widget_in_d_bits_source,
+ output auto_widget_in_d_bits_sink,
+ output auto_widget_in_d_bits_denied,
+ output [63:0] auto_widget_in_d_bits_data,
+ output auto_widget_in_d_bits_corrupt,
+ input auto_bus_xing_out_a_ready,
+ output auto_bus_xing_out_a_valid,
+ output [2:0] auto_bus_xing_out_a_bits_opcode,
+ output [2:0] auto_bus_xing_out_a_bits_param,
+ output [3:0] auto_bus_xing_out_a_bits_size,
+ output [1:0] auto_bus_xing_out_a_bits_source,
+ output [31:0] auto_bus_xing_out_a_bits_address,
+ output [7:0] auto_bus_xing_out_a_bits_mask,
+ output [63:0] auto_bus_xing_out_a_bits_data,
+ output auto_bus_xing_out_a_bits_corrupt,
+ output auto_bus_xing_out_d_ready,
+ input auto_bus_xing_out_d_valid,
+ input [2:0] auto_bus_xing_out_d_bits_opcode,
+ input [1:0] auto_bus_xing_out_d_bits_param,
+ input [3:0] auto_bus_xing_out_d_bits_size,
+ input [1:0] auto_bus_xing_out_d_bits_source,
+ input auto_bus_xing_out_d_bits_sink,
+ input auto_bus_xing_out_d_bits_denied,
+ input [63:0] auto_bus_xing_out_d_bits_data,
+ input auto_bus_xing_out_d_bits_corrupt
+);
+ wire widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ TLWidthWidget widget ( // @[WidthWidget.scala 219:28]
+ .auto_in_a_ready(widget_auto_in_a_ready),
+ .auto_in_a_valid(widget_auto_in_a_valid),
+ .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(widget_auto_in_a_bits_param),
+ .auto_in_a_bits_size(widget_auto_in_a_bits_size),
+ .auto_in_a_bits_source(widget_auto_in_a_bits_source),
+ .auto_in_a_bits_address(widget_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(widget_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(widget_auto_in_d_ready),
+ .auto_in_d_valid(widget_auto_in_d_valid),
+ .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(widget_auto_in_d_bits_param),
+ .auto_in_d_bits_size(widget_auto_in_d_bits_size),
+ .auto_in_d_bits_source(widget_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(widget_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(widget_auto_out_a_ready),
+ .auto_out_a_valid(widget_auto_out_a_valid),
+ .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(widget_auto_out_a_bits_param),
+ .auto_out_a_bits_size(widget_auto_out_a_bits_size),
+ .auto_out_a_bits_source(widget_auto_out_a_bits_source),
+ .auto_out_a_bits_address(widget_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(widget_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(widget_auto_out_d_ready),
+ .auto_out_d_valid(widget_auto_out_d_valid),
+ .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(widget_auto_out_d_bits_param),
+ .auto_out_d_bits_size(widget_auto_out_d_bits_size),
+ .auto_out_d_bits_source(widget_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(widget_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
+ );
+ assign auto_widget_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign auto_bus_xing_out_a_valid = widget_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_d_ready = widget_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign widget_auto_in_a_valid = auto_widget_in_a_valid; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_opcode = auto_widget_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_param = auto_widget_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_size = auto_widget_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_source = auto_widget_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_address = auto_widget_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_mask = auto_widget_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_data = auto_widget_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_corrupt = auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_d_ready = auto_widget_in_d_ready; // @[LazyModule.scala 309:16]
+ assign widget_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLWidthWidget_1(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLInterconnectCoupler_1(
+ input auto_widget_out_a_ready,
+ output auto_widget_out_a_valid,
+ output [2:0] auto_widget_out_a_bits_opcode,
+ output [2:0] auto_widget_out_a_bits_param,
+ output [3:0] auto_widget_out_a_bits_size,
+ output auto_widget_out_a_bits_source,
+ output [31:0] auto_widget_out_a_bits_address,
+ output [7:0] auto_widget_out_a_bits_mask,
+ output [63:0] auto_widget_out_a_bits_data,
+ output auto_widget_out_a_bits_corrupt,
+ output auto_widget_out_d_ready,
+ input auto_widget_out_d_valid,
+ input [2:0] auto_widget_out_d_bits_opcode,
+ input [1:0] auto_widget_out_d_bits_param,
+ input [3:0] auto_widget_out_d_bits_size,
+ input auto_widget_out_d_bits_sink,
+ input auto_widget_out_d_bits_denied,
+ input [63:0] auto_widget_out_d_bits_data,
+ input auto_widget_out_d_bits_corrupt,
+ output auto_bus_xing_in_a_ready,
+ input auto_bus_xing_in_a_valid,
+ input [2:0] auto_bus_xing_in_a_bits_opcode,
+ input [2:0] auto_bus_xing_in_a_bits_param,
+ input [3:0] auto_bus_xing_in_a_bits_size,
+ input auto_bus_xing_in_a_bits_source,
+ input [31:0] auto_bus_xing_in_a_bits_address,
+ input [7:0] auto_bus_xing_in_a_bits_mask,
+ input [63:0] auto_bus_xing_in_a_bits_data,
+ input auto_bus_xing_in_a_bits_corrupt,
+ input auto_bus_xing_in_d_ready,
+ output auto_bus_xing_in_d_valid,
+ output [2:0] auto_bus_xing_in_d_bits_opcode,
+ output [1:0] auto_bus_xing_in_d_bits_param,
+ output [3:0] auto_bus_xing_in_d_bits_size,
+ output auto_bus_xing_in_d_bits_sink,
+ output auto_bus_xing_in_d_bits_denied,
+ output [63:0] auto_bus_xing_in_d_bits_data,
+ output auto_bus_xing_in_d_bits_corrupt
+);
+ wire widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ TLWidthWidget_1 widget ( // @[WidthWidget.scala 219:28]
+ .auto_in_a_ready(widget_auto_in_a_ready),
+ .auto_in_a_valid(widget_auto_in_a_valid),
+ .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(widget_auto_in_a_bits_param),
+ .auto_in_a_bits_size(widget_auto_in_a_bits_size),
+ .auto_in_a_bits_source(widget_auto_in_a_bits_source),
+ .auto_in_a_bits_address(widget_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(widget_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(widget_auto_in_d_ready),
+ .auto_in_d_valid(widget_auto_in_d_valid),
+ .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(widget_auto_in_d_bits_param),
+ .auto_in_d_bits_size(widget_auto_in_d_bits_size),
+ .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(widget_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(widget_auto_out_a_ready),
+ .auto_out_a_valid(widget_auto_out_a_valid),
+ .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(widget_auto_out_a_bits_param),
+ .auto_out_a_bits_size(widget_auto_out_a_bits_size),
+ .auto_out_a_bits_source(widget_auto_out_a_bits_source),
+ .auto_out_a_bits_address(widget_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(widget_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(widget_auto_out_d_ready),
+ .auto_out_d_valid(widget_auto_out_d_valid),
+ .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(widget_auto_out_d_bits_param),
+ .auto_out_d_bits_size(widget_auto_out_d_bits_size),
+ .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(widget_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
+ );
+ assign auto_widget_out_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_widget_out_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_bus_xing_in_a_ready = widget_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_valid = widget_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_param = widget_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_size = widget_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_data = widget_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign widget_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_out_a_ready = auto_widget_out_a_ready; // @[LazyModule.scala 311:12]
+ assign widget_auto_out_d_valid = auto_widget_out_d_valid; // @[LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_opcode = auto_widget_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_param = auto_widget_out_d_bits_param; // @[LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_size = auto_widget_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_sink = auto_widget_out_d_bits_sink; // @[LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_denied = auto_widget_out_d_bits_denied; // @[LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_data = auto_widget_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_corrupt = auto_widget_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
+endmodule
+module TLInterconnectCoupler_2(
+ output auto_tl_master_clock_xing_in_a_ready,
+ input auto_tl_master_clock_xing_in_a_valid,
+ input [2:0] auto_tl_master_clock_xing_in_a_bits_opcode,
+ input [2:0] auto_tl_master_clock_xing_in_a_bits_param,
+ input [3:0] auto_tl_master_clock_xing_in_a_bits_size,
+ input auto_tl_master_clock_xing_in_a_bits_source,
+ input [31:0] auto_tl_master_clock_xing_in_a_bits_address,
+ input [7:0] auto_tl_master_clock_xing_in_a_bits_mask,
+ input [63:0] auto_tl_master_clock_xing_in_a_bits_data,
+ input auto_tl_master_clock_xing_in_a_bits_corrupt,
+ input auto_tl_master_clock_xing_in_d_ready,
+ output auto_tl_master_clock_xing_in_d_valid,
+ output [2:0] auto_tl_master_clock_xing_in_d_bits_opcode,
+ output [1:0] auto_tl_master_clock_xing_in_d_bits_param,
+ output [3:0] auto_tl_master_clock_xing_in_d_bits_size,
+ output auto_tl_master_clock_xing_in_d_bits_source,
+ output auto_tl_master_clock_xing_in_d_bits_sink,
+ output auto_tl_master_clock_xing_in_d_bits_denied,
+ output [63:0] auto_tl_master_clock_xing_in_d_bits_data,
+ output auto_tl_master_clock_xing_in_d_bits_corrupt,
+ input auto_tl_out_a_ready,
+ output auto_tl_out_a_valid,
+ output [2:0] auto_tl_out_a_bits_opcode,
+ output [2:0] auto_tl_out_a_bits_param,
+ output [3:0] auto_tl_out_a_bits_size,
+ output auto_tl_out_a_bits_source,
+ output [31:0] auto_tl_out_a_bits_address,
+ output [7:0] auto_tl_out_a_bits_mask,
+ output [63:0] auto_tl_out_a_bits_data,
+ output auto_tl_out_a_bits_corrupt,
+ output auto_tl_out_d_ready,
+ input auto_tl_out_d_valid,
+ input [2:0] auto_tl_out_d_bits_opcode,
+ input [1:0] auto_tl_out_d_bits_param,
+ input [3:0] auto_tl_out_d_bits_size,
+ input auto_tl_out_d_bits_source,
+ input auto_tl_out_d_bits_sink,
+ input auto_tl_out_d_bits_denied,
+ input [63:0] auto_tl_out_d_bits_data,
+ input auto_tl_out_d_bits_corrupt
+);
+ assign auto_tl_master_clock_xing_in_a_ready = auto_tl_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_valid = auto_tl_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_bits_opcode = auto_tl_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_bits_param = auto_tl_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_bits_size = auto_tl_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_bits_source = auto_tl_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_bits_sink = auto_tl_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_bits_denied = auto_tl_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_bits_data = auto_tl_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_master_clock_xing_in_d_bits_corrupt = auto_tl_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_out_a_valid = auto_tl_master_clock_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_opcode = auto_tl_master_clock_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_param = auto_tl_master_clock_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_size = auto_tl_master_clock_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_source = auto_tl_master_clock_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_address = auto_tl_master_clock_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_mask = auto_tl_master_clock_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_data = auto_tl_master_clock_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_corrupt = auto_tl_master_clock_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_d_ready = auto_tl_master_clock_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module SystemBus(
+ output auto_coupler_from_tile_tl_master_clock_xing_in_a_ready,
+ input auto_coupler_from_tile_tl_master_clock_xing_in_a_valid,
+ input [2:0] auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode,
+ input [2:0] auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param,
+ input [3:0] auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size,
+ input auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source,
+ input [31:0] auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address,
+ input [7:0] auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask,
+ input [63:0] auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data,
+ input auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt,
+ input auto_coupler_from_tile_tl_master_clock_xing_in_d_ready,
+ output auto_coupler_from_tile_tl_master_clock_xing_in_d_valid,
+ output [2:0] auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode,
+ output [1:0] auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param,
+ output [3:0] auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size,
+ output auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source,
+ output auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink,
+ output auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied,
+ output [63:0] auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data,
+ output auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt,
+ output auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready,
+ input auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_valid,
+ input [2:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_opcode,
+ input [2:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_param,
+ input [3:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_size,
+ input auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_source,
+ input [31:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_address,
+ input [7:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_mask,
+ input [63:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_data,
+ input auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_corrupt,
+ input auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_ready,
+ output auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid,
+ output [2:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode,
+ output [1:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param,
+ output [3:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size,
+ output auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink,
+ output auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied,
+ output [63:0] auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data,
+ output auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt,
+ input auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready,
+ output auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid,
+ output [2:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param,
+ output [3:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size,
+ output [1:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source,
+ output [31:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address,
+ output [7:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data,
+ output auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt,
+ output auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready,
+ input auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid,
+ input [2:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param,
+ input [3:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size,
+ input [1:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source,
+ input auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink,
+ input auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied,
+ input [63:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data,
+ input auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt,
+ output auto_fixedClockNode_out_1_clock,
+ output auto_fixedClockNode_out_1_reset,
+ input auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock,
+ input auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset
+);
+ wire subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_clock; // @[BusWrapper.scala 40:48]
+ wire subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_reset; // @[BusWrapper.scala 40:48]
+ wire subsystem_sbus_clock_groups_auto_out_member_subsystem_sbus_0_clock; // @[BusWrapper.scala 40:48]
+ wire subsystem_sbus_clock_groups_auto_out_member_subsystem_sbus_0_reset; // @[BusWrapper.scala 40:48]
+ wire clockGroup_auto_in_member_subsystem_sbus_0_clock; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_in_member_subsystem_sbus_0_reset; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
+ wire fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_2_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_2_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_0_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_0_reset; // @[ClockGroup.scala 106:107]
+ wire system_bus_xbar_clock; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_reset; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_a_ready; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_a_valid; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_in_1_a_bits_opcode; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_in_1_a_bits_param; // @[SystemBus.scala 40:43]
+ wire [3:0] system_bus_xbar_auto_in_1_a_bits_size; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_a_bits_source; // @[SystemBus.scala 40:43]
+ wire [31:0] system_bus_xbar_auto_in_1_a_bits_address; // @[SystemBus.scala 40:43]
+ wire [7:0] system_bus_xbar_auto_in_1_a_bits_mask; // @[SystemBus.scala 40:43]
+ wire [63:0] system_bus_xbar_auto_in_1_a_bits_data; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_a_bits_corrupt; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_d_ready; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_d_valid; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_in_1_d_bits_opcode; // @[SystemBus.scala 40:43]
+ wire [1:0] system_bus_xbar_auto_in_1_d_bits_param; // @[SystemBus.scala 40:43]
+ wire [3:0] system_bus_xbar_auto_in_1_d_bits_size; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_d_bits_source; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_d_bits_sink; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_d_bits_denied; // @[SystemBus.scala 40:43]
+ wire [63:0] system_bus_xbar_auto_in_1_d_bits_data; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_1_d_bits_corrupt; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_a_ready; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_a_valid; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_in_0_a_bits_opcode; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_in_0_a_bits_param; // @[SystemBus.scala 40:43]
+ wire [3:0] system_bus_xbar_auto_in_0_a_bits_size; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_a_bits_source; // @[SystemBus.scala 40:43]
+ wire [31:0] system_bus_xbar_auto_in_0_a_bits_address; // @[SystemBus.scala 40:43]
+ wire [7:0] system_bus_xbar_auto_in_0_a_bits_mask; // @[SystemBus.scala 40:43]
+ wire [63:0] system_bus_xbar_auto_in_0_a_bits_data; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_a_bits_corrupt; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_d_ready; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_d_valid; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_in_0_d_bits_opcode; // @[SystemBus.scala 40:43]
+ wire [1:0] system_bus_xbar_auto_in_0_d_bits_param; // @[SystemBus.scala 40:43]
+ wire [3:0] system_bus_xbar_auto_in_0_d_bits_size; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_d_bits_sink; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_d_bits_denied; // @[SystemBus.scala 40:43]
+ wire [63:0] system_bus_xbar_auto_in_0_d_bits_data; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_in_0_d_bits_corrupt; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_out_a_ready; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_out_a_valid; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_out_a_bits_opcode; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_out_a_bits_param; // @[SystemBus.scala 40:43]
+ wire [3:0] system_bus_xbar_auto_out_a_bits_size; // @[SystemBus.scala 40:43]
+ wire [1:0] system_bus_xbar_auto_out_a_bits_source; // @[SystemBus.scala 40:43]
+ wire [31:0] system_bus_xbar_auto_out_a_bits_address; // @[SystemBus.scala 40:43]
+ wire [7:0] system_bus_xbar_auto_out_a_bits_mask; // @[SystemBus.scala 40:43]
+ wire [63:0] system_bus_xbar_auto_out_a_bits_data; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_out_a_bits_corrupt; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_out_d_ready; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_out_d_valid; // @[SystemBus.scala 40:43]
+ wire [2:0] system_bus_xbar_auto_out_d_bits_opcode; // @[SystemBus.scala 40:43]
+ wire [1:0] system_bus_xbar_auto_out_d_bits_param; // @[SystemBus.scala 40:43]
+ wire [3:0] system_bus_xbar_auto_out_d_bits_size; // @[SystemBus.scala 40:43]
+ wire [1:0] system_bus_xbar_auto_out_d_bits_source; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_out_d_bits_sink; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_out_d_bits_denied; // @[SystemBus.scala 40:43]
+ wire [63:0] system_bus_xbar_auto_out_d_bits_data; // @[SystemBus.scala 40:43]
+ wire system_bus_xbar_auto_out_d_bits_corrupt; // @[SystemBus.scala 40:43]
+ wire fixer_clock; // @[FIFOFixer.scala 144:27]
+ wire fixer_reset; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_a_ready; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_a_valid; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_in_1_a_bits_opcode; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_in_1_a_bits_param; // @[FIFOFixer.scala 144:27]
+ wire [3:0] fixer_auto_in_1_a_bits_size; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_a_bits_source; // @[FIFOFixer.scala 144:27]
+ wire [31:0] fixer_auto_in_1_a_bits_address; // @[FIFOFixer.scala 144:27]
+ wire [7:0] fixer_auto_in_1_a_bits_mask; // @[FIFOFixer.scala 144:27]
+ wire [63:0] fixer_auto_in_1_a_bits_data; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_a_bits_corrupt; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_d_ready; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_d_valid; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_in_1_d_bits_opcode; // @[FIFOFixer.scala 144:27]
+ wire [1:0] fixer_auto_in_1_d_bits_param; // @[FIFOFixer.scala 144:27]
+ wire [3:0] fixer_auto_in_1_d_bits_size; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_d_bits_source; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_d_bits_sink; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_d_bits_denied; // @[FIFOFixer.scala 144:27]
+ wire [63:0] fixer_auto_in_1_d_bits_data; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_1_d_bits_corrupt; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_a_ready; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_a_valid; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_in_0_a_bits_opcode; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_in_0_a_bits_param; // @[FIFOFixer.scala 144:27]
+ wire [3:0] fixer_auto_in_0_a_bits_size; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_a_bits_source; // @[FIFOFixer.scala 144:27]
+ wire [31:0] fixer_auto_in_0_a_bits_address; // @[FIFOFixer.scala 144:27]
+ wire [7:0] fixer_auto_in_0_a_bits_mask; // @[FIFOFixer.scala 144:27]
+ wire [63:0] fixer_auto_in_0_a_bits_data; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_a_bits_corrupt; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_d_ready; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_d_valid; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_in_0_d_bits_opcode; // @[FIFOFixer.scala 144:27]
+ wire [1:0] fixer_auto_in_0_d_bits_param; // @[FIFOFixer.scala 144:27]
+ wire [3:0] fixer_auto_in_0_d_bits_size; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_d_bits_sink; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_d_bits_denied; // @[FIFOFixer.scala 144:27]
+ wire [63:0] fixer_auto_in_0_d_bits_data; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_in_0_d_bits_corrupt; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_a_ready; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_a_valid; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_out_1_a_bits_opcode; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_out_1_a_bits_param; // @[FIFOFixer.scala 144:27]
+ wire [3:0] fixer_auto_out_1_a_bits_size; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_a_bits_source; // @[FIFOFixer.scala 144:27]
+ wire [31:0] fixer_auto_out_1_a_bits_address; // @[FIFOFixer.scala 144:27]
+ wire [7:0] fixer_auto_out_1_a_bits_mask; // @[FIFOFixer.scala 144:27]
+ wire [63:0] fixer_auto_out_1_a_bits_data; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_a_bits_corrupt; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_d_ready; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_d_valid; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_out_1_d_bits_opcode; // @[FIFOFixer.scala 144:27]
+ wire [1:0] fixer_auto_out_1_d_bits_param; // @[FIFOFixer.scala 144:27]
+ wire [3:0] fixer_auto_out_1_d_bits_size; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_d_bits_source; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_d_bits_sink; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_d_bits_denied; // @[FIFOFixer.scala 144:27]
+ wire [63:0] fixer_auto_out_1_d_bits_data; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_1_d_bits_corrupt; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_a_ready; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_a_valid; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_out_0_a_bits_opcode; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_out_0_a_bits_param; // @[FIFOFixer.scala 144:27]
+ wire [3:0] fixer_auto_out_0_a_bits_size; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_a_bits_source; // @[FIFOFixer.scala 144:27]
+ wire [31:0] fixer_auto_out_0_a_bits_address; // @[FIFOFixer.scala 144:27]
+ wire [7:0] fixer_auto_out_0_a_bits_mask; // @[FIFOFixer.scala 144:27]
+ wire [63:0] fixer_auto_out_0_a_bits_data; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_a_bits_corrupt; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_d_ready; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_d_valid; // @[FIFOFixer.scala 144:27]
+ wire [2:0] fixer_auto_out_0_d_bits_opcode; // @[FIFOFixer.scala 144:27]
+ wire [1:0] fixer_auto_out_0_d_bits_param; // @[FIFOFixer.scala 144:27]
+ wire [3:0] fixer_auto_out_0_d_bits_size; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_d_bits_sink; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_d_bits_denied; // @[FIFOFixer.scala 144:27]
+ wire [63:0] fixer_auto_out_0_d_bits_data; // @[FIFOFixer.scala 144:27]
+ wire fixer_auto_out_0_d_bits_corrupt; // @[FIFOFixer.scala 144:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_tile_auto_tl_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_tile_auto_tl_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_tile_auto_tl_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_from_tile_auto_tl_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_from_tile_auto_tl_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_tile_auto_tl_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_tile_auto_tl_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_from_tile_auto_tl_out_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_tile_auto_tl_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_tile_auto_tl_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_tile_auto_tl_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ ClockGroupAggregator subsystem_sbus_clock_groups ( // @[BusWrapper.scala 40:48]
+ .auto_in_member_subsystem_sbus_0_clock(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_clock),
+ .auto_in_member_subsystem_sbus_0_reset(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_reset),
+ .auto_out_member_subsystem_sbus_0_clock(subsystem_sbus_clock_groups_auto_out_member_subsystem_sbus_0_clock),
+ .auto_out_member_subsystem_sbus_0_reset(subsystem_sbus_clock_groups_auto_out_member_subsystem_sbus_0_reset)
+ );
+ ClockGroup clockGroup ( // @[BusWrapper.scala 41:38]
+ .auto_in_member_subsystem_sbus_0_clock(clockGroup_auto_in_member_subsystem_sbus_0_clock),
+ .auto_in_member_subsystem_sbus_0_reset(clockGroup_auto_in_member_subsystem_sbus_0_reset),
+ .auto_out_clock(clockGroup_auto_out_clock),
+ .auto_out_reset(clockGroup_auto_out_reset)
+ );
+ FixedClockBroadcast fixedClockNode ( // @[ClockGroup.scala 106:107]
+ .auto_in_clock(fixedClockNode_auto_in_clock),
+ .auto_in_reset(fixedClockNode_auto_in_reset),
+ .auto_out_2_clock(fixedClockNode_auto_out_2_clock),
+ .auto_out_2_reset(fixedClockNode_auto_out_2_reset),
+ .auto_out_0_clock(fixedClockNode_auto_out_0_clock),
+ .auto_out_0_reset(fixedClockNode_auto_out_0_reset)
+ );
+ TLXbar system_bus_xbar ( // @[SystemBus.scala 40:43]
+ .clock(system_bus_xbar_clock),
+ .reset(system_bus_xbar_reset),
+ .auto_in_1_a_ready(system_bus_xbar_auto_in_1_a_ready),
+ .auto_in_1_a_valid(system_bus_xbar_auto_in_1_a_valid),
+ .auto_in_1_a_bits_opcode(system_bus_xbar_auto_in_1_a_bits_opcode),
+ .auto_in_1_a_bits_param(system_bus_xbar_auto_in_1_a_bits_param),
+ .auto_in_1_a_bits_size(system_bus_xbar_auto_in_1_a_bits_size),
+ .auto_in_1_a_bits_source(system_bus_xbar_auto_in_1_a_bits_source),
+ .auto_in_1_a_bits_address(system_bus_xbar_auto_in_1_a_bits_address),
+ .auto_in_1_a_bits_mask(system_bus_xbar_auto_in_1_a_bits_mask),
+ .auto_in_1_a_bits_data(system_bus_xbar_auto_in_1_a_bits_data),
+ .auto_in_1_a_bits_corrupt(system_bus_xbar_auto_in_1_a_bits_corrupt),
+ .auto_in_1_d_ready(system_bus_xbar_auto_in_1_d_ready),
+ .auto_in_1_d_valid(system_bus_xbar_auto_in_1_d_valid),
+ .auto_in_1_d_bits_opcode(system_bus_xbar_auto_in_1_d_bits_opcode),
+ .auto_in_1_d_bits_param(system_bus_xbar_auto_in_1_d_bits_param),
+ .auto_in_1_d_bits_size(system_bus_xbar_auto_in_1_d_bits_size),
+ .auto_in_1_d_bits_source(system_bus_xbar_auto_in_1_d_bits_source),
+ .auto_in_1_d_bits_sink(system_bus_xbar_auto_in_1_d_bits_sink),
+ .auto_in_1_d_bits_denied(system_bus_xbar_auto_in_1_d_bits_denied),
+ .auto_in_1_d_bits_data(system_bus_xbar_auto_in_1_d_bits_data),
+ .auto_in_1_d_bits_corrupt(system_bus_xbar_auto_in_1_d_bits_corrupt),
+ .auto_in_0_a_ready(system_bus_xbar_auto_in_0_a_ready),
+ .auto_in_0_a_valid(system_bus_xbar_auto_in_0_a_valid),
+ .auto_in_0_a_bits_opcode(system_bus_xbar_auto_in_0_a_bits_opcode),
+ .auto_in_0_a_bits_param(system_bus_xbar_auto_in_0_a_bits_param),
+ .auto_in_0_a_bits_size(system_bus_xbar_auto_in_0_a_bits_size),
+ .auto_in_0_a_bits_source(system_bus_xbar_auto_in_0_a_bits_source),
+ .auto_in_0_a_bits_address(system_bus_xbar_auto_in_0_a_bits_address),
+ .auto_in_0_a_bits_mask(system_bus_xbar_auto_in_0_a_bits_mask),
+ .auto_in_0_a_bits_data(system_bus_xbar_auto_in_0_a_bits_data),
+ .auto_in_0_a_bits_corrupt(system_bus_xbar_auto_in_0_a_bits_corrupt),
+ .auto_in_0_d_ready(system_bus_xbar_auto_in_0_d_ready),
+ .auto_in_0_d_valid(system_bus_xbar_auto_in_0_d_valid),
+ .auto_in_0_d_bits_opcode(system_bus_xbar_auto_in_0_d_bits_opcode),
+ .auto_in_0_d_bits_param(system_bus_xbar_auto_in_0_d_bits_param),
+ .auto_in_0_d_bits_size(system_bus_xbar_auto_in_0_d_bits_size),
+ .auto_in_0_d_bits_sink(system_bus_xbar_auto_in_0_d_bits_sink),
+ .auto_in_0_d_bits_denied(system_bus_xbar_auto_in_0_d_bits_denied),
+ .auto_in_0_d_bits_data(system_bus_xbar_auto_in_0_d_bits_data),
+ .auto_in_0_d_bits_corrupt(system_bus_xbar_auto_in_0_d_bits_corrupt),
+ .auto_out_a_ready(system_bus_xbar_auto_out_a_ready),
+ .auto_out_a_valid(system_bus_xbar_auto_out_a_valid),
+ .auto_out_a_bits_opcode(system_bus_xbar_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(system_bus_xbar_auto_out_a_bits_param),
+ .auto_out_a_bits_size(system_bus_xbar_auto_out_a_bits_size),
+ .auto_out_a_bits_source(system_bus_xbar_auto_out_a_bits_source),
+ .auto_out_a_bits_address(system_bus_xbar_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(system_bus_xbar_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(system_bus_xbar_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(system_bus_xbar_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(system_bus_xbar_auto_out_d_ready),
+ .auto_out_d_valid(system_bus_xbar_auto_out_d_valid),
+ .auto_out_d_bits_opcode(system_bus_xbar_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(system_bus_xbar_auto_out_d_bits_param),
+ .auto_out_d_bits_size(system_bus_xbar_auto_out_d_bits_size),
+ .auto_out_d_bits_source(system_bus_xbar_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(system_bus_xbar_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(system_bus_xbar_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(system_bus_xbar_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(system_bus_xbar_auto_out_d_bits_corrupt)
+ );
+ TLFIFOFixer fixer ( // @[FIFOFixer.scala 144:27]
+ .clock(fixer_clock),
+ .reset(fixer_reset),
+ .auto_in_1_a_ready(fixer_auto_in_1_a_ready),
+ .auto_in_1_a_valid(fixer_auto_in_1_a_valid),
+ .auto_in_1_a_bits_opcode(fixer_auto_in_1_a_bits_opcode),
+ .auto_in_1_a_bits_param(fixer_auto_in_1_a_bits_param),
+ .auto_in_1_a_bits_size(fixer_auto_in_1_a_bits_size),
+ .auto_in_1_a_bits_source(fixer_auto_in_1_a_bits_source),
+ .auto_in_1_a_bits_address(fixer_auto_in_1_a_bits_address),
+ .auto_in_1_a_bits_mask(fixer_auto_in_1_a_bits_mask),
+ .auto_in_1_a_bits_data(fixer_auto_in_1_a_bits_data),
+ .auto_in_1_a_bits_corrupt(fixer_auto_in_1_a_bits_corrupt),
+ .auto_in_1_d_ready(fixer_auto_in_1_d_ready),
+ .auto_in_1_d_valid(fixer_auto_in_1_d_valid),
+ .auto_in_1_d_bits_opcode(fixer_auto_in_1_d_bits_opcode),
+ .auto_in_1_d_bits_param(fixer_auto_in_1_d_bits_param),
+ .auto_in_1_d_bits_size(fixer_auto_in_1_d_bits_size),
+ .auto_in_1_d_bits_source(fixer_auto_in_1_d_bits_source),
+ .auto_in_1_d_bits_sink(fixer_auto_in_1_d_bits_sink),
+ .auto_in_1_d_bits_denied(fixer_auto_in_1_d_bits_denied),
+ .auto_in_1_d_bits_data(fixer_auto_in_1_d_bits_data),
+ .auto_in_1_d_bits_corrupt(fixer_auto_in_1_d_bits_corrupt),
+ .auto_in_0_a_ready(fixer_auto_in_0_a_ready),
+ .auto_in_0_a_valid(fixer_auto_in_0_a_valid),
+ .auto_in_0_a_bits_opcode(fixer_auto_in_0_a_bits_opcode),
+ .auto_in_0_a_bits_param(fixer_auto_in_0_a_bits_param),
+ .auto_in_0_a_bits_size(fixer_auto_in_0_a_bits_size),
+ .auto_in_0_a_bits_source(fixer_auto_in_0_a_bits_source),
+ .auto_in_0_a_bits_address(fixer_auto_in_0_a_bits_address),
+ .auto_in_0_a_bits_mask(fixer_auto_in_0_a_bits_mask),
+ .auto_in_0_a_bits_data(fixer_auto_in_0_a_bits_data),
+ .auto_in_0_a_bits_corrupt(fixer_auto_in_0_a_bits_corrupt),
+ .auto_in_0_d_ready(fixer_auto_in_0_d_ready),
+ .auto_in_0_d_valid(fixer_auto_in_0_d_valid),
+ .auto_in_0_d_bits_opcode(fixer_auto_in_0_d_bits_opcode),
+ .auto_in_0_d_bits_param(fixer_auto_in_0_d_bits_param),
+ .auto_in_0_d_bits_size(fixer_auto_in_0_d_bits_size),
+ .auto_in_0_d_bits_sink(fixer_auto_in_0_d_bits_sink),
+ .auto_in_0_d_bits_denied(fixer_auto_in_0_d_bits_denied),
+ .auto_in_0_d_bits_data(fixer_auto_in_0_d_bits_data),
+ .auto_in_0_d_bits_corrupt(fixer_auto_in_0_d_bits_corrupt),
+ .auto_out_1_a_ready(fixer_auto_out_1_a_ready),
+ .auto_out_1_a_valid(fixer_auto_out_1_a_valid),
+ .auto_out_1_a_bits_opcode(fixer_auto_out_1_a_bits_opcode),
+ .auto_out_1_a_bits_param(fixer_auto_out_1_a_bits_param),
+ .auto_out_1_a_bits_size(fixer_auto_out_1_a_bits_size),
+ .auto_out_1_a_bits_source(fixer_auto_out_1_a_bits_source),
+ .auto_out_1_a_bits_address(fixer_auto_out_1_a_bits_address),
+ .auto_out_1_a_bits_mask(fixer_auto_out_1_a_bits_mask),
+ .auto_out_1_a_bits_data(fixer_auto_out_1_a_bits_data),
+ .auto_out_1_a_bits_corrupt(fixer_auto_out_1_a_bits_corrupt),
+ .auto_out_1_d_ready(fixer_auto_out_1_d_ready),
+ .auto_out_1_d_valid(fixer_auto_out_1_d_valid),
+ .auto_out_1_d_bits_opcode(fixer_auto_out_1_d_bits_opcode),
+ .auto_out_1_d_bits_param(fixer_auto_out_1_d_bits_param),
+ .auto_out_1_d_bits_size(fixer_auto_out_1_d_bits_size),
+ .auto_out_1_d_bits_source(fixer_auto_out_1_d_bits_source),
+ .auto_out_1_d_bits_sink(fixer_auto_out_1_d_bits_sink),
+ .auto_out_1_d_bits_denied(fixer_auto_out_1_d_bits_denied),
+ .auto_out_1_d_bits_data(fixer_auto_out_1_d_bits_data),
+ .auto_out_1_d_bits_corrupt(fixer_auto_out_1_d_bits_corrupt),
+ .auto_out_0_a_ready(fixer_auto_out_0_a_ready),
+ .auto_out_0_a_valid(fixer_auto_out_0_a_valid),
+ .auto_out_0_a_bits_opcode(fixer_auto_out_0_a_bits_opcode),
+ .auto_out_0_a_bits_param(fixer_auto_out_0_a_bits_param),
+ .auto_out_0_a_bits_size(fixer_auto_out_0_a_bits_size),
+ .auto_out_0_a_bits_source(fixer_auto_out_0_a_bits_source),
+ .auto_out_0_a_bits_address(fixer_auto_out_0_a_bits_address),
+ .auto_out_0_a_bits_mask(fixer_auto_out_0_a_bits_mask),
+ .auto_out_0_a_bits_data(fixer_auto_out_0_a_bits_data),
+ .auto_out_0_a_bits_corrupt(fixer_auto_out_0_a_bits_corrupt),
+ .auto_out_0_d_ready(fixer_auto_out_0_d_ready),
+ .auto_out_0_d_valid(fixer_auto_out_0_d_valid),
+ .auto_out_0_d_bits_opcode(fixer_auto_out_0_d_bits_opcode),
+ .auto_out_0_d_bits_param(fixer_auto_out_0_d_bits_param),
+ .auto_out_0_d_bits_size(fixer_auto_out_0_d_bits_size),
+ .auto_out_0_d_bits_sink(fixer_auto_out_0_d_bits_sink),
+ .auto_out_0_d_bits_denied(fixer_auto_out_0_d_bits_denied),
+ .auto_out_0_d_bits_data(fixer_auto_out_0_d_bits_data),
+ .auto_out_0_d_bits_corrupt(fixer_auto_out_0_d_bits_corrupt)
+ );
+ TLInterconnectCoupler coupler_to_bus_named_subsystem_cbus ( // @[LazyModule.scala 432:27]
+ .auto_widget_in_a_ready(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_ready),
+ .auto_widget_in_a_valid(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_valid),
+ .auto_widget_in_a_bits_opcode(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_opcode),
+ .auto_widget_in_a_bits_param(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_param),
+ .auto_widget_in_a_bits_size(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_size),
+ .auto_widget_in_a_bits_source(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_source),
+ .auto_widget_in_a_bits_address(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_address),
+ .auto_widget_in_a_bits_mask(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_mask),
+ .auto_widget_in_a_bits_data(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_data),
+ .auto_widget_in_a_bits_corrupt(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_corrupt),
+ .auto_widget_in_d_ready(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_ready),
+ .auto_widget_in_d_valid(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_valid),
+ .auto_widget_in_d_bits_opcode(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_opcode),
+ .auto_widget_in_d_bits_param(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_param),
+ .auto_widget_in_d_bits_size(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_size),
+ .auto_widget_in_d_bits_source(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_source),
+ .auto_widget_in_d_bits_sink(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_sink),
+ .auto_widget_in_d_bits_denied(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_denied),
+ .auto_widget_in_d_bits_data(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_data),
+ .auto_widget_in_d_bits_corrupt(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_corrupt),
+ .auto_bus_xing_out_a_ready(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_ready),
+ .auto_bus_xing_out_a_valid(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_valid),
+ .auto_bus_xing_out_a_bits_opcode(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_opcode),
+ .auto_bus_xing_out_a_bits_param(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_param),
+ .auto_bus_xing_out_a_bits_size(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_size),
+ .auto_bus_xing_out_a_bits_source(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_source),
+ .auto_bus_xing_out_a_bits_address(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_address),
+ .auto_bus_xing_out_a_bits_mask(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_mask),
+ .auto_bus_xing_out_a_bits_data(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_data),
+ .auto_bus_xing_out_a_bits_corrupt(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_corrupt),
+ .auto_bus_xing_out_d_ready(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_ready),
+ .auto_bus_xing_out_d_valid(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_valid),
+ .auto_bus_xing_out_d_bits_opcode(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_opcode),
+ .auto_bus_xing_out_d_bits_param(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_param),
+ .auto_bus_xing_out_d_bits_size(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_size),
+ .auto_bus_xing_out_d_bits_source(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_source),
+ .auto_bus_xing_out_d_bits_sink(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_sink),
+ .auto_bus_xing_out_d_bits_denied(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_denied),
+ .auto_bus_xing_out_d_bits_data(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_data),
+ .auto_bus_xing_out_d_bits_corrupt(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_corrupt)
+ );
+ TLInterconnectCoupler_1 coupler_from_bus_named_subsystem_fbus ( // @[LazyModule.scala 432:27]
+ .auto_widget_out_a_ready(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_ready),
+ .auto_widget_out_a_valid(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_valid),
+ .auto_widget_out_a_bits_opcode(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_opcode),
+ .auto_widget_out_a_bits_param(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_param),
+ .auto_widget_out_a_bits_size(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_size),
+ .auto_widget_out_a_bits_source(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_source),
+ .auto_widget_out_a_bits_address(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_address),
+ .auto_widget_out_a_bits_mask(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_mask),
+ .auto_widget_out_a_bits_data(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_data),
+ .auto_widget_out_a_bits_corrupt(coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_corrupt),
+ .auto_widget_out_d_ready(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_ready),
+ .auto_widget_out_d_valid(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_valid),
+ .auto_widget_out_d_bits_opcode(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_opcode),
+ .auto_widget_out_d_bits_param(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_param),
+ .auto_widget_out_d_bits_size(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_size),
+ .auto_widget_out_d_bits_sink(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_sink),
+ .auto_widget_out_d_bits_denied(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_denied),
+ .auto_widget_out_d_bits_data(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_data),
+ .auto_widget_out_d_bits_corrupt(coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_corrupt),
+ .auto_bus_xing_in_a_ready(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_ready),
+ .auto_bus_xing_in_a_valid(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_valid),
+ .auto_bus_xing_in_a_bits_opcode(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_opcode),
+ .auto_bus_xing_in_a_bits_param(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_param),
+ .auto_bus_xing_in_a_bits_size(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_size),
+ .auto_bus_xing_in_a_bits_source(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_source),
+ .auto_bus_xing_in_a_bits_address(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_address),
+ .auto_bus_xing_in_a_bits_mask(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_mask),
+ .auto_bus_xing_in_a_bits_data(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_data),
+ .auto_bus_xing_in_a_bits_corrupt(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_corrupt),
+ .auto_bus_xing_in_d_ready(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_ready),
+ .auto_bus_xing_in_d_valid(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_valid),
+ .auto_bus_xing_in_d_bits_opcode(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_opcode),
+ .auto_bus_xing_in_d_bits_param(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_param),
+ .auto_bus_xing_in_d_bits_size(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_size),
+ .auto_bus_xing_in_d_bits_sink(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_sink),
+ .auto_bus_xing_in_d_bits_denied(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_denied),
+ .auto_bus_xing_in_d_bits_data(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_data),
+ .auto_bus_xing_in_d_bits_corrupt(coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_corrupt)
+ );
+ TLInterconnectCoupler_2 coupler_from_tile ( // @[LazyModule.scala 432:27]
+ .auto_tl_master_clock_xing_in_a_ready(coupler_from_tile_auto_tl_master_clock_xing_in_a_ready),
+ .auto_tl_master_clock_xing_in_a_valid(coupler_from_tile_auto_tl_master_clock_xing_in_a_valid),
+ .auto_tl_master_clock_xing_in_a_bits_opcode(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_opcode),
+ .auto_tl_master_clock_xing_in_a_bits_param(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_param),
+ .auto_tl_master_clock_xing_in_a_bits_size(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_size),
+ .auto_tl_master_clock_xing_in_a_bits_source(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_source),
+ .auto_tl_master_clock_xing_in_a_bits_address(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_address),
+ .auto_tl_master_clock_xing_in_a_bits_mask(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_mask),
+ .auto_tl_master_clock_xing_in_a_bits_data(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_data),
+ .auto_tl_master_clock_xing_in_a_bits_corrupt(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_corrupt),
+ .auto_tl_master_clock_xing_in_d_ready(coupler_from_tile_auto_tl_master_clock_xing_in_d_ready),
+ .auto_tl_master_clock_xing_in_d_valid(coupler_from_tile_auto_tl_master_clock_xing_in_d_valid),
+ .auto_tl_master_clock_xing_in_d_bits_opcode(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_opcode),
+ .auto_tl_master_clock_xing_in_d_bits_param(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_param),
+ .auto_tl_master_clock_xing_in_d_bits_size(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_size),
+ .auto_tl_master_clock_xing_in_d_bits_source(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_source),
+ .auto_tl_master_clock_xing_in_d_bits_sink(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_sink),
+ .auto_tl_master_clock_xing_in_d_bits_denied(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_denied),
+ .auto_tl_master_clock_xing_in_d_bits_data(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_data),
+ .auto_tl_master_clock_xing_in_d_bits_corrupt(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_corrupt),
+ .auto_tl_out_a_ready(coupler_from_tile_auto_tl_out_a_ready),
+ .auto_tl_out_a_valid(coupler_from_tile_auto_tl_out_a_valid),
+ .auto_tl_out_a_bits_opcode(coupler_from_tile_auto_tl_out_a_bits_opcode),
+ .auto_tl_out_a_bits_param(coupler_from_tile_auto_tl_out_a_bits_param),
+ .auto_tl_out_a_bits_size(coupler_from_tile_auto_tl_out_a_bits_size),
+ .auto_tl_out_a_bits_source(coupler_from_tile_auto_tl_out_a_bits_source),
+ .auto_tl_out_a_bits_address(coupler_from_tile_auto_tl_out_a_bits_address),
+ .auto_tl_out_a_bits_mask(coupler_from_tile_auto_tl_out_a_bits_mask),
+ .auto_tl_out_a_bits_data(coupler_from_tile_auto_tl_out_a_bits_data),
+ .auto_tl_out_a_bits_corrupt(coupler_from_tile_auto_tl_out_a_bits_corrupt),
+ .auto_tl_out_d_ready(coupler_from_tile_auto_tl_out_d_ready),
+ .auto_tl_out_d_valid(coupler_from_tile_auto_tl_out_d_valid),
+ .auto_tl_out_d_bits_opcode(coupler_from_tile_auto_tl_out_d_bits_opcode),
+ .auto_tl_out_d_bits_param(coupler_from_tile_auto_tl_out_d_bits_param),
+ .auto_tl_out_d_bits_size(coupler_from_tile_auto_tl_out_d_bits_size),
+ .auto_tl_out_d_bits_source(coupler_from_tile_auto_tl_out_d_bits_source),
+ .auto_tl_out_d_bits_sink(coupler_from_tile_auto_tl_out_d_bits_sink),
+ .auto_tl_out_d_bits_denied(coupler_from_tile_auto_tl_out_d_bits_denied),
+ .auto_tl_out_d_bits_data(coupler_from_tile_auto_tl_out_d_bits_data),
+ .auto_tl_out_d_bits_corrupt(coupler_from_tile_auto_tl_out_d_bits_corrupt)
+ );
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_a_ready = coupler_from_tile_auto_tl_master_clock_xing_in_a_ready
+ ; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_valid = coupler_from_tile_auto_tl_master_clock_xing_in_d_valid
+ ; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode =
+ coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param =
+ coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size =
+ coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source =
+ coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink =
+ coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied =
+ coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data =
+ coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt =
+ coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt =
+ coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready =
+ coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_1_clock = fixedClockNode_auto_out_2_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_1_reset = fixedClockNode_auto_out_2_reset; // @[LazyModule.scala 311:12]
+ assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_clock =
+ auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock; // @[LazyModule.scala 309:16]
+ assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_reset =
+ auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset; // @[LazyModule.scala 309:16]
+ assign clockGroup_auto_in_member_subsystem_sbus_0_clock =
+ subsystem_sbus_clock_groups_auto_out_member_subsystem_sbus_0_clock; // @[LazyModule.scala 298:16]
+ assign clockGroup_auto_in_member_subsystem_sbus_0_reset =
+ subsystem_sbus_clock_groups_auto_out_member_subsystem_sbus_0_reset; // @[LazyModule.scala 298:16]
+ assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
+ assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign system_bus_xbar_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_valid = fixer_auto_out_1_a_valid; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_bits_opcode = fixer_auto_out_1_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_bits_param = fixer_auto_out_1_a_bits_param; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_bits_size = fixer_auto_out_1_a_bits_size; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_bits_source = fixer_auto_out_1_a_bits_source; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_bits_address = fixer_auto_out_1_a_bits_address; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_bits_mask = fixer_auto_out_1_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_bits_data = fixer_auto_out_1_a_bits_data; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_a_bits_corrupt = fixer_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_1_d_ready = fixer_auto_out_1_d_ready; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_valid = fixer_auto_out_0_a_valid; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_bits_opcode = fixer_auto_out_0_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_bits_param = fixer_auto_out_0_a_bits_param; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_bits_size = fixer_auto_out_0_a_bits_size; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_bits_source = fixer_auto_out_0_a_bits_source; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_bits_address = fixer_auto_out_0_a_bits_address; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_bits_mask = fixer_auto_out_0_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_bits_data = fixer_auto_out_0_a_bits_data; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_a_bits_corrupt = fixer_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_in_0_d_ready = fixer_auto_out_0_d_ready; // @[LazyModule.scala 296:16]
+ assign system_bus_xbar_auto_out_a_ready = coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_ready; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_valid = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_valid; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_bits_opcode = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_bits_param = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_bits_size = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_bits_source = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_bits_sink = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_bits_denied = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_bits_data = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign system_bus_xbar_auto_out_d_bits_corrupt = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign fixer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign fixer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_valid = coupler_from_tile_auto_tl_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_bits_opcode = coupler_from_tile_auto_tl_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_bits_param = coupler_from_tile_auto_tl_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_bits_size = coupler_from_tile_auto_tl_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_bits_source = coupler_from_tile_auto_tl_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_bits_address = coupler_from_tile_auto_tl_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_bits_mask = coupler_from_tile_auto_tl_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_bits_data = coupler_from_tile_auto_tl_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_a_bits_corrupt = coupler_from_tile_auto_tl_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_1_d_ready = coupler_from_tile_auto_tl_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_valid = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_bits_opcode = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_bits_param = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_bits_size = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_bits_source = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_bits_address = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_bits_mask = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_bits_data = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_a_bits_corrupt = coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_0_d_ready = coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_a_ready = system_bus_xbar_auto_in_1_a_ready; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_valid = system_bus_xbar_auto_in_1_d_valid; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_bits_opcode = system_bus_xbar_auto_in_1_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_bits_param = system_bus_xbar_auto_in_1_d_bits_param; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_bits_size = system_bus_xbar_auto_in_1_d_bits_size; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_bits_source = system_bus_xbar_auto_in_1_d_bits_source; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_bits_sink = system_bus_xbar_auto_in_1_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_bits_denied = system_bus_xbar_auto_in_1_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_bits_data = system_bus_xbar_auto_in_1_d_bits_data; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_1_d_bits_corrupt = system_bus_xbar_auto_in_1_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_a_ready = system_bus_xbar_auto_in_0_a_ready; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_d_valid = system_bus_xbar_auto_in_0_d_valid; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_d_bits_opcode = system_bus_xbar_auto_in_0_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_d_bits_param = system_bus_xbar_auto_in_0_d_bits_param; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_d_bits_size = system_bus_xbar_auto_in_0_d_bits_size; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_d_bits_sink = system_bus_xbar_auto_in_0_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_d_bits_denied = system_bus_xbar_auto_in_0_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_d_bits_data = system_bus_xbar_auto_in_0_d_bits_data; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_0_d_bits_corrupt = system_bus_xbar_auto_in_0_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_valid = system_bus_xbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_opcode = system_bus_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_param = system_bus_xbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_size = system_bus_xbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_source = system_bus_xbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_address = system_bus_xbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_mask = system_bus_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_data = system_bus_xbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_corrupt = system_bus_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_ready = system_bus_xbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_ready =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_valid =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_opcode =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_param =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_size =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_source =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_sink =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_denied =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_data =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_corrupt =
+ auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_a_ready = fixer_auto_in_0_a_ready; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_valid = fixer_auto_in_0_d_valid; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_opcode = fixer_auto_in_0_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_param = fixer_auto_in_0_d_bits_param; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_size = fixer_auto_in_0_d_bits_size; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_sink = fixer_auto_in_0_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_denied = fixer_auto_in_0_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_data = fixer_auto_in_0_d_bits_data; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_widget_out_d_bits_corrupt = fixer_auto_in_0_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_valid =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_valid; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_opcode =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_param =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_size =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_source =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_address =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_mask =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_data =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_a_bits_corrupt =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign coupler_from_bus_named_subsystem_fbus_auto_bus_xing_in_d_ready =
+ auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_ready; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_tile_tl_master_clock_xing_in_a_valid
+ ; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_opcode =
+ auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_param =
+ auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_size =
+ auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_source =
+ auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_address =
+ auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_mask =
+ auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_data =
+ auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_corrupt =
+ auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_tile_tl_master_clock_xing_in_d_ready
+ ; // @[LazyModule.scala 309:16]
+ assign coupler_from_tile_auto_tl_out_a_ready = fixer_auto_in_1_a_ready; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_valid = fixer_auto_in_1_d_valid; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_bits_opcode = fixer_auto_in_1_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_bits_param = fixer_auto_in_1_d_bits_param; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_bits_size = fixer_auto_in_1_d_bits_size; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_bits_source = fixer_auto_in_1_d_bits_source; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_bits_sink = fixer_auto_in_1_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_bits_denied = fixer_auto_in_1_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_bits_data = fixer_auto_in_1_d_bits_data; // @[LazyModule.scala 296:16]
+ assign coupler_from_tile_auto_tl_out_d_bits_corrupt = fixer_auto_in_1_d_bits_corrupt; // @[LazyModule.scala 296:16]
+endmodule
+module ClockGroupAggregator_1(
+ input auto_in_member_subsystem_pbus_0_clock,
+ input auto_in_member_subsystem_pbus_0_reset,
+ output auto_out_member_subsystem_pbus_0_clock,
+ output auto_out_member_subsystem_pbus_0_reset
+);
+ assign auto_out_member_subsystem_pbus_0_clock = auto_in_member_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_subsystem_pbus_0_reset = auto_in_member_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockGroup_1(
+ input auto_in_member_subsystem_pbus_0_clock,
+ input auto_in_member_subsystem_pbus_0_reset,
+ output auto_out_clock,
+ output auto_out_reset
+);
+ assign auto_out_clock = auto_in_member_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_reset = auto_in_member_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module FixedClockBroadcast_1(
+ input auto_in_clock,
+ input auto_in_reset,
+ output auto_out_5_clock,
+ output auto_out_5_reset,
+ output auto_out_4_clock,
+ output auto_out_4_reset,
+ output auto_out_3_clock,
+ output auto_out_3_reset,
+ output auto_out_2_clock,
+ output auto_out_2_reset,
+ output auto_out_1_clock,
+ output auto_out_1_reset,
+ output auto_out_0_clock,
+ output auto_out_0_reset
+);
+ assign auto_out_5_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_4(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h4000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_61 = io_in_a_bits_address ^ 30'h20000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_64 = $signed(_T_62) & -31'sh10000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_66 = io_in_a_bits_address ^ 30'h10000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_69 = $signed(_T_67) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_71 = io_in_a_bits_address ^ 30'h10010000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_74 = $signed(_T_72) & -31'sh4000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_76 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_79 = $signed(_T_77) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_81 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_84 = $signed(_T_82) & -31'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_90 = _T_60 | _T_65 | _T_70 | _T_75 | _T_80 | _T_85; // @[Parameters.scala 671:42]
+ wire _T_152 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_156 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_157 = _T_156 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_161 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_165 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_279 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_292 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_309 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_347 = _T_309 & _T_90; // @[Parameters.scala 670:56]
+ wire _T_358 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_362 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_370 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_409 = _T_60 | _T_70 | _T_75 | _T_80; // @[Parameters.scala 671:42]
+ wire _T_410 = _T_309 & _T_409; // @[Parameters.scala 670:56]
+ wire _T_426 = source_ok & _T_410; // @[Monitor.scala 115:71]
+ wire _T_444 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_514 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_515 = io_in_a_bits_mask & _T_514; // @[Monitor.scala 127:31]
+ wire _T_516 = _T_515 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_520 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_581 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_589 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_650 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_658 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_719 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_731 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_735 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_739 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_743 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_747 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_751 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_755 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_766 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_770 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_783 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_803 = _T_751 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_812 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_829 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_847 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_877 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_878 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_882 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_886 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_890 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_894 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_901 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_902 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_906 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_910 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_914 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_918 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_922 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_928 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_931 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_933 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_935 = ~_T_933[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_939 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_941 = ~_T_735; // @[Monitor.scala 671:74]
+ wire _T_942 = io_in_d_valid & d_first_1 & ~_T_735; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_941 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_941 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_928 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_952 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_954 = _T_952[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_959 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_960 = io_in_d_bits_opcode == _GEN_32 | _T_959; // @[Monitor.scala 685:77]
+ wire _T_964 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_971 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_972 = io_in_d_bits_opcode == _GEN_48 | _T_971; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_976 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_986 = _T_939 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_941; // @[Monitor.scala 694:116]
+ wire _T_988 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_997 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_1023 = io_in_d_valid & d_first_2 & _T_735; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_735 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_735 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_1031 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_1041 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1061 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_279 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_516 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_516) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_581 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_581) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_719 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_719) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_731 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_731) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_766 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_766) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_770 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_770) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_766 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_766) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_770 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_770) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_803 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_803) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_803 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_803) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_878 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_878) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_882 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_882) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_886 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_886) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_894 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_894) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_902 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_902) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_906 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_906) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_910 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_910) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_914 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_914) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_918 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_918) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_922 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_922) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_935 & (_T_931 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_931 & ~reset & ~_T_935) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_954 & (_T_942 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & _T_2 & ~_T_954) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_960 & (_T_942 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & same_cycle_resp & _T_2 & ~_T_960) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_964 & (_T_942 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & same_cycle_resp & _T_2 & ~_T_964) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_972 & (_T_942 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & ~same_cycle_resp & _T_2 & ~_T_972) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_976 & (_T_942 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & ~same_cycle_resp & _T_2 & ~_T_976) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_988 & (_T_986 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_986 & _T_2 & ~_T_988) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_997 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_997) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1031[0] & (_T_1023 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1023 & _T_2 & ~_T_1031[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1041 & (_T_1023 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1023 & _T_2 & ~_T_1041) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1061 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1061) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFIFOFixer_1(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ TLMonitor_4 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[FIFOFixer.scala 87:33]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLXbar_1(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[ReadyValidCancel.scala 21:38]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Xbar.scala 228:69]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[ReadyValidCancel.scala 21:38]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_5(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h4000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_61 = io_in_a_bits_address ^ 30'h20000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_64 = $signed(_T_62) & -31'sh10000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_66 = io_in_a_bits_address ^ 30'h10000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_69 = $signed(_T_67) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_71 = io_in_a_bits_address ^ 30'h10010000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_74 = $signed(_T_72) & -31'sh4000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_76 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_79 = $signed(_T_77) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_81 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_84 = $signed(_T_82) & -31'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_90 = _T_60 | _T_65 | _T_70 | _T_75 | _T_80 | _T_85; // @[Parameters.scala 671:42]
+ wire _T_152 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_156 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_157 = _T_156 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_161 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_165 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_279 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_292 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_309 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_347 = _T_309 & _T_90; // @[Parameters.scala 670:56]
+ wire _T_358 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_362 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_370 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_409 = _T_60 | _T_70 | _T_75 | _T_80; // @[Parameters.scala 671:42]
+ wire _T_410 = _T_309 & _T_409; // @[Parameters.scala 670:56]
+ wire _T_426 = source_ok & _T_410; // @[Monitor.scala 115:71]
+ wire _T_444 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_514 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_515 = io_in_a_bits_mask & _T_514; // @[Monitor.scala 127:31]
+ wire _T_516 = _T_515 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_520 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_581 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_589 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_650 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_658 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_719 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_731 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_735 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_739 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_743 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_747 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_751 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_755 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_766 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_770 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_783 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_803 = _T_751 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_812 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_829 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_847 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_877 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_878 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_882 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_886 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_890 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_894 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_901 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_902 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_906 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_910 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_914 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_918 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_922 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_928 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_931 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_933 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_935 = ~_T_933[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_939 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_941 = ~_T_735; // @[Monitor.scala 671:74]
+ wire _T_942 = io_in_d_valid & d_first_1 & ~_T_735; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_941 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_941 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_928 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_952 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_954 = _T_952[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_959 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_960 = io_in_d_bits_opcode == _GEN_32 | _T_959; // @[Monitor.scala 685:77]
+ wire _T_964 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_971 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_972 = io_in_d_bits_opcode == _GEN_48 | _T_971; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_976 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_986 = _T_939 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_941; // @[Monitor.scala 694:116]
+ wire _T_988 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_997 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_1023 = io_in_d_valid & d_first_2 & _T_735; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_735 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_735 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_1031 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_1041 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1061 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_279 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_516 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_516) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_581 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_581) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_719 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_719) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_731 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_731) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_766 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_766) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_770 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_770) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_766 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_766) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_770 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_770) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_803 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_803) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_803 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_803) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_878 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_878) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_882 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_882) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_886 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_886) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_894 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_894) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_902 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_902) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_906 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_906) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_910 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_910) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_914 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_914) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_918 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_918) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_922 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_922) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_935 & (_T_931 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_931 & ~reset & ~_T_935) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_954 & (_T_942 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & _T_2 & ~_T_954) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_960 & (_T_942 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & same_cycle_resp & _T_2 & ~_T_960) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_964 & (_T_942 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & same_cycle_resp & _T_2 & ~_T_964) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_972 & (_T_942 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & ~same_cycle_resp & _T_2 & ~_T_972) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_976 & (_T_942 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & ~same_cycle_resp & _T_2 & ~_T_976) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_988 & (_T_986 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_986 & _T_2 & ~_T_988) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_997 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_997) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1031[0] & (_T_1023 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1023 & _T_2 & ~_T_1031[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1041 & (_T_1023 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1023 & _T_2 & ~_T_1041) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1061 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1061) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLXbar_2(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_8_a_ready,
+ output auto_out_8_a_valid,
+ output [2:0] auto_out_8_a_bits_opcode,
+ output [2:0] auto_out_8_a_bits_param,
+ output [2:0] auto_out_8_a_bits_size,
+ output [2:0] auto_out_8_a_bits_source,
+ output [29:0] auto_out_8_a_bits_address,
+ output [7:0] auto_out_8_a_bits_mask,
+ output auto_out_8_a_bits_corrupt,
+ output auto_out_8_d_ready,
+ input auto_out_8_d_valid,
+ input [2:0] auto_out_8_d_bits_size,
+ input [2:0] auto_out_8_d_bits_source,
+ input [63:0] auto_out_8_d_bits_data,
+ input auto_out_7_a_ready,
+ output auto_out_7_a_valid,
+ output [2:0] auto_out_7_a_bits_opcode,
+ output [2:0] auto_out_7_a_bits_param,
+ output [2:0] auto_out_7_a_bits_size,
+ output [2:0] auto_out_7_a_bits_source,
+ output [28:0] auto_out_7_a_bits_address,
+ output [7:0] auto_out_7_a_bits_mask,
+ output [63:0] auto_out_7_a_bits_data,
+ output auto_out_7_a_bits_corrupt,
+ output auto_out_7_d_ready,
+ input auto_out_7_d_valid,
+ input [2:0] auto_out_7_d_bits_opcode,
+ input [2:0] auto_out_7_d_bits_size,
+ input [2:0] auto_out_7_d_bits_source,
+ input [63:0] auto_out_7_d_bits_data,
+ input auto_out_6_a_ready,
+ output auto_out_6_a_valid,
+ output [2:0] auto_out_6_a_bits_opcode,
+ output [2:0] auto_out_6_a_bits_param,
+ output [2:0] auto_out_6_a_bits_size,
+ output [2:0] auto_out_6_a_bits_source,
+ output [29:0] auto_out_6_a_bits_address,
+ output [7:0] auto_out_6_a_bits_mask,
+ output auto_out_6_a_bits_corrupt,
+ output auto_out_6_d_ready,
+ input auto_out_6_d_valid,
+ input [2:0] auto_out_6_d_bits_size,
+ input [2:0] auto_out_6_d_bits_source,
+ input [63:0] auto_out_6_d_bits_data,
+ input auto_out_5_a_ready,
+ output auto_out_5_a_valid,
+ output [2:0] auto_out_5_a_bits_opcode,
+ output [2:0] auto_out_5_a_bits_param,
+ output [2:0] auto_out_5_a_bits_size,
+ output [2:0] auto_out_5_a_bits_source,
+ output [28:0] auto_out_5_a_bits_address,
+ output [7:0] auto_out_5_a_bits_mask,
+ output [63:0] auto_out_5_a_bits_data,
+ output auto_out_5_a_bits_corrupt,
+ output auto_out_5_d_ready,
+ input auto_out_5_d_valid,
+ input [2:0] auto_out_5_d_bits_opcode,
+ input [2:0] auto_out_5_d_bits_size,
+ input [2:0] auto_out_5_d_bits_source,
+ input [63:0] auto_out_5_d_bits_data,
+ input auto_out_4_a_ready,
+ output auto_out_4_a_valid,
+ output [2:0] auto_out_4_a_bits_opcode,
+ output [2:0] auto_out_4_a_bits_param,
+ output [2:0] auto_out_4_a_bits_size,
+ output [2:0] auto_out_4_a_bits_source,
+ output [28:0] auto_out_4_a_bits_address,
+ output [7:0] auto_out_4_a_bits_mask,
+ output [63:0] auto_out_4_a_bits_data,
+ output auto_out_4_a_bits_corrupt,
+ output auto_out_4_d_ready,
+ input auto_out_4_d_valid,
+ input [2:0] auto_out_4_d_bits_opcode,
+ input [2:0] auto_out_4_d_bits_size,
+ input [2:0] auto_out_4_d_bits_source,
+ input [63:0] auto_out_4_d_bits_data,
+ input auto_out_3_a_ready,
+ output auto_out_3_a_valid,
+ output [2:0] auto_out_3_a_bits_opcode,
+ output [2:0] auto_out_3_a_bits_param,
+ output [2:0] auto_out_3_a_bits_size,
+ output [2:0] auto_out_3_a_bits_source,
+ output [28:0] auto_out_3_a_bits_address,
+ output [7:0] auto_out_3_a_bits_mask,
+ output [63:0] auto_out_3_a_bits_data,
+ output auto_out_3_a_bits_corrupt,
+ output auto_out_3_d_ready,
+ input auto_out_3_d_valid,
+ input [2:0] auto_out_3_d_bits_opcode,
+ input [2:0] auto_out_3_d_bits_size,
+ input [2:0] auto_out_3_d_bits_source,
+ input [63:0] auto_out_3_d_bits_data,
+ input auto_out_2_a_ready,
+ output auto_out_2_a_valid,
+ output [2:0] auto_out_2_a_bits_opcode,
+ output [2:0] auto_out_2_a_bits_param,
+ output [2:0] auto_out_2_a_bits_size,
+ output [2:0] auto_out_2_a_bits_source,
+ output [28:0] auto_out_2_a_bits_address,
+ output [7:0] auto_out_2_a_bits_mask,
+ output [63:0] auto_out_2_a_bits_data,
+ output auto_out_2_a_bits_corrupt,
+ output auto_out_2_d_ready,
+ input auto_out_2_d_valid,
+ input [2:0] auto_out_2_d_bits_opcode,
+ input [2:0] auto_out_2_d_bits_size,
+ input [2:0] auto_out_2_d_bits_source,
+ input [63:0] auto_out_2_d_bits_data,
+ input auto_out_1_a_ready,
+ output auto_out_1_a_valid,
+ output [2:0] auto_out_1_a_bits_opcode,
+ output [2:0] auto_out_1_a_bits_param,
+ output [2:0] auto_out_1_a_bits_size,
+ output [2:0] auto_out_1_a_bits_source,
+ output [28:0] auto_out_1_a_bits_address,
+ output [7:0] auto_out_1_a_bits_mask,
+ output [63:0] auto_out_1_a_bits_data,
+ output auto_out_1_a_bits_corrupt,
+ output auto_out_1_d_ready,
+ input auto_out_1_d_valid,
+ input [2:0] auto_out_1_d_bits_opcode,
+ input [1:0] auto_out_1_d_bits_param,
+ input [2:0] auto_out_1_d_bits_size,
+ input [2:0] auto_out_1_d_bits_source,
+ input auto_out_1_d_bits_sink,
+ input auto_out_1_d_bits_denied,
+ input [63:0] auto_out_1_d_bits_data,
+ input auto_out_1_d_bits_corrupt,
+ input auto_out_0_a_ready,
+ output auto_out_0_a_valid,
+ output [2:0] auto_out_0_a_bits_opcode,
+ output [2:0] auto_out_0_a_bits_param,
+ output [2:0] auto_out_0_a_bits_size,
+ output [2:0] auto_out_0_a_bits_source,
+ output [14:0] auto_out_0_a_bits_address,
+ output [7:0] auto_out_0_a_bits_mask,
+ output [63:0] auto_out_0_a_bits_data,
+ output auto_out_0_a_bits_corrupt,
+ output auto_out_0_d_ready,
+ input auto_out_0_d_valid,
+ input [2:0] auto_out_0_d_bits_opcode,
+ input [2:0] auto_out_0_d_bits_size,
+ input [2:0] auto_out_0_d_bits_source,
+ input [63:0] auto_out_0_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ reg [2:0] beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle = beatsLeft == 3'h0; // @[Arbiter.scala 88:28]
+ wire [8:0] readys_valid = {auto_out_8_d_valid,auto_out_7_d_valid,auto_out_6_d_valid,auto_out_5_d_valid,
+ auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
+ reg [8:0] readys_mask; // @[Arbiter.scala 23:23]
+ wire [8:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
+ wire [8:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
+ wire [17:0] readys_filter = {_readys_filter_T_1,auto_out_8_d_valid,auto_out_7_d_valid,auto_out_6_d_valid,
+ auto_out_5_d_valid,auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
+ wire [17:0] _GEN_1 = {{1'd0}, readys_filter[17:1]}; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
+ wire [17:0] _GEN_2 = {{2'd0}, _readys_unready_T_1[17:2]}; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_3 = _readys_unready_T_1 | _GEN_2; // @[package.scala 253:43]
+ wire [17:0] _GEN_3 = {{4'd0}, _readys_unready_T_3[17:4]}; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_5 = _readys_unready_T_3 | _GEN_3; // @[package.scala 253:43]
+ wire [17:0] _GEN_4 = {{8'd0}, _readys_unready_T_5[17:8]}; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_7 = _readys_unready_T_5 | _GEN_4; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_10 = {readys_mask, 9'h0}; // @[Arbiter.scala 25:66]
+ wire [17:0] _GEN_5 = {{1'd0}, _readys_unready_T_7[17:1]}; // @[Arbiter.scala 25:58]
+ wire [17:0] readys_unready = _GEN_5 | _readys_unready_T_10; // @[Arbiter.scala 25:58]
+ wire [8:0] _readys_readys_T_2 = readys_unready[17:9] & readys_unready[8:0]; // @[Arbiter.scala 26:39]
+ wire [8:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
+ wire readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_0 = readys_0 & auto_out_0_d_valid; // @[Arbiter.scala 97:79]
+ reg state_0; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_148 = muxStateEarly_0 ? auto_out_0_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_1 = readys_1 & auto_out_1_d_valid; // @[Arbiter.scala 97:79]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_149 = muxStateEarly_1 ? auto_out_1_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_157 = _T_148 | _T_149; // @[Mux.scala 27:73]
+ wire readys_2 = readys_readys[2]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_2 = readys_2 & auto_out_2_d_valid; // @[Arbiter.scala 97:79]
+ reg state_2; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_2 = idle ? earlyWinner_2 : state_2; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_150 = muxStateEarly_2 ? auto_out_2_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_158 = _T_157 | _T_150; // @[Mux.scala 27:73]
+ wire readys_3 = readys_readys[3]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_3 = readys_3 & auto_out_3_d_valid; // @[Arbiter.scala 97:79]
+ reg state_3; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_3 = idle ? earlyWinner_3 : state_3; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_151 = muxStateEarly_3 ? auto_out_3_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_159 = _T_158 | _T_151; // @[Mux.scala 27:73]
+ wire readys_4 = readys_readys[4]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_4 = readys_4 & auto_out_4_d_valid; // @[Arbiter.scala 97:79]
+ reg state_4; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_4 = idle ? earlyWinner_4 : state_4; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_152 = muxStateEarly_4 ? auto_out_4_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_160 = _T_159 | _T_152; // @[Mux.scala 27:73]
+ wire readys_5 = readys_readys[5]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_5 = readys_5 & auto_out_5_d_valid; // @[Arbiter.scala 97:79]
+ reg state_5; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_5 = idle ? earlyWinner_5 : state_5; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_153 = muxStateEarly_5 ? auto_out_5_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_161 = _T_160 | _T_153; // @[Mux.scala 27:73]
+ wire readys_6 = readys_readys[6]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_6 = readys_6 & auto_out_6_d_valid; // @[Arbiter.scala 97:79]
+ reg state_6; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_6 = idle ? earlyWinner_6 : state_6; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_154 = muxStateEarly_6 ? auto_out_6_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_162 = _T_161 | _T_154; // @[Mux.scala 27:73]
+ wire readys_7 = readys_readys[7]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_7 = readys_7 & auto_out_7_d_valid; // @[Arbiter.scala 97:79]
+ reg state_7; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_7 = idle ? earlyWinner_7 : state_7; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_155 = muxStateEarly_7 ? auto_out_7_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_163 = _T_162 | _T_155; // @[Mux.scala 27:73]
+ wire readys_8 = readys_readys[8]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_8 = readys_8 & auto_out_8_d_valid; // @[Arbiter.scala 97:79]
+ reg state_8; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_8 = idle ? earlyWinner_8 : state_8; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_156 = muxStateEarly_8 ? auto_out_8_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [29:0] _requestAIO_T = auto_in_a_bits_address ^ 30'h4000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_1 = {1'b0,$signed(_requestAIO_T)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_3 = $signed(_requestAIO_T_1) & 31'sh30037000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_0 = $signed(_requestAIO_T_3) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _requestAIO_T_5 = auto_in_a_bits_address ^ 30'h20000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_6 = {1'b0,$signed(_requestAIO_T_5)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_8 = $signed(_requestAIO_T_6) & 31'sh30030000; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_9 = $signed(_requestAIO_T_8) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _requestAIO_T_10 = auto_in_a_bits_address ^ 30'h10000000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_11 = {1'b0,$signed(_requestAIO_T_10)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_13 = $signed(_requestAIO_T_11) & 31'sh30037000; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_14 = $signed(_requestAIO_T_13) == 31'sh0; // @[Parameters.scala 137:67]
+ wire requestAIO_0_1 = _requestAIO_T_9 | _requestAIO_T_14; // @[Xbar.scala 363:92]
+ wire [29:0] _requestAIO_T_16 = auto_in_a_bits_address ^ 30'h10010000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_17 = {1'b0,$signed(_requestAIO_T_16)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_19 = $signed(_requestAIO_T_17) & 31'sh30037000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_2 = $signed(_requestAIO_T_19) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _requestAIO_T_21 = auto_in_a_bits_address ^ 30'h10011000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_22 = {1'b0,$signed(_requestAIO_T_21)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_24 = $signed(_requestAIO_T_22) & 31'sh30037000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_3 = $signed(_requestAIO_T_24) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _requestAIO_T_26 = auto_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_27 = {1'b0,$signed(_requestAIO_T_26)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_29 = $signed(_requestAIO_T_27) & 31'sh30037000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_4 = $signed(_requestAIO_T_29) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _requestAIO_T_31 = auto_in_a_bits_address ^ 30'h10013000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_32 = {1'b0,$signed(_requestAIO_T_31)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_34 = $signed(_requestAIO_T_32) & 31'sh30037000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_5 = $signed(_requestAIO_T_34) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _requestAIO_T_36 = auto_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_37 = {1'b0,$signed(_requestAIO_T_36)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_39 = $signed(_requestAIO_T_37) & 31'sh30000000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_6 = $signed(_requestAIO_T_39) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _requestAIO_T_41 = auto_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_42 = {1'b0,$signed(_requestAIO_T_41)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_44 = $signed(_requestAIO_T_42) & 31'sh30037000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_7 = $signed(_requestAIO_T_44) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _requestAIO_T_46 = auto_in_a_bits_address ^ 30'h30000000; // @[Parameters.scala 137:31]
+ wire [30:0] _requestAIO_T_47 = {1'b0,$signed(_requestAIO_T_46)}; // @[Parameters.scala 137:49]
+ wire [30:0] _requestAIO_T_49 = $signed(_requestAIO_T_47) & 31'sh30000000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_8 = $signed(_requestAIO_T_49) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [12:0] _beatsDO_decode_T_1 = 13'h3f << auto_out_0_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_3 = ~_beatsDO_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode = _beatsDO_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala 220:14]
+ wire [12:0] _beatsDO_decode_T_5 = 13'h3f << auto_out_1_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_7 = ~_beatsDO_decode_T_5[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_7[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_1 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala 220:14]
+ wire [12:0] _beatsDO_decode_T_9 = 13'h3f << auto_out_2_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_11 = ~_beatsDO_decode_T_9[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_2 = _beatsDO_decode_T_11[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_2 = auto_out_2_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_2 = beatsDO_opdata_2 ? beatsDO_decode_2 : 3'h0; // @[Edges.scala 220:14]
+ wire [12:0] _beatsDO_decode_T_13 = 13'h3f << auto_out_3_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_15 = ~_beatsDO_decode_T_13[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_3 = _beatsDO_decode_T_15[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_3 = auto_out_3_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_3 = beatsDO_opdata_3 ? beatsDO_decode_3 : 3'h0; // @[Edges.scala 220:14]
+ wire [12:0] _beatsDO_decode_T_17 = 13'h3f << auto_out_4_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_19 = ~_beatsDO_decode_T_17[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_4 = _beatsDO_decode_T_19[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_4 = auto_out_4_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_4 = beatsDO_opdata_4 ? beatsDO_decode_4 : 3'h0; // @[Edges.scala 220:14]
+ wire [12:0] _beatsDO_decode_T_21 = 13'h3f << auto_out_5_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_23 = ~_beatsDO_decode_T_21[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_5 = _beatsDO_decode_T_23[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_5 = auto_out_5_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_5 = beatsDO_opdata_5 ? beatsDO_decode_5 : 3'h0; // @[Edges.scala 220:14]
+ wire [12:0] _beatsDO_decode_T_25 = 13'h3f << auto_out_6_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_27 = ~_beatsDO_decode_T_25[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_6 = _beatsDO_decode_T_27[5:3]; // @[Edges.scala 219:59]
+ wire [12:0] _beatsDO_decode_T_29 = 13'h3f << auto_out_7_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_31 = ~_beatsDO_decode_T_29[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_7 = _beatsDO_decode_T_31[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_7 = auto_out_7_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_7 = beatsDO_opdata_7 ? beatsDO_decode_7 : 3'h0; // @[Edges.scala 220:14]
+ wire [12:0] _beatsDO_decode_T_33 = 13'h3f << auto_out_8_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_35 = ~_beatsDO_decode_T_33[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_8 = _beatsDO_decode_T_35[5:3]; // @[Edges.scala 219:59]
+ wire latch = idle & auto_in_d_ready; // @[Arbiter.scala 89:24]
+ wire _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
+ wire [8:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
+ wire [9:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
+ wire [8:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[8:0]; // @[package.scala 244:43]
+ wire [10:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala 244:48]
+ wire [8:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_4[8:0]; // @[package.scala 244:43]
+ wire [12:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala 244:48]
+ wire [8:0] _readys_mask_T_9 = _readys_mask_T_6 | _readys_mask_T_7[8:0]; // @[package.scala 244:43]
+ wire [16:0] _readys_mask_T_10 = {_readys_mask_T_9, 8'h0}; // @[package.scala 244:48]
+ wire [8:0] _readys_mask_T_12 = _readys_mask_T_9 | _readys_mask_T_10[8:0]; // @[package.scala 244:43]
+ wire prefixOR_2 = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
+ wire prefixOR_3 = prefixOR_2 | earlyWinner_2; // @[Arbiter.scala 104:53]
+ wire prefixOR_4 = prefixOR_3 | earlyWinner_3; // @[Arbiter.scala 104:53]
+ wire prefixOR_5 = prefixOR_4 | earlyWinner_4; // @[Arbiter.scala 104:53]
+ wire prefixOR_6 = prefixOR_5 | earlyWinner_5; // @[Arbiter.scala 104:53]
+ wire prefixOR_7 = prefixOR_6 | earlyWinner_6; // @[Arbiter.scala 104:53]
+ wire prefixOR_8 = prefixOR_7 | earlyWinner_7; // @[Arbiter.scala 104:53]
+ wire _prefixOR_T = prefixOR_8 | earlyWinner_8; // @[Arbiter.scala 104:53]
+ wire _T_26 = ~prefixOR_8 | ~earlyWinner_8; // @[Arbiter.scala 105:64]
+ wire _T_45 = auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
+ | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid; // @[Arbiter.scala 107:36]
+ wire _T_46 = ~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
+ | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid); // @[Arbiter.scala 107:15]
+ wire [2:0] maskedBeats_0 = earlyWinner_0 ? beatsDO_0 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_1 = earlyWinner_1 ? beatsDO_1 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_2 = earlyWinner_2 ? beatsDO_2 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_3 = earlyWinner_3 ? beatsDO_3 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_4 = earlyWinner_4 ? beatsDO_4 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_5 = earlyWinner_5 ? beatsDO_5 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_6 = earlyWinner_6 ? beatsDO_decode_6 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_7 = earlyWinner_7 ? beatsDO_7 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_8 = earlyWinner_8 ? beatsDO_decode_8 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] _initBeats_T = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala 112:44]
+ wire [2:0] _initBeats_T_1 = _initBeats_T | maskedBeats_2; // @[Arbiter.scala 112:44]
+ wire [2:0] _initBeats_T_2 = _initBeats_T_1 | maskedBeats_3; // @[Arbiter.scala 112:44]
+ wire [2:0] _initBeats_T_3 = _initBeats_T_2 | maskedBeats_4; // @[Arbiter.scala 112:44]
+ wire [2:0] _initBeats_T_4 = _initBeats_T_3 | maskedBeats_5; // @[Arbiter.scala 112:44]
+ wire [2:0] _initBeats_T_5 = _initBeats_T_4 | maskedBeats_6; // @[Arbiter.scala 112:44]
+ wire [2:0] _initBeats_T_6 = _initBeats_T_5 | maskedBeats_7; // @[Arbiter.scala 112:44]
+ wire [2:0] initBeats = _initBeats_T_6 | maskedBeats_8; // @[Arbiter.scala 112:44]
+ wire _sink_ACancel_earlyValid_T_24 = state_0 & auto_out_0_d_valid | state_1 & auto_out_1_d_valid | state_2 &
+ auto_out_2_d_valid | state_3 & auto_out_3_d_valid | state_4 & auto_out_4_d_valid | state_5 & auto_out_5_d_valid |
+ state_6 & auto_out_6_d_valid | state_7 & auto_out_7_d_valid | state_8 & auto_out_8_d_valid; // @[Mux.scala 27:73]
+ wire sink_ACancel_19_earlyValid = idle ? _T_45 : _sink_ACancel_earlyValid_T_24; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_19_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ wire [2:0] _GEN_6 = {{2'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
+ wire [2:0] _beatsLeft_T_4 = beatsLeft - _GEN_6; // @[Arbiter.scala 113:52]
+ wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
+ wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala 121:24]
+ wire allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala 121:24]
+ wire allowed_4 = idle ? readys_4 : state_4; // @[Arbiter.scala 121:24]
+ wire allowed_5 = idle ? readys_5 : state_5; // @[Arbiter.scala 121:24]
+ wire allowed_6 = idle ? readys_6 : state_6; // @[Arbiter.scala 121:24]
+ wire allowed_7 = idle ? readys_7 : state_7; // @[Arbiter.scala 121:24]
+ wire allowed_8 = idle ? readys_8 : state_8; // @[Arbiter.scala 121:24]
+ wire [63:0] _T_97 = muxStateEarly_0 ? auto_out_0_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_98 = muxStateEarly_1 ? auto_out_1_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_99 = muxStateEarly_2 ? auto_out_2_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_100 = muxStateEarly_3 ? auto_out_3_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_101 = muxStateEarly_4 ? auto_out_4_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_102 = muxStateEarly_5 ? auto_out_5_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_103 = muxStateEarly_6 ? auto_out_6_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_104 = muxStateEarly_7 ? auto_out_7_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_105 = muxStateEarly_8 ? auto_out_8_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_106 = _T_97 | _T_98; // @[Mux.scala 27:73]
+ wire [63:0] _T_107 = _T_106 | _T_99; // @[Mux.scala 27:73]
+ wire [63:0] _T_108 = _T_107 | _T_100; // @[Mux.scala 27:73]
+ wire [63:0] _T_109 = _T_108 | _T_101; // @[Mux.scala 27:73]
+ wire [63:0] _T_110 = _T_109 | _T_102; // @[Mux.scala 27:73]
+ wire [63:0] _T_111 = _T_110 | _T_103; // @[Mux.scala 27:73]
+ wire [63:0] _T_112 = _T_111 | _T_104; // @[Mux.scala 27:73]
+ wire [2:0] _T_165 = muxStateEarly_0 ? auto_out_0_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_166 = muxStateEarly_1 ? auto_out_1_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_167 = muxStateEarly_2 ? auto_out_2_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_168 = muxStateEarly_3 ? auto_out_3_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_169 = muxStateEarly_4 ? auto_out_4_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_170 = muxStateEarly_5 ? auto_out_5_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_171 = muxStateEarly_6 ? auto_out_6_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_172 = muxStateEarly_7 ? auto_out_7_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_173 = muxStateEarly_8 ? auto_out_8_d_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_174 = _T_165 | _T_166; // @[Mux.scala 27:73]
+ wire [2:0] _T_175 = _T_174 | _T_167; // @[Mux.scala 27:73]
+ wire [2:0] _T_176 = _T_175 | _T_168; // @[Mux.scala 27:73]
+ wire [2:0] _T_177 = _T_176 | _T_169; // @[Mux.scala 27:73]
+ wire [2:0] _T_178 = _T_177 | _T_170; // @[Mux.scala 27:73]
+ wire [2:0] _T_179 = _T_178 | _T_171; // @[Mux.scala 27:73]
+ wire [2:0] _T_180 = _T_179 | _T_172; // @[Mux.scala 27:73]
+ wire [2:0] _T_199 = muxStateEarly_0 ? auto_out_0_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_200 = muxStateEarly_1 ? auto_out_1_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_201 = muxStateEarly_2 ? auto_out_2_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_202 = muxStateEarly_3 ? auto_out_3_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_203 = muxStateEarly_4 ? auto_out_4_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_204 = muxStateEarly_5 ? auto_out_5_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_205 = muxStateEarly_6 ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_206 = muxStateEarly_7 ? auto_out_7_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_207 = muxStateEarly_8 ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_208 = _T_199 | _T_200; // @[Mux.scala 27:73]
+ wire [2:0] _T_209 = _T_208 | _T_201; // @[Mux.scala 27:73]
+ wire [2:0] _T_210 = _T_209 | _T_202; // @[Mux.scala 27:73]
+ wire [2:0] _T_211 = _T_210 | _T_203; // @[Mux.scala 27:73]
+ wire [2:0] _T_212 = _T_211 | _T_204; // @[Mux.scala 27:73]
+ wire [2:0] _T_213 = _T_212 | _T_205; // @[Mux.scala 27:73]
+ wire [2:0] _T_214 = _T_213 | _T_206; // @[Mux.scala 27:73]
+ TLMonitor_5 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready | requestAIO_0_2 &
+ auto_out_2_a_ready | requestAIO_0_3 & auto_out_3_a_ready | requestAIO_0_4 & auto_out_4_a_ready | requestAIO_0_5 &
+ auto_out_5_a_ready | requestAIO_0_6 & auto_out_6_a_ready | requestAIO_0_7 & auto_out_7_a_ready | requestAIO_0_8 &
+ auto_out_8_a_ready; // @[Mux.scala 27:73]
+ assign auto_in_d_valid = idle ? _T_45 : _sink_ACancel_earlyValid_T_24; // @[Arbiter.scala 125:29]
+ assign auto_in_d_bits_opcode = _T_214 | _T_207; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_param = muxStateEarly_1 ? auto_out_1_d_bits_param : 2'h0; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_size = _T_180 | _T_173; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_source = _T_163 | _T_156; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_sink = muxStateEarly_1 & auto_out_1_d_bits_sink; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_denied = muxStateEarly_1 & auto_out_1_d_bits_denied; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_data = _T_112 | _T_105; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_corrupt = muxStateEarly_1 & auto_out_1_d_bits_corrupt; // @[Mux.scala 27:73]
+ assign auto_out_8_a_valid = auto_in_a_valid & requestAIO_0_8; // @[Xbar.scala 428:50]
+ assign auto_out_8_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_8_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_d_ready = auto_in_d_ready & allowed_8; // @[Arbiter.scala 123:31]
+ assign auto_out_7_a_valid = auto_in_a_valid & requestAIO_0_7; // @[Xbar.scala 428:50]
+ assign auto_out_7_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_7_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_7_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_d_ready = auto_in_d_ready & allowed_7; // @[Arbiter.scala 123:31]
+ assign auto_out_6_a_valid = auto_in_a_valid & requestAIO_0_6; // @[Xbar.scala 428:50]
+ assign auto_out_6_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_6_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_d_ready = auto_in_d_ready & allowed_6; // @[Arbiter.scala 123:31]
+ assign auto_out_5_a_valid = auto_in_a_valid & requestAIO_0_5; // @[Xbar.scala 428:50]
+ assign auto_out_5_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_5_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_5_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_d_ready = auto_in_d_ready & allowed_5; // @[Arbiter.scala 123:31]
+ assign auto_out_4_a_valid = auto_in_a_valid & requestAIO_0_4; // @[Xbar.scala 428:50]
+ assign auto_out_4_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_4_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_4_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_d_ready = auto_in_d_ready & allowed_4; // @[Arbiter.scala 123:31]
+ assign auto_out_3_a_valid = auto_in_a_valid & requestAIO_0_3; // @[Xbar.scala 428:50]
+ assign auto_out_3_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_3_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_3_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_d_ready = auto_in_d_ready & allowed_3; // @[Arbiter.scala 123:31]
+ assign auto_out_2_a_valid = auto_in_a_valid & requestAIO_0_2; // @[Xbar.scala 428:50]
+ assign auto_out_2_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_2_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_2_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_d_ready = auto_in_d_ready & allowed_2; // @[Arbiter.scala 123:31]
+ assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[Xbar.scala 428:50]
+ assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_1_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_d_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[Xbar.scala 428:50]
+ assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_0_a_bits_address = auto_in_a_bits_address[14:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_d_ready = auto_in_d_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready |
+ requestAIO_0_2 & auto_out_2_a_ready | requestAIO_0_3 & auto_out_3_a_ready | requestAIO_0_4 & auto_out_4_a_ready |
+ requestAIO_0_5 & auto_out_5_a_ready | requestAIO_0_6 & auto_out_6_a_ready | requestAIO_0_7 & auto_out_7_a_ready |
+ requestAIO_0_8 & auto_out_8_a_ready; // @[Mux.scala 27:73]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = idle ? _T_45 : _sink_ACancel_earlyValid_T_24; // @[Arbiter.scala 125:29]
+ assign monitor_io_in_d_bits_opcode = _T_214 | _T_207; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_param = muxStateEarly_1 ? auto_out_1_d_bits_param : 2'h0; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_size = _T_180 | _T_173; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_source = _T_163 | _T_156; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_sink = muxStateEarly_1 & auto_out_1_d_bits_sink; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_denied = muxStateEarly_1 & auto_out_1_d_bits_denied; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_corrupt = muxStateEarly_1 & auto_out_1_d_bits_corrupt; // @[Mux.scala 27:73]
+ always @(posedge clock) begin
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 3'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ beatsLeft <= initBeats;
+ end else begin
+ beatsLeft <= _beatsLeft_T_4;
+ end
+ if (reset) begin // @[Arbiter.scala 23:23]
+ readys_mask <= 9'h1ff; // @[Arbiter.scala 23:23]
+ end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
+ readys_mask <= _readys_mask_T_12; // @[Arbiter.scala 28:12]
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_0 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_0 <= earlyWinner_0;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_2 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_2 <= earlyWinner_2;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_3 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_3 <= earlyWinner_3;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_4 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_4 <= earlyWinner_4;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_5 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_5 <= earlyWinner_5;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_6 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_6 <= earlyWinner_6;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_7 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_7 <= earlyWinner_7;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_8 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_8 <= earlyWinner_8;
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~earlyWinner_3) & (~
+ prefixOR_4 | ~earlyWinner_4) & (~prefixOR_5 | ~earlyWinner_5) & (~prefixOR_6 | ~earlyWinner_6) & (~prefixOR_7
+ | ~earlyWinner_7) & _T_26) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 105:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~
+ earlyWinner_3) & (~prefixOR_4 | ~earlyWinner_4) & (~prefixOR_5 | ~earlyWinner_5) & (~prefixOR_6 | ~
+ earlyWinner_6) & (~prefixOR_7 | ~earlyWinner_7) & _T_26)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
+ ); // @[Arbiter.scala 105:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
+ | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid) | _prefixOR_T) &
+ _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid |
+ auto_out_4_d_valid | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid) |
+ _prefixOR_T)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_46 | _T_45) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(_T_46 | _T_45)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ beatsLeft = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ readys_mask = _RAND_1[8:0];
+ _RAND_2 = {1{`RANDOM}};
+ state_0 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ state_1 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ state_2 = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ state_3 = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ state_4 = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ state_5 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ state_6 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ state_7 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ state_8 = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_6(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h4000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_61 = io_in_a_bits_address ^ 30'h20000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_64 = $signed(_T_62) & -31'sh10000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_66 = io_in_a_bits_address ^ 30'h10000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_69 = $signed(_T_67) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_71 = io_in_a_bits_address ^ 30'h10010000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_74 = $signed(_T_72) & -31'sh4000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_76 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_79 = $signed(_T_77) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_81 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_84 = $signed(_T_82) & -31'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_90 = _T_60 | _T_65 | _T_70 | _T_75 | _T_80 | _T_85; // @[Parameters.scala 671:42]
+ wire _T_152 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_156 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_157 = _T_156 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_161 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_165 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_279 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_292 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_309 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_347 = _T_309 & _T_90; // @[Parameters.scala 670:56]
+ wire _T_358 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_362 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_370 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_409 = _T_60 | _T_70 | _T_75 | _T_80; // @[Parameters.scala 671:42]
+ wire _T_410 = _T_309 & _T_409; // @[Parameters.scala 670:56]
+ wire _T_426 = source_ok & _T_410; // @[Monitor.scala 115:71]
+ wire _T_444 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_514 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_515 = io_in_a_bits_mask & _T_514; // @[Monitor.scala 127:31]
+ wire _T_516 = _T_515 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_520 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_581 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_589 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_650 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_658 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_719 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_731 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_735 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_739 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_743 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_747 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_751 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_755 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_766 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_770 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_783 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_803 = _T_751 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_812 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_829 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_847 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_877 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_878 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_882 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_886 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_890 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_894 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_901 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_902 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_906 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_910 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_914 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_918 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_922 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_928 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_931 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_933 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_935 = ~_T_933[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_939 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_941 = ~_T_735; // @[Monitor.scala 671:74]
+ wire _T_942 = io_in_d_valid & d_first_1 & ~_T_735; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_735 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_941 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_941 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_928 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_952 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_954 = _T_952[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_959 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_960 = io_in_d_bits_opcode == _GEN_32 | _T_959; // @[Monitor.scala 685:77]
+ wire _T_964 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_971 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_972 = io_in_d_bits_opcode == _GEN_48 | _T_971; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_976 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_986 = _T_939 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_941; // @[Monitor.scala 694:116]
+ wire _T_988 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_995 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1004 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_1030 = io_in_d_valid & d_first_2 & _T_735; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_735 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_735 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_1038 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_1048 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1073 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_279 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_516 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_516) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_581 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_581) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_589 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_719 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_719) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_658 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_658 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_731 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_731) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_735 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_766 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_766) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_770 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_770) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_755 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_755 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_766 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_766) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_770 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_770) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_803 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_803) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_783 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_812 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_812 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_803 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_803) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_829 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_829 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_743) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_747 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_747) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_751 & (io_in_d_valid & _T_847 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_847 & _T_2 & ~_T_751) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_878 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_878) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_882 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_882) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_886 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_886) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_894 & (_T_877 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_877 & ~reset & ~_T_894) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_902 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_902) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_906 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_906) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_910 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_910) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_914 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_914) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_918 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_918) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_922 & (_T_901 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_901 & _T_2 & ~_T_922) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_935 & (_T_931 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_931 & ~reset & ~_T_935) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_954 & (_T_942 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & _T_2 & ~_T_954) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_960 & (_T_942 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & same_cycle_resp & _T_2 & ~_T_960) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_964 & (_T_942 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & same_cycle_resp & _T_2 & ~_T_964) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_972 & (_T_942 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & ~same_cycle_resp & _T_2 & ~_T_972) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_976 & (_T_942 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_942 & ~same_cycle_resp & _T_2 & ~_T_976) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_988 & (_T_986 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_986 & _T_2 & ~_T_988) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_995 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_995) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1004 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1004) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1038[0] & (_T_1030 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1030 & _T_2 & ~_T_1038[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1048 & (_T_1030 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1030 & _T_2 & ~_T_1048) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1073 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1073) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [29:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [29:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [29:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [29:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [29:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_address_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_address_io_deq_bits_MPORT_addr = value_1;
+ assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_address_MPORT_data = io_enq_bits_address;
+ assign ram_address_MPORT_addr = value;
+ assign ram_address_MPORT_mask = 1'h1;
+ assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = value_1;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = value;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
+ ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_address[initvar] = _RAND_4[29:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_5[7:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_1(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [1:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input io_enq_bits_sink,
+ input io_enq_bits_denied,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [1:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output io_deq_bits_sink,
+ output io_deq_bits_denied,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [1:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_sink [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_denied [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_sink_io_deq_bits_MPORT_addr = value_1;
+ assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_sink_MPORT_data = io_enq_bits_sink;
+ assign ram_sink_MPORT_addr = value;
+ assign ram_sink_MPORT_mask = 1'h1;
+ assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_denied_io_deq_bits_MPORT_addr = value_1;
+ assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_denied_MPORT_data = io_enq_bits_denied;
+ assign ram_denied_MPORT_addr = value;
+ assign ram_denied_MPORT_mask = 1'h1;
+ assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
+ ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
+ ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_sink[initvar] = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_denied[initvar] = _RAND_5[0:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_1(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [29:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [29:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_6 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_1 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_7(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h4000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_61 = io_in_a_bits_address ^ 30'h20000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_64 = $signed(_T_62) & -31'sh10000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_66 = io_in_a_bits_address ^ 30'h10000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_69 = $signed(_T_67) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_71 = io_in_a_bits_address ^ 30'h10010000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_74 = $signed(_T_72) & -31'sh4000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_76 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_79 = $signed(_T_77) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_81 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_84 = $signed(_T_82) & -31'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_90 = _T_60 | _T_65 | _T_70 | _T_75 | _T_80 | _T_85; // @[Parameters.scala 671:42]
+ wire _T_152 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_156 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_157 = _T_156 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_161 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_165 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_279 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_292 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_309 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_347 = _T_309 & _T_90; // @[Parameters.scala 670:56]
+ wire _T_358 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_362 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_370 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_409 = _T_60 | _T_70 | _T_75 | _T_80; // @[Parameters.scala 671:42]
+ wire _T_410 = _T_309 & _T_409; // @[Parameters.scala 670:56]
+ wire _T_426 = source_ok & _T_410; // @[Monitor.scala 115:71]
+ wire _T_444 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_514 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_515 = io_in_a_bits_mask & _T_514; // @[Monitor.scala 127:31]
+ wire _T_516 = _T_515 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_520 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_534 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
+ wire _T_560 = _T_534 & _T_409; // @[Parameters.scala 670:56]
+ wire _T_576 = source_ok & _T_560; // @[Monitor.scala 131:74]
+ wire _T_586 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_594 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_660 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_668 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_729 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_741 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_745 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_749 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_753 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_757 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_761 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_765 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_776 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_780 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_793 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_813 = _T_761 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_822 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_839 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_857 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_887 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_888 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_892 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_896 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_900 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_904 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_911 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_912 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_916 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_920 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_924 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_928 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_932 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_938 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_941 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_943 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_945 = ~_T_943[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_949 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_951 = ~_T_745; // @[Monitor.scala 671:74]
+ wire _T_952 = io_in_d_valid & d_first_1 & ~_T_745; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_745 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_951 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_951 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_938 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_962 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_964 = _T_962[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_969 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_970 = io_in_d_bits_opcode == _GEN_32 | _T_969; // @[Monitor.scala 685:77]
+ wire _T_974 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_981 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_982 = io_in_d_bits_opcode == _GEN_48 | _T_981; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_986 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_996 = _T_949 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_951; // @[Monitor.scala 694:116]
+ wire _T_998 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_1005 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1014 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_1040 = io_in_d_valid & d_first_2 & _T_745; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_745 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_745 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_1048 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_1058 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1083 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_279 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_516 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_516) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_729 & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~_T_729) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_741 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_741) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_749 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~_T_749) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_749 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_749) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_776 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_776) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_780 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_780) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_749 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_749) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_776 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_776) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_780 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_780) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_813 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_813) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_822 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_822 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (io_in_d_valid & _T_822 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_822 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & (io_in_d_valid & _T_822 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_822 & _T_2 & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_822 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_822 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_839 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_839 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (io_in_d_valid & _T_839 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_839 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_813 & (io_in_d_valid & _T_839 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_839 & _T_2 & ~_T_813) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_839 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_839 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_857 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_857 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (io_in_d_valid & _T_857 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_857 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & (io_in_d_valid & _T_857 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_857 & _T_2 & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_857 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_857 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_888 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_888) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_892 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_892) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_896 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_896) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_900 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_900) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_904 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_904) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_912 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_912) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_916 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_916) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_920 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_920) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_924 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_924) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_928 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_928) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_932 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_932) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_945 & (_T_941 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_941 & ~reset & ~_T_945) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_964 & (_T_952 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & _T_2 & ~_T_964) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_970 & (_T_952 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & same_cycle_resp & _T_2 & ~_T_970) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_974 & (_T_952 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & same_cycle_resp & _T_2 & ~_T_974) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_982 & (_T_952 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & ~same_cycle_resp & _T_2 & ~_T_982) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_986 & (_T_952 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & ~same_cycle_resp & _T_2 & ~_T_986) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_998 & (_T_996 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_996 & _T_2 & ~_T_998) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1005 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1005) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1014 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1014) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1048[0] & (_T_1040 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1040 & _T_2 & ~_T_1048[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (_T_1040 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1040 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLAtomicAutomata(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [63:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [63:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala 76:28]
+ reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala 77:24]
+ reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala 77:24]
+ reg [2:0] cam_a_0_bits_size; // @[AtomicAutomata.scala 77:24]
+ reg [2:0] cam_a_0_bits_source; // @[AtomicAutomata.scala 77:24]
+ reg [29:0] cam_a_0_bits_address; // @[AtomicAutomata.scala 77:24]
+ reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala 77:24]
+ reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala 77:24]
+ reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala 77:24]
+ reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala 77:24]
+ reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala 78:24]
+ reg cam_d_0_denied; // @[AtomicAutomata.scala 78:24]
+ reg cam_d_0_corrupt; // @[AtomicAutomata.scala 78:24]
+ wire cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala 80:44]
+ wire cam_amo_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala 81:44]
+ wire cam_abusy_0 = cam_s_0_state == 2'h3 | cam_amo_0; // @[AtomicAutomata.scala 82:57]
+ wire cam_dmatch_0 = cam_s_0_state != 2'h0; // @[AtomicAutomata.scala 83:49]
+ wire a_isLogical = auto_in_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala 90:47]
+ wire a_isArithmetic = auto_in_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala 91:47]
+ wire _a_isSupported_T = a_isArithmetic ? 1'h0 : 1'h1; // @[AtomicAutomata.scala 92:63]
+ wire a_isSupported = a_isLogical ? 1'h0 : _a_isSupported_T; // @[AtomicAutomata.scala 92:32]
+ wire [1:0] indexes_0 = {cam_a_0_bits_data[0],cam_d_0_data[0]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_1 = {cam_a_0_bits_data[1],cam_d_0_data[1]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_2 = {cam_a_0_bits_data[2],cam_d_0_data[2]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_3 = {cam_a_0_bits_data[3],cam_d_0_data[3]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_4 = {cam_a_0_bits_data[4],cam_d_0_data[4]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_5 = {cam_a_0_bits_data[5],cam_d_0_data[5]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_6 = {cam_a_0_bits_data[6],cam_d_0_data[6]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_7 = {cam_a_0_bits_data[7],cam_d_0_data[7]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_8 = {cam_a_0_bits_data[8],cam_d_0_data[8]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_9 = {cam_a_0_bits_data[9],cam_d_0_data[9]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_10 = {cam_a_0_bits_data[10],cam_d_0_data[10]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_11 = {cam_a_0_bits_data[11],cam_d_0_data[11]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_12 = {cam_a_0_bits_data[12],cam_d_0_data[12]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_13 = {cam_a_0_bits_data[13],cam_d_0_data[13]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_14 = {cam_a_0_bits_data[14],cam_d_0_data[14]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_15 = {cam_a_0_bits_data[15],cam_d_0_data[15]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_16 = {cam_a_0_bits_data[16],cam_d_0_data[16]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_17 = {cam_a_0_bits_data[17],cam_d_0_data[17]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_18 = {cam_a_0_bits_data[18],cam_d_0_data[18]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_19 = {cam_a_0_bits_data[19],cam_d_0_data[19]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_20 = {cam_a_0_bits_data[20],cam_d_0_data[20]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_21 = {cam_a_0_bits_data[21],cam_d_0_data[21]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_22 = {cam_a_0_bits_data[22],cam_d_0_data[22]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_23 = {cam_a_0_bits_data[23],cam_d_0_data[23]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_24 = {cam_a_0_bits_data[24],cam_d_0_data[24]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_25 = {cam_a_0_bits_data[25],cam_d_0_data[25]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_26 = {cam_a_0_bits_data[26],cam_d_0_data[26]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_27 = {cam_a_0_bits_data[27],cam_d_0_data[27]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_28 = {cam_a_0_bits_data[28],cam_d_0_data[28]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_29 = {cam_a_0_bits_data[29],cam_d_0_data[29]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_30 = {cam_a_0_bits_data[30],cam_d_0_data[30]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_31 = {cam_a_0_bits_data[31],cam_d_0_data[31]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_32 = {cam_a_0_bits_data[32],cam_d_0_data[32]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_33 = {cam_a_0_bits_data[33],cam_d_0_data[33]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_34 = {cam_a_0_bits_data[34],cam_d_0_data[34]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_35 = {cam_a_0_bits_data[35],cam_d_0_data[35]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_36 = {cam_a_0_bits_data[36],cam_d_0_data[36]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_37 = {cam_a_0_bits_data[37],cam_d_0_data[37]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_38 = {cam_a_0_bits_data[38],cam_d_0_data[38]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_39 = {cam_a_0_bits_data[39],cam_d_0_data[39]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_40 = {cam_a_0_bits_data[40],cam_d_0_data[40]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_41 = {cam_a_0_bits_data[41],cam_d_0_data[41]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_42 = {cam_a_0_bits_data[42],cam_d_0_data[42]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_43 = {cam_a_0_bits_data[43],cam_d_0_data[43]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_44 = {cam_a_0_bits_data[44],cam_d_0_data[44]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_45 = {cam_a_0_bits_data[45],cam_d_0_data[45]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_46 = {cam_a_0_bits_data[46],cam_d_0_data[46]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_47 = {cam_a_0_bits_data[47],cam_d_0_data[47]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_48 = {cam_a_0_bits_data[48],cam_d_0_data[48]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_49 = {cam_a_0_bits_data[49],cam_d_0_data[49]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_50 = {cam_a_0_bits_data[50],cam_d_0_data[50]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_51 = {cam_a_0_bits_data[51],cam_d_0_data[51]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_52 = {cam_a_0_bits_data[52],cam_d_0_data[52]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_53 = {cam_a_0_bits_data[53],cam_d_0_data[53]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_54 = {cam_a_0_bits_data[54],cam_d_0_data[54]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_55 = {cam_a_0_bits_data[55],cam_d_0_data[55]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_56 = {cam_a_0_bits_data[56],cam_d_0_data[56]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_57 = {cam_a_0_bits_data[57],cam_d_0_data[57]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_58 = {cam_a_0_bits_data[58],cam_d_0_data[58]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_59 = {cam_a_0_bits_data[59],cam_d_0_data[59]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_60 = {cam_a_0_bits_data[60],cam_d_0_data[60]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_61 = {cam_a_0_bits_data[61],cam_d_0_data[61]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_62 = {cam_a_0_bits_data[62],cam_d_0_data[62]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_63 = {cam_a_0_bits_data[63],cam_d_0_data[63]}; // @[Cat.scala 31:58]
+ wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala 114:57]
+ wire [7:0] logic_out_lo_lo_lo = {_logic_out_T_14[0],_logic_out_T_12[0],_logic_out_T_10[0],_logic_out_T_8[0],
+ _logic_out_T_6[0],_logic_out_T_4[0],_logic_out_T_2[0],_logic_out_T[0]}; // @[Cat.scala 31:58]
+ wire [15:0] logic_out_lo_lo = {_logic_out_T_30[0],_logic_out_T_28[0],_logic_out_T_26[0],_logic_out_T_24[0],
+ _logic_out_T_22[0],_logic_out_T_20[0],_logic_out_T_18[0],_logic_out_T_16[0],logic_out_lo_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] logic_out_lo_hi_lo = {_logic_out_T_46[0],_logic_out_T_44[0],_logic_out_T_42[0],_logic_out_T_40[0],
+ _logic_out_T_38[0],_logic_out_T_36[0],_logic_out_T_34[0],_logic_out_T_32[0]}; // @[Cat.scala 31:58]
+ wire [31:0] logic_out_lo = {_logic_out_T_62[0],_logic_out_T_60[0],_logic_out_T_58[0],_logic_out_T_56[0],
+ _logic_out_T_54[0],_logic_out_T_52[0],_logic_out_T_50[0],_logic_out_T_48[0],logic_out_lo_hi_lo,logic_out_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] logic_out_hi_lo_lo = {_logic_out_T_78[0],_logic_out_T_76[0],_logic_out_T_74[0],_logic_out_T_72[0],
+ _logic_out_T_70[0],_logic_out_T_68[0],_logic_out_T_66[0],_logic_out_T_64[0]}; // @[Cat.scala 31:58]
+ wire [15:0] logic_out_hi_lo = {_logic_out_T_94[0],_logic_out_T_92[0],_logic_out_T_90[0],_logic_out_T_88[0],
+ _logic_out_T_86[0],_logic_out_T_84[0],_logic_out_T_82[0],_logic_out_T_80[0],logic_out_hi_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] logic_out_hi_hi_lo = {_logic_out_T_110[0],_logic_out_T_108[0],_logic_out_T_106[0],_logic_out_T_104[0],
+ _logic_out_T_102[0],_logic_out_T_100[0],_logic_out_T_98[0],_logic_out_T_96[0]}; // @[Cat.scala 31:58]
+ wire [31:0] logic_out_hi = {_logic_out_T_126[0],_logic_out_T_124[0],_logic_out_T_122[0],_logic_out_T_120[0],
+ _logic_out_T_118[0],_logic_out_T_116[0],_logic_out_T_114[0],_logic_out_T_112[0],logic_out_hi_hi_lo,logic_out_hi_lo}; // @[Cat.scala 31:58]
+ wire [63:0] logic_out = {logic_out_hi,logic_out_lo}; // @[Cat.scala 31:58]
+ wire unsigned_ = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala 117:42]
+ wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala 118:42]
+ wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala 119:39]
+ wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala 121:25]
+ wire [7:0] _GEN_39 = {{1'd0}, cam_a_0_bits_mask[7:1]}; // @[AtomicAutomata.scala 121:31]
+ wire [7:0] _signSel_T_2 = _signSel_T | _GEN_39; // @[AtomicAutomata.scala 121:31]
+ wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala 121:23]
+ wire [7:0] signbits_a = {cam_a_0_bits_data[63],cam_a_0_bits_data[55],cam_a_0_bits_data[47],cam_a_0_bits_data[39],
+ cam_a_0_bits_data[31],cam_a_0_bits_data[23],cam_a_0_bits_data[15],cam_a_0_bits_data[7]}; // @[Cat.scala 31:58]
+ wire [7:0] signbits_d = {cam_d_0_data[63],cam_d_0_data[55],cam_d_0_data[47],cam_d_0_data[39],cam_d_0_data[31],
+ cam_d_0_data[23],cam_d_0_data[15],cam_d_0_data[7]}; // @[Cat.scala 31:58]
+ wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala 125:38]
+ wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala 125:49]
+ wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala 125:54]
+ wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala 126:38]
+ wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala 126:49]
+ wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala 126:54]
+ wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T[7:0]; // @[package.scala 244:43]
+ wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_3[7:0]; // @[package.scala 244:43]
+ wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_6[7:0]; // @[package.scala 244:43]
+ wire [7:0] _signext_a_T_19 = _signext_a_T_8[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_21 = _signext_a_T_8[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_23 = _signext_a_T_8[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_25 = _signext_a_T_8[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_27 = _signext_a_T_8[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_29 = _signext_a_T_8[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_31 = _signext_a_T_8[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_33 = _signext_a_T_8[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] signext_a = {_signext_a_T_33,_signext_a_T_31,_signext_a_T_29,_signext_a_T_27,_signext_a_T_25,
+ _signext_a_T_23,_signext_a_T_21,_signext_a_T_19}; // @[Cat.scala 31:58]
+ wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T[7:0]; // @[package.scala 244:43]
+ wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_3[7:0]; // @[package.scala 244:43]
+ wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_6[7:0]; // @[package.scala 244:43]
+ wire [7:0] _signext_d_T_19 = _signext_d_T_8[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_21 = _signext_d_T_8[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_23 = _signext_d_T_8[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_25 = _signext_d_T_8[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_27 = _signext_d_T_8[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_29 = _signext_d_T_8[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_31 = _signext_d_T_8[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_33 = _signext_d_T_8[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] signext_d = {_signext_d_T_33,_signext_d_T_31,_signext_d_T_29,_signext_d_T_27,_signext_d_T_25,
+ _signext_d_T_23,_signext_d_T_21,_signext_d_T_19}; // @[Cat.scala 31:58]
+ wire [7:0] _wide_mask_T_9 = cam_a_0_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_11 = cam_a_0_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_13 = cam_a_0_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_15 = cam_a_0_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_17 = cam_a_0_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_19 = cam_a_0_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_21 = cam_a_0_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_23 = cam_a_0_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] wide_mask = {_wide_mask_T_23,_wide_mask_T_21,_wide_mask_T_19,_wide_mask_T_17,_wide_mask_T_15,
+ _wide_mask_T_13,_wide_mask_T_11,_wide_mask_T_9}; // @[Cat.scala 31:58]
+ wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala 131:28]
+ wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala 131:41]
+ wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala 132:28]
+ wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala 132:41]
+ wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala 133:43]
+ wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala 133:26]
+ wire [63:0] adder_out = a_a_ext + a_d_inv; // @[AtomicAutomata.scala 134:33]
+ wire a_bigger_uneq = unsigned_ == a_a_ext[63]; // @[AtomicAutomata.scala 136:38]
+ wire a_bigger = a_a_ext[63] == a_d_ext[63] ? ~adder_out[63] : a_bigger_uneq; // @[AtomicAutomata.scala 137:27]
+ wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala 138:31]
+ wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala 139:50]
+ wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala 139:28]
+ wire [63:0] amo_data = cam_a_0_bits_opcode[0] ? logic_out : arith_out; // @[AtomicAutomata.scala 145:14]
+ wire a_allow = ~cam_abusy_0 & (a_isSupported | cam_free_0); // @[AtomicAutomata.scala 149:35]
+ reg [2:0] beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle = beatsLeft == 3'h0; // @[Arbiter.scala 88:28]
+ wire source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala 151:38]
+ wire [1:0] _readys_T = {source_i_valid,cam_amo_0}; // @[Cat.scala 31:58]
+ wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala 244:48]
+ wire [1:0] _readys_T_3 = _readys_T | _readys_T_1[1:0]; // @[package.scala 244:43]
+ wire [2:0] _readys_T_5 = {_readys_T_3, 1'h0}; // @[Arbiter.scala 16:78]
+ wire [1:0] _readys_T_7 = ~_readys_T_5[1:0]; // @[Arbiter.scala 16:61]
+ wire readys_1 = _readys_T_7[1]; // @[Arbiter.scala 95:86]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire out_1_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
+ wire _T = ~a_isSupported; // @[AtomicAutomata.scala 153:15]
+ wire [2:0] source_i_bits_opcode = ~a_isSupported ? 3'h4 : auto_in_a_bits_opcode; // @[AtomicAutomata.scala 152:24 153:31 154:32]
+ wire [2:0] source_i_bits_param = ~a_isSupported ? 3'h0 : auto_in_a_bits_param; // @[AtomicAutomata.scala 152:24 153:31 155:32]
+ wire source_c_bits_a_corrupt = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala 166:45]
+ wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = cam_a_0_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] source_c_bits_a_mask_sizeOH = _source_c_bits_a_mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _source_c_bits_a_mask_T = cam_a_0_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire source_c_bits_a_mask_bit = cam_a_0_bits_address[2]; // @[Misc.scala 209:26]
+ wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala 210:20]
+ wire source_c_bits_a_mask_acc = _source_c_bits_a_mask_T | source_c_bits_a_mask_size & source_c_bits_a_mask_nbit; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_acc_1 = _source_c_bits_a_mask_T | source_c_bits_a_mask_size & source_c_bits_a_mask_bit; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_size_1 = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire source_c_bits_a_mask_bit_1 = cam_a_0_bits_address[1]; // @[Misc.scala 209:26]
+ wire source_c_bits_a_mask_nbit_1 = ~source_c_bits_a_mask_bit_1; // @[Misc.scala 210:20]
+ wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_nbit & source_c_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_acc | source_c_bits_a_mask_size_1 & source_c_bits_a_mask_eq_2; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_nbit & source_c_bits_a_mask_bit_1; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_acc | source_c_bits_a_mask_size_1 & source_c_bits_a_mask_eq_3; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_bit & source_c_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_acc_1 | source_c_bits_a_mask_size_1 &
+ source_c_bits_a_mask_eq_4; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_bit & source_c_bits_a_mask_bit_1; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_acc_1 | source_c_bits_a_mask_size_1 &
+ source_c_bits_a_mask_eq_5; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_size_2 = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire source_c_bits_a_mask_bit_2 = cam_a_0_bits_address[0]; // @[Misc.scala 209:26]
+ wire source_c_bits_a_mask_nbit_2 = ~source_c_bits_a_mask_bit_2; // @[Misc.scala 210:20]
+ wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_eq_2 & source_c_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_acc_2 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_6; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_eq_2 & source_c_bits_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_acc_2 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_7; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_8 = source_c_bits_a_mask_eq_3 & source_c_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_8 = source_c_bits_a_mask_acc_3 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_8; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_9 = source_c_bits_a_mask_eq_3 & source_c_bits_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_9 = source_c_bits_a_mask_acc_3 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_9; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_10 = source_c_bits_a_mask_eq_4 & source_c_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_10 = source_c_bits_a_mask_acc_4 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_10; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_11 = source_c_bits_a_mask_eq_4 & source_c_bits_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_11 = source_c_bits_a_mask_acc_4 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_11; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_12 = source_c_bits_a_mask_eq_5 & source_c_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_12 = source_c_bits_a_mask_acc_5 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_12; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_13 = source_c_bits_a_mask_eq_5 & source_c_bits_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_13 = source_c_bits_a_mask_acc_5 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] source_c_bits_a_mask = {source_c_bits_a_mask_acc_13,source_c_bits_a_mask_acc_12,source_c_bits_a_mask_acc_11
+ ,source_c_bits_a_mask_acc_10,source_c_bits_a_mask_acc_9,source_c_bits_a_mask_acc_8,source_c_bits_a_mask_acc_7,
+ source_c_bits_a_mask_acc_6}; // @[Cat.scala 31:58]
+ wire [12:0] _decode_T_1 = 13'h3f << auto_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] _decode_T_3 = ~_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] decode = _decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire opdata = ~auto_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ wire latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
+ wire readys_0 = _readys_T_7[0]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_0 = readys_0 & cam_amo_0; // @[Arbiter.scala 97:79]
+ wire earlyWinner_1 = readys_1 & source_i_valid; // @[Arbiter.scala 97:79]
+ wire _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
+ wire _T_10 = ~reset; // @[Arbiter.scala 105:13]
+ wire _T_12 = cam_amo_0 | source_i_valid; // @[Arbiter.scala 107:36]
+ wire _T_13 = ~(cam_amo_0 | source_i_valid); // @[Arbiter.scala 107:15]
+ reg state_0; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ wire muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire _sink_ACancel_earlyValid_T_3 = state_0 & cam_amo_0 | state_1 & source_i_valid; // @[Mux.scala 27:73]
+ wire sink_ACancel_earlyValid = idle ? _T_12 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_out_a_ready & sink_ACancel_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ wire [2:0] _GEN_40 = {{2'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
+ wire [2:0] _beatsLeft_T_4 = beatsLeft - _GEN_40; // @[Arbiter.scala 113:52]
+ wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
+ wire out_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
+ wire [63:0] _T_29 = muxStateEarly_0 ? amo_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_30 = muxStateEarly_1 ? auto_in_a_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_32 = muxStateEarly_0 ? source_c_bits_a_mask : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_33 = muxStateEarly_1 ? auto_in_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
+ wire [29:0] _T_35 = muxStateEarly_0 ? cam_a_0_bits_address : 30'h0; // @[Mux.scala 27:73]
+ wire [29:0] _T_36 = muxStateEarly_1 ? auto_in_a_bits_address : 30'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_38 = muxStateEarly_0 ? cam_a_0_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_39 = muxStateEarly_1 ? auto_in_a_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_41 = muxStateEarly_0 ? cam_a_0_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_42 = muxStateEarly_1 ? auto_in_a_bits_size : 3'h0; // @[Mux.scala 27:73]
+ wire _T_50 = out_1_ready & source_i_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_41 = {{1'd0}, auto_in_a_bits_param[1:0]}; // @[Mux.scala 81:61]
+ wire [3:0] _cam_a_0_lut_T_2 = 3'h1 == _GEN_41 ? 4'he : 4'h8; // @[Mux.scala 81:58]
+ wire [1:0] _GEN_12 = cam_free_0 ? 2'h3 : cam_s_0_state; // @[AtomicAutomata.scala 187:23 188:23 76:28]
+ wire [1:0] _GEN_23 = _T_50 & _T ? _GEN_12 : cam_s_0_state; // @[AtomicAutomata.scala 174:50 76:28]
+ wire _T_53 = out_ready & cam_amo_0; // @[Decoupled.scala 50:35]
+ wire [1:0] _GEN_24 = cam_amo_0 ? 2'h1 : _GEN_23; // @[AtomicAutomata.scala 196:23 197:23]
+ wire [1:0] _GEN_25 = _T_53 ? _GEN_24 : _GEN_23; // @[AtomicAutomata.scala 194:32]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ wire d_ackd = auto_out_d_bits_opcode == 3'h1; // @[AtomicAutomata.scala 213:40]
+ wire d_cam_sel_raw_0 = cam_a_0_bits_source == auto_out_d_bits_source; // @[AtomicAutomata.scala 204:53]
+ wire d_cam_sel_match_0 = d_cam_sel_raw_0 & cam_dmatch_0; // @[AtomicAutomata.scala 205:83]
+ wire d_drop = d_first & d_ackd & d_cam_sel_match_0; // @[AtomicAutomata.scala 232:40]
+ wire bundleOut_0_d_ready = auto_in_d_ready | d_drop; // @[AtomicAutomata.scala 236:35]
+ wire _d_first_T = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_ack = auto_out_d_bits_opcode == 3'h0; // @[AtomicAutomata.scala 214:40]
+ wire d_replace = d_first & d_ack & d_cam_sel_match_0; // @[AtomicAutomata.scala 233:42]
+ TLMonitor_7 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = out_1_ready & a_allow; // @[AtomicAutomata.scala 150:38]
+ assign auto_in_d_valid = auto_out_d_valid & ~d_drop; // @[AtomicAutomata.scala 235:35]
+ assign auto_in_d_bits_opcode = d_replace ? 3'h1 : auto_out_d_bits_opcode; // @[AtomicAutomata.scala 238:19 239:26 240:28]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = d_replace ? cam_d_0_denied | auto_out_d_bits_denied : auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:19 239:26 243:29]
+ assign auto_in_d_bits_data = d_replace ? cam_d_0_data : auto_out_d_bits_data; // @[AtomicAutomata.scala 238:19 239:26 241:26]
+ assign auto_in_d_bits_corrupt = d_replace ? cam_d_0_corrupt | auto_out_d_bits_denied : auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 238:19 239:26 242:29]
+ assign auto_out_a_valid = idle ? _T_12 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ assign auto_out_a_bits_opcode = muxStateEarly_1 ? source_i_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_param = muxStateEarly_1 ? source_i_bits_param : 3'h0; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_size = _T_41 | _T_42; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_source = _T_38 | _T_39; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_address = _T_35 | _T_36; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_mask = _T_32 | _T_33; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_data = _T_29 | _T_30; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_corrupt = muxStateEarly_0 & source_c_bits_a_corrupt | muxStateEarly_1 & auto_in_a_bits_corrupt; // @[Mux.scala 27:73]
+ assign auto_out_d_ready = auto_in_d_ready | d_drop; // @[AtomicAutomata.scala 236:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = out_1_ready & a_allow; // @[AtomicAutomata.scala 150:38]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~d_drop; // @[AtomicAutomata.scala 235:35]
+ assign monitor_io_in_d_bits_opcode = d_replace ? 3'h1 : auto_out_d_bits_opcode; // @[AtomicAutomata.scala 238:19 239:26 240:28]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_denied = d_replace ? cam_d_0_denied | auto_out_d_bits_denied : auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:19 239:26 243:29]
+ assign monitor_io_in_d_bits_corrupt = d_replace ? cam_d_0_corrupt | auto_out_d_bits_denied : auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 238:19 239:26 242:29]
+ always @(posedge clock) begin
+ if (reset) begin // @[AtomicAutomata.scala 76:28]
+ cam_s_0_state <= 2'h0; // @[AtomicAutomata.scala 76:28]
+ end else if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
+ if (d_cam_sel_match_0) begin // @[AtomicAutomata.scala 225:23]
+ if (d_ackd) begin // @[AtomicAutomata.scala 227:29]
+ cam_s_0_state <= 2'h2;
+ end else begin
+ cam_s_0_state <= 2'h0;
+ end
+ end else begin
+ cam_s_0_state <= _GEN_25;
+ end
+ end else begin
+ cam_s_0_state <= _GEN_25;
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_opcode <= auto_in_a_bits_opcode; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_param <= auto_in_a_bits_param; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_size <= auto_in_a_bits_size; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_source <= auto_in_a_bits_source; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_address <= auto_in_a_bits_address; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_mask <= auto_in_a_bits_mask; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_data <= auto_in_a_bits_data; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_corrupt <= auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ if (3'h3 == _GEN_41) begin // @[Mux.scala 81:58]
+ cam_a_0_lut <= 4'hc;
+ end else if (3'h0 == _GEN_41) begin // @[Mux.scala 81:58]
+ cam_a_0_lut <= 4'h6;
+ end else begin
+ cam_a_0_lut <= _cam_a_0_lut_T_2;
+ end
+ end
+ end
+ if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
+ if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
+ cam_d_0_data <= auto_out_d_bits_data; // @[AtomicAutomata.scala 219:22]
+ end
+ end
+ if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
+ if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
+ cam_d_0_denied <= auto_out_d_bits_denied; // @[AtomicAutomata.scala 220:24]
+ end
+ end
+ if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
+ if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
+ cam_d_0_corrupt <= auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 221:25]
+ end
+ end
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 3'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ if (earlyWinner_1) begin // @[Arbiter.scala 111:73]
+ if (opdata) begin // @[Edges.scala 220:14]
+ beatsLeft <= decode;
+ end else begin
+ beatsLeft <= 3'h0;
+ end
+ end else begin
+ beatsLeft <= 3'h0;
+ end
+ end else begin
+ beatsLeft <= _beatsLeft_T_4;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_0 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_0 <= earlyWinner_0;
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~earlyWinner_0 | ~earlyWinner_1) & ~reset) begin
+ $fatal; // @[Arbiter.scala 105:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
+ ); // @[Arbiter.scala 105:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(cam_amo_0 | source_i_valid) | _prefixOR_T) & _T_10) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_10 & ~(~(cam_amo_0 | source_i_valid) | _prefixOR_T)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_13 | _T_12) & _T_10) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_10 & ~(_T_13 | _T_12)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ cam_s_0_state = _RAND_0[1:0];
+ _RAND_1 = {1{`RANDOM}};
+ cam_a_0_bits_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ cam_a_0_bits_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ cam_a_0_bits_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ cam_a_0_bits_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ cam_a_0_bits_address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ cam_a_0_bits_mask = _RAND_6[7:0];
+ _RAND_7 = {2{`RANDOM}};
+ cam_a_0_bits_data = _RAND_7[63:0];
+ _RAND_8 = {1{`RANDOM}};
+ cam_a_0_bits_corrupt = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ cam_a_0_lut = _RAND_9[3:0];
+ _RAND_10 = {2{`RANDOM}};
+ cam_d_0_data = _RAND_10[63:0];
+ _RAND_11 = {1{`RANDOM}};
+ cam_d_0_denied = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ cam_d_0_corrupt = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ beatsLeft = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ state_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ state_0 = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ d_first_counter = _RAND_16[2:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_8(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h4000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_61 = io_in_a_bits_address ^ 30'h20000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_64 = $signed(_T_62) & -31'sh10000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_66 = io_in_a_bits_address ^ 30'h10000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_69 = $signed(_T_67) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_71 = io_in_a_bits_address ^ 30'h10010000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_74 = $signed(_T_72) & -31'sh4000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_76 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_79 = $signed(_T_77) & -31'sh1000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 31'sh0; // @[Parameters.scala 137:67]
+ wire [29:0] _T_81 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_84 = $signed(_T_82) & -31'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_90 = _T_60 | _T_65 | _T_70 | _T_75 | _T_80 | _T_85; // @[Parameters.scala 671:42]
+ wire _T_152 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_156 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_157 = _T_156 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_161 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_165 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_279 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_292 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_309 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_347 = _T_309 & _T_90; // @[Parameters.scala 670:56]
+ wire _T_358 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_362 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_370 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_409 = _T_60 | _T_70 | _T_75 | _T_80; // @[Parameters.scala 671:42]
+ wire _T_410 = _T_309 & _T_409; // @[Parameters.scala 670:56]
+ wire _T_426 = source_ok & _T_410; // @[Monitor.scala 115:71]
+ wire _T_444 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_514 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_515 = io_in_a_bits_mask & _T_514; // @[Monitor.scala 127:31]
+ wire _T_516 = _T_515 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_520 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_534 = io_in_a_bits_size <= 3'h3; // @[Parameters.scala 92:42]
+ wire _T_560 = _T_534 & _T_409; // @[Parameters.scala 670:56]
+ wire _T_576 = source_ok & _T_560; // @[Monitor.scala 131:74]
+ wire _T_586 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_594 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_660 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_668 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_729 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_741 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_745 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_749 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_753 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_757 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_761 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_765 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_776 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_780 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_793 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_813 = _T_761 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_822 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_839 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_857 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_887 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_888 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_892 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_896 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_900 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_904 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_911 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_912 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_916 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_920 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_924 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_928 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_932 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_938 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_941 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_943 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_945 = ~_T_943[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_949 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_951 = ~_T_745; // @[Monitor.scala 671:74]
+ wire _T_952 = io_in_d_valid & d_first_1 & ~_T_745; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_745 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_951 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_951 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_938 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_962 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_964 = _T_962[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_969 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_970 = io_in_d_bits_opcode == _GEN_32 | _T_969; // @[Monitor.scala 685:77]
+ wire _T_974 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_981 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_982 = io_in_d_bits_opcode == _GEN_48 | _T_981; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_986 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_996 = _T_949 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_951; // @[Monitor.scala 694:116]
+ wire _T_998 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_1005 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1014 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_1040 = io_in_d_valid & d_first_2 & _T_745; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_745 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_745 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_1048 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_1058 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1083 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_152 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_152) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_279 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_157 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_157) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_165 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_165 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_292 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_292 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_370 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_370 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_426 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_426) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_358 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_516 & (io_in_a_valid & _T_444 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_444 & ~reset & ~_T_516) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_520 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_520 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_594 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_594 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_729 & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~_T_729) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_362 & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~_T_362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_161 & (io_in_a_valid & _T_668 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_668 & ~reset & ~_T_161) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_741 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_741) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_749 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~_T_749) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_745 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_745 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_749 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_749) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_776 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_776) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_780 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_780) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_765 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_765 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_749 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_749) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_776 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_776) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_780 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_780) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_813 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_813) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_793 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_793 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_822 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_822 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (io_in_d_valid & _T_822 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_822 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & (io_in_d_valid & _T_822 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_822 & _T_2 & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_822 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_822 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_839 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_839 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (io_in_d_valid & _T_839 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_839 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_813 & (io_in_d_valid & _T_839 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_839 & _T_2 & ~_T_813) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_839 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_839 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_857 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_857 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (io_in_d_valid & _T_857 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_857 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & (io_in_d_valid & _T_857 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_857 & _T_2 & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_761 & (io_in_d_valid & _T_857 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_857 & _T_2 & ~_T_761) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_888 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_888) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_892 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_892) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_896 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_896) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_900 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_900) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_904 & (_T_887 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_887 & ~reset & ~_T_904) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_912 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_912) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_916 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_916) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_920 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_920) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_924 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_924) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_928 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_928) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_932 & (_T_911 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_911 & _T_2 & ~_T_932) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_945 & (_T_941 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_941 & ~reset & ~_T_945) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_964 & (_T_952 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & _T_2 & ~_T_964) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_970 & (_T_952 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & same_cycle_resp & _T_2 & ~_T_970) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_974 & (_T_952 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & same_cycle_resp & _T_2 & ~_T_974) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_982 & (_T_952 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & ~same_cycle_resp & _T_2 & ~_T_982) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_986 & (_T_952 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_952 & ~same_cycle_resp & _T_2 & ~_T_986) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_998 & (_T_996 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_996 & _T_2 & ~_T_998) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1005 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1005) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1014 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1014) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1048[0] & (_T_1040 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1040 & _T_2 & ~_T_1048[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (_T_1040 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1040 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_2(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [29:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [29:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_8 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_1 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_9(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [14:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [14:0] _GEN_71 = {{9'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [14:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 15'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [14:0] _T_56 = io_in_a_bits_address ^ 15'h4000; // @[Parameters.scala 137:31]
+ wire [15:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [15:0] _T_59 = $signed(_T_57) & -16'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 16'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [14:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_719 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_757 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_693) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727[0] & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_727[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_737 & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_737) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[14:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [14:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [14:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [14:0] saved_address; // @[Repeater.scala 20:18]
+ reg [7:0] saved_mask; // @[Repeater.scala 20:18]
+ reg saved_corrupt; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[14:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ saved_corrupt = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [14:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [14:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [14:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [14:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [14:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [14:0] _GEN_11 = {{9'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_9 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_3(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [14:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [14:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLInterconnectCoupler_5(
+ input clock,
+ input reset,
+ output auto_buffer_in_a_ready,
+ input auto_buffer_in_a_valid,
+ input [2:0] auto_buffer_in_a_bits_opcode,
+ input [2:0] auto_buffer_in_a_bits_param,
+ input [2:0] auto_buffer_in_a_bits_size,
+ input [2:0] auto_buffer_in_a_bits_source,
+ input [14:0] auto_buffer_in_a_bits_address,
+ input [7:0] auto_buffer_in_a_bits_mask,
+ input [63:0] auto_buffer_in_a_bits_data,
+ input auto_buffer_in_a_bits_corrupt,
+ input auto_buffer_in_d_ready,
+ output auto_buffer_in_d_valid,
+ output [2:0] auto_buffer_in_d_bits_opcode,
+ output [2:0] auto_buffer_in_d_bits_size,
+ output [2:0] auto_buffer_in_d_bits_source,
+ output [63:0] auto_buffer_in_d_bits_data,
+ input auto_fragmenter_out_a_ready,
+ output auto_fragmenter_out_a_valid,
+ output [2:0] auto_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_fragmenter_out_a_bits_param,
+ output [1:0] auto_fragmenter_out_a_bits_size,
+ output [6:0] auto_fragmenter_out_a_bits_source,
+ output [14:0] auto_fragmenter_out_a_bits_address,
+ output [7:0] auto_fragmenter_out_a_bits_mask,
+ output [63:0] auto_fragmenter_out_a_bits_data,
+ output auto_fragmenter_out_a_bits_corrupt,
+ output auto_fragmenter_out_d_ready,
+ input auto_fragmenter_out_d_valid,
+ input [2:0] auto_fragmenter_out_d_bits_opcode,
+ input [1:0] auto_fragmenter_out_d_bits_size,
+ input [6:0] auto_fragmenter_out_d_bits_source,
+ input [63:0] auto_fragmenter_out_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [14:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [14:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [14:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [14:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ TLFragmenter fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ TLBuffer_3 buffer ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_data = auto_buffer_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+endmodule
+module TLSourceShrinker_1(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLWidthWidget_4(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLInterconnectCoupler_6(
+ input auto_tlserial_manager_crossing_out_a_ready,
+ output auto_tlserial_manager_crossing_out_a_valid,
+ output [2:0] auto_tlserial_manager_crossing_out_a_bits_opcode,
+ output [2:0] auto_tlserial_manager_crossing_out_a_bits_param,
+ output [2:0] auto_tlserial_manager_crossing_out_a_bits_size,
+ output [2:0] auto_tlserial_manager_crossing_out_a_bits_source,
+ output [28:0] auto_tlserial_manager_crossing_out_a_bits_address,
+ output [7:0] auto_tlserial_manager_crossing_out_a_bits_mask,
+ output [63:0] auto_tlserial_manager_crossing_out_a_bits_data,
+ output auto_tlserial_manager_crossing_out_a_bits_corrupt,
+ output auto_tlserial_manager_crossing_out_d_ready,
+ input auto_tlserial_manager_crossing_out_d_valid,
+ input [2:0] auto_tlserial_manager_crossing_out_d_bits_opcode,
+ input [1:0] auto_tlserial_manager_crossing_out_d_bits_param,
+ input [2:0] auto_tlserial_manager_crossing_out_d_bits_size,
+ input [2:0] auto_tlserial_manager_crossing_out_d_bits_source,
+ input auto_tlserial_manager_crossing_out_d_bits_sink,
+ input auto_tlserial_manager_crossing_out_d_bits_denied,
+ input [63:0] auto_tlserial_manager_crossing_out_d_bits_data,
+ input auto_tlserial_manager_crossing_out_d_bits_corrupt,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [28:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [1:0] auto_tl_in_d_bits_param,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output auto_tl_in_d_bits_sink,
+ output auto_tl_in_d_bits_denied,
+ output [63:0] auto_tl_in_d_bits_data,
+ output auto_tl_in_d_bits_corrupt
+);
+ wire shrinker_auto_in_a_ready; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_in_a_valid; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_in_a_bits_opcode; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_in_a_bits_param; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_in_a_bits_size; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_in_a_bits_source; // @[SourceShrinker.scala 88:30]
+ wire [28:0] shrinker_auto_in_a_bits_address; // @[SourceShrinker.scala 88:30]
+ wire [7:0] shrinker_auto_in_a_bits_mask; // @[SourceShrinker.scala 88:30]
+ wire [63:0] shrinker_auto_in_a_bits_data; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_in_a_bits_corrupt; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_in_d_ready; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_in_d_valid; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_in_d_bits_opcode; // @[SourceShrinker.scala 88:30]
+ wire [1:0] shrinker_auto_in_d_bits_param; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_in_d_bits_size; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_in_d_bits_source; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_in_d_bits_sink; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_in_d_bits_denied; // @[SourceShrinker.scala 88:30]
+ wire [63:0] shrinker_auto_in_d_bits_data; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_in_d_bits_corrupt; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_out_a_ready; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_out_a_valid; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_out_a_bits_opcode; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_out_a_bits_param; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_out_a_bits_size; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_out_a_bits_source; // @[SourceShrinker.scala 88:30]
+ wire [28:0] shrinker_auto_out_a_bits_address; // @[SourceShrinker.scala 88:30]
+ wire [7:0] shrinker_auto_out_a_bits_mask; // @[SourceShrinker.scala 88:30]
+ wire [63:0] shrinker_auto_out_a_bits_data; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_out_a_bits_corrupt; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_out_d_ready; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_out_d_valid; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_out_d_bits_opcode; // @[SourceShrinker.scala 88:30]
+ wire [1:0] shrinker_auto_out_d_bits_param; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_out_d_bits_size; // @[SourceShrinker.scala 88:30]
+ wire [2:0] shrinker_auto_out_d_bits_source; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_out_d_bits_sink; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_out_d_bits_denied; // @[SourceShrinker.scala 88:30]
+ wire [63:0] shrinker_auto_out_d_bits_data; // @[SourceShrinker.scala 88:30]
+ wire shrinker_auto_out_d_bits_corrupt; // @[SourceShrinker.scala 88:30]
+ wire widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [28:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [28:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ TLSourceShrinker_1 shrinker ( // @[SourceShrinker.scala 88:30]
+ .auto_in_a_ready(shrinker_auto_in_a_ready),
+ .auto_in_a_valid(shrinker_auto_in_a_valid),
+ .auto_in_a_bits_opcode(shrinker_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(shrinker_auto_in_a_bits_param),
+ .auto_in_a_bits_size(shrinker_auto_in_a_bits_size),
+ .auto_in_a_bits_source(shrinker_auto_in_a_bits_source),
+ .auto_in_a_bits_address(shrinker_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(shrinker_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(shrinker_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(shrinker_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(shrinker_auto_in_d_ready),
+ .auto_in_d_valid(shrinker_auto_in_d_valid),
+ .auto_in_d_bits_opcode(shrinker_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(shrinker_auto_in_d_bits_param),
+ .auto_in_d_bits_size(shrinker_auto_in_d_bits_size),
+ .auto_in_d_bits_source(shrinker_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(shrinker_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(shrinker_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(shrinker_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(shrinker_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(shrinker_auto_out_a_ready),
+ .auto_out_a_valid(shrinker_auto_out_a_valid),
+ .auto_out_a_bits_opcode(shrinker_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(shrinker_auto_out_a_bits_param),
+ .auto_out_a_bits_size(shrinker_auto_out_a_bits_size),
+ .auto_out_a_bits_source(shrinker_auto_out_a_bits_source),
+ .auto_out_a_bits_address(shrinker_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(shrinker_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(shrinker_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(shrinker_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(shrinker_auto_out_d_ready),
+ .auto_out_d_valid(shrinker_auto_out_d_valid),
+ .auto_out_d_bits_opcode(shrinker_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(shrinker_auto_out_d_bits_param),
+ .auto_out_d_bits_size(shrinker_auto_out_d_bits_size),
+ .auto_out_d_bits_source(shrinker_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(shrinker_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(shrinker_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(shrinker_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(shrinker_auto_out_d_bits_corrupt)
+ );
+ TLWidthWidget_4 widget ( // @[WidthWidget.scala 219:28]
+ .auto_in_a_ready(widget_auto_in_a_ready),
+ .auto_in_a_valid(widget_auto_in_a_valid),
+ .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(widget_auto_in_a_bits_param),
+ .auto_in_a_bits_size(widget_auto_in_a_bits_size),
+ .auto_in_a_bits_source(widget_auto_in_a_bits_source),
+ .auto_in_a_bits_address(widget_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(widget_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(widget_auto_in_d_ready),
+ .auto_in_d_valid(widget_auto_in_d_valid),
+ .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(widget_auto_in_d_bits_param),
+ .auto_in_d_bits_size(widget_auto_in_d_bits_size),
+ .auto_in_d_bits_source(widget_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(widget_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(widget_auto_out_a_ready),
+ .auto_out_a_valid(widget_auto_out_a_valid),
+ .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(widget_auto_out_a_bits_param),
+ .auto_out_a_bits_size(widget_auto_out_a_bits_size),
+ .auto_out_a_bits_source(widget_auto_out_a_bits_source),
+ .auto_out_a_bits_address(widget_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(widget_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(widget_auto_out_d_ready),
+ .auto_out_d_valid(widget_auto_out_d_valid),
+ .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(widget_auto_out_d_bits_param),
+ .auto_out_d_bits_size(widget_auto_out_d_bits_size),
+ .auto_out_d_bits_source(widget_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(widget_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
+ );
+ assign auto_tlserial_manager_crossing_out_a_valid = shrinker_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_a_bits_opcode = shrinker_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_a_bits_param = shrinker_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_a_bits_size = shrinker_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_a_bits_source = shrinker_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_a_bits_address = shrinker_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_a_bits_mask = shrinker_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_a_bits_data = shrinker_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_a_bits_corrupt = shrinker_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tlserial_manager_crossing_out_d_ready = shrinker_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = widget_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = widget_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_param = widget_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = widget_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = widget_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = widget_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign shrinker_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign shrinker_auto_out_a_ready = auto_tlserial_manager_crossing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_valid = auto_tlserial_manager_crossing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_bits_opcode = auto_tlserial_manager_crossing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_bits_param = auto_tlserial_manager_crossing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_bits_size = auto_tlserial_manager_crossing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_bits_source = auto_tlserial_manager_crossing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_bits_sink = auto_tlserial_manager_crossing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_bits_denied = auto_tlserial_manager_crossing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_bits_data = auto_tlserial_manager_crossing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign shrinker_auto_out_d_bits_corrupt = auto_tlserial_manager_crossing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_out_a_ready = shrinker_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_valid = shrinker_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_opcode = shrinker_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_param = shrinker_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_size = shrinker_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_source = shrinker_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_sink = shrinker_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_denied = shrinker_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_data = shrinker_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_corrupt = shrinker_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+endmodule
+module TLMonitor_10(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_56 = io_in_a_bits_address ^ 29'h10010000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_59 = $signed(_T_57) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_719 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_757 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_693) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727[0] & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_727[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_737 & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_737) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_1(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [28:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [28:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [28:0] saved_address; // @[Repeater.scala 20:18]
+ reg [7:0] saved_mask; // @[Repeater.scala 20:18]
+ reg saved_corrupt; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ saved_corrupt = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_1(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_10 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_1 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_7(
+ input clock,
+ input reset,
+ input auto_control_xing_out_a_ready,
+ output auto_control_xing_out_a_valid,
+ output [2:0] auto_control_xing_out_a_bits_opcode,
+ output [2:0] auto_control_xing_out_a_bits_param,
+ output [1:0] auto_control_xing_out_a_bits_size,
+ output [6:0] auto_control_xing_out_a_bits_source,
+ output [28:0] auto_control_xing_out_a_bits_address,
+ output [7:0] auto_control_xing_out_a_bits_mask,
+ output [63:0] auto_control_xing_out_a_bits_data,
+ output auto_control_xing_out_a_bits_corrupt,
+ output auto_control_xing_out_d_ready,
+ input auto_control_xing_out_d_valid,
+ input [2:0] auto_control_xing_out_d_bits_opcode,
+ input [1:0] auto_control_xing_out_d_bits_size,
+ input [6:0] auto_control_xing_out_d_bits_source,
+ input [63:0] auto_control_xing_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [28:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_1 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_11(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_56 = io_in_a_bits_address ^ 29'h10011000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_59 = $signed(_T_57) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_719 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_757 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_693) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727[0] & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_727[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_737 & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_737) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_2(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_11 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_1 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_8(
+ input clock,
+ input reset,
+ input auto_control_xing_out_a_ready,
+ output auto_control_xing_out_a_valid,
+ output [2:0] auto_control_xing_out_a_bits_opcode,
+ output [2:0] auto_control_xing_out_a_bits_param,
+ output [1:0] auto_control_xing_out_a_bits_size,
+ output [6:0] auto_control_xing_out_a_bits_source,
+ output [28:0] auto_control_xing_out_a_bits_address,
+ output [7:0] auto_control_xing_out_a_bits_mask,
+ output [63:0] auto_control_xing_out_a_bits_data,
+ output auto_control_xing_out_a_bits_corrupt,
+ output auto_control_xing_out_d_ready,
+ input auto_control_xing_out_d_valid,
+ input [2:0] auto_control_xing_out_d_bits_opcode,
+ input [1:0] auto_control_xing_out_d_bits_size,
+ input [6:0] auto_control_xing_out_d_bits_source,
+ input [63:0] auto_control_xing_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [28:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_2 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_12(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_56 = io_in_a_bits_address ^ 29'h10012000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_59 = $signed(_T_57) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_719 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_757 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_693) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727[0] & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_727[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_737 & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_737) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at GPIO.scala:307:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at GPIO.scala:307:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_3(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_12 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_1 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_9(
+ input clock,
+ input reset,
+ input auto_control_xing_out_a_ready,
+ output auto_control_xing_out_a_valid,
+ output [2:0] auto_control_xing_out_a_bits_opcode,
+ output [2:0] auto_control_xing_out_a_bits_param,
+ output [1:0] auto_control_xing_out_a_bits_size,
+ output [6:0] auto_control_xing_out_a_bits_source,
+ output [28:0] auto_control_xing_out_a_bits_address,
+ output [7:0] auto_control_xing_out_a_bits_mask,
+ output [63:0] auto_control_xing_out_a_bits_data,
+ output auto_control_xing_out_a_bits_corrupt,
+ output auto_control_xing_out_d_ready,
+ input auto_control_xing_out_d_valid,
+ input [2:0] auto_control_xing_out_d_bits_opcode,
+ input [1:0] auto_control_xing_out_d_bits_size,
+ input [6:0] auto_control_xing_out_d_bits_source,
+ input [63:0] auto_control_xing_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [28:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_3 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_13(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_56 = io_in_a_bits_address ^ 29'h10013000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_59 = $signed(_T_57) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_719 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_757 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_693) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727[0] & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_727[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_737 & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_737) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_4(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_13 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_1 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_10(
+ input clock,
+ input reset,
+ input auto_control_xing_out_a_ready,
+ output auto_control_xing_out_a_valid,
+ output [2:0] auto_control_xing_out_a_bits_opcode,
+ output [2:0] auto_control_xing_out_a_bits_param,
+ output [1:0] auto_control_xing_out_a_bits_size,
+ output [6:0] auto_control_xing_out_a_bits_source,
+ output [28:0] auto_control_xing_out_a_bits_address,
+ output [7:0] auto_control_xing_out_a_bits_mask,
+ output [63:0] auto_control_xing_out_a_bits_data,
+ output auto_control_xing_out_a_bits_corrupt,
+ output auto_control_xing_out_d_ready,
+ input auto_control_xing_out_d_valid,
+ input [2:0] auto_control_xing_out_d_bits_opcode,
+ input [1:0] auto_control_xing_out_d_bits_size,
+ input [6:0] auto_control_xing_out_d_bits_source,
+ input [63:0] auto_control_xing_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [28:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_4 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_14(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh10000000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_259 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_300 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_331 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_339 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_370 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_378 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_409 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [5:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [5:0] a_first_counter1 = a_first_counter - 6'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 6'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_567 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_568 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_572 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_576 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_580 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_584 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] d_first_beats1_decode = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ reg [5:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [5:0] d_first_counter1 = d_first_counter - 6'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 6'h0; // @[Edges.scala 230:25]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_591 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_600 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_604 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [5:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [5:0] a_first_counter1_1 = a_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
+ reg [5:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [5:0] d_first_counter1_1 = d_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_618 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_621 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_623 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_625 = ~_T_623[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_629 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_618 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_642 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_644 = _T_642[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_649 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_650 = 3'h1 == _GEN_32 | _T_649; // @[Monitor.scala 685:77]
+ wire _T_654 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_661 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_662 = 3'h1 == _GEN_48 | _T_661; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_666 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_674 = _T_629 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_678 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_687 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 6'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 6'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 6'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 6'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_331 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_331) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_370 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_370) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_600 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_600) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_604 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_604) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_625 & (_T_621 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_621 & ~reset & ~_T_625) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_644 & (_T_629 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & _T_2 & ~_T_644) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_674 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_674 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_687 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_687) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[5:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[5:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight = _RAND_9[4:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_10[19:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[5:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[5:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_5(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [29:0] io_enq_bits_address,
+ input io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [29:0] io_deq_bits_address,
+ output io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [29:0] saved_address; // @[Repeater.scala 20:18]
+ reg saved_mask; // @[Repeater.scala 20:18]
+ reg saved_corrupt; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ saved_corrupt = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_5(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [7:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output auto_out_a_bits_size,
+ output [9:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input auto_out_d_bits_size,
+ input [9:0] auto_out_d_bits_source,
+ input [7:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [29:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [29:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [5:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [5:0] dFragnum = auto_out_d_bits_source[5:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 6'h0; // @[Fragmenter.scala 193:29]
+ wire [1:0] _dsizeOH1_T_1 = 2'h1 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire dsizeOH1 = ~_dsizeOH1_T_1[0]; // @[package.scala 234:46]
+ wire [5:0] _GEN_7 = {{5'd0}, dsizeOH1}; // @[Fragmenter.scala 202:50]
+ wire [5:0] _T_1 = dFragnum & _GEN_7; // @[Fragmenter.scala 202:50]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire [5:0] dFirst_acknum = dFragnum | _GEN_7; // @[Fragmenter.scala 203:45]
+ wire [6:0] _dFirst_size_T_2 = {dFirst_acknum, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,dFirst_acknum}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_10 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_10 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire _T_7 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [5:0] _acknum_T_1 = acknum - 6'h1; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h0 ? 3'h0 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [7:0] _aFragOH1_T_1 = 8'h1 << aFrag; // @[package.scala 234:77]
+ wire aFragOH1 = ~_aFragOH1_T_1[0]; // @[package.scala 234:46]
+ reg [5:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 6'h0; // @[Fragmenter.scala 292:29]
+ wire [5:0] _old_gennum1_T_2 = gennum - 6'h1; // @[Fragmenter.scala 293:79]
+ wire [5:0] old_gennum1 = aFirst ? aOrigOH1 : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [5:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [5:0] _GEN_11 = {{5'd0}, aFragOH1}; // @[Fragmenter.scala 294:41]
+ wire [5:0] _new_gennum_T_2 = _new_gennum_T | _GEN_11; // @[Fragmenter.scala 294:41]
+ wire [5:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = old_gennum1 | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_11; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_3; // @[Fragmenter.scala 304:51]
+ wire [29:0] _GEN_14 = {{24'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_14 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_5 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[9:7]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_14; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full | auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[9:7]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = new_gennum != 6'h0; // @[Fragmenter.scala 302:53]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 6'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFirst_acknum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[6]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 6'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~auto_out_d_valid | _T_1 == 6'h0) & ~reset) begin
+ $fatal; // @[Fragmenter.scala 202:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~auto_out_d_valid | _T_1 == 6'h0)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:202 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n"
+ ); // @[Fragmenter.scala 202:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[5:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[5:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_15(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh10000000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_259 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_300 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_331 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_339 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_370 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_378 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_409 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [5:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [5:0] a_first_counter1 = a_first_counter - 6'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 6'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_567 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_568 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_572 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_576 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_580 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_584 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] d_first_beats1_decode = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ reg [5:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [5:0] d_first_counter1 = d_first_counter - 6'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 6'h0; // @[Edges.scala 230:25]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_591 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_600 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_604 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [5:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [5:0] a_first_counter1_1 = a_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
+ reg [5:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [5:0] d_first_counter1_1 = d_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_618 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_621 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_623 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_625 = ~_T_623[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_629 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_618 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_642 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_644 = _T_642[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_649 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_650 = 3'h1 == _GEN_32 | _T_649; // @[Monitor.scala 685:77]
+ wire _T_654 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_661 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_662 = 3'h1 == _GEN_48 | _T_661; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_666 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_674 = _T_629 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_678 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_685 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_694 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 6'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 6'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 6'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 6'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_331 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_331) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_370 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_370) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_600 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_600) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_604 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_604) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_625 & (_T_621 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_621 & ~reset & ~_T_625) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_644 & (_T_629 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & _T_2 & ~_T_644) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_674 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_674 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_685 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_685) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_694 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_694) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[5:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[5:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight = _RAND_9[4:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_10[19:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[5:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[5:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_4(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [29:0] io_enq_bits_address,
+ input io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [29:0] io_deq_bits_address,
+ output io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:7]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_param [0:7]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_size [0:7]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:7]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [29:0] ram_address [0:7]; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [29:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [29:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_mask [0:7]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:7]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] value; // @[Counter.scala 62:40]
+ reg [2:0] value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _value_T_1 = value + 3'h1; // @[Counter.scala 78:24]
+ wire [2:0] _value_T_3 = value_1 + 3'h1; // @[Counter.scala 78:24]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_address_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_address_io_deq_bits_MPORT_addr = value_1;
+ assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_address_MPORT_data = io_enq_bits_address;
+ assign ram_address_MPORT_addr = value;
+ assign ram_address_MPORT_mask = 1'h1;
+ assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = value_1;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = value;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
+ ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 3'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= _value_T_1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 3'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= _value_T_3; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_address[initvar] = _RAND_4[29:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_6[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_7 = {1{`RANDOM}};
+ value = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ value_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ maybe_full = _RAND_9[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_4(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [7:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input [7:0] auto_out_d_bits_data
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [29:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [29:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_15 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Queue_4 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_16(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh10000000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_259 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_294 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_295 = io_in_a_bits_mask & _T_294; // @[Monitor.scala 127:31]
+ wire _T_296 = _T_295 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_300 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_331 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_339 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_370 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_378 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_409 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_567 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_568 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_572 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_576 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_580 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_584 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_591 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_600 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_604 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_618 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_621 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_623 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_625 = ~_T_623[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_629 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_618 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_642 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_644 = _T_642[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_649 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_650 = 3'h1 == _GEN_32 | _T_649; // @[Monitor.scala 685:77]
+ wire _T_654 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_661 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_662 = 3'h1 == _GEN_48 | _T_661; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_666 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_674 = _T_629 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_678 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_685 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_694 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 3'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 3'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_296 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_296) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_331 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_331) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_370 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_370) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_600 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_600) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_604 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_604) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_625 & (_T_621 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_621 & ~reset & ~_T_625) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_644 & (_T_629 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & _T_2 & ~_T_644) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_674 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_674 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_685 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_685) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_694 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_694) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight = _RAND_9[4:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_10[19:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[2:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_6(
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [29:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [29:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+ assign io_enq_ready = io_deq_ready; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+endmodule
+module TLWidthWidget_5(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input [7:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeated_repeater_io_enq_ready; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_enq_valid; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_enq_bits_opcode; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_enq_bits_param; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_enq_bits_size; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_enq_bits_source; // @[Repeater.scala 35:26]
+ wire [29:0] repeated_repeater_io_enq_bits_address; // @[Repeater.scala 35:26]
+ wire [7:0] repeated_repeater_io_enq_bits_mask; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_enq_bits_corrupt; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_deq_ready; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_deq_valid; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_deq_bits_opcode; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_deq_bits_param; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_deq_bits_size; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_deq_bits_source; // @[Repeater.scala 35:26]
+ wire [29:0] repeated_repeater_io_deq_bits_address; // @[Repeater.scala 35:26]
+ wire [7:0] repeated_repeater_io_deq_bits_mask; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_deq_bits_corrupt; // @[Repeater.scala 35:26]
+ wire [29:0] cated_bits_address = repeated_repeater_io_deq_bits_address; // @[WidthWidget.scala 155:25 156:15]
+ wire [2:0] repeat_sel = cated_bits_address[2:0]; // @[WidthWidget.scala 110:39]
+ wire [7:0] cated_bits_mask = repeated_repeater_io_deq_bits_mask; // @[WidthWidget.scala 155:25 156:15]
+ wire repeat_bundleOut_0_a_bits_mask_mux_0 = cated_bits_mask[0]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_1 = cated_bits_mask[1]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_2 = cated_bits_mask[2]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_3 = cated_bits_mask[3]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_4 = cated_bits_mask[4]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_5 = cated_bits_mask[5]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_6 = cated_bits_mask[6]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_7 = cated_bits_mask[7]; // @[WidthWidget.scala 122:55]
+ wire _GEN_3 = 3'h1 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_1 : repeat_bundleOut_0_a_bits_mask_mux_0; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_4 = 3'h2 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_2 : _GEN_3; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_5 = 3'h3 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_3 : _GEN_4; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_6 = 3'h4 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_4 : _GEN_5; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_7 = 3'h5 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_5 : _GEN_6; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_8 = 3'h6 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_6 : _GEN_7; // @[WidthWidget.scala 134:{53,53}]
+ wire [9:0] _limit_T_1 = 10'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] limit = ~_limit_T_1[2:0]; // @[package.scala 234:46]
+ reg [2:0] count; // @[WidthWidget.scala 34:27]
+ wire last = count == limit; // @[WidthWidget.scala 36:26]
+ wire [2:0] _enable_T_1 = count & limit; // @[WidthWidget.scala 37:63]
+ wire enable_0 = ~(|_enable_T_1); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_3 = count ^ 3'h1; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_1 = ~(|_enable_T_4); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_6 = count ^ 3'h2; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_2 = ~(|_enable_T_7); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_9 = count ^ 3'h3; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_3 = ~(|_enable_T_10); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_4 = ~(|_enable_T_13); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_5 = ~(|_enable_T_16); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_6 = ~(|_enable_T_19); // @[WidthWidget.scala 37:47]
+ wire _bundleOut_0_d_ready_T = ~last; // @[WidthWidget.scala 70:32]
+ wire bundleOut_0_d_ready = auto_in_d_ready | ~last; // @[WidthWidget.scala 70:29]
+ wire _T = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _count_T_1 = count + 3'h1; // @[WidthWidget.scala 44:24]
+ reg bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 56:41]
+ wire bundleIn_0_d_bits_data_masked_enable_0 = enable_0 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_1 = enable_1 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_2 = enable_2 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_3 = enable_3 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_4 = enable_4 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_5 = enable_5 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_6 = enable_6 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_0; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_1; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_2; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_3; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_4; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_5; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_6; // @[WidthWidget.scala 60:24]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_0 = bundleIn_0_d_bits_data_masked_enable_0 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_0; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_1 = bundleIn_0_d_bits_data_masked_enable_1 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_1; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_2 = bundleIn_0_d_bits_data_masked_enable_2 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_2; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_3 = bundleIn_0_d_bits_data_masked_enable_3 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_3; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_4 = bundleIn_0_d_bits_data_masked_enable_4 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_4; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_5 = bundleIn_0_d_bits_data_masked_enable_5 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_5; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_6 = bundleIn_0_d_bits_data_masked_enable_6 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_6; // @[WidthWidget.scala 62:88]
+ wire _GEN_14 = _T & _bundleOut_0_d_ready_T | bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 63:35 64:30 56:41]
+ wire [31:0] bundleIn_0_d_bits_data_lo = {bundleIn_0_d_bits_data_mdata_3,bundleIn_0_d_bits_data_mdata_2,
+ bundleIn_0_d_bits_data_mdata_1,bundleIn_0_d_bits_data_mdata_0}; // @[Cat.scala 31:58]
+ wire [31:0] bundleIn_0_d_bits_data_hi = {auto_out_d_bits_data,bundleIn_0_d_bits_data_mdata_6,
+ bundleIn_0_d_bits_data_mdata_5,bundleIn_0_d_bits_data_mdata_4}; // @[Cat.scala 31:58]
+ TLMonitor_16 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_6 repeated_repeater ( // @[Repeater.scala 35:26]
+ .io_enq_ready(repeated_repeater_io_enq_ready),
+ .io_enq_valid(repeated_repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeated_repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeated_repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeated_repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeated_repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeated_repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeated_repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeated_repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeated_repeater_io_deq_ready),
+ .io_deq_valid(repeated_repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeated_repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeated_repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeated_repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeated_repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeated_repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeated_repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeated_repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeated_repeater_io_enq_ready; // @[Nodes.scala 1210:84 Repeater.scala 37:21]
+ assign auto_in_d_valid = auto_out_d_valid & last; // @[WidthWidget.scala 71:29]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = {bundleIn_0_d_bits_data_hi,bundleIn_0_d_bits_data_lo}; // @[Cat.scala 31:58]
+ assign auto_out_a_valid = repeated_repeater_io_deq_valid; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_opcode = repeated_repeater_io_deq_bits_opcode; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_param = repeated_repeater_io_deq_bits_param; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_size = repeated_repeater_io_deq_bits_size; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_source = repeated_repeater_io_deq_bits_source; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_address = repeated_repeater_io_deq_bits_address; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_mask = 3'h7 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_7 : _GEN_8; // @[WidthWidget.scala 134:{53,53}]
+ assign auto_out_a_bits_corrupt = repeated_repeater_io_deq_bits_corrupt; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_d_ready = auto_in_d_ready | ~last; // @[WidthWidget.scala 70:29]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeated_repeater_io_enq_ready; // @[Nodes.scala 1210:84 Repeater.scala 37:21]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & last; // @[WidthWidget.scala 71:29]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign repeated_repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[WidthWidget.scala 34:27]
+ count <= 3'h0; // @[WidthWidget.scala 34:27]
+ end else if (_T) begin // @[WidthWidget.scala 43:24]
+ if (last) begin // @[WidthWidget.scala 46:21]
+ count <= 3'h0; // @[WidthWidget.scala 47:17]
+ end else begin
+ count <= _count_T_1; // @[WidthWidget.scala 44:15]
+ end
+ end
+ if (reset) begin // @[WidthWidget.scala 56:41]
+ bundleIn_0_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala 56:41]
+ end else begin
+ bundleIn_0_d_bits_data_rdata_written_once <= _GEN_14;
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_0) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_0 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_1) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_1 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_2) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_2 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_3) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_3 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_4) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_4 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_5) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_5 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_6) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_6 <= auto_out_d_bits_data;
+ end
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ count = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_written_once = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_0 = _RAND_2[7:0];
+ _RAND_3 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_1 = _RAND_3[7:0];
+ _RAND_4 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_2 = _RAND_4[7:0];
+ _RAND_5 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_3 = _RAND_5[7:0];
+ _RAND_6 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_4 = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_5 = _RAND_7[7:0];
+ _RAND_8 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_6 = _RAND_8[7:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_11(
+ input clock,
+ input reset,
+ input auto_mem_xing_out_a_ready,
+ output auto_mem_xing_out_a_valid,
+ output [2:0] auto_mem_xing_out_a_bits_opcode,
+ output [2:0] auto_mem_xing_out_a_bits_param,
+ output auto_mem_xing_out_a_bits_size,
+ output [9:0] auto_mem_xing_out_a_bits_source,
+ output [29:0] auto_mem_xing_out_a_bits_address,
+ output auto_mem_xing_out_a_bits_mask,
+ output auto_mem_xing_out_a_bits_corrupt,
+ output auto_mem_xing_out_d_ready,
+ input auto_mem_xing_out_d_valid,
+ input auto_mem_xing_out_d_bits_size,
+ input [9:0] auto_mem_xing_out_d_bits_source,
+ input [7:0] auto_mem_xing_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [29:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [29:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [9:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [29:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [9:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire widget_clock; // @[WidthWidget.scala 219:28]
+ wire widget_reset; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [29:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [29:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
+ TLFragmenter_5 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ TLBuffer_4 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ TLWidthWidget_5 widget ( // @[WidthWidget.scala 219:28]
+ .clock(widget_clock),
+ .reset(widget_reset),
+ .auto_in_a_ready(widget_auto_in_a_ready),
+ .auto_in_a_valid(widget_auto_in_a_valid),
+ .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(widget_auto_in_a_bits_param),
+ .auto_in_a_bits_size(widget_auto_in_a_bits_size),
+ .auto_in_a_bits_source(widget_auto_in_a_bits_source),
+ .auto_in_a_bits_address(widget_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(widget_auto_in_d_ready),
+ .auto_in_d_valid(widget_auto_in_d_valid),
+ .auto_in_d_bits_size(widget_auto_in_d_bits_size),
+ .auto_in_d_bits_source(widget_auto_in_d_bits_source),
+ .auto_in_d_bits_data(widget_auto_in_d_bits_data),
+ .auto_out_a_ready(widget_auto_out_a_ready),
+ .auto_out_a_valid(widget_auto_out_a_valid),
+ .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(widget_auto_out_a_bits_param),
+ .auto_out_a_bits_size(widget_auto_out_a_bits_size),
+ .auto_out_a_bits_source(widget_auto_out_a_bits_source),
+ .auto_out_a_bits_address(widget_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(widget_auto_out_d_ready),
+ .auto_out_d_valid(widget_auto_out_d_valid),
+ .auto_out_d_bits_size(widget_auto_out_d_bits_size),
+ .auto_out_d_bits_source(widget_auto_out_d_bits_source),
+ .auto_out_d_bits_data(widget_auto_out_d_bits_data)
+ );
+ assign auto_mem_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = widget_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = widget_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = widget_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = widget_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = widget_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_a_ready = auto_mem_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_mem_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_mem_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_mem_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_mem_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_clock = clock;
+ assign buffer_reset = reset;
+ assign buffer_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign widget_clock = clock;
+ assign widget_reset = reset;
+ assign widget_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+endmodule
+module TLMonitor_17(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_56 = io_in_a_bits_address ^ 29'h10014000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_59 = $signed(_T_57) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_719 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_757 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_693) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727[0] & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_727[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_737 & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_737) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:118:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_6(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_17 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_1 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_12(
+ input clock,
+ input reset,
+ input auto_control_xing_out_a_ready,
+ output auto_control_xing_out_a_valid,
+ output [2:0] auto_control_xing_out_a_bits_opcode,
+ output [2:0] auto_control_xing_out_a_bits_param,
+ output [1:0] auto_control_xing_out_a_bits_size,
+ output [6:0] auto_control_xing_out_a_bits_source,
+ output [28:0] auto_control_xing_out_a_bits_address,
+ output [7:0] auto_control_xing_out_a_bits_mask,
+ output [63:0] auto_control_xing_out_a_bits_data,
+ output auto_control_xing_out_a_bits_corrupt,
+ output auto_control_xing_out_d_ready,
+ input auto_control_xing_out_d_valid,
+ input [2:0] auto_control_xing_out_d_bits_opcode,
+ input [1:0] auto_control_xing_out_d_bits_size,
+ input [6:0] auto_control_xing_out_d_bits_source,
+ input [63:0] auto_control_xing_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [28:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_6 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_18(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h30000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh10000000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_259 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_300 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_331 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_339 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_370 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_378 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_409 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [5:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [5:0] a_first_counter1 = a_first_counter - 6'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 6'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_567 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_568 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_572 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_576 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_580 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_584 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] d_first_beats1_decode = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ reg [5:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [5:0] d_first_counter1 = d_first_counter - 6'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 6'h0; // @[Edges.scala 230:25]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_591 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_600 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_604 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [5:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [5:0] a_first_counter1_1 = a_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
+ reg [5:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [5:0] d_first_counter1_1 = d_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_618 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_621 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_623 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_625 = ~_T_623[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_629 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_618 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_642 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_644 = _T_642[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_649 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_650 = 3'h1 == _GEN_32 | _T_649; // @[Monitor.scala 685:77]
+ wire _T_654 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_661 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_662 = 3'h1 == _GEN_48 | _T_661; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_666 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_674 = _T_629 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_678 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_687 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 6'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 6'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 6'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 6'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_331 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_331) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_370 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_370) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_600 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_600) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_604 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_604) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_625 & (_T_621 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_621 & ~reset & ~_T_625) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_644 & (_T_629 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & _T_2 & ~_T_644) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:131:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_674 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_674 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_687 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_687) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:131:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[5:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[5:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight = _RAND_9[4:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_10[19:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[5:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[5:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_7(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [7:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output auto_out_a_bits_size,
+ output [9:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input auto_out_d_bits_size,
+ input [9:0] auto_out_d_bits_source,
+ input [7:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [29:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [29:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [5:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [5:0] dFragnum = auto_out_d_bits_source[5:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 6'h0; // @[Fragmenter.scala 193:29]
+ wire [1:0] _dsizeOH1_T_1 = 2'h1 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire dsizeOH1 = ~_dsizeOH1_T_1[0]; // @[package.scala 234:46]
+ wire [5:0] _GEN_7 = {{5'd0}, dsizeOH1}; // @[Fragmenter.scala 202:50]
+ wire [5:0] _T_1 = dFragnum & _GEN_7; // @[Fragmenter.scala 202:50]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire [5:0] dFirst_acknum = dFragnum | _GEN_7; // @[Fragmenter.scala 203:45]
+ wire [6:0] _dFirst_size_T_2 = {dFirst_acknum, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,dFirst_acknum}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_10 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_10 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire _T_7 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [5:0] _acknum_T_1 = acknum - 6'h1; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h0 ? 3'h0 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [7:0] _aFragOH1_T_1 = 8'h1 << aFrag; // @[package.scala 234:77]
+ wire aFragOH1 = ~_aFragOH1_T_1[0]; // @[package.scala 234:46]
+ reg [5:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 6'h0; // @[Fragmenter.scala 292:29]
+ wire [5:0] _old_gennum1_T_2 = gennum - 6'h1; // @[Fragmenter.scala 293:79]
+ wire [5:0] old_gennum1 = aFirst ? aOrigOH1 : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [5:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [5:0] _GEN_11 = {{5'd0}, aFragOH1}; // @[Fragmenter.scala 294:41]
+ wire [5:0] _new_gennum_T_2 = _new_gennum_T | _GEN_11; // @[Fragmenter.scala 294:41]
+ wire [5:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = old_gennum1 | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_11; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_3; // @[Fragmenter.scala 304:51]
+ wire [29:0] _GEN_14 = {{24'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_18 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_5 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[9:7]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_14; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full | auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[9:7]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = new_gennum != 6'h0; // @[Fragmenter.scala 302:53]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 6'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFirst_acknum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[6]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 6'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~auto_out_d_valid | _T_1 == 6'h0) & ~reset) begin
+ $fatal; // @[Fragmenter.scala 202:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~auto_out_d_valid | _T_1 == 6'h0)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:202 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n"
+ ); // @[Fragmenter.scala 202:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[5:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[5:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_19(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h30000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh10000000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_259 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_300 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_331 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_339 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_370 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_378 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_409 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [5:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [5:0] a_first_counter1 = a_first_counter - 6'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 6'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_567 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_568 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_572 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_576 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_580 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_584 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] d_first_beats1_decode = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ reg [5:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [5:0] d_first_counter1 = d_first_counter - 6'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 6'h0; // @[Edges.scala 230:25]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_591 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_600 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_604 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [5:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [5:0] a_first_counter1_1 = a_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
+ reg [5:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [5:0] d_first_counter1_1 = d_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_618 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_621 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_623 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_625 = ~_T_623[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_629 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_618 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_642 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_644 = _T_642[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_649 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_650 = 3'h1 == _GEN_32 | _T_649; // @[Monitor.scala 685:77]
+ wire _T_654 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_661 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_662 = 3'h1 == _GEN_48 | _T_661; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_666 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_674 = _T_629 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_678 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_685 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_694 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 6'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 6'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 6'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 6'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_331 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_331) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_370 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_370) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_96 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & _T_96) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_600 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_600) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_604 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_604) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_625 & (_T_621 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_621 & ~reset & ~_T_625) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_644 & (_T_629 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & _T_2 & ~_T_644) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_674 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_674 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_685 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_685) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SPI.scala:132:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_694 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_694) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:132:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[5:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[5:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight = _RAND_9[4:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_10[19:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[5:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[5:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_5(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [7:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input [7:0] auto_out_d_bits_data
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [29:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [29:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_19 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Queue_4 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_20(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_56 = io_in_a_bits_address ^ 30'h30000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_59 = $signed(_T_57) & -31'sh10000000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_259 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_294 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_295 = io_in_a_bits_mask & _T_294; // @[Monitor.scala 127:31]
+ wire _T_296 = _T_295 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_300 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_331 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_339 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_370 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_378 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_409 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_567 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_568 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_572 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_576 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_580 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_584 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_591 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_600 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_604 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_618 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_621 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_623 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_625 = ~_T_623[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_629 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_618 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_642 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_644 = _T_642[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_649 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_650 = 3'h1 == _GEN_32 | _T_649; // @[Monitor.scala 685:77]
+ wire _T_654 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_661 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_662 = 3'h1 == _GEN_48 | _T_661; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_666 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_674 = _T_629 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_678 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_685 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_694 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 3'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 3'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_296 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_296) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_331 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_331) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_370 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_370) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_600 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_600) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_604 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_604) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_625 & (_T_621 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_621 & ~reset & ~_T_625) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_644 & (_T_629 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & _T_2 & ~_T_644) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_674 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_674 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_685 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_685) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SPI.scala:133:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_694 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_694) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SPI.scala:133:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight = _RAND_9[4:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_10[19:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[2:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLWidthWidget_6(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input [7:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeated_repeater_io_enq_ready; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_enq_valid; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_enq_bits_opcode; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_enq_bits_param; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_enq_bits_size; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_enq_bits_source; // @[Repeater.scala 35:26]
+ wire [29:0] repeated_repeater_io_enq_bits_address; // @[Repeater.scala 35:26]
+ wire [7:0] repeated_repeater_io_enq_bits_mask; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_enq_bits_corrupt; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_deq_ready; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_deq_valid; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_deq_bits_opcode; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_deq_bits_param; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_deq_bits_size; // @[Repeater.scala 35:26]
+ wire [2:0] repeated_repeater_io_deq_bits_source; // @[Repeater.scala 35:26]
+ wire [29:0] repeated_repeater_io_deq_bits_address; // @[Repeater.scala 35:26]
+ wire [7:0] repeated_repeater_io_deq_bits_mask; // @[Repeater.scala 35:26]
+ wire repeated_repeater_io_deq_bits_corrupt; // @[Repeater.scala 35:26]
+ wire [29:0] cated_bits_address = repeated_repeater_io_deq_bits_address; // @[WidthWidget.scala 155:25 156:15]
+ wire [2:0] repeat_sel = cated_bits_address[2:0]; // @[WidthWidget.scala 110:39]
+ wire [7:0] cated_bits_mask = repeated_repeater_io_deq_bits_mask; // @[WidthWidget.scala 155:25 156:15]
+ wire repeat_bundleOut_0_a_bits_mask_mux_0 = cated_bits_mask[0]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_1 = cated_bits_mask[1]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_2 = cated_bits_mask[2]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_3 = cated_bits_mask[3]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_4 = cated_bits_mask[4]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_5 = cated_bits_mask[5]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_6 = cated_bits_mask[6]; // @[WidthWidget.scala 122:55]
+ wire repeat_bundleOut_0_a_bits_mask_mux_7 = cated_bits_mask[7]; // @[WidthWidget.scala 122:55]
+ wire _GEN_3 = 3'h1 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_1 : repeat_bundleOut_0_a_bits_mask_mux_0; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_4 = 3'h2 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_2 : _GEN_3; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_5 = 3'h3 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_3 : _GEN_4; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_6 = 3'h4 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_4 : _GEN_5; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_7 = 3'h5 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_5 : _GEN_6; // @[WidthWidget.scala 134:{53,53}]
+ wire _GEN_8 = 3'h6 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_6 : _GEN_7; // @[WidthWidget.scala 134:{53,53}]
+ wire [9:0] _limit_T_1 = 10'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] limit = ~_limit_T_1[2:0]; // @[package.scala 234:46]
+ reg [2:0] count; // @[WidthWidget.scala 34:27]
+ wire last = count == limit; // @[WidthWidget.scala 36:26]
+ wire [2:0] _enable_T_1 = count & limit; // @[WidthWidget.scala 37:63]
+ wire enable_0 = ~(|_enable_T_1); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_3 = count ^ 3'h1; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_1 = ~(|_enable_T_4); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_6 = count ^ 3'h2; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_2 = ~(|_enable_T_7); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_9 = count ^ 3'h3; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_3 = ~(|_enable_T_10); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_12 = count ^ 3'h4; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_13 = _enable_T_12 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_4 = ~(|_enable_T_13); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_15 = count ^ 3'h5; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_16 = _enable_T_15 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_5 = ~(|_enable_T_16); // @[WidthWidget.scala 37:47]
+ wire [2:0] _enable_T_18 = count ^ 3'h6; // @[WidthWidget.scala 37:56]
+ wire [2:0] _enable_T_19 = _enable_T_18 & limit; // @[WidthWidget.scala 37:63]
+ wire enable_6 = ~(|_enable_T_19); // @[WidthWidget.scala 37:47]
+ wire _bundleOut_0_d_ready_T = ~last; // @[WidthWidget.scala 70:32]
+ wire bundleOut_0_d_ready = auto_in_d_ready | ~last; // @[WidthWidget.scala 70:29]
+ wire _T = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _count_T_1 = count + 3'h1; // @[WidthWidget.scala 44:24]
+ reg bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 56:41]
+ wire bundleIn_0_d_bits_data_masked_enable_0 = enable_0 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_1 = enable_1 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_2 = enable_2 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_3 = enable_3 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_4 = enable_4 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_5 = enable_5 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ wire bundleIn_0_d_bits_data_masked_enable_6 = enable_6 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_0; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_1; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_2; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_3; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_4; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_5; // @[WidthWidget.scala 60:24]
+ reg [7:0] bundleIn_0_d_bits_data_rdata_6; // @[WidthWidget.scala 60:24]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_0 = bundleIn_0_d_bits_data_masked_enable_0 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_0; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_1 = bundleIn_0_d_bits_data_masked_enable_1 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_1; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_2 = bundleIn_0_d_bits_data_masked_enable_2 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_2; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_3 = bundleIn_0_d_bits_data_masked_enable_3 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_3; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_4 = bundleIn_0_d_bits_data_masked_enable_4 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_4; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_5 = bundleIn_0_d_bits_data_masked_enable_5 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_5; // @[WidthWidget.scala 62:88]
+ wire [7:0] bundleIn_0_d_bits_data_mdata_6 = bundleIn_0_d_bits_data_masked_enable_6 ? auto_out_d_bits_data :
+ bundleIn_0_d_bits_data_rdata_6; // @[WidthWidget.scala 62:88]
+ wire _GEN_14 = _T & _bundleOut_0_d_ready_T | bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 63:35 64:30 56:41]
+ wire [31:0] bundleIn_0_d_bits_data_lo = {bundleIn_0_d_bits_data_mdata_3,bundleIn_0_d_bits_data_mdata_2,
+ bundleIn_0_d_bits_data_mdata_1,bundleIn_0_d_bits_data_mdata_0}; // @[Cat.scala 31:58]
+ wire [31:0] bundleIn_0_d_bits_data_hi = {auto_out_d_bits_data,bundleIn_0_d_bits_data_mdata_6,
+ bundleIn_0_d_bits_data_mdata_5,bundleIn_0_d_bits_data_mdata_4}; // @[Cat.scala 31:58]
+ TLMonitor_20 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_6 repeated_repeater ( // @[Repeater.scala 35:26]
+ .io_enq_ready(repeated_repeater_io_enq_ready),
+ .io_enq_valid(repeated_repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeated_repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeated_repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeated_repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeated_repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeated_repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeated_repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeated_repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeated_repeater_io_deq_ready),
+ .io_deq_valid(repeated_repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeated_repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeated_repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeated_repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeated_repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeated_repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeated_repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeated_repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeated_repeater_io_enq_ready; // @[Nodes.scala 1210:84 Repeater.scala 37:21]
+ assign auto_in_d_valid = auto_out_d_valid & last; // @[WidthWidget.scala 71:29]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = {bundleIn_0_d_bits_data_hi,bundleIn_0_d_bits_data_lo}; // @[Cat.scala 31:58]
+ assign auto_out_a_valid = repeated_repeater_io_deq_valid; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_opcode = repeated_repeater_io_deq_bits_opcode; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_param = repeated_repeater_io_deq_bits_param; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_size = repeated_repeater_io_deq_bits_size; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_source = repeated_repeater_io_deq_bits_source; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_address = repeated_repeater_io_deq_bits_address; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_a_bits_mask = 3'h7 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_7 : _GEN_8; // @[WidthWidget.scala 134:{53,53}]
+ assign auto_out_a_bits_corrupt = repeated_repeater_io_deq_bits_corrupt; // @[WidthWidget.scala 155:25 156:15]
+ assign auto_out_d_ready = auto_in_d_ready | ~last; // @[WidthWidget.scala 70:29]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeated_repeater_io_enq_ready; // @[Nodes.scala 1210:84 Repeater.scala 37:21]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & last; // @[WidthWidget.scala 71:29]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign repeated_repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeated_repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[WidthWidget.scala 34:27]
+ count <= 3'h0; // @[WidthWidget.scala 34:27]
+ end else if (_T) begin // @[WidthWidget.scala 43:24]
+ if (last) begin // @[WidthWidget.scala 46:21]
+ count <= 3'h0; // @[WidthWidget.scala 47:17]
+ end else begin
+ count <= _count_T_1; // @[WidthWidget.scala 44:15]
+ end
+ end
+ if (reset) begin // @[WidthWidget.scala 56:41]
+ bundleIn_0_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala 56:41]
+ end else begin
+ bundleIn_0_d_bits_data_rdata_written_once <= _GEN_14;
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_0) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_0 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_1) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_1 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_2) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_2 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_3) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_3 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_4) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_4 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_5) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_5 <= auto_out_d_bits_data;
+ end
+ end
+ if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
+ if (bundleIn_0_d_bits_data_masked_enable_6) begin // @[WidthWidget.scala 62:88]
+ bundleIn_0_d_bits_data_rdata_6 <= auto_out_d_bits_data;
+ end
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ count = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_written_once = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_0 = _RAND_2[7:0];
+ _RAND_3 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_1 = _RAND_3[7:0];
+ _RAND_4 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_2 = _RAND_4[7:0];
+ _RAND_5 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_3 = _RAND_5[7:0];
+ _RAND_6 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_4 = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_5 = _RAND_7[7:0];
+ _RAND_8 = {1{`RANDOM}};
+ bundleIn_0_d_bits_data_rdata_6 = _RAND_8[7:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_13(
+ input clock,
+ input reset,
+ input auto_mem_xing_out_a_ready,
+ output auto_mem_xing_out_a_valid,
+ output [2:0] auto_mem_xing_out_a_bits_opcode,
+ output [2:0] auto_mem_xing_out_a_bits_param,
+ output auto_mem_xing_out_a_bits_size,
+ output [9:0] auto_mem_xing_out_a_bits_source,
+ output [29:0] auto_mem_xing_out_a_bits_address,
+ output auto_mem_xing_out_a_bits_mask,
+ output auto_mem_xing_out_a_bits_corrupt,
+ output auto_mem_xing_out_d_ready,
+ input auto_mem_xing_out_d_valid,
+ input auto_mem_xing_out_d_bits_size,
+ input [9:0] auto_mem_xing_out_d_bits_source,
+ input [7:0] auto_mem_xing_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [29:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [29:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [9:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [29:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [9:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire widget_clock; // @[WidthWidget.scala 219:28]
+ wire widget_reset; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [29:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [29:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
+ TLFragmenter_7 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ TLBuffer_5 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ TLWidthWidget_6 widget ( // @[WidthWidget.scala 219:28]
+ .clock(widget_clock),
+ .reset(widget_reset),
+ .auto_in_a_ready(widget_auto_in_a_ready),
+ .auto_in_a_valid(widget_auto_in_a_valid),
+ .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(widget_auto_in_a_bits_param),
+ .auto_in_a_bits_size(widget_auto_in_a_bits_size),
+ .auto_in_a_bits_source(widget_auto_in_a_bits_source),
+ .auto_in_a_bits_address(widget_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(widget_auto_in_d_ready),
+ .auto_in_d_valid(widget_auto_in_d_valid),
+ .auto_in_d_bits_size(widget_auto_in_d_bits_size),
+ .auto_in_d_bits_source(widget_auto_in_d_bits_source),
+ .auto_in_d_bits_data(widget_auto_in_d_bits_data),
+ .auto_out_a_ready(widget_auto_out_a_ready),
+ .auto_out_a_valid(widget_auto_out_a_valid),
+ .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(widget_auto_out_a_bits_param),
+ .auto_out_a_bits_size(widget_auto_out_a_bits_size),
+ .auto_out_a_bits_source(widget_auto_out_a_bits_source),
+ .auto_out_a_bits_address(widget_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(widget_auto_out_d_ready),
+ .auto_out_d_valid(widget_auto_out_d_valid),
+ .auto_out_d_bits_size(widget_auto_out_d_bits_size),
+ .auto_out_d_bits_source(widget_auto_out_d_bits_source),
+ .auto_out_d_bits_data(widget_auto_out_d_bits_data)
+ );
+ assign auto_mem_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = widget_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = widget_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = widget_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = widget_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = widget_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_a_ready = auto_mem_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_mem_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_mem_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_mem_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_mem_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_clock = clock;
+ assign buffer_reset = reset;
+ assign buffer_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign widget_clock = clock;
+ assign widget_reset = reset;
+ assign widget_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign widget_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+endmodule
+module TLMonitor_21(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [14:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [14:0] _GEN_71 = {{12'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [14:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 15'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [14:0] _T_33 = io_in_a_bits_address ^ 15'h4000; // @[Parameters.scala 137:31]
+ wire [15:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [15:0] _T_36 = $signed(_T_34) & -16'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 16'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [14:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[14:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module PeripheryBus(
+ input auto_coupler_to_device_named_qspi_1_mem_xing_out_a_ready,
+ output auto_coupler_to_device_named_qspi_1_mem_xing_out_a_valid,
+ output [2:0] auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_param,
+ output auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_size,
+ output [9:0] auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_source,
+ output [29:0] auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_address,
+ output auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_mask,
+ output auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_corrupt,
+ output auto_coupler_to_device_named_qspi_1_mem_xing_out_d_ready,
+ input auto_coupler_to_device_named_qspi_1_mem_xing_out_d_valid,
+ input auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_size,
+ input [9:0] auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_source,
+ input [7:0] auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_data,
+ input auto_coupler_to_device_named_qspi_1_control_xing_out_a_ready,
+ output auto_coupler_to_device_named_qspi_1_control_xing_out_a_valid,
+ output [2:0] auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_param,
+ output [1:0] auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_size,
+ output [6:0] auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_source,
+ output [28:0] auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_address,
+ output [7:0] auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_data,
+ output auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_corrupt,
+ output auto_coupler_to_device_named_qspi_1_control_xing_out_d_ready,
+ input auto_coupler_to_device_named_qspi_1_control_xing_out_d_valid,
+ input [2:0] auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_size,
+ input [6:0] auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_source,
+ input [63:0] auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_data,
+ input auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready,
+ output auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid,
+ output [2:0] auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param,
+ output auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size,
+ output [9:0] auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source,
+ output [29:0] auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address,
+ output auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask,
+ output auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt,
+ output auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready,
+ input auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid,
+ input auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size,
+ input [9:0] auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source,
+ input [7:0] auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data,
+ input auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready,
+ output auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid,
+ output [2:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param,
+ output [1:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size,
+ output [6:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source,
+ output [28:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address,
+ output [7:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data,
+ output auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt,
+ output auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready,
+ input auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid,
+ input [2:0] auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size,
+ input [6:0] auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source,
+ input [63:0] auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data,
+ input auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready,
+ output auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid,
+ output [2:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param,
+ output [1:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size,
+ output [6:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source,
+ output [28:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address,
+ output [7:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data,
+ output auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt,
+ output auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready,
+ input auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid,
+ input [2:0] auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size,
+ input [6:0] auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source,
+ input [63:0] auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data,
+ input auto_coupler_to_device_named_uart_1_control_xing_out_a_ready,
+ output auto_coupler_to_device_named_uart_1_control_xing_out_a_valid,
+ output [2:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param,
+ output [1:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size,
+ output [6:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source,
+ output [28:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address,
+ output [7:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data,
+ output auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt,
+ output auto_coupler_to_device_named_uart_1_control_xing_out_d_ready,
+ input auto_coupler_to_device_named_uart_1_control_xing_out_d_valid,
+ input [2:0] auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size,
+ input [6:0] auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source,
+ input [63:0] auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data,
+ input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready,
+ output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid,
+ output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param,
+ output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size,
+ output [6:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source,
+ output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address,
+ output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data,
+ output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt,
+ output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready,
+ input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid,
+ input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size,
+ input [6:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source,
+ input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data,
+ input auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_ready,
+ output auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid,
+ output [2:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param,
+ output [2:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size,
+ output [2:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source,
+ output [28:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address,
+ output [7:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data,
+ output auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt,
+ output auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready,
+ input auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_valid,
+ input [2:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_param,
+ input [2:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_size,
+ input [2:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_source,
+ input auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_sink,
+ input auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_denied,
+ input [63:0] auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_data,
+ input auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_corrupt,
+ output auto_fixedClockNode_out_4_clock,
+ output auto_fixedClockNode_out_4_reset,
+ output auto_fixedClockNode_out_3_clock,
+ output auto_fixedClockNode_out_3_reset,
+ output auto_fixedClockNode_out_2_clock,
+ output auto_fixedClockNode_out_2_reset,
+ output auto_fixedClockNode_out_1_clock,
+ output auto_fixedClockNode_out_1_reset,
+ output auto_fixedClockNode_out_0_clock,
+ output auto_fixedClockNode_out_0_reset,
+ input auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock,
+ input auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset,
+ output auto_bus_xing_in_a_ready,
+ input auto_bus_xing_in_a_valid,
+ input [2:0] auto_bus_xing_in_a_bits_opcode,
+ input [2:0] auto_bus_xing_in_a_bits_param,
+ input [2:0] auto_bus_xing_in_a_bits_size,
+ input [2:0] auto_bus_xing_in_a_bits_source,
+ input [29:0] auto_bus_xing_in_a_bits_address,
+ input [7:0] auto_bus_xing_in_a_bits_mask,
+ input [63:0] auto_bus_xing_in_a_bits_data,
+ input auto_bus_xing_in_a_bits_corrupt,
+ input auto_bus_xing_in_d_ready,
+ output auto_bus_xing_in_d_valid,
+ output [2:0] auto_bus_xing_in_d_bits_opcode,
+ output [1:0] auto_bus_xing_in_d_bits_param,
+ output [2:0] auto_bus_xing_in_d_bits_size,
+ output [2:0] auto_bus_xing_in_d_bits_source,
+ output auto_bus_xing_in_d_bits_sink,
+ output auto_bus_xing_in_d_bits_denied,
+ output [63:0] auto_bus_xing_in_d_bits_data,
+ output auto_bus_xing_in_d_bits_corrupt,
+ output clock,
+ output reset
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [63:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ wire subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_clock; // @[BusWrapper.scala 40:48]
+ wire subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_reset; // @[BusWrapper.scala 40:48]
+ wire subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_clock; // @[BusWrapper.scala 40:48]
+ wire subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_reset; // @[BusWrapper.scala 40:48]
+ wire clockGroup_auto_in_member_subsystem_pbus_0_clock; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_in_member_subsystem_pbus_0_reset; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
+ wire fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_5_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_5_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_4_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_4_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_3_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_3_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_2_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_2_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_1_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_1_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_0_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_0_reset; // @[ClockGroup.scala 106:107]
+ wire fixer_clock; // @[PeripheryBus.scala 47:33]
+ wire fixer_reset; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_a_ready; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_a_valid; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_a_bits_opcode; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_a_bits_param; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_a_bits_size; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_a_bits_source; // @[PeripheryBus.scala 47:33]
+ wire [29:0] fixer_auto_in_a_bits_address; // @[PeripheryBus.scala 47:33]
+ wire [7:0] fixer_auto_in_a_bits_mask; // @[PeripheryBus.scala 47:33]
+ wire [63:0] fixer_auto_in_a_bits_data; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_ready; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_valid; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_d_bits_opcode; // @[PeripheryBus.scala 47:33]
+ wire [1:0] fixer_auto_in_d_bits_param; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_d_bits_size; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_d_bits_source; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_bits_sink; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_bits_denied; // @[PeripheryBus.scala 47:33]
+ wire [63:0] fixer_auto_in_d_bits_data; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_a_ready; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_a_valid; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_a_bits_opcode; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_a_bits_param; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_a_bits_size; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_a_bits_source; // @[PeripheryBus.scala 47:33]
+ wire [29:0] fixer_auto_out_a_bits_address; // @[PeripheryBus.scala 47:33]
+ wire [7:0] fixer_auto_out_a_bits_mask; // @[PeripheryBus.scala 47:33]
+ wire [63:0] fixer_auto_out_a_bits_data; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_ready; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_valid; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_d_bits_opcode; // @[PeripheryBus.scala 47:33]
+ wire [1:0] fixer_auto_out_d_bits_param; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_d_bits_size; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_d_bits_source; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_bits_sink; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_bits_denied; // @[PeripheryBus.scala 47:33]
+ wire [63:0] fixer_auto_out_d_bits_data; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 47:33]
+ wire in_xbar_auto_in_a_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_a_valid; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 49:29]
+ wire [29:0] in_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 49:29]
+ wire [7:0] in_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_d_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_d_valid; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 49:29]
+ wire [1:0] in_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_a_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_a_valid; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_a_bits_opcode; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_a_bits_param; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_a_bits_size; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_a_bits_source; // @[PeripheryBus.scala 49:29]
+ wire [29:0] in_xbar_auto_out_a_bits_address; // @[PeripheryBus.scala 49:29]
+ wire [7:0] in_xbar_auto_out_a_bits_mask; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_out_a_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_valid; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_d_bits_opcode; // @[PeripheryBus.scala 49:29]
+ wire [1:0] in_xbar_auto_out_d_bits_param; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_d_bits_size; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_d_bits_source; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_bits_sink; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_bits_denied; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_out_d_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 49:29]
+ wire out_xbar_clock; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_reset; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [29:0] out_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [1:0] out_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [29:0] out_xbar_auto_out_8_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_8_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_8_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [28:0] out_xbar_auto_out_7_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_7_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_7_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_7_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [29:0] out_xbar_auto_out_6_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_6_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_6_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [28:0] out_xbar_auto_out_5_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_5_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_5_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_5_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [28:0] out_xbar_auto_out_4_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_4_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_4_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_4_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [28:0] out_xbar_auto_out_3_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_3_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_3_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_3_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [28:0] out_xbar_auto_out_2_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_2_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_2_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_2_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [28:0] out_xbar_auto_out_1_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_1_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_1_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [1:0] out_xbar_auto_out_1_d_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_bits_sink; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_bits_denied; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_1_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [14:0] out_xbar_auto_out_0_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_0_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_0_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_0_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire atomics_clock; // @[AtomicAutomata.scala 283:29]
+ wire atomics_reset; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_a_ready; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_a_valid; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_a_bits_opcode; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_a_bits_param; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_a_bits_size; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_a_bits_source; // @[AtomicAutomata.scala 283:29]
+ wire [29:0] atomics_auto_in_a_bits_address; // @[AtomicAutomata.scala 283:29]
+ wire [7:0] atomics_auto_in_a_bits_mask; // @[AtomicAutomata.scala 283:29]
+ wire [63:0] atomics_auto_in_a_bits_data; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_ready; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_valid; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala 283:29]
+ wire [1:0] atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala 283:29]
+ wire [63:0] atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_a_ready; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_a_valid; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala 283:29]
+ wire [29:0] atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala 283:29]
+ wire [7:0] atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala 283:29]
+ wire [63:0] atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_ready; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_valid; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_d_bits_opcode; // @[AtomicAutomata.scala 283:29]
+ wire [1:0] atomics_auto_out_d_bits_param; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_d_bits_size; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_d_bits_source; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_bits_sink; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_bits_denied; // @[AtomicAutomata.scala 283:29]
+ wire [63:0] atomics_auto_out_d_bits_data; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 283:29]
+ wire buffer_1_clock; // @[Buffer.scala 68:28]
+ wire buffer_1_reset; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire coupler_to_slave_named_bootaddressreg_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [14:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [14:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_uart_1_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_uart_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_gpio_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_gpio_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [9:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [29:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [9:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [29:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_0_1_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [28:0] coupler_to_device_named_qspi_1_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_qspi_1_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_1_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [9:0] coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [29:0] coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [9:0] coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [29:0] coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_device_named_qspi_1_1_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [14:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire bundleIn_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ reg [63:0] bootAddrReg; // @[BootAddrReg.scala 34:32]
+ wire [7:0] oldBytes_0 = bootAddrReg[7:0]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_1 = bootAddrReg[15:8]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_2 = bootAddrReg[23:16]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_3 = bootAddrReg[31:24]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_4 = bootAddrReg[39:32]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_5 = bootAddrReg[47:40]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_6 = bootAddrReg[55:48]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_7 = bootAddrReg[63:56]; // @[RegField.scala 151:53]
+ wire bundleIn_0_2_a_valid = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [2:0] bundleIn_0_2_a_bits_opcode = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire in_bits_read = bundleIn_0_2_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [14:0] bundleIn_0_2_a_bits_address = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [8:0] in_bits_index = bundleIn_0_2_a_bits_address[11:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire bundleIn_0_2_d_ready = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire out_woready_0 = bundleIn_0_2_a_valid & bundleIn_0_2_d_ready & ~in_bits_read & in_bits_index == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] bundleIn_0_2_a_bits_mask = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [7:0] _out_backMask_T_23 = bundleIn_0_2_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_21 = bundleIn_0_2_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_19 = bundleIn_0_2_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_17 = bundleIn_0_2_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_15 = bundleIn_0_2_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_13 = bundleIn_0_2_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_11 = bundleIn_0_2_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_9 = bundleIn_0_2_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_backMask = {_out_backMask_T_23,_out_backMask_T_21,_out_backMask_T_19,_out_backMask_T_17,
+ _out_backMask_T_15,_out_backMask_T_13,_out_backMask_T_11,_out_backMask_T_9}; // @[Cat.scala 31:58]
+ wire out_womask = &out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala 83:24]
+ wire out_womask_1 = &out_backMask[15:8]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_1 = out_woready_0 & out_womask_1; // @[RegisterRouter.scala 83:24]
+ wire out_womask_2 = &out_backMask[23:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_2 = out_woready_0 & out_womask_2; // @[RegisterRouter.scala 83:24]
+ wire out_womask_3 = &out_backMask[31:24]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_3 = out_woready_0 & out_womask_3; // @[RegisterRouter.scala 83:24]
+ wire out_womask_4 = &out_backMask[39:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_4 = out_woready_0 & out_womask_4; // @[RegisterRouter.scala 83:24]
+ wire out_womask_5 = &out_backMask[47:40]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_5 = out_woready_0 & out_womask_5; // @[RegisterRouter.scala 83:24]
+ wire out_womask_6 = &out_backMask[55:48]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_6 = out_woready_0 & out_womask_6; // @[RegisterRouter.scala 83:24]
+ wire out_womask_7 = &out_backMask[63:56]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_7 = out_woready_0 & out_womask_7; // @[RegisterRouter.scala 83:24]
+ wire [63:0] bundleIn_0_2_a_bits_data = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [7:0] newBytes_1 = out_f_woready_1 ? bundleIn_0_2_a_bits_data[15:8] : oldBytes_1; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_0 = out_f_woready ? bundleIn_0_2_a_bits_data[7:0] : oldBytes_0; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_3 = out_f_woready_3 ? bundleIn_0_2_a_bits_data[31:24] : oldBytes_3; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_2 = out_f_woready_2 ? bundleIn_0_2_a_bits_data[23:16] : oldBytes_2; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_5 = out_f_woready_5 ? bundleIn_0_2_a_bits_data[47:40] : oldBytes_5; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_4 = out_f_woready_4 ? bundleIn_0_2_a_bits_data[39:32] : oldBytes_4; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_7 = out_f_woready_7 ? bundleIn_0_2_a_bits_data[63:56] : oldBytes_7; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_6 = out_f_woready_6 ? bundleIn_0_2_a_bits_data[55:48] : oldBytes_6; // @[RegField.scala 158:{20,33}]
+ wire [63:0] _bootAddrReg_T = {newBytes_7,newBytes_6,newBytes_5,newBytes_4,newBytes_3,newBytes_2,newBytes_1,newBytes_0}
+ ; // @[RegField.scala 154:52]
+ wire [63:0] out_prepend_6 = {oldBytes_7,oldBytes_6,oldBytes_5,oldBytes_4,oldBytes_3,oldBytes_2,oldBytes_1,oldBytes_0}; // @[Cat.scala 31:58]
+ wire bundleIn_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ ClockGroupAggregator_1 subsystem_pbus_clock_groups ( // @[BusWrapper.scala 40:48]
+ .auto_in_member_subsystem_pbus_0_clock(subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_clock),
+ .auto_in_member_subsystem_pbus_0_reset(subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_reset),
+ .auto_out_member_subsystem_pbus_0_clock(subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_clock),
+ .auto_out_member_subsystem_pbus_0_reset(subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_reset)
+ );
+ ClockGroup_1 clockGroup ( // @[BusWrapper.scala 41:38]
+ .auto_in_member_subsystem_pbus_0_clock(clockGroup_auto_in_member_subsystem_pbus_0_clock),
+ .auto_in_member_subsystem_pbus_0_reset(clockGroup_auto_in_member_subsystem_pbus_0_reset),
+ .auto_out_clock(clockGroup_auto_out_clock),
+ .auto_out_reset(clockGroup_auto_out_reset)
+ );
+ FixedClockBroadcast_1 fixedClockNode ( // @[ClockGroup.scala 106:107]
+ .auto_in_clock(fixedClockNode_auto_in_clock),
+ .auto_in_reset(fixedClockNode_auto_in_reset),
+ .auto_out_5_clock(fixedClockNode_auto_out_5_clock),
+ .auto_out_5_reset(fixedClockNode_auto_out_5_reset),
+ .auto_out_4_clock(fixedClockNode_auto_out_4_clock),
+ .auto_out_4_reset(fixedClockNode_auto_out_4_reset),
+ .auto_out_3_clock(fixedClockNode_auto_out_3_clock),
+ .auto_out_3_reset(fixedClockNode_auto_out_3_reset),
+ .auto_out_2_clock(fixedClockNode_auto_out_2_clock),
+ .auto_out_2_reset(fixedClockNode_auto_out_2_reset),
+ .auto_out_1_clock(fixedClockNode_auto_out_1_clock),
+ .auto_out_1_reset(fixedClockNode_auto_out_1_reset),
+ .auto_out_0_clock(fixedClockNode_auto_out_0_clock),
+ .auto_out_0_reset(fixedClockNode_auto_out_0_reset)
+ );
+ TLFIFOFixer_1 fixer ( // @[PeripheryBus.scala 47:33]
+ .clock(fixer_clock),
+ .reset(fixer_reset),
+ .auto_in_a_ready(fixer_auto_in_a_ready),
+ .auto_in_a_valid(fixer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fixer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fixer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fixer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fixer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fixer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fixer_auto_in_d_ready),
+ .auto_in_d_valid(fixer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(fixer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(fixer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fixer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(fixer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(fixer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(fixer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(fixer_auto_out_a_ready),
+ .auto_out_a_valid(fixer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fixer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fixer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fixer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fixer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fixer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fixer_auto_out_d_ready),
+ .auto_out_d_valid(fixer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(fixer_auto_out_d_bits_param),
+ .auto_out_d_bits_size(fixer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fixer_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(fixer_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(fixer_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(fixer_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt)
+ );
+ TLXbar_1 in_xbar ( // @[PeripheryBus.scala 49:29]
+ .auto_in_a_ready(in_xbar_auto_in_a_ready),
+ .auto_in_a_valid(in_xbar_auto_in_a_valid),
+ .auto_in_a_bits_opcode(in_xbar_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(in_xbar_auto_in_a_bits_param),
+ .auto_in_a_bits_size(in_xbar_auto_in_a_bits_size),
+ .auto_in_a_bits_source(in_xbar_auto_in_a_bits_source),
+ .auto_in_a_bits_address(in_xbar_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(in_xbar_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(in_xbar_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(in_xbar_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(in_xbar_auto_in_d_ready),
+ .auto_in_d_valid(in_xbar_auto_in_d_valid),
+ .auto_in_d_bits_opcode(in_xbar_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(in_xbar_auto_in_d_bits_param),
+ .auto_in_d_bits_size(in_xbar_auto_in_d_bits_size),
+ .auto_in_d_bits_source(in_xbar_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(in_xbar_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(in_xbar_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(in_xbar_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(in_xbar_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(in_xbar_auto_out_a_ready),
+ .auto_out_a_valid(in_xbar_auto_out_a_valid),
+ .auto_out_a_bits_opcode(in_xbar_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(in_xbar_auto_out_a_bits_param),
+ .auto_out_a_bits_size(in_xbar_auto_out_a_bits_size),
+ .auto_out_a_bits_source(in_xbar_auto_out_a_bits_source),
+ .auto_out_a_bits_address(in_xbar_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(in_xbar_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(in_xbar_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(in_xbar_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(in_xbar_auto_out_d_ready),
+ .auto_out_d_valid(in_xbar_auto_out_d_valid),
+ .auto_out_d_bits_opcode(in_xbar_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(in_xbar_auto_out_d_bits_param),
+ .auto_out_d_bits_size(in_xbar_auto_out_d_bits_size),
+ .auto_out_d_bits_source(in_xbar_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(in_xbar_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(in_xbar_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(in_xbar_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(in_xbar_auto_out_d_bits_corrupt)
+ );
+ TLXbar_2 out_xbar ( // @[PeripheryBus.scala 50:30]
+ .clock(out_xbar_clock),
+ .reset(out_xbar_reset),
+ .auto_in_a_ready(out_xbar_auto_in_a_ready),
+ .auto_in_a_valid(out_xbar_auto_in_a_valid),
+ .auto_in_a_bits_opcode(out_xbar_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(out_xbar_auto_in_a_bits_param),
+ .auto_in_a_bits_size(out_xbar_auto_in_a_bits_size),
+ .auto_in_a_bits_source(out_xbar_auto_in_a_bits_source),
+ .auto_in_a_bits_address(out_xbar_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(out_xbar_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(out_xbar_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(out_xbar_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(out_xbar_auto_in_d_ready),
+ .auto_in_d_valid(out_xbar_auto_in_d_valid),
+ .auto_in_d_bits_opcode(out_xbar_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(out_xbar_auto_in_d_bits_param),
+ .auto_in_d_bits_size(out_xbar_auto_in_d_bits_size),
+ .auto_in_d_bits_source(out_xbar_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(out_xbar_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(out_xbar_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(out_xbar_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(out_xbar_auto_in_d_bits_corrupt),
+ .auto_out_8_a_ready(out_xbar_auto_out_8_a_ready),
+ .auto_out_8_a_valid(out_xbar_auto_out_8_a_valid),
+ .auto_out_8_a_bits_opcode(out_xbar_auto_out_8_a_bits_opcode),
+ .auto_out_8_a_bits_param(out_xbar_auto_out_8_a_bits_param),
+ .auto_out_8_a_bits_size(out_xbar_auto_out_8_a_bits_size),
+ .auto_out_8_a_bits_source(out_xbar_auto_out_8_a_bits_source),
+ .auto_out_8_a_bits_address(out_xbar_auto_out_8_a_bits_address),
+ .auto_out_8_a_bits_mask(out_xbar_auto_out_8_a_bits_mask),
+ .auto_out_8_a_bits_corrupt(out_xbar_auto_out_8_a_bits_corrupt),
+ .auto_out_8_d_ready(out_xbar_auto_out_8_d_ready),
+ .auto_out_8_d_valid(out_xbar_auto_out_8_d_valid),
+ .auto_out_8_d_bits_size(out_xbar_auto_out_8_d_bits_size),
+ .auto_out_8_d_bits_source(out_xbar_auto_out_8_d_bits_source),
+ .auto_out_8_d_bits_data(out_xbar_auto_out_8_d_bits_data),
+ .auto_out_7_a_ready(out_xbar_auto_out_7_a_ready),
+ .auto_out_7_a_valid(out_xbar_auto_out_7_a_valid),
+ .auto_out_7_a_bits_opcode(out_xbar_auto_out_7_a_bits_opcode),
+ .auto_out_7_a_bits_param(out_xbar_auto_out_7_a_bits_param),
+ .auto_out_7_a_bits_size(out_xbar_auto_out_7_a_bits_size),
+ .auto_out_7_a_bits_source(out_xbar_auto_out_7_a_bits_source),
+ .auto_out_7_a_bits_address(out_xbar_auto_out_7_a_bits_address),
+ .auto_out_7_a_bits_mask(out_xbar_auto_out_7_a_bits_mask),
+ .auto_out_7_a_bits_data(out_xbar_auto_out_7_a_bits_data),
+ .auto_out_7_a_bits_corrupt(out_xbar_auto_out_7_a_bits_corrupt),
+ .auto_out_7_d_ready(out_xbar_auto_out_7_d_ready),
+ .auto_out_7_d_valid(out_xbar_auto_out_7_d_valid),
+ .auto_out_7_d_bits_opcode(out_xbar_auto_out_7_d_bits_opcode),
+ .auto_out_7_d_bits_size(out_xbar_auto_out_7_d_bits_size),
+ .auto_out_7_d_bits_source(out_xbar_auto_out_7_d_bits_source),
+ .auto_out_7_d_bits_data(out_xbar_auto_out_7_d_bits_data),
+ .auto_out_6_a_ready(out_xbar_auto_out_6_a_ready),
+ .auto_out_6_a_valid(out_xbar_auto_out_6_a_valid),
+ .auto_out_6_a_bits_opcode(out_xbar_auto_out_6_a_bits_opcode),
+ .auto_out_6_a_bits_param(out_xbar_auto_out_6_a_bits_param),
+ .auto_out_6_a_bits_size(out_xbar_auto_out_6_a_bits_size),
+ .auto_out_6_a_bits_source(out_xbar_auto_out_6_a_bits_source),
+ .auto_out_6_a_bits_address(out_xbar_auto_out_6_a_bits_address),
+ .auto_out_6_a_bits_mask(out_xbar_auto_out_6_a_bits_mask),
+ .auto_out_6_a_bits_corrupt(out_xbar_auto_out_6_a_bits_corrupt),
+ .auto_out_6_d_ready(out_xbar_auto_out_6_d_ready),
+ .auto_out_6_d_valid(out_xbar_auto_out_6_d_valid),
+ .auto_out_6_d_bits_size(out_xbar_auto_out_6_d_bits_size),
+ .auto_out_6_d_bits_source(out_xbar_auto_out_6_d_bits_source),
+ .auto_out_6_d_bits_data(out_xbar_auto_out_6_d_bits_data),
+ .auto_out_5_a_ready(out_xbar_auto_out_5_a_ready),
+ .auto_out_5_a_valid(out_xbar_auto_out_5_a_valid),
+ .auto_out_5_a_bits_opcode(out_xbar_auto_out_5_a_bits_opcode),
+ .auto_out_5_a_bits_param(out_xbar_auto_out_5_a_bits_param),
+ .auto_out_5_a_bits_size(out_xbar_auto_out_5_a_bits_size),
+ .auto_out_5_a_bits_source(out_xbar_auto_out_5_a_bits_source),
+ .auto_out_5_a_bits_address(out_xbar_auto_out_5_a_bits_address),
+ .auto_out_5_a_bits_mask(out_xbar_auto_out_5_a_bits_mask),
+ .auto_out_5_a_bits_data(out_xbar_auto_out_5_a_bits_data),
+ .auto_out_5_a_bits_corrupt(out_xbar_auto_out_5_a_bits_corrupt),
+ .auto_out_5_d_ready(out_xbar_auto_out_5_d_ready),
+ .auto_out_5_d_valid(out_xbar_auto_out_5_d_valid),
+ .auto_out_5_d_bits_opcode(out_xbar_auto_out_5_d_bits_opcode),
+ .auto_out_5_d_bits_size(out_xbar_auto_out_5_d_bits_size),
+ .auto_out_5_d_bits_source(out_xbar_auto_out_5_d_bits_source),
+ .auto_out_5_d_bits_data(out_xbar_auto_out_5_d_bits_data),
+ .auto_out_4_a_ready(out_xbar_auto_out_4_a_ready),
+ .auto_out_4_a_valid(out_xbar_auto_out_4_a_valid),
+ .auto_out_4_a_bits_opcode(out_xbar_auto_out_4_a_bits_opcode),
+ .auto_out_4_a_bits_param(out_xbar_auto_out_4_a_bits_param),
+ .auto_out_4_a_bits_size(out_xbar_auto_out_4_a_bits_size),
+ .auto_out_4_a_bits_source(out_xbar_auto_out_4_a_bits_source),
+ .auto_out_4_a_bits_address(out_xbar_auto_out_4_a_bits_address),
+ .auto_out_4_a_bits_mask(out_xbar_auto_out_4_a_bits_mask),
+ .auto_out_4_a_bits_data(out_xbar_auto_out_4_a_bits_data),
+ .auto_out_4_a_bits_corrupt(out_xbar_auto_out_4_a_bits_corrupt),
+ .auto_out_4_d_ready(out_xbar_auto_out_4_d_ready),
+ .auto_out_4_d_valid(out_xbar_auto_out_4_d_valid),
+ .auto_out_4_d_bits_opcode(out_xbar_auto_out_4_d_bits_opcode),
+ .auto_out_4_d_bits_size(out_xbar_auto_out_4_d_bits_size),
+ .auto_out_4_d_bits_source(out_xbar_auto_out_4_d_bits_source),
+ .auto_out_4_d_bits_data(out_xbar_auto_out_4_d_bits_data),
+ .auto_out_3_a_ready(out_xbar_auto_out_3_a_ready),
+ .auto_out_3_a_valid(out_xbar_auto_out_3_a_valid),
+ .auto_out_3_a_bits_opcode(out_xbar_auto_out_3_a_bits_opcode),
+ .auto_out_3_a_bits_param(out_xbar_auto_out_3_a_bits_param),
+ .auto_out_3_a_bits_size(out_xbar_auto_out_3_a_bits_size),
+ .auto_out_3_a_bits_source(out_xbar_auto_out_3_a_bits_source),
+ .auto_out_3_a_bits_address(out_xbar_auto_out_3_a_bits_address),
+ .auto_out_3_a_bits_mask(out_xbar_auto_out_3_a_bits_mask),
+ .auto_out_3_a_bits_data(out_xbar_auto_out_3_a_bits_data),
+ .auto_out_3_a_bits_corrupt(out_xbar_auto_out_3_a_bits_corrupt),
+ .auto_out_3_d_ready(out_xbar_auto_out_3_d_ready),
+ .auto_out_3_d_valid(out_xbar_auto_out_3_d_valid),
+ .auto_out_3_d_bits_opcode(out_xbar_auto_out_3_d_bits_opcode),
+ .auto_out_3_d_bits_size(out_xbar_auto_out_3_d_bits_size),
+ .auto_out_3_d_bits_source(out_xbar_auto_out_3_d_bits_source),
+ .auto_out_3_d_bits_data(out_xbar_auto_out_3_d_bits_data),
+ .auto_out_2_a_ready(out_xbar_auto_out_2_a_ready),
+ .auto_out_2_a_valid(out_xbar_auto_out_2_a_valid),
+ .auto_out_2_a_bits_opcode(out_xbar_auto_out_2_a_bits_opcode),
+ .auto_out_2_a_bits_param(out_xbar_auto_out_2_a_bits_param),
+ .auto_out_2_a_bits_size(out_xbar_auto_out_2_a_bits_size),
+ .auto_out_2_a_bits_source(out_xbar_auto_out_2_a_bits_source),
+ .auto_out_2_a_bits_address(out_xbar_auto_out_2_a_bits_address),
+ .auto_out_2_a_bits_mask(out_xbar_auto_out_2_a_bits_mask),
+ .auto_out_2_a_bits_data(out_xbar_auto_out_2_a_bits_data),
+ .auto_out_2_a_bits_corrupt(out_xbar_auto_out_2_a_bits_corrupt),
+ .auto_out_2_d_ready(out_xbar_auto_out_2_d_ready),
+ .auto_out_2_d_valid(out_xbar_auto_out_2_d_valid),
+ .auto_out_2_d_bits_opcode(out_xbar_auto_out_2_d_bits_opcode),
+ .auto_out_2_d_bits_size(out_xbar_auto_out_2_d_bits_size),
+ .auto_out_2_d_bits_source(out_xbar_auto_out_2_d_bits_source),
+ .auto_out_2_d_bits_data(out_xbar_auto_out_2_d_bits_data),
+ .auto_out_1_a_ready(out_xbar_auto_out_1_a_ready),
+ .auto_out_1_a_valid(out_xbar_auto_out_1_a_valid),
+ .auto_out_1_a_bits_opcode(out_xbar_auto_out_1_a_bits_opcode),
+ .auto_out_1_a_bits_param(out_xbar_auto_out_1_a_bits_param),
+ .auto_out_1_a_bits_size(out_xbar_auto_out_1_a_bits_size),
+ .auto_out_1_a_bits_source(out_xbar_auto_out_1_a_bits_source),
+ .auto_out_1_a_bits_address(out_xbar_auto_out_1_a_bits_address),
+ .auto_out_1_a_bits_mask(out_xbar_auto_out_1_a_bits_mask),
+ .auto_out_1_a_bits_data(out_xbar_auto_out_1_a_bits_data),
+ .auto_out_1_a_bits_corrupt(out_xbar_auto_out_1_a_bits_corrupt),
+ .auto_out_1_d_ready(out_xbar_auto_out_1_d_ready),
+ .auto_out_1_d_valid(out_xbar_auto_out_1_d_valid),
+ .auto_out_1_d_bits_opcode(out_xbar_auto_out_1_d_bits_opcode),
+ .auto_out_1_d_bits_param(out_xbar_auto_out_1_d_bits_param),
+ .auto_out_1_d_bits_size(out_xbar_auto_out_1_d_bits_size),
+ .auto_out_1_d_bits_source(out_xbar_auto_out_1_d_bits_source),
+ .auto_out_1_d_bits_sink(out_xbar_auto_out_1_d_bits_sink),
+ .auto_out_1_d_bits_denied(out_xbar_auto_out_1_d_bits_denied),
+ .auto_out_1_d_bits_data(out_xbar_auto_out_1_d_bits_data),
+ .auto_out_1_d_bits_corrupt(out_xbar_auto_out_1_d_bits_corrupt),
+ .auto_out_0_a_ready(out_xbar_auto_out_0_a_ready),
+ .auto_out_0_a_valid(out_xbar_auto_out_0_a_valid),
+ .auto_out_0_a_bits_opcode(out_xbar_auto_out_0_a_bits_opcode),
+ .auto_out_0_a_bits_param(out_xbar_auto_out_0_a_bits_param),
+ .auto_out_0_a_bits_size(out_xbar_auto_out_0_a_bits_size),
+ .auto_out_0_a_bits_source(out_xbar_auto_out_0_a_bits_source),
+ .auto_out_0_a_bits_address(out_xbar_auto_out_0_a_bits_address),
+ .auto_out_0_a_bits_mask(out_xbar_auto_out_0_a_bits_mask),
+ .auto_out_0_a_bits_data(out_xbar_auto_out_0_a_bits_data),
+ .auto_out_0_a_bits_corrupt(out_xbar_auto_out_0_a_bits_corrupt),
+ .auto_out_0_d_ready(out_xbar_auto_out_0_d_ready),
+ .auto_out_0_d_valid(out_xbar_auto_out_0_d_valid),
+ .auto_out_0_d_bits_opcode(out_xbar_auto_out_0_d_bits_opcode),
+ .auto_out_0_d_bits_size(out_xbar_auto_out_0_d_bits_size),
+ .auto_out_0_d_bits_source(out_xbar_auto_out_0_d_bits_source),
+ .auto_out_0_d_bits_data(out_xbar_auto_out_0_d_bits_data)
+ );
+ TLBuffer_1 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
+ );
+ TLAtomicAutomata atomics ( // @[AtomicAutomata.scala 283:29]
+ .clock(atomics_clock),
+ .reset(atomics_reset),
+ .auto_in_a_ready(atomics_auto_in_a_ready),
+ .auto_in_a_valid(atomics_auto_in_a_valid),
+ .auto_in_a_bits_opcode(atomics_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(atomics_auto_in_a_bits_param),
+ .auto_in_a_bits_size(atomics_auto_in_a_bits_size),
+ .auto_in_a_bits_source(atomics_auto_in_a_bits_source),
+ .auto_in_a_bits_address(atomics_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(atomics_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(atomics_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(atomics_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(atomics_auto_in_d_ready),
+ .auto_in_d_valid(atomics_auto_in_d_valid),
+ .auto_in_d_bits_opcode(atomics_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(atomics_auto_in_d_bits_param),
+ .auto_in_d_bits_size(atomics_auto_in_d_bits_size),
+ .auto_in_d_bits_source(atomics_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(atomics_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(atomics_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(atomics_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(atomics_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(atomics_auto_out_a_ready),
+ .auto_out_a_valid(atomics_auto_out_a_valid),
+ .auto_out_a_bits_opcode(atomics_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(atomics_auto_out_a_bits_param),
+ .auto_out_a_bits_size(atomics_auto_out_a_bits_size),
+ .auto_out_a_bits_source(atomics_auto_out_a_bits_source),
+ .auto_out_a_bits_address(atomics_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(atomics_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(atomics_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(atomics_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(atomics_auto_out_d_ready),
+ .auto_out_d_valid(atomics_auto_out_d_valid),
+ .auto_out_d_bits_opcode(atomics_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(atomics_auto_out_d_bits_param),
+ .auto_out_d_bits_size(atomics_auto_out_d_bits_size),
+ .auto_out_d_bits_source(atomics_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(atomics_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(atomics_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(atomics_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(atomics_auto_out_d_bits_corrupt)
+ );
+ TLBuffer_2 buffer_1 ( // @[Buffer.scala 68:28]
+ .clock(buffer_1_clock),
+ .reset(buffer_1_reset),
+ .auto_in_a_ready(buffer_1_auto_in_a_ready),
+ .auto_in_a_valid(buffer_1_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_1_auto_in_d_ready),
+ .auto_in_d_valid(buffer_1_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_1_auto_out_a_ready),
+ .auto_out_a_valid(buffer_1_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_1_auto_out_d_ready),
+ .auto_out_d_valid(buffer_1_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt)
+ );
+ TLInterconnectCoupler_5 coupler_to_slave_named_bootaddressreg ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_slave_named_bootaddressreg_clock),
+ .reset(coupler_to_slave_named_bootaddressreg_reset),
+ .auto_buffer_in_a_ready(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_ready),
+ .auto_buffer_in_a_valid(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_valid),
+ .auto_buffer_in_a_bits_opcode(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_opcode),
+ .auto_buffer_in_a_bits_param(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_param),
+ .auto_buffer_in_a_bits_size(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_size),
+ .auto_buffer_in_a_bits_source(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_source),
+ .auto_buffer_in_a_bits_address(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_address),
+ .auto_buffer_in_a_bits_mask(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_mask),
+ .auto_buffer_in_a_bits_data(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_data),
+ .auto_buffer_in_a_bits_corrupt(coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_corrupt),
+ .auto_buffer_in_d_ready(coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_ready),
+ .auto_buffer_in_d_valid(coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_valid),
+ .auto_buffer_in_d_bits_opcode(coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_opcode),
+ .auto_buffer_in_d_bits_size(coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_size),
+ .auto_buffer_in_d_bits_source(coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_source),
+ .auto_buffer_in_d_bits_data(coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_data),
+ .auto_fragmenter_out_a_ready(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_ready),
+ .auto_fragmenter_out_a_valid(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_valid),
+ .auto_fragmenter_out_a_bits_opcode(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_opcode),
+ .auto_fragmenter_out_a_bits_param(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_param),
+ .auto_fragmenter_out_a_bits_size(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_size),
+ .auto_fragmenter_out_a_bits_source(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_source),
+ .auto_fragmenter_out_a_bits_address(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_address),
+ .auto_fragmenter_out_a_bits_mask(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_mask),
+ .auto_fragmenter_out_a_bits_data(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_data),
+ .auto_fragmenter_out_a_bits_corrupt(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_corrupt),
+ .auto_fragmenter_out_d_ready(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_ready),
+ .auto_fragmenter_out_d_valid(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_valid),
+ .auto_fragmenter_out_d_bits_opcode(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_opcode),
+ .auto_fragmenter_out_d_bits_size(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_size),
+ .auto_fragmenter_out_d_bits_source(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_source),
+ .auto_fragmenter_out_d_bits_data(coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_data)
+ );
+ TLInterconnectCoupler_6 coupler_to_port_named_serial_tl_mem ( // @[LazyModule.scala 432:27]
+ .auto_tlserial_manager_crossing_out_a_ready(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_ready),
+ .auto_tlserial_manager_crossing_out_a_valid(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_valid),
+ .auto_tlserial_manager_crossing_out_a_bits_opcode(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_opcode),
+ .auto_tlserial_manager_crossing_out_a_bits_param(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_param),
+ .auto_tlserial_manager_crossing_out_a_bits_size(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_size),
+ .auto_tlserial_manager_crossing_out_a_bits_source(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_source),
+ .auto_tlserial_manager_crossing_out_a_bits_address(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_address),
+ .auto_tlserial_manager_crossing_out_a_bits_mask(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_mask),
+ .auto_tlserial_manager_crossing_out_a_bits_data(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_data),
+ .auto_tlserial_manager_crossing_out_a_bits_corrupt(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_corrupt),
+ .auto_tlserial_manager_crossing_out_d_ready(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_ready),
+ .auto_tlserial_manager_crossing_out_d_valid(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_valid),
+ .auto_tlserial_manager_crossing_out_d_bits_opcode(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_opcode),
+ .auto_tlserial_manager_crossing_out_d_bits_param(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_param),
+ .auto_tlserial_manager_crossing_out_d_bits_size(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_size),
+ .auto_tlserial_manager_crossing_out_d_bits_source(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_source),
+ .auto_tlserial_manager_crossing_out_d_bits_sink(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_sink),
+ .auto_tlserial_manager_crossing_out_d_bits_denied(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_denied),
+ .auto_tlserial_manager_crossing_out_d_bits_data(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_data),
+ .auto_tlserial_manager_crossing_out_d_bits_corrupt(
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_corrupt),
+ .auto_tl_in_a_ready(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_param(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_param),
+ .auto_tl_in_d_bits_size(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_sink(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_sink),
+ .auto_tl_in_d_bits_denied(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_denied),
+ .auto_tl_in_d_bits_data(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_data),
+ .auto_tl_in_d_bits_corrupt(coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_corrupt)
+ );
+ TLInterconnectCoupler_7 coupler_to_device_named_uart_0 ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_device_named_uart_0_clock),
+ .reset(coupler_to_device_named_uart_0_reset),
+ .auto_control_xing_out_a_ready(coupler_to_device_named_uart_0_auto_control_xing_out_a_ready),
+ .auto_control_xing_out_a_valid(coupler_to_device_named_uart_0_auto_control_xing_out_a_valid),
+ .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_opcode),
+ .auto_control_xing_out_a_bits_param(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_param),
+ .auto_control_xing_out_a_bits_size(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_size),
+ .auto_control_xing_out_a_bits_source(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_source),
+ .auto_control_xing_out_a_bits_address(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_address),
+ .auto_control_xing_out_a_bits_mask(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_mask),
+ .auto_control_xing_out_a_bits_data(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_data),
+ .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_corrupt),
+ .auto_control_xing_out_d_ready(coupler_to_device_named_uart_0_auto_control_xing_out_d_ready),
+ .auto_control_xing_out_d_valid(coupler_to_device_named_uart_0_auto_control_xing_out_d_valid),
+ .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_opcode),
+ .auto_control_xing_out_d_bits_size(coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_size),
+ .auto_control_xing_out_d_bits_source(coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_source),
+ .auto_control_xing_out_d_bits_data(coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_device_named_uart_0_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_device_named_uart_0_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_device_named_uart_0_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_device_named_uart_0_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_device_named_uart_0_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_device_named_uart_0_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_device_named_uart_0_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_device_named_uart_0_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_device_named_uart_0_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_device_named_uart_0_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_device_named_uart_0_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_device_named_uart_0_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(coupler_to_device_named_uart_0_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_device_named_uart_0_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_device_named_uart_0_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_8 coupler_to_device_named_uart_1 ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_device_named_uart_1_clock),
+ .reset(coupler_to_device_named_uart_1_reset),
+ .auto_control_xing_out_a_ready(coupler_to_device_named_uart_1_auto_control_xing_out_a_ready),
+ .auto_control_xing_out_a_valid(coupler_to_device_named_uart_1_auto_control_xing_out_a_valid),
+ .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_opcode),
+ .auto_control_xing_out_a_bits_param(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_param),
+ .auto_control_xing_out_a_bits_size(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_size),
+ .auto_control_xing_out_a_bits_source(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_source),
+ .auto_control_xing_out_a_bits_address(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_address),
+ .auto_control_xing_out_a_bits_mask(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_mask),
+ .auto_control_xing_out_a_bits_data(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_data),
+ .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_corrupt),
+ .auto_control_xing_out_d_ready(coupler_to_device_named_uart_1_auto_control_xing_out_d_ready),
+ .auto_control_xing_out_d_valid(coupler_to_device_named_uart_1_auto_control_xing_out_d_valid),
+ .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_opcode),
+ .auto_control_xing_out_d_bits_size(coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_size),
+ .auto_control_xing_out_d_bits_source(coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_source),
+ .auto_control_xing_out_d_bits_data(coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_device_named_uart_1_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_device_named_uart_1_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_device_named_uart_1_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_device_named_uart_1_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_device_named_uart_1_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_device_named_uart_1_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_device_named_uart_1_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_device_named_uart_1_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_device_named_uart_1_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_device_named_uart_1_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_device_named_uart_1_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_device_named_uart_1_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_device_named_uart_1_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(coupler_to_device_named_uart_1_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_device_named_uart_1_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_device_named_uart_1_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_9 coupler_to_device_named_gpio_0 ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_device_named_gpio_0_clock),
+ .reset(coupler_to_device_named_gpio_0_reset),
+ .auto_control_xing_out_a_ready(coupler_to_device_named_gpio_0_auto_control_xing_out_a_ready),
+ .auto_control_xing_out_a_valid(coupler_to_device_named_gpio_0_auto_control_xing_out_a_valid),
+ .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_opcode),
+ .auto_control_xing_out_a_bits_param(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_param),
+ .auto_control_xing_out_a_bits_size(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_size),
+ .auto_control_xing_out_a_bits_source(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_source),
+ .auto_control_xing_out_a_bits_address(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_address),
+ .auto_control_xing_out_a_bits_mask(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_mask),
+ .auto_control_xing_out_a_bits_data(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_data),
+ .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_corrupt),
+ .auto_control_xing_out_d_ready(coupler_to_device_named_gpio_0_auto_control_xing_out_d_ready),
+ .auto_control_xing_out_d_valid(coupler_to_device_named_gpio_0_auto_control_xing_out_d_valid),
+ .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_opcode),
+ .auto_control_xing_out_d_bits_size(coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_size),
+ .auto_control_xing_out_d_bits_source(coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_source),
+ .auto_control_xing_out_d_bits_data(coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_device_named_gpio_0_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_device_named_gpio_0_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_device_named_gpio_0_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_device_named_gpio_0_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_device_named_gpio_0_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(coupler_to_device_named_gpio_0_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_device_named_gpio_0_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_device_named_gpio_0_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_10 coupler_to_device_named_qspi_0 ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_device_named_qspi_0_clock),
+ .reset(coupler_to_device_named_qspi_0_reset),
+ .auto_control_xing_out_a_ready(coupler_to_device_named_qspi_0_auto_control_xing_out_a_ready),
+ .auto_control_xing_out_a_valid(coupler_to_device_named_qspi_0_auto_control_xing_out_a_valid),
+ .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_opcode),
+ .auto_control_xing_out_a_bits_param(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_param),
+ .auto_control_xing_out_a_bits_size(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_size),
+ .auto_control_xing_out_a_bits_source(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_source),
+ .auto_control_xing_out_a_bits_address(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_address),
+ .auto_control_xing_out_a_bits_mask(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_mask),
+ .auto_control_xing_out_a_bits_data(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_data),
+ .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_corrupt),
+ .auto_control_xing_out_d_ready(coupler_to_device_named_qspi_0_auto_control_xing_out_d_ready),
+ .auto_control_xing_out_d_valid(coupler_to_device_named_qspi_0_auto_control_xing_out_d_valid),
+ .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_opcode),
+ .auto_control_xing_out_d_bits_size(coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_size),
+ .auto_control_xing_out_d_bits_source(coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_source),
+ .auto_control_xing_out_d_bits_data(coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_device_named_qspi_0_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_device_named_qspi_0_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_device_named_qspi_0_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_device_named_qspi_0_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_device_named_qspi_0_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(coupler_to_device_named_qspi_0_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_device_named_qspi_0_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_device_named_qspi_0_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_11 coupler_to_device_named_qspi_0_1 ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_device_named_qspi_0_1_clock),
+ .reset(coupler_to_device_named_qspi_0_1_reset),
+ .auto_mem_xing_out_a_ready(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_ready),
+ .auto_mem_xing_out_a_valid(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_valid),
+ .auto_mem_xing_out_a_bits_opcode(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_opcode),
+ .auto_mem_xing_out_a_bits_param(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_param),
+ .auto_mem_xing_out_a_bits_size(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_size),
+ .auto_mem_xing_out_a_bits_source(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_source),
+ .auto_mem_xing_out_a_bits_address(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_address),
+ .auto_mem_xing_out_a_bits_mask(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_mask),
+ .auto_mem_xing_out_a_bits_corrupt(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_corrupt),
+ .auto_mem_xing_out_d_ready(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_ready),
+ .auto_mem_xing_out_d_valid(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_valid),
+ .auto_mem_xing_out_d_bits_size(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_size),
+ .auto_mem_xing_out_d_bits_source(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_source),
+ .auto_mem_xing_out_d_bits_data(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_device_named_qspi_0_1_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_device_named_qspi_0_1_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_corrupt(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_device_named_qspi_0_1_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_device_named_qspi_0_1_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_size(coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_12 coupler_to_device_named_qspi_1 ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_device_named_qspi_1_clock),
+ .reset(coupler_to_device_named_qspi_1_reset),
+ .auto_control_xing_out_a_ready(coupler_to_device_named_qspi_1_auto_control_xing_out_a_ready),
+ .auto_control_xing_out_a_valid(coupler_to_device_named_qspi_1_auto_control_xing_out_a_valid),
+ .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_opcode),
+ .auto_control_xing_out_a_bits_param(coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_param),
+ .auto_control_xing_out_a_bits_size(coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_size),
+ .auto_control_xing_out_a_bits_source(coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_source),
+ .auto_control_xing_out_a_bits_address(coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_address),
+ .auto_control_xing_out_a_bits_mask(coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_mask),
+ .auto_control_xing_out_a_bits_data(coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_data),
+ .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_corrupt),
+ .auto_control_xing_out_d_ready(coupler_to_device_named_qspi_1_auto_control_xing_out_d_ready),
+ .auto_control_xing_out_d_valid(coupler_to_device_named_qspi_1_auto_control_xing_out_d_valid),
+ .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_opcode),
+ .auto_control_xing_out_d_bits_size(coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_size),
+ .auto_control_xing_out_d_bits_source(coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_source),
+ .auto_control_xing_out_d_bits_data(coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_device_named_qspi_1_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_device_named_qspi_1_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_device_named_qspi_1_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_device_named_qspi_1_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_device_named_qspi_1_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_device_named_qspi_1_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_device_named_qspi_1_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_device_named_qspi_1_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_device_named_qspi_1_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_device_named_qspi_1_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_device_named_qspi_1_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_device_named_qspi_1_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_device_named_qspi_1_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(coupler_to_device_named_qspi_1_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_device_named_qspi_1_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_device_named_qspi_1_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_13 coupler_to_device_named_qspi_1_1 ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_device_named_qspi_1_1_clock),
+ .reset(coupler_to_device_named_qspi_1_1_reset),
+ .auto_mem_xing_out_a_ready(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_ready),
+ .auto_mem_xing_out_a_valid(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_valid),
+ .auto_mem_xing_out_a_bits_opcode(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_opcode),
+ .auto_mem_xing_out_a_bits_param(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_param),
+ .auto_mem_xing_out_a_bits_size(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_size),
+ .auto_mem_xing_out_a_bits_source(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_source),
+ .auto_mem_xing_out_a_bits_address(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_address),
+ .auto_mem_xing_out_a_bits_mask(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_mask),
+ .auto_mem_xing_out_a_bits_corrupt(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_corrupt),
+ .auto_mem_xing_out_d_ready(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_ready),
+ .auto_mem_xing_out_d_valid(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_valid),
+ .auto_mem_xing_out_d_bits_size(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_size),
+ .auto_mem_xing_out_d_bits_source(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_source),
+ .auto_mem_xing_out_d_bits_data(coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_device_named_qspi_1_1_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_device_named_qspi_1_1_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_corrupt(coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_device_named_qspi_1_1_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_device_named_qspi_1_1_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_size(coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_data)
+ );
+ TLMonitor_21 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_a_valid =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_opcode =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_param =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_size =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_source =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_address =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_mask =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_corrupt =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_mem_xing_out_d_ready =
+ coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_valid =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_opcode =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_param =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_size =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_source =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_address =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_mask =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_data =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_corrupt =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_1_control_xing_out_d_ready =
+ coupler_to_device_named_qspi_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready =
+ coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready =
+ coupler_to_device_named_qspi_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready =
+ coupler_to_device_named_gpio_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_valid =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt =
+ coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_1_control_xing_out_d_ready =
+ coupler_to_device_named_uart_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt =
+ coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready =
+ coupler_to_device_named_uart_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready =
+ coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_4_clock = fixedClockNode_auto_out_5_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_4_reset = fixedClockNode_auto_out_5_reset; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_3_clock = fixedClockNode_auto_out_4_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_3_reset = fixedClockNode_auto_out_4_reset; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_2_clock = fixedClockNode_auto_out_3_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_2_reset = fixedClockNode_auto_out_3_reset; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_1_clock = fixedClockNode_auto_out_2_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_1_reset = fixedClockNode_auto_out_2_reset; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_0_clock = fixedClockNode_auto_out_1_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_0_reset = fixedClockNode_auto_out_1_reset; // @[LazyModule.scala 311:12]
+ assign auto_bus_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_clock =
+ auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock; // @[LazyModule.scala 309:16]
+ assign subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_reset =
+ auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset; // @[LazyModule.scala 309:16]
+ assign clockGroup_auto_in_member_subsystem_pbus_0_clock =
+ subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_clock; // @[LazyModule.scala 298:16]
+ assign clockGroup_auto_in_member_subsystem_pbus_0_reset =
+ subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_reset; // @[LazyModule.scala 298:16]
+ assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
+ assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
+ assign fixer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign fixer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign fixer_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_a_ready = out_xbar_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_valid = out_xbar_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_opcode = out_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_param = out_xbar_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_size = out_xbar_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_source = out_xbar_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_sink = out_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_denied = out_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_data = out_xbar_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_corrupt = out_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_in_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_out_a_ready = atomics_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_valid = atomics_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_opcode = atomics_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_param = atomics_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_size = atomics_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_source = atomics_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_sink = atomics_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_denied = atomics_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_data = atomics_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_corrupt = atomics_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign out_xbar_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign out_xbar_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_a_ready = coupler_to_device_named_qspi_1_1_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_valid = coupler_to_device_named_qspi_1_1_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_size = coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_source = coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_data = coupler_to_device_named_qspi_1_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_a_ready = coupler_to_device_named_qspi_1_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_valid = coupler_to_device_named_qspi_1_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_opcode = coupler_to_device_named_qspi_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_size = coupler_to_device_named_qspi_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_source = coupler_to_device_named_qspi_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_data = coupler_to_device_named_qspi_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_a_ready = coupler_to_device_named_qspi_0_1_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_d_valid = coupler_to_device_named_qspi_0_1_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_d_bits_size = coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_d_bits_source = coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_d_bits_data = coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_a_ready = coupler_to_device_named_qspi_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_valid = coupler_to_device_named_qspi_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_opcode = coupler_to_device_named_qspi_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_size = coupler_to_device_named_qspi_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_source = coupler_to_device_named_qspi_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_data = coupler_to_device_named_qspi_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_a_ready = coupler_to_device_named_gpio_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_valid = coupler_to_device_named_gpio_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_bits_opcode = coupler_to_device_named_gpio_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_bits_size = coupler_to_device_named_gpio_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_bits_source = coupler_to_device_named_gpio_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_bits_data = coupler_to_device_named_gpio_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_a_ready = coupler_to_device_named_uart_1_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_valid = coupler_to_device_named_uart_1_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_bits_opcode = coupler_to_device_named_uart_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_bits_size = coupler_to_device_named_uart_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_bits_source = coupler_to_device_named_uart_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_bits_data = coupler_to_device_named_uart_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_a_ready = coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_valid = coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_bits_opcode = coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_bits_size = coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_bits_source = coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_bits_data = coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_a_ready = coupler_to_port_named_serial_tl_mem_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_valid = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_opcode = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_param = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_size = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_source = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_sink = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_denied = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_data = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_corrupt = coupler_to_port_named_serial_tl_mem_auto_tl_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_a_ready = coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_valid = coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_opcode = coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_size = coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_source = coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_data = coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign buffer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_in_a_valid = atomics_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_opcode = atomics_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_param = atomics_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_size = atomics_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_source = atomics_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_address = atomics_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_mask = atomics_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_data = atomics_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_corrupt = atomics_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_d_ready = atomics_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign atomics_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign atomics_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign atomics_auto_in_a_valid = in_xbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_opcode = in_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_param = in_xbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_size = in_xbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_source = in_xbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_address = in_xbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_mask = in_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_data = in_xbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_corrupt = in_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_d_ready = in_xbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
+ assign atomics_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_1_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_out_a_ready = in_xbar_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_valid = in_xbar_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_opcode = in_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_param = in_xbar_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_size = in_xbar_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_source = in_xbar_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_sink = in_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_denied = in_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_data = in_xbar_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_corrupt = in_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign coupler_to_slave_named_bootaddressreg_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_bootaddressreg_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_valid = out_xbar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_opcode = out_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_param = out_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_size = out_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_source = out_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_address = out_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_mask = out_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_data = out_xbar_auto_out_0_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_a_bits_corrupt = out_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_buffer_in_d_ready = out_xbar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_ready =
+ coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_valid =
+ coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_size =
+ coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_source =
+ coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_bits_data = in_bits_index == 9'h0 ? out_prepend_6
+ : 64'h0; // @[RegisterRouter.scala 83:24]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_a_ready =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_valid =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_opcode =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_param =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_param; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_size =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_source =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_sink =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_sink; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_denied =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_denied; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_data =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tlserial_manager_crossing_out_d_bits_corrupt =
+ auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_valid = out_xbar_auto_out_1_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_opcode = out_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_param = out_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_size = out_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_source = out_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_address = out_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_mask = out_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_data = out_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_port_named_serial_tl_mem_auto_tl_in_d_ready = out_xbar_auto_out_1_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_uart_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_uart_0_auto_control_xing_out_a_ready =
+ auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_0_auto_control_xing_out_d_valid =
+ auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_opcode =
+ auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_size =
+ auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_source =
+ auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_data =
+ auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_valid = out_xbar_auto_out_2_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_2_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_param = out_xbar_auto_out_2_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_size = out_xbar_auto_out_2_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_source = out_xbar_auto_out_2_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_address = out_xbar_auto_out_2_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_2_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_data = out_xbar_auto_out_2_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_2_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_0_auto_tl_in_d_ready = out_xbar_auto_out_2_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_uart_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_uart_1_auto_control_xing_out_a_ready =
+ auto_coupler_to_device_named_uart_1_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_1_auto_control_xing_out_d_valid =
+ auto_coupler_to_device_named_uart_1_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_opcode =
+ auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_size =
+ auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_source =
+ auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_data =
+ auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_valid = out_xbar_auto_out_3_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_opcode = out_xbar_auto_out_3_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_param = out_xbar_auto_out_3_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_size = out_xbar_auto_out_3_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_source = out_xbar_auto_out_3_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_address = out_xbar_auto_out_3_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_mask = out_xbar_auto_out_3_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_data = out_xbar_auto_out_3_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_3_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_uart_1_auto_tl_in_d_ready = out_xbar_auto_out_3_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_gpio_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_gpio_0_auto_control_xing_out_a_ready =
+ auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_valid =
+ auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_opcode =
+ auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_size =
+ auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_source =
+ auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_data =
+ auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_valid = out_xbar_auto_out_4_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_4_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_param = out_xbar_auto_out_4_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_size = out_xbar_auto_out_4_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_source = out_xbar_auto_out_4_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_address = out_xbar_auto_out_4_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_4_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_data = out_xbar_auto_out_4_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_4_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_gpio_0_auto_tl_in_d_ready = out_xbar_auto_out_4_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_qspi_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_qspi_0_auto_control_xing_out_a_ready =
+ auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_valid =
+ auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_opcode =
+ auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_size =
+ auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_source =
+ auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_data =
+ auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_valid = out_xbar_auto_out_5_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_5_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_param = out_xbar_auto_out_5_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_size = out_xbar_auto_out_5_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_source = out_xbar_auto_out_5_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_address = out_xbar_auto_out_5_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_5_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_data = out_xbar_auto_out_5_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_5_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_auto_tl_in_d_ready = out_xbar_auto_out_5_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_qspi_0_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_ready =
+ auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_valid =
+ auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_size =
+ auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_source =
+ auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_data =
+ auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_valid = out_xbar_auto_out_6_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_opcode = out_xbar_auto_out_6_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_param = out_xbar_auto_out_6_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_size = out_xbar_auto_out_6_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_source = out_xbar_auto_out_6_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_address = out_xbar_auto_out_6_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_mask = out_xbar_auto_out_6_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_6_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_0_1_auto_tl_in_d_ready = out_xbar_auto_out_6_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_qspi_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_qspi_1_auto_control_xing_out_a_ready =
+ auto_coupler_to_device_named_qspi_1_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_auto_control_xing_out_d_valid =
+ auto_coupler_to_device_named_qspi_1_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_opcode =
+ auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_size =
+ auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_source =
+ auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_auto_control_xing_out_d_bits_data =
+ auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_valid = out_xbar_auto_out_7_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_bits_opcode = out_xbar_auto_out_7_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_bits_param = out_xbar_auto_out_7_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_bits_size = out_xbar_auto_out_7_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_bits_source = out_xbar_auto_out_7_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_bits_address = out_xbar_auto_out_7_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_bits_mask = out_xbar_auto_out_7_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_bits_data = out_xbar_auto_out_7_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_7_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_auto_tl_in_d_ready = out_xbar_auto_out_7_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_qspi_1_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_device_named_qspi_1_1_auto_mem_xing_out_a_ready =
+ auto_coupler_to_device_named_qspi_1_mem_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_valid =
+ auto_coupler_to_device_named_qspi_1_mem_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_size =
+ auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_source =
+ auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_1_auto_mem_xing_out_d_bits_data =
+ auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_a_valid = out_xbar_auto_out_8_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_opcode = out_xbar_auto_out_8_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_param = out_xbar_auto_out_8_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_size = out_xbar_auto_out_8_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_source = out_xbar_auto_out_8_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_address = out_xbar_auto_out_8_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_mask = out_xbar_auto_out_8_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_8_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_device_named_qspi_1_1_auto_tl_in_d_ready = out_xbar_auto_out_8_d_ready; // @[LazyModule.scala 298:16]
+ assign monitor_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_ready = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_valid = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_opcode = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_param = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_size = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_source = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_address = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_mask = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_corrupt = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_ready = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_valid = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_bits_source = coupler_to_slave_named_bootaddressreg_auto_fragmenter_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ always @(posedge bundleIn_0_clock) begin
+ if (bundleIn_0_reset) begin // @[BootAddrReg.scala 34:32]
+ bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala 34:32]
+ end else if (out_f_woready | out_f_woready_1 | out_f_woready_2 | out_f_woready_3 | out_f_woready_4 | out_f_woready_5
+ | out_f_woready_6 | out_f_woready_7) begin // @[RegField.scala 154:34]
+ bootAddrReg <= _bootAddrReg_T; // @[RegField.scala 154:40]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {2{`RANDOM}};
+ bootAddrReg = _RAND_0[63:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockGroupAggregator_2(
+ input auto_in_member_subsystem_fbus_0_clock,
+ input auto_in_member_subsystem_fbus_0_reset,
+ output auto_out_member_subsystem_fbus_0_clock,
+ output auto_out_member_subsystem_fbus_0_reset
+);
+ assign auto_out_member_subsystem_fbus_0_clock = auto_in_member_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_subsystem_fbus_0_reset = auto_in_member_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockGroup_2(
+ input auto_in_member_subsystem_fbus_0_clock,
+ input auto_in_member_subsystem_fbus_0_reset,
+ output auto_out_clock,
+ output auto_out_reset
+);
+ assign auto_out_clock = auto_in_member_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_reset = auto_in_member_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module FixedClockBroadcast_2(
+ input auto_in_clock,
+ input auto_in_reset,
+ output auto_out_1_clock,
+ output auto_out_1_reset,
+ output auto_out_0_clock,
+ output auto_out_0_reset
+);
+ assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLXbar_3(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[ReadyValidCancel.scala 21:38]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[ReadyValidCancel.scala 21:38]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_22(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_17 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_20 = _T_17 & _source_ok_T; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_26 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_28 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_29 = {1'b0,$signed(_T_28)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_31 = $signed(_T_29) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_32 = $signed(_T_31) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_33 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_36 = $signed(_T_34) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_38 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_39 = {1'b0,$signed(_T_38)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_41 = $signed(_T_39) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_42 = $signed(_T_41) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_43 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_44 = {1'b0,$signed(_T_43)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_46 = $signed(_T_44) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_47 = $signed(_T_46) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_48 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_51 = $signed(_T_49) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_52 = $signed(_T_51) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_53 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_54 = {1'b0,$signed(_T_53)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_56 = $signed(_T_54) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_57 = $signed(_T_56) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_58 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_59 = {1'b0,$signed(_T_58)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_61 = $signed(_T_59) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_62 = $signed(_T_61) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_63 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_66 = $signed(_T_64) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_67 = $signed(_T_66) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_68 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_71 = $signed(_T_69) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_72 = $signed(_T_71) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_73 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_76 = $signed(_T_74) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_77 = $signed(_T_76) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_78 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_79 = {1'b0,$signed(_T_78)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_81 = $signed(_T_79) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_82 = $signed(_T_81) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_191 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_195 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_196 = _T_195 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_200 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_204 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_384 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_397 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_416 = _T_17 & _T_32; // @[Parameters.scala 670:56]
+ wire _T_418 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_485 = _T_27 | _T_37 | _T_42 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_77 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_486 = _T_418 & _T_485; // @[Parameters.scala 670:56]
+ wire _T_488 = _T_416 | _T_486; // @[Parameters.scala 672:30]
+ wire _T_498 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_502 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_510 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_577 = _T_27 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_578 = _T_418 & _T_577; // @[Parameters.scala 670:56]
+ wire _T_599 = _T_416 | _T_578; // @[Parameters.scala 672:30]
+ wire _T_601 = _T_20 & _T_599; // @[Monitor.scala 115:71]
+ wire _T_619 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_724 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_725 = io_in_a_bits_mask & _T_724; // @[Monitor.scala 127:31]
+ wire _T_726 = _T_725 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_730 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_738 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_793 = _T_27 | _T_32 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_794 = _T_738 & _T_793; // @[Parameters.scala 670:56]
+ wire _T_816 = _T_20 & _T_794; // @[Monitor.scala 131:74]
+ wire _T_826 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_834 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_930 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_938 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1024 = _T_20 & _T_416; // @[Monitor.scala 147:68]
+ wire _T_1034 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1046 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
+ wire _T_1050 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1054 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1058 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1062 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1066 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1070 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1081 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1085 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1098 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1118 = _T_1066 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1127 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1144 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1162 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1192 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1193 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1197 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1201 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1205 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1209 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1216 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1217 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1221 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1225 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1229 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1233 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1237 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [2:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [3:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_75 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1243 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1246 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [2:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [19:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire _T_1250 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1254 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1256 = ~_T_1050; // @[Monitor.scala 671:74]
+ wire _T_1257 = io_in_d_valid & d_first_1 & ~_T_1050; // @[Monitor.scala 671:71]
+ wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1050 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _GEN_3 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [30:0] _GEN_4 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [30:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_1256 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1256 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1256 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1243 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire _T_1269 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1274 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1275 = io_in_d_bits_opcode == _GEN_32 | _T_1274; // @[Monitor.scala 685:77]
+ wire _T_1279 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1286 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1287 = io_in_d_bits_opcode == _GEN_48 | _T_1286; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1291 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1301 = _T_1254 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1256; // @[Monitor.scala 694:116]
+ wire _T_1303 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set_wo_ready = _GEN_15[0];
+ wire d_clr_wo_ready = _GEN_21[0];
+ wire _T_1310 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [7:0] a_sizes_set = _GEN_20[7:0];
+ wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [7:0] d_sizes_clr = _GEN_24[7:0];
+ wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1319 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [15:0] _GEN_83 = {{8'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_83 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1345 = io_in_d_valid & d_first_2 & _T_1050; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1050 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire _T_1353 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1363 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
+ wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_384 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_384) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_20 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_20) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_488 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_488) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_726 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_726) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_826 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_826) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_930 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_930) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1024 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1024) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1034 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1034) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1046 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1046) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1066 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1066) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1193 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1193) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1197 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1201 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1201) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1205 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1205) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1209 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1209) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1217 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1217) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1221 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1221) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1225 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1225) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1229 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1233 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1237 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1237) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1246 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1246 & ~reset & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1269 & (_T_1257 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_2 & ~_T_1269) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1257 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & same_cycle_resp & _T_2 & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1279 & (_T_1257 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & same_cycle_resp & _T_2 & ~_T_1279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1287 & (_T_1257 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~same_cycle_resp & _T_2 & ~_T_1287) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1291 & (_T_1257 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~same_cycle_resp & _T_2 & ~_T_1291) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1303 & (_T_1301 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1301 & _T_2 & ~_T_1303) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1310 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1310) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1319 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1319) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1353 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1353) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1363 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1363) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[3:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[7:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_19[7:0];
+ _RAND_20 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_20[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_6(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [3:0] io_enq_bits_size,
+ input io_enq_bits_source,
+ input [31:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [3:0] io_deq_bits_size,
+ output io_deq_bits_source,
+ output [31:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [31:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_address_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_address_io_deq_bits_MPORT_addr = value_1;
+ assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_address_MPORT_data = io_enq_bits_address;
+ assign ram_address_MPORT_addr = value;
+ assign ram_address_MPORT_mask = 1'h1;
+ assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = value_1;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = value;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
+ ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[3:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_address[initvar] = _RAND_4[31:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_5[7:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_7(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [1:0] io_enq_bits_param,
+ input [3:0] io_enq_bits_size,
+ input io_enq_bits_source,
+ input io_enq_bits_sink,
+ input io_enq_bits_denied,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [1:0] io_deq_bits_param,
+ output [3:0] io_deq_bits_size,
+ output io_deq_bits_source,
+ output io_deq_bits_sink,
+ output io_deq_bits_denied,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [1:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_sink [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_denied [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_sink_io_deq_bits_MPORT_addr = value_1;
+ assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_sink_MPORT_data = io_enq_bits_sink;
+ assign ram_sink_MPORT_addr = value;
+ assign ram_sink_MPORT_mask = 1'h1;
+ assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_denied_io_deq_bits_MPORT_addr = value_1;
+ assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_denied_MPORT_data = io_enq_bits_denied;
+ assign ram_denied_MPORT_addr = value;
+ assign ram_denied_MPORT_mask = 1'h1;
+ assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
+ ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
+ ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[3:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_sink[initvar] = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_denied[initvar] = _RAND_5[0:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_6(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_22 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_6 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_7 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_23(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_17 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_20 = _T_17 & _source_ok_T; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_26 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_28 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_29 = {1'b0,$signed(_T_28)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_31 = $signed(_T_29) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_32 = $signed(_T_31) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_33 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_36 = $signed(_T_34) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_38 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_39 = {1'b0,$signed(_T_38)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_41 = $signed(_T_39) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_42 = $signed(_T_41) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_43 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_44 = {1'b0,$signed(_T_43)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_46 = $signed(_T_44) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_47 = $signed(_T_46) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_48 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_51 = $signed(_T_49) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_52 = $signed(_T_51) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_53 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_54 = {1'b0,$signed(_T_53)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_56 = $signed(_T_54) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_57 = $signed(_T_56) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_58 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_59 = {1'b0,$signed(_T_58)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_61 = $signed(_T_59) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_62 = $signed(_T_61) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_63 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_66 = $signed(_T_64) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_67 = $signed(_T_66) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_68 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_71 = $signed(_T_69) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_72 = $signed(_T_71) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_73 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_76 = $signed(_T_74) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_77 = $signed(_T_76) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_78 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_79 = {1'b0,$signed(_T_78)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_81 = $signed(_T_79) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_82 = $signed(_T_81) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_191 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_195 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_196 = _T_195 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_200 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_204 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_384 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_397 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_416 = _T_17 & _T_32; // @[Parameters.scala 670:56]
+ wire _T_418 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_485 = _T_27 | _T_37 | _T_42 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_77 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_486 = _T_418 & _T_485; // @[Parameters.scala 670:56]
+ wire _T_488 = _T_416 | _T_486; // @[Parameters.scala 672:30]
+ wire _T_498 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_502 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_510 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_577 = _T_27 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_578 = _T_418 & _T_577; // @[Parameters.scala 670:56]
+ wire _T_599 = _T_416 | _T_578; // @[Parameters.scala 672:30]
+ wire _T_601 = _T_20 & _T_599; // @[Monitor.scala 115:71]
+ wire _T_619 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_724 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_725 = io_in_a_bits_mask & _T_724; // @[Monitor.scala 127:31]
+ wire _T_726 = _T_725 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_730 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_738 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_793 = _T_27 | _T_32 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_794 = _T_738 & _T_793; // @[Parameters.scala 670:56]
+ wire _T_816 = _T_20 & _T_794; // @[Monitor.scala 131:74]
+ wire _T_826 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_834 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_930 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_938 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1024 = _T_20 & _T_416; // @[Monitor.scala 147:68]
+ wire _T_1034 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1046 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
+ wire _T_1050 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1054 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1058 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1062 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1066 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1070 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1081 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1085 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1098 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1118 = _T_1066 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1127 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1144 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1162 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1192 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1193 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1197 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1201 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1205 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1209 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1216 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1217 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1221 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1225 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1229 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1233 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1237 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [2:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [3:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_75 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1243 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1246 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [2:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [19:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire _T_1250 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1254 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1256 = ~_T_1050; // @[Monitor.scala 671:74]
+ wire _T_1257 = io_in_d_valid & d_first_1 & ~_T_1050; // @[Monitor.scala 671:71]
+ wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1050 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _GEN_3 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [30:0] _GEN_4 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [30:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_1256 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1256 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1256 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1243 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire _T_1269 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1274 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1275 = io_in_d_bits_opcode == _GEN_32 | _T_1274; // @[Monitor.scala 685:77]
+ wire _T_1279 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1286 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1287 = io_in_d_bits_opcode == _GEN_48 | _T_1286; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1291 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1301 = _T_1254 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1256; // @[Monitor.scala 694:116]
+ wire _T_1303 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set_wo_ready = _GEN_15[0];
+ wire d_clr_wo_ready = _GEN_21[0];
+ wire _T_1310 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [7:0] a_sizes_set = _GEN_20[7:0];
+ wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [7:0] d_sizes_clr = _GEN_24[7:0];
+ wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1319 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [15:0] _GEN_83 = {{8'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_83 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1345 = io_in_d_valid & d_first_2 & _T_1050; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1050 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire _T_1353 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1363 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
+ wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_384 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_384) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_20 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_20) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_488 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_488) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_726 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_726) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_826 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_826) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_930 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_930) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1024 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1024) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1034 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1034) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_200 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_200) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1046 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1046) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1066 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1066) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1193 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1193) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1197 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1201 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1201) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1205 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1205) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1209 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1209) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1217 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1217) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1221 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1221) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1225 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1225) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1229 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1233 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1237 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1237) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1246 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1246 & ~reset & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1269 & (_T_1257 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_2 & ~_T_1269) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1257 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & same_cycle_resp & _T_2 & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1279 & (_T_1257 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & same_cycle_resp & _T_2 & ~_T_1279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1287 & (_T_1257 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~same_cycle_resp & _T_2 & ~_T_1287) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1291 & (_T_1257 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~same_cycle_resp & _T_2 & ~_T_1291) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1303 & (_T_1301 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1301 & _T_2 & ~_T_1303) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1310 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1310) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 6 (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1319 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1319) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1353 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1353) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1363 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1363) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at SerialAdapter.scala:390:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[3:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[7:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_19[7:0];
+ _RAND_20 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_20[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_7(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_23 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_6 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_7 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLInterconnectCoupler_14(
+ input clock,
+ input reset,
+ output auto_buffer_in_a_ready,
+ input auto_buffer_in_a_valid,
+ input [2:0] auto_buffer_in_a_bits_opcode,
+ input [2:0] auto_buffer_in_a_bits_param,
+ input [3:0] auto_buffer_in_a_bits_size,
+ input auto_buffer_in_a_bits_source,
+ input [31:0] auto_buffer_in_a_bits_address,
+ input [7:0] auto_buffer_in_a_bits_mask,
+ input [63:0] auto_buffer_in_a_bits_data,
+ input auto_buffer_in_a_bits_corrupt,
+ input auto_buffer_in_d_ready,
+ output auto_buffer_in_d_valid,
+ output [2:0] auto_buffer_in_d_bits_opcode,
+ output [1:0] auto_buffer_in_d_bits_param,
+ output [3:0] auto_buffer_in_d_bits_size,
+ output auto_buffer_in_d_bits_source,
+ output auto_buffer_in_d_bits_sink,
+ output auto_buffer_in_d_bits_denied,
+ output [63:0] auto_buffer_in_d_bits_data,
+ output auto_buffer_in_d_bits_corrupt,
+ input auto_tl_out_a_ready,
+ output auto_tl_out_a_valid,
+ output [2:0] auto_tl_out_a_bits_opcode,
+ output [2:0] auto_tl_out_a_bits_param,
+ output [3:0] auto_tl_out_a_bits_size,
+ output auto_tl_out_a_bits_source,
+ output [31:0] auto_tl_out_a_bits_address,
+ output [7:0] auto_tl_out_a_bits_mask,
+ output [63:0] auto_tl_out_a_bits_data,
+ output auto_tl_out_a_bits_corrupt,
+ output auto_tl_out_d_ready,
+ input auto_tl_out_d_valid,
+ input [2:0] auto_tl_out_d_bits_opcode,
+ input [1:0] auto_tl_out_d_bits_param,
+ input [3:0] auto_tl_out_d_bits_size,
+ input auto_tl_out_d_bits_sink,
+ input auto_tl_out_d_bits_denied,
+ input [63:0] auto_tl_out_d_bits_data,
+ input auto_tl_out_d_bits_corrupt
+);
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ TLBuffer_7 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
+ );
+ assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign auto_tl_out_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_out_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_clock = clock;
+ assign buffer_reset = reset;
+ assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_data = auto_buffer_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = auto_tl_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_valid = auto_tl_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_opcode = auto_tl_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_param = auto_tl_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_size = auto_tl_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_sink = auto_tl_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_denied = auto_tl_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_data = auto_tl_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_corrupt = auto_tl_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module FrontBus(
+ output auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready,
+ input auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_valid,
+ input [2:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_opcode,
+ input [2:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_param,
+ input [3:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_size,
+ input auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_source,
+ input [31:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_address,
+ input [7:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_mask,
+ input [63:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_data,
+ input auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_corrupt,
+ input auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_ready,
+ output auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid,
+ output [2:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode,
+ output [1:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param,
+ output [3:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size,
+ output auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source,
+ output auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink,
+ output auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied,
+ output [63:0] auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data,
+ output auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt,
+ output auto_fixedClockNode_out_clock,
+ output auto_fixedClockNode_out_reset,
+ input auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock,
+ input auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset,
+ input auto_bus_xing_out_a_ready,
+ output auto_bus_xing_out_a_valid,
+ output [2:0] auto_bus_xing_out_a_bits_opcode,
+ output [2:0] auto_bus_xing_out_a_bits_param,
+ output [3:0] auto_bus_xing_out_a_bits_size,
+ output auto_bus_xing_out_a_bits_source,
+ output [31:0] auto_bus_xing_out_a_bits_address,
+ output [7:0] auto_bus_xing_out_a_bits_mask,
+ output [63:0] auto_bus_xing_out_a_bits_data,
+ output auto_bus_xing_out_a_bits_corrupt,
+ output auto_bus_xing_out_d_ready,
+ input auto_bus_xing_out_d_valid,
+ input [2:0] auto_bus_xing_out_d_bits_opcode,
+ input [1:0] auto_bus_xing_out_d_bits_param,
+ input [3:0] auto_bus_xing_out_d_bits_size,
+ input auto_bus_xing_out_d_bits_sink,
+ input auto_bus_xing_out_d_bits_denied,
+ input [63:0] auto_bus_xing_out_d_bits_data,
+ input auto_bus_xing_out_d_bits_corrupt
+);
+ wire subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_clock; // @[BusWrapper.scala 40:48]
+ wire subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_reset; // @[BusWrapper.scala 40:48]
+ wire subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_clock; // @[BusWrapper.scala 40:48]
+ wire subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_reset; // @[BusWrapper.scala 40:48]
+ wire clockGroup_auto_in_member_subsystem_fbus_0_clock; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_in_member_subsystem_fbus_0_reset; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
+ wire fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_1_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_1_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_0_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_0_reset; // @[ClockGroup.scala 106:107]
+ wire subsystem_fbus_xbar_auto_in_a_ready; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_in_a_valid; // @[BusWrapper.scala 372:32]
+ wire [2:0] subsystem_fbus_xbar_auto_in_a_bits_opcode; // @[BusWrapper.scala 372:32]
+ wire [2:0] subsystem_fbus_xbar_auto_in_a_bits_param; // @[BusWrapper.scala 372:32]
+ wire [3:0] subsystem_fbus_xbar_auto_in_a_bits_size; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_in_a_bits_source; // @[BusWrapper.scala 372:32]
+ wire [31:0] subsystem_fbus_xbar_auto_in_a_bits_address; // @[BusWrapper.scala 372:32]
+ wire [7:0] subsystem_fbus_xbar_auto_in_a_bits_mask; // @[BusWrapper.scala 372:32]
+ wire [63:0] subsystem_fbus_xbar_auto_in_a_bits_data; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_in_a_bits_corrupt; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_in_d_ready; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_in_d_valid; // @[BusWrapper.scala 372:32]
+ wire [2:0] subsystem_fbus_xbar_auto_in_d_bits_opcode; // @[BusWrapper.scala 372:32]
+ wire [1:0] subsystem_fbus_xbar_auto_in_d_bits_param; // @[BusWrapper.scala 372:32]
+ wire [3:0] subsystem_fbus_xbar_auto_in_d_bits_size; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_in_d_bits_sink; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_in_d_bits_denied; // @[BusWrapper.scala 372:32]
+ wire [63:0] subsystem_fbus_xbar_auto_in_d_bits_data; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_in_d_bits_corrupt; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_a_ready; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_a_valid; // @[BusWrapper.scala 372:32]
+ wire [2:0] subsystem_fbus_xbar_auto_out_a_bits_opcode; // @[BusWrapper.scala 372:32]
+ wire [2:0] subsystem_fbus_xbar_auto_out_a_bits_param; // @[BusWrapper.scala 372:32]
+ wire [3:0] subsystem_fbus_xbar_auto_out_a_bits_size; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_a_bits_source; // @[BusWrapper.scala 372:32]
+ wire [31:0] subsystem_fbus_xbar_auto_out_a_bits_address; // @[BusWrapper.scala 372:32]
+ wire [7:0] subsystem_fbus_xbar_auto_out_a_bits_mask; // @[BusWrapper.scala 372:32]
+ wire [63:0] subsystem_fbus_xbar_auto_out_a_bits_data; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_a_bits_corrupt; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_d_ready; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_d_valid; // @[BusWrapper.scala 372:32]
+ wire [2:0] subsystem_fbus_xbar_auto_out_d_bits_opcode; // @[BusWrapper.scala 372:32]
+ wire [1:0] subsystem_fbus_xbar_auto_out_d_bits_param; // @[BusWrapper.scala 372:32]
+ wire [3:0] subsystem_fbus_xbar_auto_out_d_bits_size; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_d_bits_sink; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_d_bits_denied; // @[BusWrapper.scala 372:32]
+ wire [63:0] subsystem_fbus_xbar_auto_out_d_bits_data; // @[BusWrapper.scala 372:32]
+ wire subsystem_fbus_xbar_auto_out_d_bits_corrupt; // @[BusWrapper.scala 372:32]
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire coupler_from_port_named_serial_tl_ctrl_clock; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_reset; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ ClockGroupAggregator_2 subsystem_fbus_clock_groups ( // @[BusWrapper.scala 40:48]
+ .auto_in_member_subsystem_fbus_0_clock(subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_clock),
+ .auto_in_member_subsystem_fbus_0_reset(subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_reset),
+ .auto_out_member_subsystem_fbus_0_clock(subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_clock),
+ .auto_out_member_subsystem_fbus_0_reset(subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_reset)
+ );
+ ClockGroup_2 clockGroup ( // @[BusWrapper.scala 41:38]
+ .auto_in_member_subsystem_fbus_0_clock(clockGroup_auto_in_member_subsystem_fbus_0_clock),
+ .auto_in_member_subsystem_fbus_0_reset(clockGroup_auto_in_member_subsystem_fbus_0_reset),
+ .auto_out_clock(clockGroup_auto_out_clock),
+ .auto_out_reset(clockGroup_auto_out_reset)
+ );
+ FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala 106:107]
+ .auto_in_clock(fixedClockNode_auto_in_clock),
+ .auto_in_reset(fixedClockNode_auto_in_reset),
+ .auto_out_1_clock(fixedClockNode_auto_out_1_clock),
+ .auto_out_1_reset(fixedClockNode_auto_out_1_reset),
+ .auto_out_0_clock(fixedClockNode_auto_out_0_clock),
+ .auto_out_0_reset(fixedClockNode_auto_out_0_reset)
+ );
+ TLXbar_3 subsystem_fbus_xbar ( // @[BusWrapper.scala 372:32]
+ .auto_in_a_ready(subsystem_fbus_xbar_auto_in_a_ready),
+ .auto_in_a_valid(subsystem_fbus_xbar_auto_in_a_valid),
+ .auto_in_a_bits_opcode(subsystem_fbus_xbar_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(subsystem_fbus_xbar_auto_in_a_bits_param),
+ .auto_in_a_bits_size(subsystem_fbus_xbar_auto_in_a_bits_size),
+ .auto_in_a_bits_source(subsystem_fbus_xbar_auto_in_a_bits_source),
+ .auto_in_a_bits_address(subsystem_fbus_xbar_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(subsystem_fbus_xbar_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(subsystem_fbus_xbar_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(subsystem_fbus_xbar_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(subsystem_fbus_xbar_auto_in_d_ready),
+ .auto_in_d_valid(subsystem_fbus_xbar_auto_in_d_valid),
+ .auto_in_d_bits_opcode(subsystem_fbus_xbar_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(subsystem_fbus_xbar_auto_in_d_bits_param),
+ .auto_in_d_bits_size(subsystem_fbus_xbar_auto_in_d_bits_size),
+ .auto_in_d_bits_sink(subsystem_fbus_xbar_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(subsystem_fbus_xbar_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(subsystem_fbus_xbar_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(subsystem_fbus_xbar_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(subsystem_fbus_xbar_auto_out_a_ready),
+ .auto_out_a_valid(subsystem_fbus_xbar_auto_out_a_valid),
+ .auto_out_a_bits_opcode(subsystem_fbus_xbar_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(subsystem_fbus_xbar_auto_out_a_bits_param),
+ .auto_out_a_bits_size(subsystem_fbus_xbar_auto_out_a_bits_size),
+ .auto_out_a_bits_source(subsystem_fbus_xbar_auto_out_a_bits_source),
+ .auto_out_a_bits_address(subsystem_fbus_xbar_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(subsystem_fbus_xbar_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(subsystem_fbus_xbar_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(subsystem_fbus_xbar_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(subsystem_fbus_xbar_auto_out_d_ready),
+ .auto_out_d_valid(subsystem_fbus_xbar_auto_out_d_valid),
+ .auto_out_d_bits_opcode(subsystem_fbus_xbar_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(subsystem_fbus_xbar_auto_out_d_bits_param),
+ .auto_out_d_bits_size(subsystem_fbus_xbar_auto_out_d_bits_size),
+ .auto_out_d_bits_sink(subsystem_fbus_xbar_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(subsystem_fbus_xbar_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(subsystem_fbus_xbar_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(subsystem_fbus_xbar_auto_out_d_bits_corrupt)
+ );
+ TLBuffer_6 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
+ );
+ TLInterconnectCoupler_14 coupler_from_port_named_serial_tl_ctrl ( // @[LazyModule.scala 432:27]
+ .clock(coupler_from_port_named_serial_tl_ctrl_clock),
+ .reset(coupler_from_port_named_serial_tl_ctrl_reset),
+ .auto_buffer_in_a_ready(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_ready),
+ .auto_buffer_in_a_valid(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_valid),
+ .auto_buffer_in_a_bits_opcode(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_opcode),
+ .auto_buffer_in_a_bits_param(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_param),
+ .auto_buffer_in_a_bits_size(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_size),
+ .auto_buffer_in_a_bits_source(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_source),
+ .auto_buffer_in_a_bits_address(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_address),
+ .auto_buffer_in_a_bits_mask(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_mask),
+ .auto_buffer_in_a_bits_data(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_data),
+ .auto_buffer_in_a_bits_corrupt(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_corrupt),
+ .auto_buffer_in_d_ready(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_ready),
+ .auto_buffer_in_d_valid(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_valid),
+ .auto_buffer_in_d_bits_opcode(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_opcode),
+ .auto_buffer_in_d_bits_param(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_param),
+ .auto_buffer_in_d_bits_size(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_size),
+ .auto_buffer_in_d_bits_source(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_source),
+ .auto_buffer_in_d_bits_sink(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_sink),
+ .auto_buffer_in_d_bits_denied(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_denied),
+ .auto_buffer_in_d_bits_data(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_data),
+ .auto_buffer_in_d_bits_corrupt(coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_corrupt),
+ .auto_tl_out_a_ready(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_ready),
+ .auto_tl_out_a_valid(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_valid),
+ .auto_tl_out_a_bits_opcode(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_opcode),
+ .auto_tl_out_a_bits_param(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_param),
+ .auto_tl_out_a_bits_size(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_size),
+ .auto_tl_out_a_bits_source(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_source),
+ .auto_tl_out_a_bits_address(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_address),
+ .auto_tl_out_a_bits_mask(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_mask),
+ .auto_tl_out_a_bits_data(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_data),
+ .auto_tl_out_a_bits_corrupt(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_corrupt),
+ .auto_tl_out_d_ready(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_ready),
+ .auto_tl_out_d_valid(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_valid),
+ .auto_tl_out_d_bits_opcode(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_opcode),
+ .auto_tl_out_d_bits_param(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_param),
+ .auto_tl_out_d_bits_size(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_size),
+ .auto_tl_out_d_bits_sink(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_sink),
+ .auto_tl_out_d_bits_denied(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_denied),
+ .auto_tl_out_d_bits_data(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_data),
+ .auto_tl_out_d_bits_corrupt(coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_corrupt)
+ );
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt =
+ coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign auto_fixedClockNode_out_clock = fixedClockNode_auto_out_1_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_reset = fixedClockNode_auto_out_1_reset; // @[LazyModule.scala 311:12]
+ assign auto_bus_xing_out_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_clock =
+ auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock; // @[LazyModule.scala 309:16]
+ assign subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_reset =
+ auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset; // @[LazyModule.scala 309:16]
+ assign clockGroup_auto_in_member_subsystem_fbus_0_clock =
+ subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_clock; // @[LazyModule.scala 298:16]
+ assign clockGroup_auto_in_member_subsystem_fbus_0_reset =
+ subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_reset; // @[LazyModule.scala 298:16]
+ assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
+ assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_in_a_valid = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_valid; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_a_bits_opcode = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_a_bits_param = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_a_bits_size = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_a_bits_source = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_a_bits_address = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_a_bits_mask = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_a_bits_data = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_a_bits_corrupt = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_in_d_ready = coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_ready; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_xbar_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_fbus_xbar_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign buffer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_in_a_valid = subsystem_fbus_xbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_opcode = subsystem_fbus_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_param = subsystem_fbus_xbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_size = subsystem_fbus_xbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_source = subsystem_fbus_xbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_address = subsystem_fbus_xbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_mask = subsystem_fbus_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_data = subsystem_fbus_xbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_corrupt = subsystem_fbus_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_d_ready = subsystem_fbus_xbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign coupler_from_port_named_serial_tl_ctrl_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_valid =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_valid; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_opcode =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_param =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_size =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_source =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_address =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_mask =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_data =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_a_bits_corrupt =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_buffer_in_d_ready =
+ auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_ready; // @[LazyModule.scala 309:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_a_ready = subsystem_fbus_xbar_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_valid = subsystem_fbus_xbar_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_opcode = subsystem_fbus_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_param = subsystem_fbus_xbar_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_size = subsystem_fbus_xbar_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_sink = subsystem_fbus_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_denied = subsystem_fbus_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_data = subsystem_fbus_xbar_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_serial_tl_ctrl_auto_tl_out_d_bits_corrupt = subsystem_fbus_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+endmodule
+module ClockGroupAggregator_3(
+ input auto_in_member_subsystem_cbus_0_clock,
+ input auto_in_member_subsystem_cbus_0_reset,
+ output auto_out_member_subsystem_cbus_0_clock,
+ output auto_out_member_subsystem_cbus_0_reset
+);
+ assign auto_out_member_subsystem_cbus_0_clock = auto_in_member_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_subsystem_cbus_0_reset = auto_in_member_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockGroup_3(
+ input auto_in_member_subsystem_cbus_0_clock,
+ input auto_in_member_subsystem_cbus_0_reset,
+ output auto_out_clock,
+ output auto_out_reset
+);
+ assign auto_out_clock = auto_in_member_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_reset = auto_in_member_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_24(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [63:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [63:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_44 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_53 = _T_44 & source_ok; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_59 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_61 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_64 = $signed(_T_62) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_66 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_69 = $signed(_T_67) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_71 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_74 = $signed(_T_72) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_76 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_79 = $signed(_T_77) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_81 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_84 = $signed(_T_82) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_86 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_87 = {1'b0,$signed(_T_86)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_89 = $signed(_T_87) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_90 = $signed(_T_89) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_91 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_92 = {1'b0,$signed(_T_91)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_94 = $signed(_T_92) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_95 = $signed(_T_94) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_96 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_97 = {1'b0,$signed(_T_96)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_99 = $signed(_T_97) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_100 = $signed(_T_99) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_101 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_102 = {1'b0,$signed(_T_101)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_104 = $signed(_T_102) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_105 = $signed(_T_104) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_106 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_107 = {1'b0,$signed(_T_106)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_109 = $signed(_T_107) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_110 = $signed(_T_109) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_111 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_112 = {1'b0,$signed(_T_111)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_114 = $signed(_T_112) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_115 = $signed(_T_114) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_224 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_228 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_229 = _T_228 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_233 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_237 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_423 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_436 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_461 = _T_44 & _T_65; // @[Parameters.scala 670:56]
+ wire _T_463 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_530 = _T_60 | _T_70 | _T_75 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_110 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_531 = _T_463 & _T_530; // @[Parameters.scala 670:56]
+ wire _T_533 = _T_461 | _T_531; // @[Parameters.scala 672:30]
+ wire _T_543 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_547 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_555 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_628 = _T_60 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_629 = _T_463 & _T_628; // @[Parameters.scala 670:56]
+ wire _T_650 = _T_461 | _T_629; // @[Parameters.scala 672:30]
+ wire _T_652 = _T_53 & _T_650; // @[Monitor.scala 115:71]
+ wire _T_670 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_781 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_782 = io_in_a_bits_mask & _T_781; // @[Monitor.scala 127:31]
+ wire _T_783 = _T_782 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_787 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_801 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire [31:0] _T_809 = io_in_a_bits_address ^ 32'h4000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_810 = {1'b0,$signed(_T_809)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_812 = $signed(_T_810) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_813 = $signed(_T_812) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_832 = _T_65 | _T_813 | _T_95 | _T_100 | _T_105; // @[Parameters.scala 671:42]
+ wire _T_833 = _T_801 & _T_832; // @[Parameters.scala 670:56]
+ wire _T_879 = 4'h2 <= io_in_a_bits_size & io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:37]
+ wire _T_886 = _T_879 & _T_115; // @[Parameters.scala 670:56]
+ wire _T_889 = _T_833 | _T_886; // @[Parameters.scala 672:30]
+ wire _T_890 = _T_53 & _T_889; // @[Monitor.scala 131:74]
+ wire _T_900 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_908 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_1021 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_1029 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1121 = _T_53 & _T_461; // @[Monitor.scala 147:68]
+ wire _T_1131 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1143 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_1147 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1151 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1155 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1159 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1163 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1167 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1178 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1182 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1195 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1215 = _T_1163 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1224 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1241 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1259 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1289 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1290 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1294 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1298 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1302 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1306 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1313 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1314 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1318 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1322 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1326 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1330 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1334 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [39:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [5:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [39:0] _GEN_75 = {{24'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala 638:144]
+ wire _T_1340 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_1343 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [5:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [67:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [67:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_1345 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_1347 = ~_T_1345[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [67:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 68'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1351 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1353 = ~_T_1147; // @[Monitor.scala 671:74]
+ wire _T_1354 = io_in_d_valid & d_first_1 & ~_T_1147; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [78:0] _GEN_4 = {{63'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [78:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_1353 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_1353 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire [78:0] _GEN_24 = _d_first_T & d_first_1 & _T_1353 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1340 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_1364 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_1366 = _T_1364[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1371 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1372 = io_in_d_bits_opcode == _GEN_32 | _T_1371; // @[Monitor.scala 685:77]
+ wire _T_1376 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1383 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1384 = io_in_d_bits_opcode == _GEN_48 | _T_1383; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1388 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1398 = _T_1351 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1353; // @[Monitor.scala 694:116]
+ wire _T_1400 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [39:0] a_sizes_set = _GEN_20[39:0];
+ wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [39:0] d_sizes_clr = _GEN_24[39:0];
+ wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1409 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [39:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [39:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
+ wire [39:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala 747:146]
+ wire _T_1435 = io_in_d_valid & d_first_2 & _T_1147; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_1147 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_69 = _d_first_T & d_first_2 & _T_1147 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 786:21]
+ wire [4:0] _T_1443 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1453 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [39:0] d_sizes_clr_1 = _GEN_69[39:0];
+ wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [39:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1473 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 40'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 40'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_224 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_224) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_229 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_224 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_224) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_423 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_423) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_229 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_53 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_53) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_533 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_533) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_652 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_652) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_652 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_652) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_783 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_783) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_900 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_900) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1021 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_1021) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1121 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_1121) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1131 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_1131) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1163 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1163) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1178 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1178) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1182 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1182) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1178 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1178) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1182 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1182) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1215 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1215) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1215 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~_T_1215) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1290 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1290) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1294 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1294) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1298 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1298) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1302 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1306 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1306) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1314 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1314) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1318 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1318) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1322 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1322) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1326 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1326) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1330 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1330) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1334 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1334) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1347 & (_T_1343 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1343 & ~reset & ~_T_1347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1366 & (_T_1354 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & _T_2 & ~_T_1366) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1372 & (_T_1354 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & same_cycle_resp & _T_2 & ~_T_1372) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1376 & (_T_1354 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & same_cycle_resp & _T_2 & ~_T_1376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1384 & (_T_1354 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & ~same_cycle_resp & _T_2 & ~_T_1384) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1388 & (_T_1354 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & ~same_cycle_resp & _T_2 & ~_T_1388) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1400 & (_T_1398 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1398 & _T_2 & ~_T_1400) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1409 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1443[0] & (_T_1435 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1435 & _T_2 & ~_T_1443[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1453 & (_T_1435 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1435 & _T_2 & ~_T_1453) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1473 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1473) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:54:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {2{`RANDOM}};
+ inflight_sizes = _RAND_15[39:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {2{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[39:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFIFOFixer_2(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ TLMonitor_24 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[FIFOFixer.scala 87:33]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_25(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input [1:0] io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input [1:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_48 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_49 = $signed(_T_48) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_50 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_53 = $signed(_T_51) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_54 = $signed(_T_53) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_55 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_58 = $signed(_T_56) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_59 = $signed(_T_58) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_60 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_63 = $signed(_T_61) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_64 = $signed(_T_63) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_65 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_68 = $signed(_T_66) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_69 = $signed(_T_68) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_70 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_73 = $signed(_T_71) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_74 = $signed(_T_73) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_75 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_78 = $signed(_T_76) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_79 = $signed(_T_78) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_80 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_83 = $signed(_T_81) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_84 = $signed(_T_83) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_85 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_88 = $signed(_T_86) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_89 = $signed(_T_88) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_90 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_93 = $signed(_T_91) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_94 = $signed(_T_93) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_95 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_98 = $signed(_T_96) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_99 = $signed(_T_98) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_100 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_103 = $signed(_T_101) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_104 = $signed(_T_103) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_213 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_217 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_218 = _T_217 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_222 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_226 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_410 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_423 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_446 = _T_35 & _T_54; // @[Parameters.scala 670:56]
+ wire _T_448 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_515 = _T_49 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104; // @[Parameters.scala 671:42]
+ wire _T_516 = _T_448 & _T_515; // @[Parameters.scala 670:56]
+ wire _T_518 = _T_446 | _T_516; // @[Parameters.scala 672:30]
+ wire _T_528 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_532 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_540 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_611 = _T_49 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_104; // @[Parameters.scala 671:42]
+ wire _T_612 = _T_448 & _T_611; // @[Parameters.scala 670:56]
+ wire _T_633 = _T_446 | _T_612; // @[Parameters.scala 672:30]
+ wire _T_635 = _T_42 & _T_633; // @[Monitor.scala 115:71]
+ wire _T_653 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_762 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_763 = io_in_a_bits_mask & _T_762; // @[Monitor.scala 127:31]
+ wire _T_764 = _T_763 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_768 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_780 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_835 = _T_49 | _T_54 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_104; // @[Parameters.scala 671:42]
+ wire _T_836 = _T_780 & _T_835; // @[Parameters.scala 670:56]
+ wire _T_858 = _T_42 & _T_836; // @[Monitor.scala 131:74]
+ wire _T_868 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_876 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_976 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_984 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1074 = _T_42 & _T_446; // @[Monitor.scala 147:68]
+ wire _T_1084 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1096 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_4 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_6 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
+ wire _T_1100 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1104 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1108 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1112 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1116 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1120 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1131 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1135 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1148 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1168 = _T_1116 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1177 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1194 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1212 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg [1:0] source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1242 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1243 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1247 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1251 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1255 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1259 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg [1:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1266 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1267 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1271 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1275 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1279 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1283 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1287 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [2:0] inflight; // @[Monitor.scala 611:27]
+ reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [23:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
+ wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
+ wire _T_1293 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1296 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [3:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [2:0] _T_1298 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_1300 = ~_T_1298[0]; // @[Monitor.scala 658:17]
+ wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
+ wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
+ wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1304 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1306 = ~_T_1100; // @[Monitor.scala 671:74]
+ wire _T_1307 = io_in_d_valid & d_first_1 & ~_T_1100; // @[Monitor.scala 671:71]
+ wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1100 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
+ wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1306 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
+ wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1306 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
+ wire [46:0] _GEN_24 = _d_first_T & d_first_1 & _T_1306 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1293 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [2:0] _T_1317 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_1319 = _T_1317[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1324 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1325 = io_in_d_bits_opcode == _GEN_32 | _T_1324; // @[Monitor.scala 685:77]
+ wire _T_1329 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1336 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1337 = io_in_d_bits_opcode == _GEN_48 | _T_1336; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1341 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1351 = _T_1304 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1306; // @[Monitor.scala 694:116]
+ wire _T_1353 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [2:0] a_set_wo_ready = _GEN_15[2:0];
+ wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
+ wire _T_1360 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [2:0] a_set = _GEN_16[2:0];
+ wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [2:0] d_clr = _GEN_22[2:0];
+ wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [11:0] a_opcodes_set = _GEN_19[11:0];
+ wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [11:0] d_opcodes_clr = _GEN_23[11:0];
+ wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [23:0] a_sizes_set = _GEN_20[23:0];
+ wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [23:0] d_sizes_clr = _GEN_24[23:0];
+ wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1369 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [2:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
+ wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
+ wire _T_1395 = io_in_d_valid & d_first_2 & _T_1100; // @[Monitor.scala 779:71]
+ wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_1100 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
+ wire [46:0] _GEN_69 = _d_first_T & d_first_2 & _T_1100 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
+ wire [2:0] _T_1403 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1413 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [2:0] d_clr_1 = _GEN_67[2:0];
+ wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [23:0] d_sizes_clr_1 = _GEN_69[23:0];
+ wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [23:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1438 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 3'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_213 & (io_in_a_valid & _T_33 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset & ~_T_213) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_33 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_222 & (io_in_a_valid & _T_33 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_33 & ~reset & ~_T_222) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_226 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_226 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_226 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_213 & (io_in_a_valid & _T_226 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset & ~_T_213) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_410 & (io_in_a_valid & _T_226 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset & ~_T_410) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_226 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_222 & (io_in_a_valid & _T_226 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_226 & ~reset & ~_T_222) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_42 & (io_in_a_valid & _T_423 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_423 & ~reset & ~_T_42) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_518 & (io_in_a_valid & _T_423 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_423 & ~reset & ~_T_518) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_423 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_423 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_423 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_423 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_528 & (io_in_a_valid & _T_423 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_423 & ~reset & ~_T_528) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_532 & (io_in_a_valid & _T_423 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_423 & ~reset & ~_T_532) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_222 & (io_in_a_valid & _T_423 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_423 & ~reset & ~_T_222) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_635 & (io_in_a_valid & _T_540 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_540 & ~reset & ~_T_635) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_540 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_540 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_540 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_540 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_528 & (io_in_a_valid & _T_540 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_540 & ~reset & ~_T_528) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_532 & (io_in_a_valid & _T_540 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_540 & ~reset & ~_T_532) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_635 & (io_in_a_valid & _T_653 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_653 & ~reset & ~_T_635) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_653 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_653 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_653 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_653 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_528 & (io_in_a_valid & _T_653 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_653 & ~reset & ~_T_528) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_764 & (io_in_a_valid & _T_653 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_653 & ~reset & ~_T_764) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_858 & (io_in_a_valid & _T_768 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_768 & ~reset & ~_T_858) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_768 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_768 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_768 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_768 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_868 & (io_in_a_valid & _T_768 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_768 & ~reset & ~_T_868) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_532 & (io_in_a_valid & _T_768 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_768 & ~reset & ~_T_532) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_858 & (io_in_a_valid & _T_876 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_876 & ~reset & ~_T_858) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_876 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_876 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_876 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_876 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_976 & (io_in_a_valid & _T_876 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_876 & ~reset & ~_T_976) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_532 & (io_in_a_valid & _T_876 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_876 & ~reset & ~_T_532) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1074 & (io_in_a_valid & _T_984 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_984 & ~reset & ~_T_1074) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_984 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_984 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_984 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_984 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1084 & (io_in_a_valid & _T_984 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_984 & ~reset & ~_T_1084) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_532 & (io_in_a_valid & _T_984 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_984 & ~reset & ~_T_532) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_222 & (io_in_a_valid & _T_984 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_984 & ~reset & ~_T_222) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1096 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1096) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1100 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1100 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1104 & (io_in_d_valid & _T_1100 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1100 & _T_2 & ~_T_1104) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1108 & (io_in_d_valid & _T_1100 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1100 & _T_2 & ~_T_1108) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1112 & (io_in_d_valid & _T_1100 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1100 & _T_2 & ~_T_1112) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1116 & (io_in_d_valid & _T_1100 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1100 & _T_2 & ~_T_1116) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1120 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1120 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1120 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1120 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1104 & (io_in_d_valid & _T_1120 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1120 & _T_2 & ~_T_1104) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1131 & (io_in_d_valid & _T_1120 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1120 & _T_2 & ~_T_1131) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1135 & (io_in_d_valid & _T_1120 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1120 & _T_2 & ~_T_1135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1112 & (io_in_d_valid & _T_1120 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1120 & _T_2 & ~_T_1112) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1148 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1148 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1148 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1148 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1104 & (io_in_d_valid & _T_1148 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1148 & _T_2 & ~_T_1104) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1131 & (io_in_d_valid & _T_1148 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1148 & _T_2 & ~_T_1131) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1135 & (io_in_d_valid & _T_1148 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1148 & _T_2 & ~_T_1135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1168 & (io_in_d_valid & _T_1148 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1148 & _T_2 & ~_T_1168) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1177 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1177 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1108 & (io_in_d_valid & _T_1177 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1177 & _T_2 & ~_T_1108) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1112 & (io_in_d_valid & _T_1177 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1177 & _T_2 & ~_T_1112) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1194 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1194 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1108 & (io_in_d_valid & _T_1194 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1194 & _T_2 & ~_T_1108) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1168 & (io_in_d_valid & _T_1194 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1194 & _T_2 & ~_T_1168) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1212 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1212 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1108 & (io_in_d_valid & _T_1212 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1212 & _T_2 & ~_T_1108) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1112 & (io_in_d_valid & _T_1212 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1212 & _T_2 & ~_T_1112) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1243 & (_T_1242 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1242 & ~reset & ~_T_1243) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1247 & (_T_1242 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1242 & ~reset & ~_T_1247) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1251 & (_T_1242 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1242 & ~reset & ~_T_1251) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1255 & (_T_1242 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1242 & ~reset & ~_T_1255) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1259 & (_T_1242 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1242 & ~reset & ~_T_1259) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1267 & (_T_1266 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1266 & _T_2 & ~_T_1267) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1271 & (_T_1266 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1266 & _T_2 & ~_T_1271) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1266 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1266 & _T_2 & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1279 & (_T_1266 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1266 & _T_2 & ~_T_1279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1283 & (_T_1266 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1266 & _T_2 & ~_T_1283) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1287 & (_T_1266 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1266 & _T_2 & ~_T_1287) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1300 & (_T_1296 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1296 & ~reset & ~_T_1300) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1319 & (_T_1307 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1307 & _T_2 & ~_T_1319) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1325 & (_T_1307 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1307 & same_cycle_resp & _T_2 & ~_T_1325) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1329 & (_T_1307 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1307 & same_cycle_resp & _T_2 & ~_T_1329) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1337 & (_T_1307 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1307 & ~same_cycle_resp & _T_2 & ~_T_1337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1341 & (_T_1307 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1307 & ~same_cycle_resp & _T_2 & ~_T_1341) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1353 & (_T_1351 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1351 & _T_2 & ~_T_1353) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1360 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1360) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1369 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1369) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1403[0] & (_T_1395 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1395 & _T_2 & ~_T_1403[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1413 & (_T_1395 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1395 & _T_2 & ~_T_1413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1438 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1438) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[1:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[1:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[11:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[23:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[2:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[23:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_26(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [31:0] io_in_a_bits_address,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & 32'h3; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_nbit | mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_nbit | mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_nbit | mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_nbit | mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_bit | mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_bit | mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_bit | mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_bit | mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_26 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_28 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_29 = {1'b0,$signed(_T_28)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_31 = $signed(_T_29) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_32 = $signed(_T_31) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_43 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_44 = {1'b0,$signed(_T_43)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_46 = $signed(_T_44) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_47 = $signed(_T_46) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_48 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_51 = $signed(_T_49) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_52 = $signed(_T_51) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_53 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_54 = {1'b0,$signed(_T_53)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_56 = $signed(_T_54) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_57 = $signed(_T_56) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_58 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_59 = {1'b0,$signed(_T_58)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_61 = $signed(_T_59) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_62 = $signed(_T_61) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_63 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_66 = $signed(_T_64) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_67 = $signed(_T_66) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_68 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_71 = $signed(_T_69) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_72 = $signed(_T_71) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_78 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_79 = {1'b0,$signed(_T_78)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_81 = $signed(_T_79) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_82 = $signed(_T_81) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_502 = 8'hf == mask; // @[Monitor.scala 110:30]
+ wire _T_577 = _T_27 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_599 = _T_32 | _T_577; // @[Parameters.scala 672:30]
+ wire _T_1046 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _T_1050 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1054 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1058 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1062 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1066 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1070 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1081 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1085 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1098 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1118 = _T_1066 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1127 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1144 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1162 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1192 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1209 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1216 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1217 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1221 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1225 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1233 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1237 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{8'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1243 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1246 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? 4'h1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [4:0] a_sizes_set_interm = a_first_done & a_first_1 ? 5'h5 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire _T_1250 = ~inflight; // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1254 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1256 = ~_T_1050; // @[Monitor.scala 671:74]
+ wire _T_1257 = io_in_d_valid & d_first_1 & ~_T_1050; // @[Monitor.scala 671:71]
+ wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1050 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_sizes_clr_T_5 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [30:0] _GEN_23 = _T_1257 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _T_1257 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire _T_1269 = inflight | _T_1243; // @[Monitor.scala 682:49]
+ wire _T_1275 = _T_1127 | _T_1127; // @[Monitor.scala 685:77]
+ wire _T_1279 = 4'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1286 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1287 = io_in_d_bits_opcode == _GEN_48 | _T_1286; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_75 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1291 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1301 = _T_1254 & a_first_1 & io_in_a_valid & _T_1256; // @[Monitor.scala 694:116]
+ wire a_set_wo_ready = _GEN_15[0];
+ wire d_clr_wo_ready = _GEN_21[0];
+ wire _T_1310 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire a_set = _GEN_16[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [7:0] a_sizes_set = _GEN_20[7:0];
+ wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [7:0] d_sizes_clr = _GEN_24[7:0];
+ wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1319 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _GEN_78 = {{8'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_78 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1345 = io_in_d_valid & d_first_2 & _T_1050; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_69 = _T_1345 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1363 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
+ wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 9'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr_wo_ready; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 9'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | io_in_d_valid) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_599 & (io_in_a_valid & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & ~reset & ~_T_599) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:91:33)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:91:33)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:91:33)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1046 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1046) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1066 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1066) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1209 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1209) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:91:33)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1217 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1217) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1221 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1221) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1225 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1225) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1233 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1237 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1237) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1246 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1246 & ~reset & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:91:33)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1269 & (_T_1257 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_2 & ~_T_1269) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1257 & _T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_1243 & _T_2 & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1279 & (_T_1257 & _T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_1243 & _T_2 & ~_T_1279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1287 & (_T_1257 & ~_T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~_T_1243 & _T_2 & ~_T_1287) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1291 & (_T_1257 & ~_T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~_T_1243 & _T_2 & ~_T_1291) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~io_in_a_ready & (_T_1301 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1301 & _T_2 & ~io_in_a_ready) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1310 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1310) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1319 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1319) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:91:33)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1363 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1363) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:91:33)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ address = _RAND_1[31:0];
+ _RAND_2 = {1{`RANDOM}};
+ d_first_counter = _RAND_2[8:0];
+ _RAND_3 = {1{`RANDOM}};
+ opcode_1 = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ param_1 = _RAND_4[1:0];
+ _RAND_5 = {1{`RANDOM}};
+ size_1 = _RAND_5[3:0];
+ _RAND_6 = {1{`RANDOM}};
+ sink = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ denied = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ inflight = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_sizes = _RAND_10[7:0];
+ _RAND_11 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_11[8:0];
+ _RAND_12 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_12[8:0];
+ _RAND_13 = {1{`RANDOM}};
+ watchdog = _RAND_13[31:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_14[7:0];
+ _RAND_15 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_15[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLXbar_4(
+ input clock,
+ input reset,
+ output auto_in_1_a_ready,
+ input auto_in_1_a_valid,
+ input [31:0] auto_in_1_a_bits_address,
+ input [63:0] auto_in_1_a_bits_data,
+ output auto_in_1_d_valid,
+ output auto_in_0_a_ready,
+ input auto_in_0_a_valid,
+ input [2:0] auto_in_0_a_bits_opcode,
+ input [2:0] auto_in_0_a_bits_param,
+ input [3:0] auto_in_0_a_bits_size,
+ input [1:0] auto_in_0_a_bits_source,
+ input [31:0] auto_in_0_a_bits_address,
+ input [7:0] auto_in_0_a_bits_mask,
+ input [63:0] auto_in_0_a_bits_data,
+ input auto_in_0_a_bits_corrupt,
+ input auto_in_0_d_ready,
+ output auto_in_0_d_valid,
+ output [2:0] auto_in_0_d_bits_opcode,
+ output [1:0] auto_in_0_d_bits_param,
+ output [3:0] auto_in_0_d_bits_size,
+ output [1:0] auto_in_0_d_bits_source,
+ output auto_in_0_d_bits_sink,
+ output auto_in_0_d_bits_denied,
+ output [63:0] auto_in_0_d_bits_data,
+ output auto_in_0_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_clock; // @[Nodes.scala 24:25]
+ wire monitor_1_reset; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire requestDOI_0_0 = ~auto_out_d_bits_source[2]; // @[Parameters.scala 54:32]
+ wire requestDOI_0_1 = auto_out_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire [26:0] _beatsAI_decode_T_1 = 27'hfff << auto_in_0_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] _beatsAI_decode_T_3 = ~_beatsAI_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] beatsAI_decode = _beatsAI_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire beatsAI_opdata = ~auto_in_0_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle = beatsLeft == 9'h0; // @[Arbiter.scala 88:28]
+ wire latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
+ wire [1:0] readys_valid = {auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 31:58]
+ wire _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
+ reg [1:0] readys_mask; // @[Arbiter.scala 23:23]
+ wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
+ wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
+ wire [3:0] readys_filter = {_readys_filter_T_1,auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 31:58]
+ wire [3:0] _GEN_1 = {{1'd0}, readys_filter[3:1]}; // @[package.scala 253:43]
+ wire [3:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
+ wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
+ wire [3:0] _GEN_2 = {{1'd0}, _readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
+ wire [3:0] readys_unready = _GEN_2 | _readys_unready_T_4; // @[Arbiter.scala 25:58]
+ wire [1:0] _readys_readys_T_2 = readys_unready[3:2] & readys_unready[1:0]; // @[Arbiter.scala 26:39]
+ wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
+ wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
+ wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
+ wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[1:0]; // @[package.scala 244:43]
+ wire readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
+ wire readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_0 = readys_0 & auto_in_0_a_valid; // @[Arbiter.scala 97:79]
+ wire earlyWinner_1 = readys_1 & auto_in_1_a_valid; // @[Arbiter.scala 97:79]
+ wire _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
+ wire _T_10 = auto_in_0_a_valid | auto_in_1_a_valid; // @[Arbiter.scala 107:36]
+ wire _T_11 = ~(auto_in_0_a_valid | auto_in_1_a_valid); // @[Arbiter.scala 107:15]
+ reg state_0; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire _out_0_a_earlyValid_T_3 = state_0 & auto_in_0_a_valid | state_1 & auto_in_1_a_valid; // @[Mux.scala 27:73]
+ wire out_2_0_a_earlyValid = idle ? _T_10 : _out_0_a_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_out_a_ready & out_2_0_a_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ wire [8:0] _GEN_3 = {{8'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
+ wire [8:0] _beatsLeft_T_4 = beatsLeft - _GEN_3; // @[Arbiter.scala 113:52]
+ wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
+ wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire [63:0] _T_27 = muxStateEarly_0 ? auto_in_0_a_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_28 = muxStateEarly_1 ? auto_in_1_a_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_30 = muxStateEarly_0 ? auto_in_0_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_31 = muxStateEarly_1 ? 8'hf : 8'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_33 = muxStateEarly_0 ? auto_in_0_a_bits_address : 32'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_34 = muxStateEarly_1 ? auto_in_1_a_bits_address : 32'h0; // @[Mux.scala 27:73]
+ wire [2:0] in_0_a_bits_source = {{1'd0}, auto_in_0_a_bits_source}; // @[Xbar.scala 231:18 237:29]
+ wire [2:0] _T_36 = muxStateEarly_0 ? in_0_a_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_37 = muxStateEarly_1 ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_39 = muxStateEarly_0 ? auto_in_0_a_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_40 = muxStateEarly_1 ? 4'h2 : 4'h0; // @[Mux.scala 27:73]
+ TLMonitor_25 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ TLMonitor_26 monitor_1 ( // @[Nodes.scala 24:25]
+ .clock(monitor_1_clock),
+ .reset(monitor_1_reset),
+ .io_in_a_ready(monitor_1_io_in_a_ready),
+ .io_in_a_valid(monitor_1_io_in_a_valid),
+ .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
+ .io_in_d_valid(monitor_1_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_1_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
+ .io_in_d_bits_sink(monitor_1_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_1_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_1_io_in_d_bits_corrupt)
+ );
+ assign auto_in_1_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign auto_in_1_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
+ assign auto_in_0_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign auto_in_0_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
+ assign auto_in_0_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_source = auto_out_d_bits_source[1:0]; // @[Xbar.scala 228:69]
+ assign auto_in_0_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign auto_in_0_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = idle ? _T_10 : _out_0_a_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ assign auto_out_a_bits_opcode = muxStateEarly_0 ? auto_in_0_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_param = muxStateEarly_0 ? auto_in_0_a_bits_param : 3'h0; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_size = _T_39 | _T_40; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_source = _T_36 | _T_37; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_address = _T_33 | _T_34; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_mask = _T_30 | _T_31; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_data = _T_27 | _T_28; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_corrupt = muxStateEarly_0 & auto_in_0_a_bits_corrupt; // @[Mux.scala 27:73]
+ assign auto_out_d_ready = requestDOI_0_0 & auto_in_0_d_ready | requestDOI_0_1; // @[Mux.scala 27:73]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign monitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[1:0]; // @[Xbar.scala 228:69]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_clock = clock;
+ assign monitor_1_reset = reset;
+ assign monitor_1_io_in_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign monitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
+ assign monitor_1_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign monitor_1_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 9'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ if (earlyWinner_0) begin // @[Arbiter.scala 111:73]
+ if (beatsAI_opdata) begin // @[Edges.scala 220:14]
+ beatsLeft <= beatsAI_decode;
+ end else begin
+ beatsLeft <= 9'h0;
+ end
+ end else begin
+ beatsLeft <= 9'h0;
+ end
+ end else begin
+ beatsLeft <= _beatsLeft_T_4;
+ end
+ if (reset) begin // @[Arbiter.scala 23:23]
+ readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
+ end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
+ readys_mask <= _readys_mask_T_3; // @[Arbiter.scala 28:12]
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_0 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_0 <= earlyWinner_0;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~earlyWinner_0 | ~earlyWinner_1) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 105:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
+ ); // @[Arbiter.scala 105:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(auto_in_0_a_valid | auto_in_1_a_valid) | _prefixOR_T) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~(auto_in_0_a_valid | auto_in_1_a_valid) | _prefixOR_T)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_11 | _T_10) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(_T_11 | _T_10)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ beatsLeft = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ readys_mask = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ state_0 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ state_1 = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_27(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [63:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [63:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_44 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_53 = _T_44 & source_ok; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_59 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_61 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_64 = $signed(_T_62) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_66 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_69 = $signed(_T_67) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_71 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_74 = $signed(_T_72) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_76 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_79 = $signed(_T_77) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_81 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_84 = $signed(_T_82) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_86 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_87 = {1'b0,$signed(_T_86)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_89 = $signed(_T_87) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_90 = $signed(_T_89) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_91 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_92 = {1'b0,$signed(_T_91)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_94 = $signed(_T_92) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_95 = $signed(_T_94) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_96 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_97 = {1'b0,$signed(_T_96)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_99 = $signed(_T_97) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_100 = $signed(_T_99) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_101 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_102 = {1'b0,$signed(_T_101)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_104 = $signed(_T_102) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_105 = $signed(_T_104) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_106 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_107 = {1'b0,$signed(_T_106)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_109 = $signed(_T_107) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_110 = $signed(_T_109) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_111 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_112 = {1'b0,$signed(_T_111)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_114 = $signed(_T_112) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_115 = $signed(_T_114) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_224 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_228 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_229 = _T_228 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_233 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_237 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_423 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_436 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_461 = _T_44 & _T_65; // @[Parameters.scala 670:56]
+ wire _T_463 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_530 = _T_60 | _T_70 | _T_75 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_110 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_531 = _T_463 & _T_530; // @[Parameters.scala 670:56]
+ wire _T_533 = _T_461 | _T_531; // @[Parameters.scala 672:30]
+ wire _T_543 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_547 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_555 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_628 = _T_60 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_629 = _T_463 & _T_628; // @[Parameters.scala 670:56]
+ wire _T_650 = _T_461 | _T_629; // @[Parameters.scala 672:30]
+ wire _T_652 = _T_53 & _T_650; // @[Monitor.scala 115:71]
+ wire _T_670 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_781 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_782 = io_in_a_bits_mask & _T_781; // @[Monitor.scala 127:31]
+ wire _T_783 = _T_782 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_787 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_801 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire [31:0] _T_809 = io_in_a_bits_address ^ 32'h4000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_810 = {1'b0,$signed(_T_809)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_812 = $signed(_T_810) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_813 = $signed(_T_812) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_832 = _T_65 | _T_813 | _T_95 | _T_100 | _T_105; // @[Parameters.scala 671:42]
+ wire _T_833 = _T_801 & _T_832; // @[Parameters.scala 670:56]
+ wire _T_879 = 4'h2 <= io_in_a_bits_size & io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:37]
+ wire _T_886 = _T_879 & _T_115; // @[Parameters.scala 670:56]
+ wire _T_889 = _T_833 | _T_886; // @[Parameters.scala 672:30]
+ wire _T_890 = _T_53 & _T_889; // @[Monitor.scala 131:74]
+ wire _T_900 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_908 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_1021 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_1029 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1121 = _T_53 & _T_461; // @[Monitor.scala 147:68]
+ wire _T_1131 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1143 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_1147 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1151 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1155 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1159 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1163 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1167 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1178 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1182 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1195 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1215 = _T_1163 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1224 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1241 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1259 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1289 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1290 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1294 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1298 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1302 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1306 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1313 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1314 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1318 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1322 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1326 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1330 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1334 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [39:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [5:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [39:0] _GEN_75 = {{24'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala 638:144]
+ wire _T_1340 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_1343 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [5:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [67:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [67:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_1345 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_1347 = ~_T_1345[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [67:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 68'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1351 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1353 = ~_T_1147; // @[Monitor.scala 671:74]
+ wire _T_1354 = io_in_d_valid & d_first_1 & ~_T_1147; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [78:0] _GEN_4 = {{63'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [78:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_1353 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_1353 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire [78:0] _GEN_24 = _d_first_T & d_first_1 & _T_1353 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1340 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_1364 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_1366 = _T_1364[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1371 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1372 = io_in_d_bits_opcode == _GEN_32 | _T_1371; // @[Monitor.scala 685:77]
+ wire _T_1376 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1383 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1384 = io_in_d_bits_opcode == _GEN_48 | _T_1383; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1388 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1398 = _T_1351 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1353; // @[Monitor.scala 694:116]
+ wire _T_1400 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [39:0] a_sizes_set = _GEN_20[39:0];
+ wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [39:0] d_sizes_clr = _GEN_24[39:0];
+ wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1409 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [39:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [39:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
+ wire [39:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala 747:146]
+ wire _T_1435 = io_in_d_valid & d_first_2 & _T_1147; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_1147 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_69 = _d_first_T & d_first_2 & _T_1147 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 786:21]
+ wire [4:0] _T_1443 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1453 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [39:0] d_sizes_clr_1 = _GEN_69[39:0];
+ wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [39:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1473 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 40'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 40'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_224 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_224) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_229 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_224 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_224) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_423 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_423) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_229 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_53 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_53) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_533 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_533) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_652 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_652) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_652 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_652) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_783 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_783) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_900 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_900) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1021 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_1021) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1121 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_1121) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1131 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_1131) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1163 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1163) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1178 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1178) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1182 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1182) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1178 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1178) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1182 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1182) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1215 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1215) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1215 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~_T_1215) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1290 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1290) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1294 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1294) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1298 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1298) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1302 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1306 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1306) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1314 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1314) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1318 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1318) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1322 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1322) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1326 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1326) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1330 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1330) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1334 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1334) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1347 & (_T_1343 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1343 & ~reset & ~_T_1347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1366 & (_T_1354 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & _T_2 & ~_T_1366) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1372 & (_T_1354 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & same_cycle_resp & _T_2 & ~_T_1372) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1376 & (_T_1354 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & same_cycle_resp & _T_2 & ~_T_1376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1384 & (_T_1354 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & ~same_cycle_resp & _T_2 & ~_T_1384) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1388 & (_T_1354 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & ~same_cycle_resp & _T_2 & ~_T_1388) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1400 & (_T_1398 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1398 & _T_2 & ~_T_1400) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1409 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1443[0] & (_T_1435 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1435 & _T_2 & ~_T_1443[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1453 & (_T_1435 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1435 & _T_2 & ~_T_1453) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1473 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1473) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:53:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {2{`RANDOM}};
+ inflight_sizes = _RAND_15[39:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {2{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[39:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLXbar_5(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_8_a_ready,
+ output auto_out_8_a_valid,
+ output [2:0] auto_out_8_a_bits_opcode,
+ output [2:0] auto_out_8_a_bits_param,
+ output [2:0] auto_out_8_a_bits_size,
+ output [2:0] auto_out_8_a_bits_source,
+ output [20:0] auto_out_8_a_bits_address,
+ output [7:0] auto_out_8_a_bits_mask,
+ output [63:0] auto_out_8_a_bits_data,
+ output auto_out_8_a_bits_corrupt,
+ output auto_out_8_d_ready,
+ input auto_out_8_d_valid,
+ input [2:0] auto_out_8_d_bits_opcode,
+ input [1:0] auto_out_8_d_bits_param,
+ input [2:0] auto_out_8_d_bits_size,
+ input [2:0] auto_out_8_d_bits_source,
+ input auto_out_8_d_bits_sink,
+ input auto_out_8_d_bits_denied,
+ input [63:0] auto_out_8_d_bits_data,
+ input auto_out_8_d_bits_corrupt,
+ input auto_out_7_a_ready,
+ output auto_out_7_a_valid,
+ output [2:0] auto_out_7_a_bits_opcode,
+ output [2:0] auto_out_7_a_bits_param,
+ output [2:0] auto_out_7_a_bits_size,
+ output [2:0] auto_out_7_a_bits_source,
+ output [20:0] auto_out_7_a_bits_address,
+ output [7:0] auto_out_7_a_bits_mask,
+ output [63:0] auto_out_7_a_bits_data,
+ output auto_out_7_a_bits_corrupt,
+ output auto_out_7_d_ready,
+ input auto_out_7_d_valid,
+ input [2:0] auto_out_7_d_bits_opcode,
+ input [1:0] auto_out_7_d_bits_param,
+ input [2:0] auto_out_7_d_bits_size,
+ input [2:0] auto_out_7_d_bits_source,
+ input auto_out_7_d_bits_sink,
+ input auto_out_7_d_bits_denied,
+ input [63:0] auto_out_7_d_bits_data,
+ input auto_out_7_d_bits_corrupt,
+ input auto_out_6_a_ready,
+ output auto_out_6_a_valid,
+ output [2:0] auto_out_6_a_bits_opcode,
+ output [2:0] auto_out_6_a_bits_param,
+ output [2:0] auto_out_6_a_bits_size,
+ output [2:0] auto_out_6_a_bits_source,
+ output [16:0] auto_out_6_a_bits_address,
+ output [7:0] auto_out_6_a_bits_mask,
+ output auto_out_6_a_bits_corrupt,
+ output auto_out_6_d_ready,
+ input auto_out_6_d_valid,
+ input [2:0] auto_out_6_d_bits_size,
+ input [2:0] auto_out_6_d_bits_source,
+ input [63:0] auto_out_6_d_bits_data,
+ input auto_out_5_a_ready,
+ output auto_out_5_a_valid,
+ output [2:0] auto_out_5_a_bits_opcode,
+ output [2:0] auto_out_5_a_bits_param,
+ output [2:0] auto_out_5_a_bits_size,
+ output [2:0] auto_out_5_a_bits_source,
+ output [31:0] auto_out_5_a_bits_address,
+ output [7:0] auto_out_5_a_bits_mask,
+ output [63:0] auto_out_5_a_bits_data,
+ output auto_out_5_d_ready,
+ input auto_out_5_d_valid,
+ input [2:0] auto_out_5_d_bits_opcode,
+ input [1:0] auto_out_5_d_bits_param,
+ input [2:0] auto_out_5_d_bits_size,
+ input [2:0] auto_out_5_d_bits_source,
+ input auto_out_5_d_bits_sink,
+ input auto_out_5_d_bits_denied,
+ input [63:0] auto_out_5_d_bits_data,
+ input auto_out_5_d_bits_corrupt,
+ input auto_out_4_a_ready,
+ output auto_out_4_a_valid,
+ output [2:0] auto_out_4_a_bits_opcode,
+ output [2:0] auto_out_4_a_bits_param,
+ output [2:0] auto_out_4_a_bits_size,
+ output [2:0] auto_out_4_a_bits_source,
+ output [11:0] auto_out_4_a_bits_address,
+ output [7:0] auto_out_4_a_bits_mask,
+ output [63:0] auto_out_4_a_bits_data,
+ output auto_out_4_a_bits_corrupt,
+ output auto_out_4_d_ready,
+ input auto_out_4_d_valid,
+ input [2:0] auto_out_4_d_bits_opcode,
+ input [2:0] auto_out_4_d_bits_size,
+ input [2:0] auto_out_4_d_bits_source,
+ input [63:0] auto_out_4_d_bits_data,
+ input auto_out_3_a_ready,
+ output auto_out_3_a_valid,
+ output [2:0] auto_out_3_a_bits_opcode,
+ output [2:0] auto_out_3_a_bits_param,
+ output [2:0] auto_out_3_a_bits_size,
+ output [2:0] auto_out_3_a_bits_source,
+ output [25:0] auto_out_3_a_bits_address,
+ output [7:0] auto_out_3_a_bits_mask,
+ output [63:0] auto_out_3_a_bits_data,
+ output auto_out_3_a_bits_corrupt,
+ output auto_out_3_d_ready,
+ input auto_out_3_d_valid,
+ input [2:0] auto_out_3_d_bits_opcode,
+ input [2:0] auto_out_3_d_bits_size,
+ input [2:0] auto_out_3_d_bits_source,
+ input [63:0] auto_out_3_d_bits_data,
+ input auto_out_2_a_ready,
+ output auto_out_2_a_valid,
+ output [2:0] auto_out_2_a_bits_opcode,
+ output [2:0] auto_out_2_a_bits_param,
+ output [2:0] auto_out_2_a_bits_size,
+ output [2:0] auto_out_2_a_bits_source,
+ output [27:0] auto_out_2_a_bits_address,
+ output [7:0] auto_out_2_a_bits_mask,
+ output [63:0] auto_out_2_a_bits_data,
+ output auto_out_2_a_bits_corrupt,
+ output auto_out_2_d_ready,
+ input auto_out_2_d_valid,
+ input [2:0] auto_out_2_d_bits_opcode,
+ input [2:0] auto_out_2_d_bits_size,
+ input [2:0] auto_out_2_d_bits_source,
+ input [63:0] auto_out_2_d_bits_data,
+ input auto_out_1_a_ready,
+ output auto_out_1_a_valid,
+ output [2:0] auto_out_1_a_bits_opcode,
+ output [2:0] auto_out_1_a_bits_param,
+ output [2:0] auto_out_1_a_bits_size,
+ output [2:0] auto_out_1_a_bits_source,
+ output [29:0] auto_out_1_a_bits_address,
+ output [7:0] auto_out_1_a_bits_mask,
+ output [63:0] auto_out_1_a_bits_data,
+ output auto_out_1_a_bits_corrupt,
+ output auto_out_1_d_ready,
+ input auto_out_1_d_valid,
+ input [2:0] auto_out_1_d_bits_opcode,
+ input [1:0] auto_out_1_d_bits_param,
+ input [2:0] auto_out_1_d_bits_size,
+ input [2:0] auto_out_1_d_bits_source,
+ input auto_out_1_d_bits_sink,
+ input auto_out_1_d_bits_denied,
+ input [63:0] auto_out_1_d_bits_data,
+ input auto_out_1_d_bits_corrupt,
+ input auto_out_0_a_ready,
+ output auto_out_0_a_valid,
+ output [2:0] auto_out_0_a_bits_opcode,
+ output [2:0] auto_out_0_a_bits_param,
+ output [3:0] auto_out_0_a_bits_size,
+ output [2:0] auto_out_0_a_bits_source,
+ output [13:0] auto_out_0_a_bits_address,
+ output [7:0] auto_out_0_a_bits_mask,
+ output auto_out_0_a_bits_corrupt,
+ output auto_out_0_d_ready,
+ input auto_out_0_d_valid,
+ input [2:0] auto_out_0_d_bits_opcode,
+ input [1:0] auto_out_0_d_bits_param,
+ input [3:0] auto_out_0_d_bits_size,
+ input [2:0] auto_out_0_d_bits_source,
+ input auto_out_0_d_bits_sink,
+ input auto_out_0_d_bits_denied,
+ input [63:0] auto_out_0_d_bits_data,
+ input auto_out_0_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ reg [8:0] beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle = beatsLeft == 9'h0; // @[Arbiter.scala 88:28]
+ wire [8:0] readys_valid = {auto_out_8_d_valid,auto_out_7_d_valid,auto_out_6_d_valid,auto_out_5_d_valid,
+ auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
+ reg [8:0] readys_mask; // @[Arbiter.scala 23:23]
+ wire [8:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
+ wire [8:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
+ wire [17:0] readys_filter = {_readys_filter_T_1,auto_out_8_d_valid,auto_out_7_d_valid,auto_out_6_d_valid,
+ auto_out_5_d_valid,auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
+ wire [17:0] _GEN_1 = {{1'd0}, readys_filter[17:1]}; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
+ wire [17:0] _GEN_2 = {{2'd0}, _readys_unready_T_1[17:2]}; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_3 = _readys_unready_T_1 | _GEN_2; // @[package.scala 253:43]
+ wire [17:0] _GEN_3 = {{4'd0}, _readys_unready_T_3[17:4]}; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_5 = _readys_unready_T_3 | _GEN_3; // @[package.scala 253:43]
+ wire [17:0] _GEN_4 = {{8'd0}, _readys_unready_T_5[17:8]}; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_7 = _readys_unready_T_5 | _GEN_4; // @[package.scala 253:43]
+ wire [17:0] _readys_unready_T_10 = {readys_mask, 9'h0}; // @[Arbiter.scala 25:66]
+ wire [17:0] _GEN_5 = {{1'd0}, _readys_unready_T_7[17:1]}; // @[Arbiter.scala 25:58]
+ wire [17:0] readys_unready = _GEN_5 | _readys_unready_T_10; // @[Arbiter.scala 25:58]
+ wire [8:0] _readys_readys_T_2 = readys_unready[17:9] & readys_unready[8:0]; // @[Arbiter.scala 26:39]
+ wire [8:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
+ wire readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_0 = readys_0 & auto_out_0_d_valid; // @[Arbiter.scala 97:79]
+ reg state_0; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_148 = muxStateEarly_0 ? auto_out_0_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_1 = readys_1 & auto_out_1_d_valid; // @[Arbiter.scala 97:79]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_149 = muxStateEarly_1 ? auto_out_1_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_157 = _T_148 | _T_149; // @[Mux.scala 27:73]
+ wire readys_2 = readys_readys[2]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_2 = readys_2 & auto_out_2_d_valid; // @[Arbiter.scala 97:79]
+ reg state_2; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_2 = idle ? earlyWinner_2 : state_2; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_150 = muxStateEarly_2 ? auto_out_2_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_158 = _T_157 | _T_150; // @[Mux.scala 27:73]
+ wire readys_3 = readys_readys[3]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_3 = readys_3 & auto_out_3_d_valid; // @[Arbiter.scala 97:79]
+ reg state_3; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_3 = idle ? earlyWinner_3 : state_3; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_151 = muxStateEarly_3 ? auto_out_3_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_159 = _T_158 | _T_151; // @[Mux.scala 27:73]
+ wire readys_4 = readys_readys[4]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_4 = readys_4 & auto_out_4_d_valid; // @[Arbiter.scala 97:79]
+ reg state_4; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_4 = idle ? earlyWinner_4 : state_4; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_152 = muxStateEarly_4 ? auto_out_4_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_160 = _T_159 | _T_152; // @[Mux.scala 27:73]
+ wire readys_5 = readys_readys[5]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_5 = readys_5 & auto_out_5_d_valid; // @[Arbiter.scala 97:79]
+ reg state_5; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_5 = idle ? earlyWinner_5 : state_5; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_153 = muxStateEarly_5 ? auto_out_5_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_161 = _T_160 | _T_153; // @[Mux.scala 27:73]
+ wire readys_6 = readys_readys[6]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_6 = readys_6 & auto_out_6_d_valid; // @[Arbiter.scala 97:79]
+ reg state_6; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_6 = idle ? earlyWinner_6 : state_6; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_154 = muxStateEarly_6 ? auto_out_6_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_162 = _T_161 | _T_154; // @[Mux.scala 27:73]
+ wire readys_7 = readys_readys[7]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_7 = readys_7 & auto_out_7_d_valid; // @[Arbiter.scala 97:79]
+ reg state_7; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_7 = idle ? earlyWinner_7 : state_7; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_155 = muxStateEarly_7 ? auto_out_7_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_163 = _T_162 | _T_155; // @[Mux.scala 27:73]
+ wire readys_8 = readys_readys[8]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_8 = readys_8 & auto_out_8_d_valid; // @[Arbiter.scala 97:79]
+ reg state_8; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_8 = idle ? earlyWinner_8 : state_8; // @[Arbiter.scala 117:30]
+ wire [2:0] _T_156 = muxStateEarly_8 ? auto_out_8_d_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [31:0] _requestAIO_T = auto_in_a_bits_address ^ 32'h2000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_1 = {1'b0,$signed(_requestAIO_T)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_3 = $signed(_requestAIO_T_1) & 33'shba136000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_0 = $signed(_requestAIO_T_3) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_5 = auto_in_a_bits_address ^ 32'h4000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_6 = {1'b0,$signed(_requestAIO_T_5)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_8 = $signed(_requestAIO_T_6) & 33'shba136000; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_9 = $signed(_requestAIO_T_8) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_10 = auto_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_11 = {1'b0,$signed(_requestAIO_T_10)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_13 = $signed(_requestAIO_T_11) & 33'shba130000; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_14 = $signed(_requestAIO_T_13) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_15 = auto_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_16 = {1'b0,$signed(_requestAIO_T_15)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_18 = $signed(_requestAIO_T_16) & 33'shba136000; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_19 = $signed(_requestAIO_T_18) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_20 = auto_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_21 = {1'b0,$signed(_requestAIO_T_20)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_23 = $signed(_requestAIO_T_21) & 33'shba134000; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_24 = $signed(_requestAIO_T_23) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_25 = auto_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_26 = {1'b0,$signed(_requestAIO_T_25)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_28 = $signed(_requestAIO_T_26) & 33'shba136000; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_29 = $signed(_requestAIO_T_28) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_30 = auto_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_31 = {1'b0,$signed(_requestAIO_T_30)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_33 = $signed(_requestAIO_T_31) & 33'sha0000000; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_34 = $signed(_requestAIO_T_33) == 33'sh0; // @[Parameters.scala 137:67]
+ wire requestAIO_0_1 = _requestAIO_T_9 | _requestAIO_T_14 | _requestAIO_T_19 | _requestAIO_T_24 | _requestAIO_T_29 |
+ _requestAIO_T_34; // @[Xbar.scala 363:92]
+ wire [31:0] _requestAIO_T_40 = auto_in_a_bits_address ^ 32'h8000000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_41 = {1'b0,$signed(_requestAIO_T_40)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_43 = $signed(_requestAIO_T_41) & 33'shb8000000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_2 = $signed(_requestAIO_T_43) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_45 = auto_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_46 = {1'b0,$signed(_requestAIO_T_45)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_48 = $signed(_requestAIO_T_46) & 33'shba130000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_3 = $signed(_requestAIO_T_48) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [32:0] _requestAIO_T_51 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_53 = $signed(_requestAIO_T_51) & 33'shba136000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_4 = $signed(_requestAIO_T_53) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_55 = auto_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_56 = {1'b0,$signed(_requestAIO_T_55)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_58 = $signed(_requestAIO_T_56) & 33'shba134000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_5 = $signed(_requestAIO_T_58) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_60 = auto_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_61 = {1'b0,$signed(_requestAIO_T_60)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_63 = $signed(_requestAIO_T_61) & 33'shba130000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_6 = $signed(_requestAIO_T_63) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_65 = auto_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_66 = {1'b0,$signed(_requestAIO_T_65)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_68 = $signed(_requestAIO_T_66) & 33'shba136000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_7 = $signed(_requestAIO_T_68) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _requestAIO_T_70 = auto_in_a_bits_address ^ 32'h110000; // @[Parameters.scala 137:31]
+ wire [32:0] _requestAIO_T_71 = {1'b0,$signed(_requestAIO_T_70)}; // @[Parameters.scala 137:49]
+ wire [32:0] _requestAIO_T_73 = $signed(_requestAIO_T_71) & 33'shba136000; // @[Parameters.scala 137:52]
+ wire requestAIO_0_8 = $signed(_requestAIO_T_73) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [26:0] _beatsDO_decode_T_1 = 27'hfff << auto_out_0_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _beatsDO_decode_T_3 = ~_beatsDO_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] beatsDO_decode = _beatsDO_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala 220:14]
+ wire [3:0] out_1_1_d_bits_size = {{1'd0}, auto_out_1_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
+ wire [20:0] _beatsDO_decode_T_5 = 21'h3f << out_1_1_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_7 = ~_beatsDO_decode_T_5[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_7[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_1 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala 220:14]
+ wire [3:0] out_1_2_d_bits_size = {{1'd0}, auto_out_2_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
+ wire [20:0] _beatsDO_decode_T_9 = 21'h3f << out_1_2_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_11 = ~_beatsDO_decode_T_9[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_2 = _beatsDO_decode_T_11[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_2 = auto_out_2_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_2 = beatsDO_opdata_2 ? beatsDO_decode_2 : 3'h0; // @[Edges.scala 220:14]
+ wire [3:0] out_1_3_d_bits_size = {{1'd0}, auto_out_3_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
+ wire [20:0] _beatsDO_decode_T_13 = 21'h3f << out_1_3_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_15 = ~_beatsDO_decode_T_13[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_3 = _beatsDO_decode_T_15[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_3 = auto_out_3_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_3 = beatsDO_opdata_3 ? beatsDO_decode_3 : 3'h0; // @[Edges.scala 220:14]
+ wire [3:0] out_1_4_d_bits_size = {{1'd0}, auto_out_4_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
+ wire [20:0] _beatsDO_decode_T_17 = 21'h3f << out_1_4_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_19 = ~_beatsDO_decode_T_17[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_4 = _beatsDO_decode_T_19[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_4 = auto_out_4_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_4 = beatsDO_opdata_4 ? beatsDO_decode_4 : 3'h0; // @[Edges.scala 220:14]
+ wire [3:0] out_1_5_d_bits_size = {{1'd0}, auto_out_5_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
+ wire [20:0] _beatsDO_decode_T_21 = 21'h3f << out_1_5_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_23 = ~_beatsDO_decode_T_21[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_5 = _beatsDO_decode_T_23[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_5 = auto_out_5_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_5 = beatsDO_opdata_5 ? beatsDO_decode_5 : 3'h0; // @[Edges.scala 220:14]
+ wire [3:0] out_1_6_d_bits_size = {{1'd0}, auto_out_6_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
+ wire [20:0] _beatsDO_decode_T_25 = 21'h3f << out_1_6_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_27 = ~_beatsDO_decode_T_25[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_6 = _beatsDO_decode_T_27[5:3]; // @[Edges.scala 219:59]
+ wire [3:0] out_1_7_d_bits_size = {{1'd0}, auto_out_7_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
+ wire [20:0] _beatsDO_decode_T_29 = 21'h3f << out_1_7_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_31 = ~_beatsDO_decode_T_29[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_7 = _beatsDO_decode_T_31[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_7 = auto_out_7_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_7 = beatsDO_opdata_7 ? beatsDO_decode_7 : 3'h0; // @[Edges.scala 220:14]
+ wire [3:0] out_1_8_d_bits_size = {{1'd0}, auto_out_8_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
+ wire [20:0] _beatsDO_decode_T_33 = 21'h3f << out_1_8_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _beatsDO_decode_T_35 = ~_beatsDO_decode_T_33[5:0]; // @[package.scala 234:46]
+ wire [2:0] beatsDO_decode_8 = _beatsDO_decode_T_35[5:3]; // @[Edges.scala 219:59]
+ wire beatsDO_opdata_8 = auto_out_8_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [2:0] beatsDO_8 = beatsDO_opdata_8 ? beatsDO_decode_8 : 3'h0; // @[Edges.scala 220:14]
+ wire latch = idle & auto_in_d_ready; // @[Arbiter.scala 89:24]
+ wire _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
+ wire [8:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
+ wire [9:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
+ wire [8:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[8:0]; // @[package.scala 244:43]
+ wire [10:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala 244:48]
+ wire [8:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_4[8:0]; // @[package.scala 244:43]
+ wire [12:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala 244:48]
+ wire [8:0] _readys_mask_T_9 = _readys_mask_T_6 | _readys_mask_T_7[8:0]; // @[package.scala 244:43]
+ wire [16:0] _readys_mask_T_10 = {_readys_mask_T_9, 8'h0}; // @[package.scala 244:48]
+ wire [8:0] _readys_mask_T_12 = _readys_mask_T_9 | _readys_mask_T_10[8:0]; // @[package.scala 244:43]
+ wire prefixOR_2 = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
+ wire prefixOR_3 = prefixOR_2 | earlyWinner_2; // @[Arbiter.scala 104:53]
+ wire prefixOR_4 = prefixOR_3 | earlyWinner_3; // @[Arbiter.scala 104:53]
+ wire prefixOR_5 = prefixOR_4 | earlyWinner_4; // @[Arbiter.scala 104:53]
+ wire prefixOR_6 = prefixOR_5 | earlyWinner_5; // @[Arbiter.scala 104:53]
+ wire prefixOR_7 = prefixOR_6 | earlyWinner_6; // @[Arbiter.scala 104:53]
+ wire prefixOR_8 = prefixOR_7 | earlyWinner_7; // @[Arbiter.scala 104:53]
+ wire _prefixOR_T = prefixOR_8 | earlyWinner_8; // @[Arbiter.scala 104:53]
+ wire _T_26 = ~prefixOR_8 | ~earlyWinner_8; // @[Arbiter.scala 105:64]
+ wire _T_45 = auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
+ | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid; // @[Arbiter.scala 107:36]
+ wire _T_46 = ~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
+ | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid); // @[Arbiter.scala 107:15]
+ wire [8:0] maskedBeats_0 = earlyWinner_0 ? beatsDO_0 : 9'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_1 = earlyWinner_1 ? beatsDO_1 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_2 = earlyWinner_2 ? beatsDO_2 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_3 = earlyWinner_3 ? beatsDO_3 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_4 = earlyWinner_4 ? beatsDO_4 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_5 = earlyWinner_5 ? beatsDO_5 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_6 = earlyWinner_6 ? beatsDO_decode_6 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_7 = earlyWinner_7 ? beatsDO_7 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [2:0] maskedBeats_8 = earlyWinner_8 ? beatsDO_8 : 3'h0; // @[Arbiter.scala 111:73]
+ wire [8:0] _GEN_6 = {{6'd0}, maskedBeats_1}; // @[Arbiter.scala 112:44]
+ wire [8:0] _initBeats_T = maskedBeats_0 | _GEN_6; // @[Arbiter.scala 112:44]
+ wire [8:0] _GEN_7 = {{6'd0}, maskedBeats_2}; // @[Arbiter.scala 112:44]
+ wire [8:0] _initBeats_T_1 = _initBeats_T | _GEN_7; // @[Arbiter.scala 112:44]
+ wire [8:0] _GEN_8 = {{6'd0}, maskedBeats_3}; // @[Arbiter.scala 112:44]
+ wire [8:0] _initBeats_T_2 = _initBeats_T_1 | _GEN_8; // @[Arbiter.scala 112:44]
+ wire [8:0] _GEN_9 = {{6'd0}, maskedBeats_4}; // @[Arbiter.scala 112:44]
+ wire [8:0] _initBeats_T_3 = _initBeats_T_2 | _GEN_9; // @[Arbiter.scala 112:44]
+ wire [8:0] _GEN_10 = {{6'd0}, maskedBeats_5}; // @[Arbiter.scala 112:44]
+ wire [8:0] _initBeats_T_4 = _initBeats_T_3 | _GEN_10; // @[Arbiter.scala 112:44]
+ wire [8:0] _GEN_11 = {{6'd0}, maskedBeats_6}; // @[Arbiter.scala 112:44]
+ wire [8:0] _initBeats_T_5 = _initBeats_T_4 | _GEN_11; // @[Arbiter.scala 112:44]
+ wire [8:0] _GEN_12 = {{6'd0}, maskedBeats_7}; // @[Arbiter.scala 112:44]
+ wire [8:0] _initBeats_T_6 = _initBeats_T_5 | _GEN_12; // @[Arbiter.scala 112:44]
+ wire [8:0] _GEN_13 = {{6'd0}, maskedBeats_8}; // @[Arbiter.scala 112:44]
+ wire [8:0] initBeats = _initBeats_T_6 | _GEN_13; // @[Arbiter.scala 112:44]
+ wire _sink_ACancel_earlyValid_T_24 = state_0 & auto_out_0_d_valid | state_1 & auto_out_1_d_valid | state_2 &
+ auto_out_2_d_valid | state_3 & auto_out_3_d_valid | state_4 & auto_out_4_d_valid | state_5 & auto_out_5_d_valid |
+ state_6 & auto_out_6_d_valid | state_7 & auto_out_7_d_valid | state_8 & auto_out_8_d_valid; // @[Mux.scala 27:73]
+ wire sink_ACancel_19_earlyValid = idle ? _T_45 : _sink_ACancel_earlyValid_T_24; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_19_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ wire [8:0] _GEN_14 = {{8'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
+ wire [8:0] _beatsLeft_T_4 = beatsLeft - _GEN_14; // @[Arbiter.scala 113:52]
+ wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
+ wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala 121:24]
+ wire allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala 121:24]
+ wire allowed_4 = idle ? readys_4 : state_4; // @[Arbiter.scala 121:24]
+ wire allowed_5 = idle ? readys_5 : state_5; // @[Arbiter.scala 121:24]
+ wire allowed_6 = idle ? readys_6 : state_6; // @[Arbiter.scala 121:24]
+ wire allowed_7 = idle ? readys_7 : state_7; // @[Arbiter.scala 121:24]
+ wire allowed_8 = idle ? readys_8 : state_8; // @[Arbiter.scala 121:24]
+ wire [63:0] _T_97 = muxStateEarly_0 ? auto_out_0_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_98 = muxStateEarly_1 ? auto_out_1_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_99 = muxStateEarly_2 ? auto_out_2_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_100 = muxStateEarly_3 ? auto_out_3_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_101 = muxStateEarly_4 ? auto_out_4_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_102 = muxStateEarly_5 ? auto_out_5_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_103 = muxStateEarly_6 ? auto_out_6_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_104 = muxStateEarly_7 ? auto_out_7_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_105 = muxStateEarly_8 ? auto_out_8_d_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_106 = _T_97 | _T_98; // @[Mux.scala 27:73]
+ wire [63:0] _T_107 = _T_106 | _T_99; // @[Mux.scala 27:73]
+ wire [63:0] _T_108 = _T_107 | _T_100; // @[Mux.scala 27:73]
+ wire [63:0] _T_109 = _T_108 | _T_101; // @[Mux.scala 27:73]
+ wire [63:0] _T_110 = _T_109 | _T_102; // @[Mux.scala 27:73]
+ wire [63:0] _T_111 = _T_110 | _T_103; // @[Mux.scala 27:73]
+ wire [63:0] _T_112 = _T_111 | _T_104; // @[Mux.scala 27:73]
+ wire [3:0] _T_165 = muxStateEarly_0 ? auto_out_0_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_166 = muxStateEarly_1 ? out_1_1_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_167 = muxStateEarly_2 ? out_1_2_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_168 = muxStateEarly_3 ? out_1_3_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_169 = muxStateEarly_4 ? out_1_4_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_170 = muxStateEarly_5 ? out_1_5_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_171 = muxStateEarly_6 ? out_1_6_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_172 = muxStateEarly_7 ? out_1_7_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_173 = muxStateEarly_8 ? out_1_8_d_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_174 = _T_165 | _T_166; // @[Mux.scala 27:73]
+ wire [3:0] _T_175 = _T_174 | _T_167; // @[Mux.scala 27:73]
+ wire [3:0] _T_176 = _T_175 | _T_168; // @[Mux.scala 27:73]
+ wire [3:0] _T_177 = _T_176 | _T_169; // @[Mux.scala 27:73]
+ wire [3:0] _T_178 = _T_177 | _T_170; // @[Mux.scala 27:73]
+ wire [3:0] _T_179 = _T_178 | _T_171; // @[Mux.scala 27:73]
+ wire [3:0] _T_180 = _T_179 | _T_172; // @[Mux.scala 27:73]
+ wire [1:0] _T_182 = muxStateEarly_0 ? auto_out_0_d_bits_param : 2'h0; // @[Mux.scala 27:73]
+ wire [1:0] _T_183 = muxStateEarly_1 ? auto_out_1_d_bits_param : 2'h0; // @[Mux.scala 27:73]
+ wire [1:0] _T_187 = muxStateEarly_5 ? auto_out_5_d_bits_param : 2'h0; // @[Mux.scala 27:73]
+ wire [1:0] _T_189 = muxStateEarly_7 ? auto_out_7_d_bits_param : 2'h0; // @[Mux.scala 27:73]
+ wire [1:0] _T_190 = muxStateEarly_8 ? auto_out_8_d_bits_param : 2'h0; // @[Mux.scala 27:73]
+ wire [1:0] _T_191 = _T_182 | _T_183; // @[Mux.scala 27:73]
+ wire [1:0] _T_195 = _T_191 | _T_187; // @[Mux.scala 27:73]
+ wire [1:0] _T_197 = _T_195 | _T_189; // @[Mux.scala 27:73]
+ wire [2:0] _T_199 = muxStateEarly_0 ? auto_out_0_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_200 = muxStateEarly_1 ? auto_out_1_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_201 = muxStateEarly_2 ? auto_out_2_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_202 = muxStateEarly_3 ? auto_out_3_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_203 = muxStateEarly_4 ? auto_out_4_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_204 = muxStateEarly_5 ? auto_out_5_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_205 = muxStateEarly_6 ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_206 = muxStateEarly_7 ? auto_out_7_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_207 = muxStateEarly_8 ? auto_out_8_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_208 = _T_199 | _T_200; // @[Mux.scala 27:73]
+ wire [2:0] _T_209 = _T_208 | _T_201; // @[Mux.scala 27:73]
+ wire [2:0] _T_210 = _T_209 | _T_202; // @[Mux.scala 27:73]
+ wire [2:0] _T_211 = _T_210 | _T_203; // @[Mux.scala 27:73]
+ wire [2:0] _T_212 = _T_211 | _T_204; // @[Mux.scala 27:73]
+ wire [2:0] _T_213 = _T_212 | _T_205; // @[Mux.scala 27:73]
+ wire [2:0] _T_214 = _T_213 | _T_206; // @[Mux.scala 27:73]
+ TLMonitor_27 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready | requestAIO_0_2 &
+ auto_out_2_a_ready | requestAIO_0_3 & auto_out_3_a_ready | requestAIO_0_4 & auto_out_4_a_ready | requestAIO_0_5 &
+ auto_out_5_a_ready | requestAIO_0_6 & auto_out_6_a_ready | requestAIO_0_7 & auto_out_7_a_ready | requestAIO_0_8 &
+ auto_out_8_a_ready; // @[Mux.scala 27:73]
+ assign auto_in_d_valid = idle ? _T_45 : _sink_ACancel_earlyValid_T_24; // @[Arbiter.scala 125:29]
+ assign auto_in_d_bits_opcode = _T_214 | _T_207; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_param = _T_197 | _T_190; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_size = _T_180 | _T_173; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_source = _T_163 | _T_156; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_sink = muxStateEarly_0 & auto_out_0_d_bits_sink | muxStateEarly_1 & auto_out_1_d_bits_sink |
+ muxStateEarly_5 & auto_out_5_d_bits_sink | muxStateEarly_7 & auto_out_7_d_bits_sink | muxStateEarly_8 &
+ auto_out_8_d_bits_sink; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied | muxStateEarly_1 & auto_out_1_d_bits_denied
+ | muxStateEarly_5 & auto_out_5_d_bits_denied | muxStateEarly_7 & auto_out_7_d_bits_denied | muxStateEarly_8 &
+ auto_out_8_d_bits_denied; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_data = _T_112 | _T_105; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt | muxStateEarly_1 &
+ auto_out_1_d_bits_corrupt | muxStateEarly_5 & auto_out_5_d_bits_corrupt | muxStateEarly_7 &
+ auto_out_7_d_bits_corrupt | muxStateEarly_8 & auto_out_8_d_bits_corrupt; // @[Mux.scala 27:73]
+ assign auto_out_8_a_valid = auto_in_a_valid & requestAIO_0_8; // @[Xbar.scala 428:50]
+ assign auto_out_8_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_8_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_8_a_bits_address = auto_in_a_bits_address[20:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_8_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_8_d_ready = auto_in_d_ready & allowed_8; // @[Arbiter.scala 123:31]
+ assign auto_out_7_a_valid = auto_in_a_valid & requestAIO_0_7; // @[Xbar.scala 428:50]
+ assign auto_out_7_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_7_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_7_a_bits_address = auto_in_a_bits_address[20:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_7_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_7_d_ready = auto_in_d_ready & allowed_7; // @[Arbiter.scala 123:31]
+ assign auto_out_6_a_valid = auto_in_a_valid & requestAIO_0_6; // @[Xbar.scala 428:50]
+ assign auto_out_6_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_6_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_6_a_bits_address = auto_in_a_bits_address[16:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_6_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_6_d_ready = auto_in_d_ready & allowed_6; // @[Arbiter.scala 123:31]
+ assign auto_out_5_a_valid = auto_in_a_valid & requestAIO_0_5; // @[Xbar.scala 428:50]
+ assign auto_out_5_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_5_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_5_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_5_d_ready = auto_in_d_ready & allowed_5; // @[Arbiter.scala 123:31]
+ assign auto_out_4_a_valid = auto_in_a_valid & requestAIO_0_4; // @[Xbar.scala 428:50]
+ assign auto_out_4_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_4_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_4_a_bits_address = auto_in_a_bits_address[11:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_4_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_d_ready = auto_in_d_ready & allowed_4; // @[Arbiter.scala 123:31]
+ assign auto_out_3_a_valid = auto_in_a_valid & requestAIO_0_3; // @[Xbar.scala 428:50]
+ assign auto_out_3_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_3_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_3_a_bits_address = auto_in_a_bits_address[25:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_3_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_d_ready = auto_in_d_ready & allowed_3; // @[Arbiter.scala 123:31]
+ assign auto_out_2_a_valid = auto_in_a_valid & requestAIO_0_2; // @[Xbar.scala 428:50]
+ assign auto_out_2_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_2_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_2_a_bits_address = auto_in_a_bits_address[27:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_2_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_d_ready = auto_in_d_ready & allowed_2; // @[Arbiter.scala 123:31]
+ assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[Xbar.scala 428:50]
+ assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_1_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_1_a_bits_address = auto_in_a_bits_address[29:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_d_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[Xbar.scala 428:50]
+ assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_0_a_bits_address = auto_in_a_bits_address[13:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_d_ready = auto_in_d_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready |
+ requestAIO_0_2 & auto_out_2_a_ready | requestAIO_0_3 & auto_out_3_a_ready | requestAIO_0_4 & auto_out_4_a_ready |
+ requestAIO_0_5 & auto_out_5_a_ready | requestAIO_0_6 & auto_out_6_a_ready | requestAIO_0_7 & auto_out_7_a_ready |
+ requestAIO_0_8 & auto_out_8_a_ready; // @[Mux.scala 27:73]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = idle ? _T_45 : _sink_ACancel_earlyValid_T_24; // @[Arbiter.scala 125:29]
+ assign monitor_io_in_d_bits_opcode = _T_214 | _T_207; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_param = _T_197 | _T_190; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_size = _T_180 | _T_173; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_source = _T_163 | _T_156; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_sink = muxStateEarly_0 & auto_out_0_d_bits_sink | muxStateEarly_1 & auto_out_1_d_bits_sink
+ | muxStateEarly_5 & auto_out_5_d_bits_sink | muxStateEarly_7 & auto_out_7_d_bits_sink | muxStateEarly_8 &
+ auto_out_8_d_bits_sink; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied | muxStateEarly_1 &
+ auto_out_1_d_bits_denied | muxStateEarly_5 & auto_out_5_d_bits_denied | muxStateEarly_7 & auto_out_7_d_bits_denied
+ | muxStateEarly_8 & auto_out_8_d_bits_denied; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt | muxStateEarly_1 &
+ auto_out_1_d_bits_corrupt | muxStateEarly_5 & auto_out_5_d_bits_corrupt | muxStateEarly_7 &
+ auto_out_7_d_bits_corrupt | muxStateEarly_8 & auto_out_8_d_bits_corrupt; // @[Mux.scala 27:73]
+ always @(posedge clock) begin
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 9'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ beatsLeft <= initBeats;
+ end else begin
+ beatsLeft <= _beatsLeft_T_4;
+ end
+ if (reset) begin // @[Arbiter.scala 23:23]
+ readys_mask <= 9'h1ff; // @[Arbiter.scala 23:23]
+ end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
+ readys_mask <= _readys_mask_T_12; // @[Arbiter.scala 28:12]
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_0 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_0 <= earlyWinner_0;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_2 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_2 <= earlyWinner_2;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_3 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_3 <= earlyWinner_3;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_4 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_4 <= earlyWinner_4;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_5 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_5 <= earlyWinner_5;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_6 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_6 <= earlyWinner_6;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_7 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_7 <= earlyWinner_7;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_8 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_8 <= earlyWinner_8;
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~earlyWinner_3) & (~
+ prefixOR_4 | ~earlyWinner_4) & (~prefixOR_5 | ~earlyWinner_5) & (~prefixOR_6 | ~earlyWinner_6) & (~prefixOR_7
+ | ~earlyWinner_7) & _T_26) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 105:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~
+ earlyWinner_3) & (~prefixOR_4 | ~earlyWinner_4) & (~prefixOR_5 | ~earlyWinner_5) & (~prefixOR_6 | ~
+ earlyWinner_6) & (~prefixOR_7 | ~earlyWinner_7) & _T_26)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
+ ); // @[Arbiter.scala 105:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
+ | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid) | _prefixOR_T) &
+ _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid |
+ auto_out_4_d_valid | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid) |
+ _prefixOR_T)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_46 | _T_45) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(_T_46 | _T_45)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ beatsLeft = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ readys_mask = _RAND_1[8:0];
+ _RAND_2 = {1{`RANDOM}};
+ state_0 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ state_1 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ state_2 = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ state_3 = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ state_4 = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ state_5 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ state_6 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ state_7 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ state_8 = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_28(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [63:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [63:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_44 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_53 = _T_44 & source_ok; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_59 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_61 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_64 = $signed(_T_62) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_66 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_69 = $signed(_T_67) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_71 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_74 = $signed(_T_72) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_76 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_79 = $signed(_T_77) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_81 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_84 = $signed(_T_82) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_86 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_87 = {1'b0,$signed(_T_86)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_89 = $signed(_T_87) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_90 = $signed(_T_89) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_91 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_92 = {1'b0,$signed(_T_91)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_94 = $signed(_T_92) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_95 = $signed(_T_94) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_96 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_97 = {1'b0,$signed(_T_96)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_99 = $signed(_T_97) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_100 = $signed(_T_99) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_101 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_102 = {1'b0,$signed(_T_101)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_104 = $signed(_T_102) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_105 = $signed(_T_104) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_106 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_107 = {1'b0,$signed(_T_106)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_109 = $signed(_T_107) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_110 = $signed(_T_109) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_111 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_112 = {1'b0,$signed(_T_111)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_114 = $signed(_T_112) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_115 = $signed(_T_114) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_224 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_228 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_229 = _T_228 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_233 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_237 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_423 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_436 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_461 = _T_44 & _T_65; // @[Parameters.scala 670:56]
+ wire _T_463 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_530 = _T_60 | _T_70 | _T_75 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_110 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_531 = _T_463 & _T_530; // @[Parameters.scala 670:56]
+ wire _T_533 = _T_461 | _T_531; // @[Parameters.scala 672:30]
+ wire _T_543 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_547 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_555 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_628 = _T_60 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_629 = _T_463 & _T_628; // @[Parameters.scala 670:56]
+ wire _T_650 = _T_461 | _T_629; // @[Parameters.scala 672:30]
+ wire _T_652 = _T_53 & _T_650; // @[Monitor.scala 115:71]
+ wire _T_670 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_781 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_782 = io_in_a_bits_mask & _T_781; // @[Monitor.scala 127:31]
+ wire _T_783 = _T_782 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_787 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_801 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire [31:0] _T_809 = io_in_a_bits_address ^ 32'h4000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_810 = {1'b0,$signed(_T_809)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_812 = $signed(_T_810) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_813 = $signed(_T_812) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_832 = _T_65 | _T_813 | _T_95 | _T_100 | _T_105; // @[Parameters.scala 671:42]
+ wire _T_833 = _T_801 & _T_832; // @[Parameters.scala 670:56]
+ wire _T_879 = 4'h2 <= io_in_a_bits_size & io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:37]
+ wire _T_886 = _T_879 & _T_115; // @[Parameters.scala 670:56]
+ wire _T_889 = _T_833 | _T_886; // @[Parameters.scala 672:30]
+ wire _T_890 = _T_53 & _T_889; // @[Monitor.scala 131:74]
+ wire _T_900 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_908 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_1021 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_1029 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1121 = _T_53 & _T_461; // @[Monitor.scala 147:68]
+ wire _T_1131 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1143 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_1147 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1151 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1155 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1159 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1163 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1167 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1178 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1182 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1195 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1215 = _T_1163 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1224 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1241 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1259 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1289 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1290 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1294 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1298 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1302 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1306 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1313 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1314 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1318 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1322 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1326 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1330 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1334 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [39:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [5:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [39:0] _GEN_75 = {{24'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala 638:144]
+ wire _T_1340 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1343 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [5:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [67:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [67:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_1345 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_1347 = ~_T_1345[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [67:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 68'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1351 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1353 = ~_T_1147; // @[Monitor.scala 671:74]
+ wire _T_1354 = io_in_d_valid & d_first_1 & ~_T_1147; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1147 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [78:0] _GEN_4 = {{63'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [78:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_1353 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_1353 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire [78:0] _GEN_24 = _d_first_T & d_first_1 & _T_1353 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1340 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_1364 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_1366 = _T_1364[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1371 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1372 = io_in_d_bits_opcode == _GEN_32 | _T_1371; // @[Monitor.scala 685:77]
+ wire _T_1376 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1383 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1384 = io_in_d_bits_opcode == _GEN_48 | _T_1383; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1388 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1398 = _T_1351 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1353; // @[Monitor.scala 694:116]
+ wire _T_1400 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_1407 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [39:0] a_sizes_set = _GEN_20[39:0];
+ wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [39:0] d_sizes_clr = _GEN_24[39:0];
+ wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1416 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [39:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [39:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
+ wire [39:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala 747:146]
+ wire _T_1442 = io_in_d_valid & d_first_2 & _T_1147; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_1147 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_69 = _d_first_T & d_first_2 & _T_1147 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 786:21]
+ wire [4:0] _T_1450 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1460 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [39:0] d_sizes_clr_1 = _GEN_69[39:0];
+ wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [39:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1485 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 40'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 40'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_224 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_224) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_229 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_224 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_224) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_423 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_423) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_229 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_53 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_53) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_533 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_533) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_652 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_652) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_652 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_652) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_783 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_783) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_900 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_900) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_890 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_890) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1021 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_1021) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_908 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_908 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1121 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_1121) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1131 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_1131) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_1029 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1029 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1163 & (io_in_d_valid & _T_1147 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1147 & _T_2 & ~_T_1163) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1178 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1178) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1182 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1182) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1167 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1167 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1151 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1151) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1178 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1178) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1182 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1182) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1215 & (io_in_d_valid & _T_1195 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1195 & _T_2 & ~_T_1215) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1224 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1224 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1215 & (io_in_d_valid & _T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1241 & _T_2 & ~_T_1215) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1155 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~_T_1155) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1159 & (io_in_d_valid & _T_1259 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1259 & _T_2 & ~_T_1159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1290 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1290) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1294 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1294) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1298 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1298) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1302 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1306 & (_T_1289 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1289 & ~reset & ~_T_1306) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1314 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1314) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1318 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1318) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1322 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1322) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1326 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1326) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1330 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1330) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1334 & (_T_1313 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1313 & _T_2 & ~_T_1334) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1347 & (_T_1343 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1343 & ~reset & ~_T_1347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1366 & (_T_1354 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & _T_2 & ~_T_1366) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1372 & (_T_1354 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & same_cycle_resp & _T_2 & ~_T_1372) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1376 & (_T_1354 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & same_cycle_resp & _T_2 & ~_T_1376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1384 & (_T_1354 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & ~same_cycle_resp & _T_2 & ~_T_1384) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1388 & (_T_1354 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1354 & ~same_cycle_resp & _T_2 & ~_T_1388) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1400 & (_T_1398 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1398 & _T_2 & ~_T_1400) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1407 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1407) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1416 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1416) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1450[0] & (_T_1442 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1442 & _T_2 & ~_T_1450[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1460 & (_T_1442 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1442 & _T_2 & ~_T_1460) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1485 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1485) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:55:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {2{`RANDOM}};
+ inflight_sizes = _RAND_15[39:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {2{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[39:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_10(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [3:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [31:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [3:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [31:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [31:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_address_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_address_io_deq_bits_MPORT_addr = value_1;
+ assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_address_MPORT_data = io_enq_bits_address;
+ assign ram_address_MPORT_addr = value;
+ assign ram_address_MPORT_mask = 1'h1;
+ assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = value_1;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = value;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
+ ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[3:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_address[initvar] = _RAND_4[31:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_5[7:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_11(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [1:0] io_enq_bits_param,
+ input [3:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input io_enq_bits_sink,
+ input io_enq_bits_denied,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [1:0] io_deq_bits_param,
+ output [3:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output io_deq_bits_sink,
+ output io_deq_bits_denied,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [1:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_sink [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_denied [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_sink_io_deq_bits_MPORT_addr = value_1;
+ assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_sink_MPORT_data = io_enq_bits_sink;
+ assign ram_sink_MPORT_addr = value;
+ assign ram_sink_MPORT_mask = 1'h1;
+ assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_denied_io_deq_bits_MPORT_addr = value_1;
+ assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_denied_MPORT_data = io_enq_bits_denied;
+ assign ram_denied_MPORT_addr = value;
+ assign ram_denied_MPORT_mask = 1'h1;
+ assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
+ ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
+ ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[3:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_sink[initvar] = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_denied[initvar] = _RAND_5[0:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_8(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_28 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_10 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_11 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_29(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [63:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [63:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_44 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_53 = _T_44 & source_ok; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_59 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_61 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_64 = $signed(_T_62) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_66 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_67 = {1'b0,$signed(_T_66)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_69 = $signed(_T_67) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_70 = $signed(_T_69) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_71 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_72 = {1'b0,$signed(_T_71)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_74 = $signed(_T_72) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_75 = $signed(_T_74) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_76 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_77 = {1'b0,$signed(_T_76)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_79 = $signed(_T_77) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_80 = $signed(_T_79) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_81 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_82 = {1'b0,$signed(_T_81)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_84 = $signed(_T_82) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_85 = $signed(_T_84) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_86 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_87 = {1'b0,$signed(_T_86)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_89 = $signed(_T_87) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_90 = $signed(_T_89) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_91 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_92 = {1'b0,$signed(_T_91)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_94 = $signed(_T_92) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_95 = $signed(_T_94) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_96 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_97 = {1'b0,$signed(_T_96)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_99 = $signed(_T_97) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_100 = $signed(_T_99) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_101 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_102 = {1'b0,$signed(_T_101)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_104 = $signed(_T_102) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_105 = $signed(_T_104) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_106 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_107 = {1'b0,$signed(_T_106)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_109 = $signed(_T_107) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_110 = $signed(_T_109) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_111 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_112 = {1'b0,$signed(_T_111)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_114 = $signed(_T_112) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_115 = $signed(_T_114) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_224 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_228 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_229 = _T_228 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_233 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_237 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_423 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_436 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_461 = _T_44 & _T_65; // @[Parameters.scala 670:56]
+ wire _T_463 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_530 = _T_60 | _T_70 | _T_75 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_110 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_531 = _T_463 & _T_530; // @[Parameters.scala 670:56]
+ wire _T_533 = _T_461 | _T_531; // @[Parameters.scala 672:30]
+ wire _T_543 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_547 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_555 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_628 = _T_60 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_629 = _T_463 & _T_628; // @[Parameters.scala 670:56]
+ wire _T_650 = _T_461 | _T_629; // @[Parameters.scala 672:30]
+ wire _T_652 = _T_53 & _T_650; // @[Monitor.scala 115:71]
+ wire _T_670 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_781 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_782 = io_in_a_bits_mask & _T_781; // @[Monitor.scala 127:31]
+ wire _T_783 = _T_782 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_787 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_801 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_856 = _T_60 | _T_65 | _T_80 | _T_85 | _T_90 | _T_95 | _T_100 | _T_105 | _T_115; // @[Parameters.scala 671:42]
+ wire _T_857 = _T_801 & _T_856; // @[Parameters.scala 670:56]
+ wire _T_879 = _T_53 & _T_857; // @[Monitor.scala 131:74]
+ wire _T_889 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_897 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_999 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_1007 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1099 = _T_53 & _T_461; // @[Monitor.scala 147:68]
+ wire _T_1109 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1121 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_1125 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1129 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1133 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1137 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1141 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1145 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1156 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1160 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1173 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1193 = _T_1141 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1202 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1219 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1237 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1267 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1268 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1272 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1276 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1280 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1284 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1291 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1292 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1296 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1300 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1304 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1308 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1312 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [39:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [5:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [39:0] _GEN_75 = {{24'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala 638:144]
+ wire _T_1318 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1321 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [5:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [67:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [67:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_1323 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_1325 = ~_T_1323[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [67:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 68'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1329 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1331 = ~_T_1125; // @[Monitor.scala 671:74]
+ wire _T_1332 = io_in_d_valid & d_first_1 & ~_T_1125; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1125 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [78:0] _GEN_4 = {{63'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [78:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_1331 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_1331 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire [78:0] _GEN_24 = _d_first_T & d_first_1 & _T_1331 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1318 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_1342 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_1344 = _T_1342[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1349 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1350 = io_in_d_bits_opcode == _GEN_32 | _T_1349; // @[Monitor.scala 685:77]
+ wire _T_1354 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1361 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1362 = io_in_d_bits_opcode == _GEN_48 | _T_1361; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1366 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1376 = _T_1329 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1331; // @[Monitor.scala 694:116]
+ wire _T_1378 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_1385 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [39:0] a_sizes_set = _GEN_20[39:0];
+ wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [39:0] d_sizes_clr = _GEN_24[39:0];
+ wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1394 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [39:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [39:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
+ wire [39:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala 747:146]
+ wire _T_1420 = io_in_d_valid & d_first_2 & _T_1125; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_1125 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_69 = _d_first_T & d_first_2 & _T_1125 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 786:21]
+ wire [4:0] _T_1428 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1438 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [39:0] d_sizes_clr_1 = _GEN_69[39:0];
+ wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [39:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1463 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 40'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 40'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_224 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_224) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_229 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_224 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_224) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_423 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_423) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_229 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_229) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_53 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_53) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_533 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_533) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_436 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_436 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_652 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_652) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_555 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_555 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_652 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_652) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_783 & (io_in_a_valid & _T_670 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_670 & ~reset & ~_T_783) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_879 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_879) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_889 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_889) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_787 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_787 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_879 & (io_in_a_valid & _T_897 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_897 & ~reset & ~_T_879) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_897 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_897 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_897 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_897 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_999 & (io_in_a_valid & _T_897 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_897 & ~reset & ~_T_999) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_897 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_897 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1099 & (io_in_a_valid & _T_1007 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1007 & ~reset & ~_T_1099) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_1007 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1007 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_1007 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1007 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1109 & (io_in_a_valid & _T_1007 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1007 & ~reset & ~_T_1109) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_547 & (io_in_a_valid & _T_1007 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1007 & ~reset & ~_T_547) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_233 & (io_in_a_valid & _T_1007 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_1007 & ~reset & ~_T_233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1121 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1121) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1125 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1125 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1129 & (io_in_d_valid & _T_1125 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1125 & _T_2 & ~_T_1129) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1133 & (io_in_d_valid & _T_1125 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1125 & _T_2 & ~_T_1133) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1137 & (io_in_d_valid & _T_1125 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1125 & _T_2 & ~_T_1137) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1141 & (io_in_d_valid & _T_1125 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1125 & _T_2 & ~_T_1141) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1145 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1145 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1145 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1145 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1129 & (io_in_d_valid & _T_1145 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1145 & _T_2 & ~_T_1129) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1156 & (io_in_d_valid & _T_1145 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1145 & _T_2 & ~_T_1156) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1160 & (io_in_d_valid & _T_1145 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1145 & _T_2 & ~_T_1160) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1137 & (io_in_d_valid & _T_1145 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1145 & _T_2 & ~_T_1137) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1173 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1173 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1173 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1173 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1129 & (io_in_d_valid & _T_1173 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1173 & _T_2 & ~_T_1129) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1156 & (io_in_d_valid & _T_1173 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1173 & _T_2 & ~_T_1156) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1160 & (io_in_d_valid & _T_1173 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1173 & _T_2 & ~_T_1160) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1193 & (io_in_d_valid & _T_1173 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1173 & _T_2 & ~_T_1193) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1202 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1202 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1133 & (io_in_d_valid & _T_1202 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1202 & _T_2 & ~_T_1133) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1137 & (io_in_d_valid & _T_1202 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1202 & _T_2 & ~_T_1137) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1219 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1219 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1133 & (io_in_d_valid & _T_1219 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1219 & _T_2 & ~_T_1133) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1193 & (io_in_d_valid & _T_1219 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1219 & _T_2 & ~_T_1193) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1237 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1237 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1133 & (io_in_d_valid & _T_1237 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1237 & _T_2 & ~_T_1133) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1137 & (io_in_d_valid & _T_1237 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1237 & _T_2 & ~_T_1137) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1268 & (_T_1267 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1267 & ~reset & ~_T_1268) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1272 & (_T_1267 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1267 & ~reset & ~_T_1272) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1276 & (_T_1267 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1267 & ~reset & ~_T_1276) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1280 & (_T_1267 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1267 & ~reset & ~_T_1280) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1284 & (_T_1267 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1267 & ~reset & ~_T_1284) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1292 & (_T_1291 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1291 & _T_2 & ~_T_1292) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1296 & (_T_1291 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1291 & _T_2 & ~_T_1296) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1300 & (_T_1291 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1291 & _T_2 & ~_T_1300) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1304 & (_T_1291 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1291 & _T_2 & ~_T_1304) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1308 & (_T_1291 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1291 & _T_2 & ~_T_1308) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1312 & (_T_1291 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1291 & _T_2 & ~_T_1312) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1325 & (_T_1321 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1321 & ~reset & ~_T_1325) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1344 & (_T_1332 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1332 & _T_2 & ~_T_1344) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1350 & (_T_1332 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1332 & same_cycle_resp & _T_2 & ~_T_1350) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1354 & (_T_1332 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1332 & same_cycle_resp & _T_2 & ~_T_1354) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1362 & (_T_1332 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1332 & ~same_cycle_resp & _T_2 & ~_T_1362) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1366 & (_T_1332 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1332 & ~same_cycle_resp & _T_2 & ~_T_1366) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1378 & (_T_1376 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1376 & _T_2 & ~_T_1378) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1385 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1394 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1394) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1428[0] & (_T_1420 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1420 & _T_2 & ~_T_1428[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1438 & (_T_1420 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1420 & _T_2 & ~_T_1438) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1463 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1463) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:58:7)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {2{`RANDOM}};
+ inflight_sizes = _RAND_15[39:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {2{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[39:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLAtomicAutomata_1(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [63:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [63:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala 76:28]
+ reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala 77:24]
+ reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala 77:24]
+ reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala 77:24]
+ reg [2:0] cam_a_0_bits_source; // @[AtomicAutomata.scala 77:24]
+ reg [31:0] cam_a_0_bits_address; // @[AtomicAutomata.scala 77:24]
+ reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala 77:24]
+ reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala 77:24]
+ reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala 77:24]
+ reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala 77:24]
+ reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala 78:24]
+ reg cam_d_0_denied; // @[AtomicAutomata.scala 78:24]
+ reg cam_d_0_corrupt; // @[AtomicAutomata.scala 78:24]
+ wire cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala 80:44]
+ wire cam_amo_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala 81:44]
+ wire cam_abusy_0 = cam_s_0_state == 2'h3 | cam_amo_0; // @[AtomicAutomata.scala 82:57]
+ wire cam_dmatch_0 = cam_s_0_state != 2'h0; // @[AtomicAutomata.scala 83:49]
+ wire _a_canLogical_T_1 = auto_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire [31:0] _a_canLogical_T_4 = auto_in_a_bits_address ^ 32'h2000; // @[Parameters.scala 137:31]
+ wire [32:0] _a_canLogical_T_5 = {1'b0,$signed(_a_canLogical_T_4)}; // @[Parameters.scala 137:49]
+ wire [32:0] _a_canLogical_T_7 = $signed(_a_canLogical_T_5) & 33'shba036000; // @[Parameters.scala 137:52]
+ wire _a_canLogical_T_8 = $signed(_a_canLogical_T_7) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _a_canLogical_T_9 = auto_in_a_bits_address ^ 32'h4000; // @[Parameters.scala 137:31]
+ wire [32:0] _a_canLogical_T_10 = {1'b0,$signed(_a_canLogical_T_9)}; // @[Parameters.scala 137:49]
+ wire [32:0] _a_canLogical_T_12 = $signed(_a_canLogical_T_10) & 33'shba036000; // @[Parameters.scala 137:52]
+ wire _a_canLogical_T_13 = $signed(_a_canLogical_T_12) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _a_canLogical_T_14 = auto_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _a_canLogical_T_15 = {1'b0,$signed(_a_canLogical_T_14)}; // @[Parameters.scala 137:49]
+ wire [32:0] _a_canLogical_T_17 = $signed(_a_canLogical_T_15) & 33'shba036000; // @[Parameters.scala 137:52]
+ wire _a_canLogical_T_18 = $signed(_a_canLogical_T_17) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _a_canLogical_T_19 = auto_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _a_canLogical_T_20 = {1'b0,$signed(_a_canLogical_T_19)}; // @[Parameters.scala 137:49]
+ wire [32:0] _a_canLogical_T_22 = $signed(_a_canLogical_T_20) & 33'shba034000; // @[Parameters.scala 137:52]
+ wire _a_canLogical_T_23 = $signed(_a_canLogical_T_22) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _a_canLogical_T_24 = auto_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _a_canLogical_T_25 = {1'b0,$signed(_a_canLogical_T_24)}; // @[Parameters.scala 137:49]
+ wire [32:0] _a_canLogical_T_27 = $signed(_a_canLogical_T_25) & 33'shba036000; // @[Parameters.scala 137:52]
+ wire _a_canLogical_T_28 = $signed(_a_canLogical_T_27) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _a_canLogical_T_32 = _a_canLogical_T_8 | _a_canLogical_T_13 | _a_canLogical_T_18 | _a_canLogical_T_23 |
+ _a_canLogical_T_28; // @[Parameters.scala 671:42]
+ wire _a_canLogical_T_33 = _a_canLogical_T_1 & _a_canLogical_T_32; // @[Parameters.scala 670:56]
+ wire _a_canLogical_T_73 = 4'h2 <= auto_in_a_bits_size & auto_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:37]
+ wire [31:0] _a_canLogical_T_75 = auto_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _a_canLogical_T_76 = {1'b0,$signed(_a_canLogical_T_75)}; // @[Parameters.scala 137:49]
+ wire [32:0] _a_canLogical_T_78 = $signed(_a_canLogical_T_76) & 33'shba034000; // @[Parameters.scala 137:52]
+ wire _a_canLogical_T_79 = $signed(_a_canLogical_T_78) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _a_canLogical_T_80 = _a_canLogical_T_73 & _a_canLogical_T_79; // @[Parameters.scala 670:56]
+ wire a_canLogical = _a_canLogical_T_33 | _a_canLogical_T_80; // @[Parameters.scala 672:30]
+ wire a_isLogical = auto_in_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala 90:47]
+ wire a_isArithmetic = auto_in_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala 91:47]
+ wire _a_isSupported_T = a_isArithmetic ? a_canLogical : 1'h1; // @[AtomicAutomata.scala 92:63]
+ wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala 92:32]
+ wire [1:0] indexes_0 = {cam_a_0_bits_data[0],cam_d_0_data[0]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_1 = {cam_a_0_bits_data[1],cam_d_0_data[1]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_2 = {cam_a_0_bits_data[2],cam_d_0_data[2]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_3 = {cam_a_0_bits_data[3],cam_d_0_data[3]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_4 = {cam_a_0_bits_data[4],cam_d_0_data[4]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_5 = {cam_a_0_bits_data[5],cam_d_0_data[5]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_6 = {cam_a_0_bits_data[6],cam_d_0_data[6]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_7 = {cam_a_0_bits_data[7],cam_d_0_data[7]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_8 = {cam_a_0_bits_data[8],cam_d_0_data[8]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_9 = {cam_a_0_bits_data[9],cam_d_0_data[9]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_10 = {cam_a_0_bits_data[10],cam_d_0_data[10]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_11 = {cam_a_0_bits_data[11],cam_d_0_data[11]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_12 = {cam_a_0_bits_data[12],cam_d_0_data[12]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_13 = {cam_a_0_bits_data[13],cam_d_0_data[13]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_14 = {cam_a_0_bits_data[14],cam_d_0_data[14]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_15 = {cam_a_0_bits_data[15],cam_d_0_data[15]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_16 = {cam_a_0_bits_data[16],cam_d_0_data[16]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_17 = {cam_a_0_bits_data[17],cam_d_0_data[17]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_18 = {cam_a_0_bits_data[18],cam_d_0_data[18]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_19 = {cam_a_0_bits_data[19],cam_d_0_data[19]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_20 = {cam_a_0_bits_data[20],cam_d_0_data[20]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_21 = {cam_a_0_bits_data[21],cam_d_0_data[21]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_22 = {cam_a_0_bits_data[22],cam_d_0_data[22]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_23 = {cam_a_0_bits_data[23],cam_d_0_data[23]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_24 = {cam_a_0_bits_data[24],cam_d_0_data[24]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_25 = {cam_a_0_bits_data[25],cam_d_0_data[25]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_26 = {cam_a_0_bits_data[26],cam_d_0_data[26]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_27 = {cam_a_0_bits_data[27],cam_d_0_data[27]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_28 = {cam_a_0_bits_data[28],cam_d_0_data[28]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_29 = {cam_a_0_bits_data[29],cam_d_0_data[29]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_30 = {cam_a_0_bits_data[30],cam_d_0_data[30]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_31 = {cam_a_0_bits_data[31],cam_d_0_data[31]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_32 = {cam_a_0_bits_data[32],cam_d_0_data[32]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_33 = {cam_a_0_bits_data[33],cam_d_0_data[33]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_34 = {cam_a_0_bits_data[34],cam_d_0_data[34]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_35 = {cam_a_0_bits_data[35],cam_d_0_data[35]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_36 = {cam_a_0_bits_data[36],cam_d_0_data[36]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_37 = {cam_a_0_bits_data[37],cam_d_0_data[37]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_38 = {cam_a_0_bits_data[38],cam_d_0_data[38]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_39 = {cam_a_0_bits_data[39],cam_d_0_data[39]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_40 = {cam_a_0_bits_data[40],cam_d_0_data[40]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_41 = {cam_a_0_bits_data[41],cam_d_0_data[41]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_42 = {cam_a_0_bits_data[42],cam_d_0_data[42]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_43 = {cam_a_0_bits_data[43],cam_d_0_data[43]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_44 = {cam_a_0_bits_data[44],cam_d_0_data[44]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_45 = {cam_a_0_bits_data[45],cam_d_0_data[45]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_46 = {cam_a_0_bits_data[46],cam_d_0_data[46]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_47 = {cam_a_0_bits_data[47],cam_d_0_data[47]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_48 = {cam_a_0_bits_data[48],cam_d_0_data[48]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_49 = {cam_a_0_bits_data[49],cam_d_0_data[49]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_50 = {cam_a_0_bits_data[50],cam_d_0_data[50]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_51 = {cam_a_0_bits_data[51],cam_d_0_data[51]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_52 = {cam_a_0_bits_data[52],cam_d_0_data[52]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_53 = {cam_a_0_bits_data[53],cam_d_0_data[53]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_54 = {cam_a_0_bits_data[54],cam_d_0_data[54]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_55 = {cam_a_0_bits_data[55],cam_d_0_data[55]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_56 = {cam_a_0_bits_data[56],cam_d_0_data[56]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_57 = {cam_a_0_bits_data[57],cam_d_0_data[57]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_58 = {cam_a_0_bits_data[58],cam_d_0_data[58]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_59 = {cam_a_0_bits_data[59],cam_d_0_data[59]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_60 = {cam_a_0_bits_data[60],cam_d_0_data[60]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_61 = {cam_a_0_bits_data[61],cam_d_0_data[61]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_62 = {cam_a_0_bits_data[62],cam_d_0_data[62]}; // @[Cat.scala 31:58]
+ wire [1:0] indexes_63 = {cam_a_0_bits_data[63],cam_d_0_data[63]}; // @[Cat.scala 31:58]
+ wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala 114:57]
+ wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala 114:57]
+ wire [7:0] logic_out_lo_lo_lo = {_logic_out_T_14[0],_logic_out_T_12[0],_logic_out_T_10[0],_logic_out_T_8[0],
+ _logic_out_T_6[0],_logic_out_T_4[0],_logic_out_T_2[0],_logic_out_T[0]}; // @[Cat.scala 31:58]
+ wire [15:0] logic_out_lo_lo = {_logic_out_T_30[0],_logic_out_T_28[0],_logic_out_T_26[0],_logic_out_T_24[0],
+ _logic_out_T_22[0],_logic_out_T_20[0],_logic_out_T_18[0],_logic_out_T_16[0],logic_out_lo_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] logic_out_lo_hi_lo = {_logic_out_T_46[0],_logic_out_T_44[0],_logic_out_T_42[0],_logic_out_T_40[0],
+ _logic_out_T_38[0],_logic_out_T_36[0],_logic_out_T_34[0],_logic_out_T_32[0]}; // @[Cat.scala 31:58]
+ wire [31:0] logic_out_lo = {_logic_out_T_62[0],_logic_out_T_60[0],_logic_out_T_58[0],_logic_out_T_56[0],
+ _logic_out_T_54[0],_logic_out_T_52[0],_logic_out_T_50[0],_logic_out_T_48[0],logic_out_lo_hi_lo,logic_out_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] logic_out_hi_lo_lo = {_logic_out_T_78[0],_logic_out_T_76[0],_logic_out_T_74[0],_logic_out_T_72[0],
+ _logic_out_T_70[0],_logic_out_T_68[0],_logic_out_T_66[0],_logic_out_T_64[0]}; // @[Cat.scala 31:58]
+ wire [15:0] logic_out_hi_lo = {_logic_out_T_94[0],_logic_out_T_92[0],_logic_out_T_90[0],_logic_out_T_88[0],
+ _logic_out_T_86[0],_logic_out_T_84[0],_logic_out_T_82[0],_logic_out_T_80[0],logic_out_hi_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] logic_out_hi_hi_lo = {_logic_out_T_110[0],_logic_out_T_108[0],_logic_out_T_106[0],_logic_out_T_104[0],
+ _logic_out_T_102[0],_logic_out_T_100[0],_logic_out_T_98[0],_logic_out_T_96[0]}; // @[Cat.scala 31:58]
+ wire [31:0] logic_out_hi = {_logic_out_T_126[0],_logic_out_T_124[0],_logic_out_T_122[0],_logic_out_T_120[0],
+ _logic_out_T_118[0],_logic_out_T_116[0],_logic_out_T_114[0],_logic_out_T_112[0],logic_out_hi_hi_lo,logic_out_hi_lo}; // @[Cat.scala 31:58]
+ wire [63:0] logic_out = {logic_out_hi,logic_out_lo}; // @[Cat.scala 31:58]
+ wire unsigned_ = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala 117:42]
+ wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala 118:42]
+ wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala 119:39]
+ wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala 121:25]
+ wire [7:0] _GEN_39 = {{1'd0}, cam_a_0_bits_mask[7:1]}; // @[AtomicAutomata.scala 121:31]
+ wire [7:0] _signSel_T_2 = _signSel_T | _GEN_39; // @[AtomicAutomata.scala 121:31]
+ wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala 121:23]
+ wire [7:0] signbits_a = {cam_a_0_bits_data[63],cam_a_0_bits_data[55],cam_a_0_bits_data[47],cam_a_0_bits_data[39],
+ cam_a_0_bits_data[31],cam_a_0_bits_data[23],cam_a_0_bits_data[15],cam_a_0_bits_data[7]}; // @[Cat.scala 31:58]
+ wire [7:0] signbits_d = {cam_d_0_data[63],cam_d_0_data[55],cam_d_0_data[47],cam_d_0_data[39],cam_d_0_data[31],
+ cam_d_0_data[23],cam_d_0_data[15],cam_d_0_data[7]}; // @[Cat.scala 31:58]
+ wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala 125:38]
+ wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala 125:49]
+ wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala 125:54]
+ wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala 126:38]
+ wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala 126:49]
+ wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala 126:54]
+ wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T[7:0]; // @[package.scala 244:43]
+ wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_3[7:0]; // @[package.scala 244:43]
+ wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_6[7:0]; // @[package.scala 244:43]
+ wire [7:0] _signext_a_T_19 = _signext_a_T_8[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_21 = _signext_a_T_8[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_23 = _signext_a_T_8[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_25 = _signext_a_T_8[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_27 = _signext_a_T_8[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_29 = _signext_a_T_8[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_31 = _signext_a_T_8[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_a_T_33 = _signext_a_T_8[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] signext_a = {_signext_a_T_33,_signext_a_T_31,_signext_a_T_29,_signext_a_T_27,_signext_a_T_25,
+ _signext_a_T_23,_signext_a_T_21,_signext_a_T_19}; // @[Cat.scala 31:58]
+ wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T[7:0]; // @[package.scala 244:43]
+ wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_3[7:0]; // @[package.scala 244:43]
+ wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala 244:48]
+ wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_6[7:0]; // @[package.scala 244:43]
+ wire [7:0] _signext_d_T_19 = _signext_d_T_8[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_21 = _signext_d_T_8[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_23 = _signext_d_T_8[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_25 = _signext_d_T_8[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_27 = _signext_d_T_8[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_29 = _signext_d_T_8[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_31 = _signext_d_T_8[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _signext_d_T_33 = _signext_d_T_8[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] signext_d = {_signext_d_T_33,_signext_d_T_31,_signext_d_T_29,_signext_d_T_27,_signext_d_T_25,
+ _signext_d_T_23,_signext_d_T_21,_signext_d_T_19}; // @[Cat.scala 31:58]
+ wire [7:0] _wide_mask_T_9 = cam_a_0_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_11 = cam_a_0_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_13 = cam_a_0_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_15 = cam_a_0_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_17 = cam_a_0_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_19 = cam_a_0_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_21 = cam_a_0_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _wide_mask_T_23 = cam_a_0_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] wide_mask = {_wide_mask_T_23,_wide_mask_T_21,_wide_mask_T_19,_wide_mask_T_17,_wide_mask_T_15,
+ _wide_mask_T_13,_wide_mask_T_11,_wide_mask_T_9}; // @[Cat.scala 31:58]
+ wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala 131:28]
+ wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala 131:41]
+ wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala 132:28]
+ wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala 132:41]
+ wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala 133:43]
+ wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala 133:26]
+ wire [63:0] adder_out = a_a_ext + a_d_inv; // @[AtomicAutomata.scala 134:33]
+ wire a_bigger_uneq = unsigned_ == a_a_ext[63]; // @[AtomicAutomata.scala 136:38]
+ wire a_bigger = a_a_ext[63] == a_d_ext[63] ? ~adder_out[63] : a_bigger_uneq; // @[AtomicAutomata.scala 137:27]
+ wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala 138:31]
+ wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala 139:50]
+ wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala 139:28]
+ wire [63:0] amo_data = cam_a_0_bits_opcode[0] ? logic_out : arith_out; // @[AtomicAutomata.scala 145:14]
+ wire a_allow = ~cam_abusy_0 & (a_isSupported | cam_free_0); // @[AtomicAutomata.scala 149:35]
+ reg [8:0] beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle = beatsLeft == 9'h0; // @[Arbiter.scala 88:28]
+ wire source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala 151:38]
+ wire [1:0] _readys_T = {source_i_valid,cam_amo_0}; // @[Cat.scala 31:58]
+ wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala 244:48]
+ wire [1:0] _readys_T_3 = _readys_T | _readys_T_1[1:0]; // @[package.scala 244:43]
+ wire [2:0] _readys_T_5 = {_readys_T_3, 1'h0}; // @[Arbiter.scala 16:78]
+ wire [1:0] _readys_T_7 = ~_readys_T_5[1:0]; // @[Arbiter.scala 16:61]
+ wire readys_1 = _readys_T_7[1]; // @[Arbiter.scala 95:86]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire out_1_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
+ wire _T = ~a_isSupported; // @[AtomicAutomata.scala 153:15]
+ wire [2:0] source_i_bits_opcode = ~a_isSupported ? 3'h4 : auto_in_a_bits_opcode; // @[AtomicAutomata.scala 152:24 153:31 154:32]
+ wire [2:0] source_i_bits_param = ~a_isSupported ? 3'h0 : auto_in_a_bits_param; // @[AtomicAutomata.scala 152:24 153:31 155:32]
+ wire source_c_bits_a_corrupt = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala 166:45]
+ wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = cam_a_0_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] source_c_bits_a_mask_sizeOH = _source_c_bits_a_mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _source_c_bits_a_mask_T = cam_a_0_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire source_c_bits_a_mask_bit = cam_a_0_bits_address[2]; // @[Misc.scala 209:26]
+ wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala 210:20]
+ wire source_c_bits_a_mask_acc = _source_c_bits_a_mask_T | source_c_bits_a_mask_size & source_c_bits_a_mask_nbit; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_acc_1 = _source_c_bits_a_mask_T | source_c_bits_a_mask_size & source_c_bits_a_mask_bit; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_size_1 = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire source_c_bits_a_mask_bit_1 = cam_a_0_bits_address[1]; // @[Misc.scala 209:26]
+ wire source_c_bits_a_mask_nbit_1 = ~source_c_bits_a_mask_bit_1; // @[Misc.scala 210:20]
+ wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_nbit & source_c_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_acc | source_c_bits_a_mask_size_1 & source_c_bits_a_mask_eq_2; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_nbit & source_c_bits_a_mask_bit_1; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_acc | source_c_bits_a_mask_size_1 & source_c_bits_a_mask_eq_3; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_bit & source_c_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_acc_1 | source_c_bits_a_mask_size_1 &
+ source_c_bits_a_mask_eq_4; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_bit & source_c_bits_a_mask_bit_1; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_acc_1 | source_c_bits_a_mask_size_1 &
+ source_c_bits_a_mask_eq_5; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_size_2 = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire source_c_bits_a_mask_bit_2 = cam_a_0_bits_address[0]; // @[Misc.scala 209:26]
+ wire source_c_bits_a_mask_nbit_2 = ~source_c_bits_a_mask_bit_2; // @[Misc.scala 210:20]
+ wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_eq_2 & source_c_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_acc_2 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_6; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_eq_2 & source_c_bits_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_acc_2 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_7; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_8 = source_c_bits_a_mask_eq_3 & source_c_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_8 = source_c_bits_a_mask_acc_3 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_8; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_9 = source_c_bits_a_mask_eq_3 & source_c_bits_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_9 = source_c_bits_a_mask_acc_3 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_9; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_10 = source_c_bits_a_mask_eq_4 & source_c_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_10 = source_c_bits_a_mask_acc_4 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_10; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_11 = source_c_bits_a_mask_eq_4 & source_c_bits_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_11 = source_c_bits_a_mask_acc_4 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_11; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_12 = source_c_bits_a_mask_eq_5 & source_c_bits_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_12 = source_c_bits_a_mask_acc_5 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_12; // @[Misc.scala 214:29]
+ wire source_c_bits_a_mask_eq_13 = source_c_bits_a_mask_eq_5 & source_c_bits_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire source_c_bits_a_mask_acc_13 = source_c_bits_a_mask_acc_5 | source_c_bits_a_mask_size_2 &
+ source_c_bits_a_mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] source_c_bits_a_mask = {source_c_bits_a_mask_acc_13,source_c_bits_a_mask_acc_12,source_c_bits_a_mask_acc_11
+ ,source_c_bits_a_mask_acc_10,source_c_bits_a_mask_acc_9,source_c_bits_a_mask_acc_8,source_c_bits_a_mask_acc_7,
+ source_c_bits_a_mask_acc_6}; // @[Cat.scala 31:58]
+ wire [26:0] _decode_T_1 = 27'hfff << auto_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] _decode_T_3 = ~_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] decode = _decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire opdata = ~auto_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ wire latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
+ wire readys_0 = _readys_T_7[0]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_0 = readys_0 & cam_amo_0; // @[Arbiter.scala 97:79]
+ wire earlyWinner_1 = readys_1 & source_i_valid; // @[Arbiter.scala 97:79]
+ wire _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
+ wire _T_10 = ~reset; // @[Arbiter.scala 105:13]
+ wire _T_12 = cam_amo_0 | source_i_valid; // @[Arbiter.scala 107:36]
+ wire _T_13 = ~(cam_amo_0 | source_i_valid); // @[Arbiter.scala 107:15]
+ reg state_0; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ wire muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire _sink_ACancel_earlyValid_T_3 = state_0 & cam_amo_0 | state_1 & source_i_valid; // @[Mux.scala 27:73]
+ wire sink_ACancel_earlyValid = idle ? _T_12 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_out_a_ready & sink_ACancel_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ wire [8:0] _GEN_40 = {{8'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
+ wire [8:0] _beatsLeft_T_4 = beatsLeft - _GEN_40; // @[Arbiter.scala 113:52]
+ wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
+ wire out_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
+ wire [63:0] _T_29 = muxStateEarly_0 ? amo_data : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _T_30 = muxStateEarly_1 ? auto_in_a_bits_data : 64'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_32 = muxStateEarly_0 ? source_c_bits_a_mask : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_33 = muxStateEarly_1 ? auto_in_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_35 = muxStateEarly_0 ? cam_a_0_bits_address : 32'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_36 = muxStateEarly_1 ? auto_in_a_bits_address : 32'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_38 = muxStateEarly_0 ? cam_a_0_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_39 = muxStateEarly_1 ? auto_in_a_bits_source : 3'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_41 = muxStateEarly_0 ? cam_a_0_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_42 = muxStateEarly_1 ? auto_in_a_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire _T_50 = out_1_ready & source_i_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_41 = {{1'd0}, auto_in_a_bits_param[1:0]}; // @[Mux.scala 81:61]
+ wire [3:0] _cam_a_0_lut_T_2 = 3'h1 == _GEN_41 ? 4'he : 4'h8; // @[Mux.scala 81:58]
+ wire [1:0] _GEN_12 = cam_free_0 ? 2'h3 : cam_s_0_state; // @[AtomicAutomata.scala 187:23 188:23 76:28]
+ wire [1:0] _GEN_23 = _T_50 & _T ? _GEN_12 : cam_s_0_state; // @[AtomicAutomata.scala 174:50 76:28]
+ wire _T_53 = out_ready & cam_amo_0; // @[Decoupled.scala 50:35]
+ wire [1:0] _GEN_24 = cam_amo_0 ? 2'h1 : _GEN_23; // @[AtomicAutomata.scala 196:23 197:23]
+ wire [1:0] _GEN_25 = _T_53 ? _GEN_24 : _GEN_23; // @[AtomicAutomata.scala 194:32]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ wire d_ackd = auto_out_d_bits_opcode == 3'h1; // @[AtomicAutomata.scala 213:40]
+ wire d_cam_sel_raw_0 = cam_a_0_bits_source == auto_out_d_bits_source; // @[AtomicAutomata.scala 204:53]
+ wire d_cam_sel_match_0 = d_cam_sel_raw_0 & cam_dmatch_0; // @[AtomicAutomata.scala 205:83]
+ wire d_drop = d_first & d_ackd & d_cam_sel_match_0; // @[AtomicAutomata.scala 232:40]
+ wire bundleOut_0_d_ready = auto_in_d_ready | d_drop; // @[AtomicAutomata.scala 236:35]
+ wire _d_first_T = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_ack = auto_out_d_bits_opcode == 3'h0; // @[AtomicAutomata.scala 214:40]
+ wire d_replace = d_first & d_ack & d_cam_sel_match_0; // @[AtomicAutomata.scala 233:42]
+ TLMonitor_29 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = out_1_ready & a_allow; // @[AtomicAutomata.scala 150:38]
+ assign auto_in_d_valid = auto_out_d_valid & ~d_drop; // @[AtomicAutomata.scala 235:35]
+ assign auto_in_d_bits_opcode = d_replace ? 3'h1 : auto_out_d_bits_opcode; // @[AtomicAutomata.scala 238:19 239:26 240:28]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = d_replace ? cam_d_0_denied | auto_out_d_bits_denied : auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:19 239:26 243:29]
+ assign auto_in_d_bits_data = d_replace ? cam_d_0_data : auto_out_d_bits_data; // @[AtomicAutomata.scala 238:19 239:26 241:26]
+ assign auto_in_d_bits_corrupt = d_replace ? cam_d_0_corrupt | auto_out_d_bits_denied : auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 238:19 239:26 242:29]
+ assign auto_out_a_valid = idle ? _T_12 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ assign auto_out_a_bits_opcode = muxStateEarly_1 ? source_i_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_param = muxStateEarly_1 ? source_i_bits_param : 3'h0; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_size = _T_41 | _T_42; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_source = _T_38 | _T_39; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_address = _T_35 | _T_36; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_mask = _T_32 | _T_33; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_data = _T_29 | _T_30; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_corrupt = muxStateEarly_0 & source_c_bits_a_corrupt | muxStateEarly_1 & auto_in_a_bits_corrupt; // @[Mux.scala 27:73]
+ assign auto_out_d_ready = auto_in_d_ready | d_drop; // @[AtomicAutomata.scala 236:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = out_1_ready & a_allow; // @[AtomicAutomata.scala 150:38]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~d_drop; // @[AtomicAutomata.scala 235:35]
+ assign monitor_io_in_d_bits_opcode = d_replace ? 3'h1 : auto_out_d_bits_opcode; // @[AtomicAutomata.scala 238:19 239:26 240:28]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_denied = d_replace ? cam_d_0_denied | auto_out_d_bits_denied : auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:19 239:26 243:29]
+ assign monitor_io_in_d_bits_corrupt = d_replace ? cam_d_0_corrupt | auto_out_d_bits_denied : auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 238:19 239:26 242:29]
+ always @(posedge clock) begin
+ if (reset) begin // @[AtomicAutomata.scala 76:28]
+ cam_s_0_state <= 2'h0; // @[AtomicAutomata.scala 76:28]
+ end else if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
+ if (d_cam_sel_match_0) begin // @[AtomicAutomata.scala 225:23]
+ if (d_ackd) begin // @[AtomicAutomata.scala 227:29]
+ cam_s_0_state <= 2'h2;
+ end else begin
+ cam_s_0_state <= 2'h0;
+ end
+ end else begin
+ cam_s_0_state <= _GEN_25;
+ end
+ end else begin
+ cam_s_0_state <= _GEN_25;
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_opcode <= auto_in_a_bits_opcode; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_param <= auto_in_a_bits_param; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_size <= auto_in_a_bits_size; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_source <= auto_in_a_bits_source; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_address <= auto_in_a_bits_address; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_mask <= auto_in_a_bits_mask; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_data <= auto_in_a_bits_data; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ cam_a_0_bits_corrupt <= auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 178:24]
+ end
+ end
+ if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
+ if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
+ if (3'h3 == _GEN_41) begin // @[Mux.scala 81:58]
+ cam_a_0_lut <= 4'hc;
+ end else if (3'h0 == _GEN_41) begin // @[Mux.scala 81:58]
+ cam_a_0_lut <= 4'h6;
+ end else begin
+ cam_a_0_lut <= _cam_a_0_lut_T_2;
+ end
+ end
+ end
+ if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
+ if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
+ cam_d_0_data <= auto_out_d_bits_data; // @[AtomicAutomata.scala 219:22]
+ end
+ end
+ if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
+ if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
+ cam_d_0_denied <= auto_out_d_bits_denied; // @[AtomicAutomata.scala 220:24]
+ end
+ end
+ if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
+ if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
+ cam_d_0_corrupt <= auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 221:25]
+ end
+ end
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 9'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ if (earlyWinner_1) begin // @[Arbiter.scala 111:73]
+ if (opdata) begin // @[Edges.scala 220:14]
+ beatsLeft <= decode;
+ end else begin
+ beatsLeft <= 9'h0;
+ end
+ end else begin
+ beatsLeft <= 9'h0;
+ end
+ end else begin
+ beatsLeft <= _beatsLeft_T_4;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_0 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_0 <= earlyWinner_0;
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~earlyWinner_0 | ~earlyWinner_1) & ~reset) begin
+ $fatal; // @[Arbiter.scala 105:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
+ ); // @[Arbiter.scala 105:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(cam_amo_0 | source_i_valid) | _prefixOR_T) & _T_10) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_10 & ~(~(cam_amo_0 | source_i_valid) | _prefixOR_T)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_13 | _T_12) & _T_10) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_10 & ~(_T_13 | _T_12)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ cam_s_0_state = _RAND_0[1:0];
+ _RAND_1 = {1{`RANDOM}};
+ cam_a_0_bits_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ cam_a_0_bits_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ cam_a_0_bits_size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ cam_a_0_bits_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ cam_a_0_bits_address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ cam_a_0_bits_mask = _RAND_6[7:0];
+ _RAND_7 = {2{`RANDOM}};
+ cam_a_0_bits_data = _RAND_7[63:0];
+ _RAND_8 = {1{`RANDOM}};
+ cam_a_0_bits_corrupt = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ cam_a_0_lut = _RAND_9[3:0];
+ _RAND_10 = {2{`RANDOM}};
+ cam_d_0_data = _RAND_10[63:0];
+ _RAND_11 = {1{`RANDOM}};
+ cam_d_0_denied = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ cam_d_0_corrupt = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ beatsLeft = _RAND_13[8:0];
+ _RAND_14 = {1{`RANDOM}};
+ state_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ state_0 = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ d_first_counter = _RAND_16[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_30(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [13:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [3:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [63:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [63:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [13:0] _GEN_71 = {{2'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [13:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_44 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_53 = _T_44 & source_ok; // @[Parameters.scala 1160:30]
+ wire [13:0] _T_56 = io_in_a_bits_address ^ 14'h3000; // @[Parameters.scala 137:31]
+ wire [14:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [14:0] _T_59 = $signed(_T_57) & -15'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 15'sh0; // @[Parameters.scala 137:67]
+ wire _T_76 = _T_44 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = _T_53 & _T_76; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_320 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_328 = _T_320 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_330 = _T_53 & _T_328; // @[Monitor.scala 131:74]
+ wire _T_340 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_348 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_382 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_390 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_424 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_436 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_440 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_444 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_452 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_460 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_488 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_517 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_534 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_552 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [13:0] address; // @[Monitor.scala 388:22]
+ wire _T_582 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_583 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_587 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_591 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_595 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_599 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_606 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_607 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_615 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_619 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [39:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [5:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [39:0] _GEN_75 = {{24'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala 638:144]
+ wire _T_633 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_636 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [5:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [67:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [67:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_638 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_640 = ~_T_638[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [67:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 68'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_644 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_646 = ~_T_440; // @[Monitor.scala 671:74]
+ wire _T_647 = io_in_d_valid & d_first_1 & ~_T_440; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_440 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [78:0] _GEN_4 = {{63'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [78:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_646 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_646 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire [78:0] _GEN_24 = _d_first_T & d_first_1 & _T_646 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_633 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_657 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_659 = _T_657[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_664 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_665 = io_in_d_bits_opcode == _GEN_32 | _T_664; // @[Monitor.scala 685:77]
+ wire _T_669 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_676 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_677 = io_in_d_bits_opcode == _GEN_48 | _T_676; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_681 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_691 = _T_644 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_646; // @[Monitor.scala 694:116]
+ wire _T_693 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_700 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [39:0] a_sizes_set = _GEN_20[39:0];
+ wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [39:0] d_sizes_clr = _GEN_24[39:0];
+ wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_709 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [39:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [39:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
+ wire [39:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala 747:146]
+ wire _T_735 = io_in_d_valid & d_first_2 & _T_440; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_440 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_69 = _d_first_T & d_first_2 & _T_440 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 786:21]
+ wire [4:0] _T_743 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_753 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [39:0] d_sizes_clr_1 = _GEN_69[39:0];
+ wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [39:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_778 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 40'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 40'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_53 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_53) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_76 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_76) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_330 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_330) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_340 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_340) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_330 & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~_T_330) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_382 & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~_T_382) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_424 & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~_T_424) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_436 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_436) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_440 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_444 & (io_in_d_valid & _T_440 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2 & ~_T_444) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_452 & (io_in_d_valid & _T_440 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2 & ~_T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_460 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_444 & (io_in_d_valid & _T_460 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2 & ~_T_444) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_452 & (io_in_d_valid & _T_460 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2 & ~_T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_488 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_444 & (io_in_d_valid & _T_488 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2 & ~_T_444) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_452 & (io_in_d_valid & _T_488 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2 & _T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_517 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_517 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_452 & (io_in_d_valid & _T_517 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_517 & _T_2 & ~_T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_534 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_534 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_452 & (io_in_d_valid & _T_534 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_534 & _T_2 & _T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_552 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_552 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_452 & (io_in_d_valid & _T_552 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_552 & _T_2 & ~_T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_583 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_583) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_587 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_587) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_591 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_591) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_595 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_595) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_599 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_599) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_607 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_607) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_615 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_615) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_619 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_619) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_640 & (_T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_636 & ~reset & ~_T_640) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_659 & (_T_647 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & _T_2 & ~_T_659) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_665 & (_T_647 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & same_cycle_resp & _T_2 & ~_T_665) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_669 & (_T_647 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & same_cycle_resp & _T_2 & ~_T_669) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_677 & (_T_647 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & ~same_cycle_resp & _T_2 & ~_T_677) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_681 & (_T_647 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & ~same_cycle_resp & _T_2 & ~_T_681) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & (_T_691 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_691 & _T_2 & ~_T_693) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_700 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_700) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_709 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_709) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743[0] & (_T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_735 & _T_2 & ~_T_743[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (_T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_735 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_778 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_778) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:43:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[13:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[3:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {2{`RANDOM}};
+ inflight_sizes = _RAND_12[39:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[8:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[8:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {2{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[39:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[8:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_12(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [3:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [3:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [3:0] ram_size [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire empty = ~maybe_full; // @[Decoupled.scala 264:28]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = 1'h0;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = 1'h0;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = 1'h0;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_size[initvar] = _RAND_1[3:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_source[initvar] = _RAND_2[2:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_3 = {1{`RANDOM}};
+ maybe_full = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLError(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [13:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [3:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [13:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire a_clock; // @[Decoupled.scala 361:21]
+ wire a_reset; // @[Decoupled.scala 361:21]
+ wire a_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire a_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] a_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [3:0] a_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] a_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire a_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire a_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] a_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [3:0] a_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] a_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire _a_last_T = a_io_deq_ready & a_io_deq_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _a_last_beats1_decode_T_1 = 27'hfff << a_io_deq_bits_size; // @[package.scala 234:77]
+ wire [11:0] _a_last_beats1_decode_T_3 = ~_a_last_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire a_last_beats1_opdata = ~a_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala 220:14]
+ reg [8:0] a_last_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_last_counter1 = a_last_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala 230:25]
+ wire a_last = a_last_counter == 9'h1 | a_last_beats1 == 9'h0; // @[Edges.scala 231:37]
+ wire da_valid = a_io_deq_valid & a_last; // @[Error.scala 51:25]
+ wire _T = auto_in_d_ready & da_valid; // @[Decoupled.scala 50:35]
+ wire [3:0] da_bits_size = a_io_deq_bits_size; // @[Error.scala 43:18 55:21]
+ wire [26:0] _beats1_decode_T_1 = 27'hfff << da_bits_size; // @[package.scala 234:77]
+ wire [11:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] beats1_decode = _beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire [2:0] _GEN_4 = 3'h2 == a_io_deq_bits_opcode ? 3'h1 : 3'h0; // @[Error.scala 53:{21,21}]
+ wire [2:0] _GEN_5 = 3'h3 == a_io_deq_bits_opcode ? 3'h1 : _GEN_4; // @[Error.scala 53:{21,21}]
+ wire [2:0] _GEN_6 = 3'h4 == a_io_deq_bits_opcode ? 3'h1 : _GEN_5; // @[Error.scala 53:{21,21}]
+ wire [2:0] _GEN_7 = 3'h5 == a_io_deq_bits_opcode ? 3'h2 : _GEN_6; // @[Error.scala 53:{21,21}]
+ wire [2:0] _GEN_8 = 3'h6 == a_io_deq_bits_opcode ? 3'h4 : _GEN_7; // @[Error.scala 53:{21,21}]
+ wire [2:0] da_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 53:{21,21}]
+ wire beats1_opdata = da_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [8:0] beats1 = beats1_opdata ? beats1_decode : 9'h0; // @[Edges.scala 220:14]
+ reg [8:0] counter; // @[Edges.scala 228:27]
+ wire [8:0] counter1 = counter - 9'h1; // @[Edges.scala 229:28]
+ wire da_first = counter == 9'h0; // @[Edges.scala 230:25]
+ wire da_last = counter == 9'h1 | beats1 == 9'h0; // @[Edges.scala 231:37]
+ TLMonitor_30 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_12 a ( // @[Decoupled.scala 361:21]
+ .clock(a_clock),
+ .reset(a_reset),
+ .io_enq_ready(a_io_enq_ready),
+ .io_enq_valid(a_io_enq_valid),
+ .io_enq_bits_opcode(a_io_enq_bits_opcode),
+ .io_enq_bits_size(a_io_enq_bits_size),
+ .io_enq_bits_source(a_io_enq_bits_source),
+ .io_deq_ready(a_io_deq_ready),
+ .io_deq_valid(a_io_deq_valid),
+ .io_deq_bits_opcode(a_io_deq_bits_opcode),
+ .io_deq_bits_size(a_io_deq_bits_size),
+ .io_deq_bits_source(a_io_deq_bits_source)
+ );
+ assign auto_in_a_ready = a_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = a_io_deq_valid & a_last; // @[Error.scala 51:25]
+ assign auto_in_d_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 53:{21,21}]
+ assign auto_in_d_bits_size = a_io_deq_bits_size; // @[Error.scala 43:18 55:21]
+ assign auto_in_d_bits_source = a_io_deq_bits_source; // @[Error.scala 43:18 56:21]
+ assign auto_in_d_bits_corrupt = da_bits_opcode[0]; // @[Edges.scala 105:36]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = a_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = a_io_deq_valid & a_last; // @[Error.scala 51:25]
+ assign monitor_io_in_d_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 53:{21,21}]
+ assign monitor_io_in_d_bits_size = a_io_deq_bits_size; // @[Error.scala 43:18 55:21]
+ assign monitor_io_in_d_bits_source = a_io_deq_bits_source; // @[Error.scala 43:18 56:21]
+ assign monitor_io_in_d_bits_corrupt = da_bits_opcode[0]; // @[Edges.scala 105:36]
+ assign a_clock = clock;
+ assign a_reset = reset;
+ assign a_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign a_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign a_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign a_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign a_io_deq_ready = auto_in_d_ready & da_last | ~a_last; // @[Error.scala 50:46]
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_last_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_last_T) begin // @[Edges.scala 234:17]
+ if (a_last_first) begin // @[Edges.scala 235:21]
+ if (a_last_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_last_counter <= a_last_beats1_decode;
+ end else begin
+ a_last_counter <= 9'h0;
+ end
+ end else begin
+ a_last_counter <= a_last_counter1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_T) begin // @[Edges.scala 234:17]
+ if (da_first) begin // @[Edges.scala 235:21]
+ if (beats1_opdata) begin // @[Edges.scala 220:14]
+ counter <= beats1_decode;
+ end else begin
+ counter <= 9'h0;
+ end
+ end else begin
+ counter <= counter1;
+ end
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_last_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ counter = _RAND_1[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_31(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [13:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [63:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [63:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [13:0] _GEN_71 = {{2'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [13:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_44 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_53 = _T_44 & source_ok; // @[Parameters.scala 1160:30]
+ wire [13:0] _T_56 = io_in_a_bits_address ^ 14'h3000; // @[Parameters.scala 137:31]
+ wire [14:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [14:0] _T_59 = $signed(_T_57) & -15'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 15'sh0; // @[Parameters.scala 137:67]
+ wire _T_76 = _T_44 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = _T_53 & _T_76; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_320 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_328 = _T_320 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_330 = _T_53 & _T_328; // @[Monitor.scala 131:74]
+ wire _T_340 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_348 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_382 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_390 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_424 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_436 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_440 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_444 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_448 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_452 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_456 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_460 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_471 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_475 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_488 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = _T_456 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_517 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_534 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_552 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [13:0] address; // @[Monitor.scala 388:22]
+ wire _T_582 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_583 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_587 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_591 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_595 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_599 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_606 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_607 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_611 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_615 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_619 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_623 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_627 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [39:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [5:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [39:0] _GEN_75 = {{24'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
+ wire [39:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala 638:144]
+ wire _T_633 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_636 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [5:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [67:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [67:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_638 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_640 = ~_T_638[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [67:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 68'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_644 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_646 = ~_T_440; // @[Monitor.scala 671:74]
+ wire _T_647 = io_in_d_valid & d_first_1 & ~_T_440; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_440 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [78:0] _GEN_4 = {{63'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [78:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_646 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_646 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire [78:0] _GEN_24 = _d_first_T & d_first_1 & _T_646 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_633 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_657 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_659 = _T_657[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_664 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_665 = io_in_d_bits_opcode == _GEN_32 | _T_664; // @[Monitor.scala 685:77]
+ wire _T_669 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_676 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_677 = io_in_d_bits_opcode == _GEN_48 | _T_676; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_681 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_691 = _T_644 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_646; // @[Monitor.scala 694:116]
+ wire _T_693 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_700 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [39:0] a_sizes_set = _GEN_20[39:0];
+ wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [39:0] d_sizes_clr = _GEN_24[39:0];
+ wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_709 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [39:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [39:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
+ wire [39:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala 747:146]
+ wire _T_735 = io_in_d_valid & d_first_2 & _T_440; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_440 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_69 = _d_first_T & d_first_2 & _T_440 ? _d_sizes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 786:21]
+ wire [4:0] _T_743 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_753 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [39:0] d_sizes_clr_1 = _GEN_69[39:0];
+ wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [39:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_778 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 40'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 40'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_53 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_53) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_76 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_76) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_330 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_330) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_340 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_340) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_330 & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~_T_330) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_382 & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~_T_382) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_348 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_348 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_424 & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~_T_424) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_390 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_390 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_436 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_436) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_440 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_444 & (io_in_d_valid & _T_440 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2 & ~_T_444) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_448 & (io_in_d_valid & _T_440 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2 & ~_T_448) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_452 & (io_in_d_valid & _T_440 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2 & ~_T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_456 & (io_in_d_valid & _T_440 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_440 & _T_2 & ~_T_456) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_460 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_444 & (io_in_d_valid & _T_460 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2 & ~_T_444) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_471 & (io_in_d_valid & _T_460 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2 & ~_T_471) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_475 & (io_in_d_valid & _T_460 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2 & ~_T_475) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_452 & (io_in_d_valid & _T_460 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_460 & _T_2 & ~_T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_488 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_444 & (io_in_d_valid & _T_488 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2 & ~_T_444) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_471 & (io_in_d_valid & _T_488 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2 & ~_T_471) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_475 & (io_in_d_valid & _T_488 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2 & ~_T_475) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_508 & (io_in_d_valid & _T_488 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_488 & _T_2 & ~_T_508) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_517 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_517 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_448 & (io_in_d_valid & _T_517 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_517 & _T_2 & ~_T_448) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_452 & (io_in_d_valid & _T_517 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_517 & _T_2 & ~_T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_534 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_534 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_448 & (io_in_d_valid & _T_534 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_534 & _T_2 & ~_T_448) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_508 & (io_in_d_valid & _T_534 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_534 & _T_2 & ~_T_508) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_552 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_552 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_448 & (io_in_d_valid & _T_552 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_552 & _T_2 & ~_T_448) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_452 & (io_in_d_valid & _T_552 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_552 & _T_2 & ~_T_452) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_583 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_583) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_587 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_587) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_591 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_591) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_595 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_595) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_599 & (_T_582 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_582 & ~reset & ~_T_599) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_607 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_607) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_611 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_611) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_615 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_615) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_619 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_619) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_623 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_623) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_627 & (_T_606 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_606 & _T_2 & ~_T_627) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_640 & (_T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_636 & ~reset & ~_T_640) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_659 & (_T_647 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & _T_2 & ~_T_659) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_665 & (_T_647 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & same_cycle_resp & _T_2 & ~_T_665) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_669 & (_T_647 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & same_cycle_resp & _T_2 & ~_T_669) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_677 & (_T_647 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & ~same_cycle_resp & _T_2 & ~_T_677) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_681 & (_T_647 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_647 & ~same_cycle_resp & _T_2 & ~_T_681) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & (_T_691 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_691 & _T_2 & ~_T_693) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_700 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_700) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_709 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_709) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_743[0] & (_T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_735 & _T_2 & ~_T_743[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_753 & (_T_735 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_735 & _T_2 & ~_T_753) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_778 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_778) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:44:9)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[13:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {2{`RANDOM}};
+ inflight_sizes = _RAND_15[39:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {2{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[39:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_13(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [3:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [13:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [3:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [13:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [13:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [13:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [13:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_address_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_address_io_deq_bits_MPORT_addr = value_1;
+ assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_address_MPORT_data = io_enq_bits_address;
+ assign ram_address_MPORT_addr = value;
+ assign ram_address_MPORT_mask = 1'h1;
+ assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = value_1;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = value;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
+ ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[3:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_address[initvar] = _RAND_4[13:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_5[7:0];
+ _RAND_6 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_6[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_7 = {1{`RANDOM}};
+ value = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ value_1 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ maybe_full = _RAND_9[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_9(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [13:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [13:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [3:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [13:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [13:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [13:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_31 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_13 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_11 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = 2'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = 1'h1; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = 64'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ErrorDeviceWrapper(
+ input clock,
+ input reset,
+ output auto_buffer_in_a_ready,
+ input auto_buffer_in_a_valid,
+ input [2:0] auto_buffer_in_a_bits_opcode,
+ input [2:0] auto_buffer_in_a_bits_param,
+ input [3:0] auto_buffer_in_a_bits_size,
+ input [2:0] auto_buffer_in_a_bits_source,
+ input [13:0] auto_buffer_in_a_bits_address,
+ input [7:0] auto_buffer_in_a_bits_mask,
+ input auto_buffer_in_a_bits_corrupt,
+ input auto_buffer_in_d_ready,
+ output auto_buffer_in_d_valid,
+ output [2:0] auto_buffer_in_d_bits_opcode,
+ output [1:0] auto_buffer_in_d_bits_param,
+ output [3:0] auto_buffer_in_d_bits_size,
+ output [2:0] auto_buffer_in_d_bits_source,
+ output auto_buffer_in_d_bits_sink,
+ output auto_buffer_in_d_bits_denied,
+ output [63:0] auto_buffer_in_d_bits_data,
+ output auto_buffer_in_d_bits_corrupt
+);
+ wire error_clock; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire error_reset; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire error_auto_in_a_ready; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire error_auto_in_a_valid; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [2:0] error_auto_in_a_bits_opcode; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [2:0] error_auto_in_a_bits_param; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [3:0] error_auto_in_a_bits_size; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [2:0] error_auto_in_a_bits_source; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [13:0] error_auto_in_a_bits_address; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [7:0] error_auto_in_a_bits_mask; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire error_auto_in_a_bits_corrupt; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire error_auto_in_d_ready; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire error_auto_in_d_valid; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [2:0] error_auto_in_d_bits_opcode; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [3:0] error_auto_in_d_bits_size; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire [2:0] error_auto_in_d_bits_source; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire error_auto_in_d_bits_corrupt; // @[CanHaveBuiltInDevices.scala 38:29]
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [13:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [13:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ TLError error ( // @[CanHaveBuiltInDevices.scala 38:29]
+ .clock(error_clock),
+ .reset(error_reset),
+ .auto_in_a_ready(error_auto_in_a_ready),
+ .auto_in_a_valid(error_auto_in_a_valid),
+ .auto_in_a_bits_opcode(error_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(error_auto_in_a_bits_param),
+ .auto_in_a_bits_size(error_auto_in_a_bits_size),
+ .auto_in_a_bits_source(error_auto_in_a_bits_source),
+ .auto_in_a_bits_address(error_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(error_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(error_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(error_auto_in_d_ready),
+ .auto_in_d_valid(error_auto_in_d_valid),
+ .auto_in_d_bits_opcode(error_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(error_auto_in_d_bits_size),
+ .auto_in_d_bits_source(error_auto_in_d_bits_source),
+ .auto_in_d_bits_corrupt(error_auto_in_d_bits_corrupt)
+ );
+ TLBuffer_9 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
+ );
+ assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign error_clock = clock;
+ assign error_reset = reset;
+ assign error_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign error_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign error_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign error_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign error_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign error_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign error_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign error_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign error_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign buffer_clock = clock;
+ assign buffer_reset = reset;
+ assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = error_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = error_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = error_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_size = error_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = error_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_corrupt = error_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+endmodule
+module TLBuffer_10(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input [1:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output [1:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [1:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input [1:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLWidthWidget_7(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLInterconnectCoupler_15(
+ output auto_widget_in_a_ready,
+ input auto_widget_in_a_valid,
+ input [2:0] auto_widget_in_a_bits_opcode,
+ input [2:0] auto_widget_in_a_bits_param,
+ input [2:0] auto_widget_in_a_bits_size,
+ input [2:0] auto_widget_in_a_bits_source,
+ input [29:0] auto_widget_in_a_bits_address,
+ input [7:0] auto_widget_in_a_bits_mask,
+ input [63:0] auto_widget_in_a_bits_data,
+ input auto_widget_in_a_bits_corrupt,
+ input auto_widget_in_d_ready,
+ output auto_widget_in_d_valid,
+ output [2:0] auto_widget_in_d_bits_opcode,
+ output [1:0] auto_widget_in_d_bits_param,
+ output [2:0] auto_widget_in_d_bits_size,
+ output [2:0] auto_widget_in_d_bits_source,
+ output auto_widget_in_d_bits_sink,
+ output auto_widget_in_d_bits_denied,
+ output [63:0] auto_widget_in_d_bits_data,
+ output auto_widget_in_d_bits_corrupt,
+ input auto_bus_xing_out_a_ready,
+ output auto_bus_xing_out_a_valid,
+ output [2:0] auto_bus_xing_out_a_bits_opcode,
+ output [2:0] auto_bus_xing_out_a_bits_param,
+ output [2:0] auto_bus_xing_out_a_bits_size,
+ output [2:0] auto_bus_xing_out_a_bits_source,
+ output [29:0] auto_bus_xing_out_a_bits_address,
+ output [7:0] auto_bus_xing_out_a_bits_mask,
+ output [63:0] auto_bus_xing_out_a_bits_data,
+ output auto_bus_xing_out_a_bits_corrupt,
+ output auto_bus_xing_out_d_ready,
+ input auto_bus_xing_out_d_valid,
+ input [2:0] auto_bus_xing_out_d_bits_opcode,
+ input [1:0] auto_bus_xing_out_d_bits_param,
+ input [2:0] auto_bus_xing_out_d_bits_size,
+ input [2:0] auto_bus_xing_out_d_bits_source,
+ input auto_bus_xing_out_d_bits_sink,
+ input auto_bus_xing_out_d_bits_denied,
+ input [63:0] auto_bus_xing_out_d_bits_data,
+ input auto_bus_xing_out_d_bits_corrupt
+);
+ wire widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [29:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [29:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ TLWidthWidget_7 widget ( // @[WidthWidget.scala 219:28]
+ .auto_in_a_ready(widget_auto_in_a_ready),
+ .auto_in_a_valid(widget_auto_in_a_valid),
+ .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(widget_auto_in_a_bits_param),
+ .auto_in_a_bits_size(widget_auto_in_a_bits_size),
+ .auto_in_a_bits_source(widget_auto_in_a_bits_source),
+ .auto_in_a_bits_address(widget_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(widget_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(widget_auto_in_d_ready),
+ .auto_in_d_valid(widget_auto_in_d_valid),
+ .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(widget_auto_in_d_bits_param),
+ .auto_in_d_bits_size(widget_auto_in_d_bits_size),
+ .auto_in_d_bits_source(widget_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(widget_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(widget_auto_out_a_ready),
+ .auto_out_a_valid(widget_auto_out_a_valid),
+ .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(widget_auto_out_a_bits_param),
+ .auto_out_a_bits_size(widget_auto_out_a_bits_size),
+ .auto_out_a_bits_source(widget_auto_out_a_bits_source),
+ .auto_out_a_bits_address(widget_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(widget_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(widget_auto_out_d_ready),
+ .auto_out_d_valid(widget_auto_out_d_valid),
+ .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(widget_auto_out_d_bits_param),
+ .auto_out_d_bits_size(widget_auto_out_d_bits_size),
+ .auto_out_d_bits_source(widget_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(widget_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
+ );
+ assign auto_widget_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_widget_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign auto_bus_xing_out_a_valid = widget_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_bus_xing_out_d_ready = widget_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign widget_auto_in_a_valid = auto_widget_in_a_valid; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_opcode = auto_widget_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_param = auto_widget_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_size = auto_widget_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_source = auto_widget_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_address = auto_widget_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_mask = auto_widget_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_data = auto_widget_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_corrupt = auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign widget_auto_in_d_ready = auto_widget_in_d_ready; // @[LazyModule.scala 309:16]
+ assign widget_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_32(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [27:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [27:0] _GEN_71 = {{22'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [27:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [27:0] _T_56 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 137:31]
+ wire [28:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [28:0] _T_59 = $signed(_T_57) & -29'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 29'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [27:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_691 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_700 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_726 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_734 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_744 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_769 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_691 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_691) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_700 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_700) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_734[0] & (_T_726 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_726 & _T_2 & ~_T_734[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_744 & (_T_726 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_726 & _T_2 & ~_T_744) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:63)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_769 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_769) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Plic.scala:363:63)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[27:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_10(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [27:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [27:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [27:0] saved_address; // @[Repeater.scala 20:18]
+ reg [7:0] saved_mask; // @[Repeater.scala 20:18]
+ reg saved_corrupt; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[27:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ saved_corrupt = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_8(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [27:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [27:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [27:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [27:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [27:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [27:0] _GEN_11 = {{22'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_32 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_10 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_16(
+ input clock,
+ input reset,
+ input auto_fragmenter_out_a_ready,
+ output auto_fragmenter_out_a_valid,
+ output [2:0] auto_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_fragmenter_out_a_bits_param,
+ output [1:0] auto_fragmenter_out_a_bits_size,
+ output [6:0] auto_fragmenter_out_a_bits_source,
+ output [27:0] auto_fragmenter_out_a_bits_address,
+ output [7:0] auto_fragmenter_out_a_bits_mask,
+ output [63:0] auto_fragmenter_out_a_bits_data,
+ output auto_fragmenter_out_a_bits_corrupt,
+ output auto_fragmenter_out_d_ready,
+ input auto_fragmenter_out_d_valid,
+ input [2:0] auto_fragmenter_out_d_bits_opcode,
+ input [1:0] auto_fragmenter_out_d_bits_size,
+ input [6:0] auto_fragmenter_out_d_bits_source,
+ input [63:0] auto_fragmenter_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [27:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [27:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [27:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_8 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+endmodule
+module TLMonitor_33(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [25:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [25:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [25:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [25:0] _T_56 = io_in_a_bits_address ^ 26'h2000000; // @[Parameters.scala 137:31]
+ wire [26:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [26:0] _T_59 = $signed(_T_57) & -27'sh10000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 27'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [25:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_719 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_757 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_693) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727[0] & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_727[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_737 & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_737) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:65)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CLINT.scala:111:65)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[25:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_11(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [25:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [25:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [25:0] saved_address; // @[Repeater.scala 20:18]
+ reg [7:0] saved_mask; // @[Repeater.scala 20:18]
+ reg saved_corrupt; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[25:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ saved_corrupt = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_9(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [25:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [25:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [25:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [25:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [25:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [25:0] _GEN_11 = {{20'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_33 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_11 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_17(
+ input clock,
+ input reset,
+ input auto_fragmenter_out_a_ready,
+ output auto_fragmenter_out_a_valid,
+ output [2:0] auto_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_fragmenter_out_a_bits_param,
+ output [1:0] auto_fragmenter_out_a_bits_size,
+ output [6:0] auto_fragmenter_out_a_bits_source,
+ output [25:0] auto_fragmenter_out_a_bits_address,
+ output [7:0] auto_fragmenter_out_a_bits_mask,
+ output [63:0] auto_fragmenter_out_a_bits_data,
+ output auto_fragmenter_out_a_bits_corrupt,
+ output auto_fragmenter_out_d_ready,
+ input auto_fragmenter_out_d_valid,
+ input [2:0] auto_fragmenter_out_d_bits_opcode,
+ input [1:0] auto_fragmenter_out_d_bits_size,
+ input [6:0] auto_fragmenter_out_d_bits_source,
+ input [63:0] auto_fragmenter_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [25:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [25:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [25:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_9 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+endmodule
+module TLMonitor_34(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [11:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [11:0] _GEN_71 = {{6'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [11:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [12:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [12:0] _T_59 = $signed(_T_7) & 13'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 13'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [11:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_719 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_757 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_693 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_693) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727[0] & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_727[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_737 & (_T_719 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_719 & _T_2 & ~_T_737) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:64)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Periphery.scala:88:64)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[11:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[4:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[19:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[2:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_1 = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[19:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[2:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_12(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [11:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [11:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [11:0] saved_address; // @[Repeater.scala 20:18]
+ reg [7:0] saved_mask; // @[Repeater.scala 20:18]
+ reg saved_corrupt; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[11:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ saved_corrupt = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_10(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [11:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [11:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [11:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [11:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [11:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [11:0] _GEN_11 = {{6'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_34 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_12 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_18(
+ input clock,
+ input reset,
+ input auto_fragmenter_out_a_ready,
+ output auto_fragmenter_out_a_valid,
+ output [2:0] auto_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_fragmenter_out_a_bits_param,
+ output [1:0] auto_fragmenter_out_a_bits_size,
+ output [6:0] auto_fragmenter_out_a_bits_source,
+ output [11:0] auto_fragmenter_out_a_bits_address,
+ output [7:0] auto_fragmenter_out_a_bits_mask,
+ output [63:0] auto_fragmenter_out_a_bits_data,
+ output auto_fragmenter_out_a_bits_corrupt,
+ output auto_fragmenter_out_d_ready,
+ input auto_fragmenter_out_d_valid,
+ input [2:0] auto_fragmenter_out_d_bits_opcode,
+ input [1:0] auto_fragmenter_out_d_bits_size,
+ input [6:0] auto_fragmenter_out_d_bits_source,
+ input [63:0] auto_fragmenter_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [11:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [11:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [11:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_10 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+endmodule
+module TLWidthWidget_8(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLInterconnectCoupler_19(
+ input auto_tl_slave_clock_xing_out_a_ready,
+ output auto_tl_slave_clock_xing_out_a_valid,
+ output [2:0] auto_tl_slave_clock_xing_out_a_bits_opcode,
+ output [2:0] auto_tl_slave_clock_xing_out_a_bits_param,
+ output [2:0] auto_tl_slave_clock_xing_out_a_bits_size,
+ output [2:0] auto_tl_slave_clock_xing_out_a_bits_source,
+ output [31:0] auto_tl_slave_clock_xing_out_a_bits_address,
+ output [7:0] auto_tl_slave_clock_xing_out_a_bits_mask,
+ output [63:0] auto_tl_slave_clock_xing_out_a_bits_data,
+ output auto_tl_slave_clock_xing_out_d_ready,
+ input auto_tl_slave_clock_xing_out_d_valid,
+ input [2:0] auto_tl_slave_clock_xing_out_d_bits_opcode,
+ input [1:0] auto_tl_slave_clock_xing_out_d_bits_param,
+ input [2:0] auto_tl_slave_clock_xing_out_d_bits_size,
+ input [2:0] auto_tl_slave_clock_xing_out_d_bits_source,
+ input auto_tl_slave_clock_xing_out_d_bits_sink,
+ input auto_tl_slave_clock_xing_out_d_bits_denied,
+ input [63:0] auto_tl_slave_clock_xing_out_d_bits_data,
+ input auto_tl_slave_clock_xing_out_d_bits_corrupt,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [31:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [1:0] auto_tl_in_d_bits_param,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output auto_tl_in_d_bits_sink,
+ output auto_tl_in_d_bits_denied,
+ output [63:0] auto_tl_in_d_bits_data,
+ output auto_tl_in_d_bits_corrupt
+);
+ wire widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
+ wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
+ wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
+ wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
+ wire [2:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 219:28]
+ wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
+ wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 219:28]
+ TLWidthWidget_8 widget ( // @[WidthWidget.scala 219:28]
+ .auto_in_a_ready(widget_auto_in_a_ready),
+ .auto_in_a_valid(widget_auto_in_a_valid),
+ .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(widget_auto_in_a_bits_param),
+ .auto_in_a_bits_size(widget_auto_in_a_bits_size),
+ .auto_in_a_bits_source(widget_auto_in_a_bits_source),
+ .auto_in_a_bits_address(widget_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(widget_auto_in_a_bits_data),
+ .auto_in_d_ready(widget_auto_in_d_ready),
+ .auto_in_d_valid(widget_auto_in_d_valid),
+ .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(widget_auto_in_d_bits_param),
+ .auto_in_d_bits_size(widget_auto_in_d_bits_size),
+ .auto_in_d_bits_source(widget_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(widget_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(widget_auto_out_a_ready),
+ .auto_out_a_valid(widget_auto_out_a_valid),
+ .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(widget_auto_out_a_bits_param),
+ .auto_out_a_bits_size(widget_auto_out_a_bits_size),
+ .auto_out_a_bits_source(widget_auto_out_a_bits_source),
+ .auto_out_a_bits_address(widget_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(widget_auto_out_a_bits_data),
+ .auto_out_d_ready(widget_auto_out_d_ready),
+ .auto_out_d_valid(widget_auto_out_d_valid),
+ .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(widget_auto_out_d_bits_param),
+ .auto_out_d_bits_size(widget_auto_out_d_bits_size),
+ .auto_out_d_bits_source(widget_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(widget_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
+ );
+ assign auto_tl_slave_clock_xing_out_a_valid = widget_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_out_d_ready = widget_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_in_a_ready = widget_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = widget_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_param = widget_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = widget_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = widget_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = widget_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign widget_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign widget_auto_out_a_ready = auto_tl_slave_clock_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_valid = auto_tl_slave_clock_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_opcode = auto_tl_slave_clock_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_param = auto_tl_slave_clock_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_size = auto_tl_slave_clock_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_source = auto_tl_slave_clock_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_sink = auto_tl_slave_clock_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_denied = auto_tl_slave_clock_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_data = auto_tl_slave_clock_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign widget_auto_out_d_bits_corrupt = auto_tl_slave_clock_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module TLMonitor_35(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [16:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [16:0] _GEN_71 = {{11'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [16:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [16:0] _T_56 = io_in_a_bits_address ^ 17'h10000; // @[Parameters.scala 137:31]
+ wire [17:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [17:0] _T_59 = $signed(_T_57) & -18'sh10000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 18'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_259 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_294 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_295 = io_in_a_bits_mask & _T_294; // @[Monitor.scala 127:31]
+ wire _T_296 = _T_295 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_300 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_331 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_339 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_370 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_378 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_409 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [16:0] address; // @[Monitor.scala 388:22]
+ wire _T_567 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_568 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_572 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_576 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_580 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_584 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_591 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_600 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_604 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_618 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_621 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_623 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_625 = ~_T_623[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_629 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_618 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_642 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_644 = _T_642[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_649 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_650 = 3'h1 == _GEN_32 | _T_649; // @[Monitor.scala 685:77]
+ wire _T_654 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_661 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_662 = 3'h1 == _GEN_48 | _T_661; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_666 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_674 = _T_629 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_678 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_687 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 3'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 3'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_296 & (io_in_a_valid & _T_259 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_259 & ~reset & ~_T_296) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_331 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_331) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_370 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_370) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_339 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_339 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_378 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_378 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & ~reset & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_600 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_600) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BootROM.scala:84:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_604 & (_T_591 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & _T_2 & ~_T_604) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BootROM.scala:84:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_625 & (_T_621 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_621 & ~reset & ~_T_625) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_644 & (_T_629 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & _T_2 & ~_T_644) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BootROM.scala:84:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BootROM.scala:84:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_629 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & same_cycle_resp & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BootROM.scala:84:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BootROM.scala:84:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_629 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_629 & ~same_cycle_resp & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BootROM.scala:84:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_674 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_674 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_687 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_687) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BootROM.scala:84:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[16:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight = _RAND_9[4:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_10[19:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes = _RAND_11[19:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[2:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[2:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_13(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [16:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [16:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [16:0] saved_address; // @[Repeater.scala 20:18]
+ reg [7:0] saved_mask; // @[Repeater.scala 20:18]
+ reg saved_corrupt; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[16:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ saved_corrupt = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_11(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [16:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [16:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [16:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [16:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [16:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire _T_7 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _acknum_T_1 = acknum - 3'h1; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_9 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_9; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [16:0] _GEN_10 = {{11'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_35 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ Repeater_13 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_10; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = new_gennum != 3'h0; // @[Fragmenter.scala 302:53]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_20(
+ input clock,
+ input reset,
+ input auto_fragmenter_out_a_ready,
+ output auto_fragmenter_out_a_valid,
+ output [2:0] auto_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_fragmenter_out_a_bits_param,
+ output [1:0] auto_fragmenter_out_a_bits_size,
+ output [6:0] auto_fragmenter_out_a_bits_source,
+ output [16:0] auto_fragmenter_out_a_bits_address,
+ output [7:0] auto_fragmenter_out_a_bits_mask,
+ output auto_fragmenter_out_a_bits_corrupt,
+ output auto_fragmenter_out_d_ready,
+ input auto_fragmenter_out_d_valid,
+ input [1:0] auto_fragmenter_out_d_bits_size,
+ input [6:0] auto_fragmenter_out_d_bits_source,
+ input [63:0] auto_fragmenter_out_d_bits_data,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [2:0] auto_tl_in_a_bits_size,
+ input [2:0] auto_tl_in_a_bits_source,
+ input [16:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_size,
+ output [2:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [16:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [16:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ TLFragmenter_11 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
+ );
+ assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+endmodule
+module TLInterconnectCoupler_21(
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [31:0] auto_tl_in_a_bits_address,
+ input [63:0] auto_tl_in_a_bits_data,
+ output auto_tl_in_d_valid,
+ input auto_tl_out_a_ready,
+ output auto_tl_out_a_valid,
+ output [31:0] auto_tl_out_a_bits_address,
+ output [63:0] auto_tl_out_a_bits_data,
+ input auto_tl_out_d_valid
+);
+ assign auto_tl_in_a_ready = auto_tl_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_in_d_valid = auto_tl_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_tl_out_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_out_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_36(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [20:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [95:0] _RAND_13;
+ reg [319:0] _RAND_14;
+ reg [319:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [95:0] _RAND_19;
+ reg [319:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [20:0] _GEN_71 = {{18'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [20:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [20:0] _T_33 = io_in_a_bits_address ^ 21'h100000; // @[Parameters.scala 137:31]
+ wire [21:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [21:0] _T_36 = $signed(_T_34) & -22'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 22'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_409 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_413 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_417 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_432 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_436 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_469 = _T_417 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [20:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_572 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_584 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_588 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [127:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [127:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 671:90 672:22]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set_wo_ready = _GEN_15[79:0];
+ wire [79:0] d_clr_wo_ready = _GEN_21[79:0];
+ wire _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_714 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_413 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_432 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_432) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_436 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_436) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_413 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_432 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_432) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_436 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_436) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_469 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_469) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_413 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_T_413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_469 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_469) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_413 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_T_413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_588 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_588) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_661 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_661) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_670 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_670) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_704[0] & (_T_696 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_696 & _T_2 & ~_T_704[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_714 & (_T_696 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_696 & _T_2 & ~_T_714) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[20:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[1:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[6:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {3{`RANDOM}};
+ inflight = _RAND_13[79:0];
+ _RAND_14 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_14[319:0];
+ _RAND_15 = {10{`RANDOM}};
+ inflight_sizes = _RAND_15[319:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[0:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[0:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {3{`RANDOM}};
+ inflight_1 = _RAND_19[79:0];
+ _RAND_20 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[319:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[0:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_15(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [1:0] io_enq_bits_size,
+ input [6:0] io_enq_bits_source,
+ input [20:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [1:0] io_deq_bits_size,
+ output [6:0] io_deq_bits_source,
+ output [20:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [1:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [6:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [6:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [6:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [20:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [20:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [20:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_address_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_address_io_deq_bits_MPORT_addr = value_1;
+ assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_address_MPORT_data = io_enq_bits_address;
+ assign ram_address_MPORT_addr = value;
+ assign ram_address_MPORT_mask = 1'h1;
+ assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = value_1;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = value;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
+ ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[1:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[6:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_address[initvar] = _RAND_4[20:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_5[7:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_16(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [1:0] io_enq_bits_size,
+ input [6:0] io_enq_bits_source,
+ input [63:0] io_enq_bits_data,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [1:0] io_deq_bits_param,
+ output [1:0] io_deq_bits_size,
+ output [6:0] io_deq_bits_source,
+ output io_deq_bits_sink,
+ output io_deq_bits_denied,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [1:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [1:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [6:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [6:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [6:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_sink [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_sink_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_denied [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_denied_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = 2'h0;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_sink_io_deq_bits_MPORT_addr = value_1;
+ assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_sink_MPORT_data = 1'h0;
+ assign ram_sink_MPORT_addr = value;
+ assign ram_sink_MPORT_mask = 1'h1;
+ assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_denied_io_deq_bits_MPORT_addr = value_1;
+ assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_denied_MPORT_data = 1'h0;
+ assign ram_denied_MPORT_addr = value;
+ assign ram_denied_MPORT_mask = 1'h1;
+ assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = 1'h0;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
+ ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
+ ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[1:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[6:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_sink[initvar] = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_denied[initvar] = _RAND_5[0:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_11(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [1:0] auto_in_a_bits_size,
+ input [6:0] auto_in_a_bits_source,
+ input [20:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [1:0] auto_in_d_bits_size,
+ output [6:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [20:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [20:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [6:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [20:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [6:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [20:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [6:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [6:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_36 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_15 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_16 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_37(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [20:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [20:0] _GEN_71 = {{15'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [20:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [20:0] _T_56 = io_in_a_bits_address ^ 21'h100000; // @[Parameters.scala 137:31]
+ wire [21:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [21:0] _T_59 = $signed(_T_57) & -22'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 22'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_439 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_443 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_447 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_462 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_466 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_499 = _T_447 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [20:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_602 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_614 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_618 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_691 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_700 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_726 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_734 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_744 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_769 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_439 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_439) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_443 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_443) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_462 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_462) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_466 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_466) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_443 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_443) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_462 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_462) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_466 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_466) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_439 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~_T_439) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_443 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~_T_443) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_439 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~_T_439) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_439 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_439) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_443 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_443) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_602 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_602) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_614 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_614) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_691 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_691) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_700 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_700) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_734[0] & (_T_726 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_726 & _T_2 & ~_T_734[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_744 & (_T_726 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_726 & _T_2 & ~_T_744) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_769 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_769) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[20:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_14(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [20:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [20:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [20:0] saved_address; // @[Repeater.scala 20:18]
+ reg [7:0] saved_mask; // @[Repeater.scala 20:18]
+ reg saved_corrupt; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[20:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ saved_corrupt = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_12(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [20:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [20:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [20:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [20:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [20:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [20:0] _GEN_11 = {{15'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_37 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Repeater_14 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_12(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [20:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [20:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLInterconnectCoupler_22(
+ input clock,
+ input reset,
+ output auto_buffer_in_a_ready,
+ input auto_buffer_in_a_valid,
+ input [2:0] auto_buffer_in_a_bits_opcode,
+ input [2:0] auto_buffer_in_a_bits_param,
+ input [2:0] auto_buffer_in_a_bits_size,
+ input [2:0] auto_buffer_in_a_bits_source,
+ input [20:0] auto_buffer_in_a_bits_address,
+ input [7:0] auto_buffer_in_a_bits_mask,
+ input [63:0] auto_buffer_in_a_bits_data,
+ input auto_buffer_in_a_bits_corrupt,
+ input auto_buffer_in_d_ready,
+ output auto_buffer_in_d_valid,
+ output [2:0] auto_buffer_in_d_bits_opcode,
+ output [1:0] auto_buffer_in_d_bits_param,
+ output [2:0] auto_buffer_in_d_bits_size,
+ output [2:0] auto_buffer_in_d_bits_source,
+ output auto_buffer_in_d_bits_sink,
+ output auto_buffer_in_d_bits_denied,
+ output [63:0] auto_buffer_in_d_bits_data,
+ output auto_buffer_in_d_bits_corrupt,
+ input auto_buffer_out_a_ready,
+ output auto_buffer_out_a_valid,
+ output [2:0] auto_buffer_out_a_bits_opcode,
+ output [2:0] auto_buffer_out_a_bits_param,
+ output [1:0] auto_buffer_out_a_bits_size,
+ output [6:0] auto_buffer_out_a_bits_source,
+ output [20:0] auto_buffer_out_a_bits_address,
+ output [7:0] auto_buffer_out_a_bits_mask,
+ output [63:0] auto_buffer_out_a_bits_data,
+ output auto_buffer_out_a_bits_corrupt,
+ output auto_buffer_out_d_ready,
+ input auto_buffer_out_d_valid,
+ input [2:0] auto_buffer_out_d_bits_opcode,
+ input [1:0] auto_buffer_out_d_bits_size,
+ input [6:0] auto_buffer_out_d_bits_source,
+ input [63:0] auto_buffer_out_d_bits_data
+);
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [20:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [20:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [20:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_in_d_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_bits_sink; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_bits_denied; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [20:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_bits_sink; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_bits_denied; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [20:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [20:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ TLBuffer_11 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ TLFragmenter_12 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(fragmenter_auto_in_d_bits_param),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(fragmenter_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(fragmenter_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(fragmenter_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(fragmenter_auto_out_d_bits_param),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(fragmenter_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(fragmenter_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(fragmenter_auto_out_d_bits_corrupt)
+ );
+ TLBuffer_12 buffer_1 ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_1_auto_in_a_ready),
+ .auto_in_a_valid(buffer_1_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_1_auto_in_d_ready),
+ .auto_in_d_valid(buffer_1_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_1_auto_out_a_ready),
+ .auto_out_a_valid(buffer_1_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_1_auto_out_d_ready),
+ .auto_out_d_valid(buffer_1_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt)
+ );
+ assign auto_buffer_in_a_ready = buffer_1_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_valid = buffer_1_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign auto_buffer_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 311:12]
+ assign buffer_clock = clock;
+ assign buffer_reset = reset;
+ assign buffer_auto_in_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_a_ready = auto_buffer_out_a_ready; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_valid = auto_buffer_out_d_valid; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_data = auto_buffer_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_param = fragmenter_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_sink = fragmenter_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_denied = fragmenter_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_corrupt = fragmenter_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+endmodule
+module TLMonitor_38(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [20:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [95:0] _RAND_13;
+ reg [319:0] _RAND_14;
+ reg [319:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [95:0] _RAND_19;
+ reg [319:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [20:0] _GEN_71 = {{18'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [20:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [20:0] _T_33 = io_in_a_bits_address ^ 21'h110000; // @[Parameters.scala 137:31]
+ wire [21:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [21:0] _T_36 = $signed(_T_34) & -22'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 22'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_409 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_413 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_417 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_432 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_436 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_469 = _T_417 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [20:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_572 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_584 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_588 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [127:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [127:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 671:90 672:22]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set_wo_ready = _GEN_15[79:0];
+ wire [79:0] d_clr_wo_ready = _GEN_21[79:0];
+ wire _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_714 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_413 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_432 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_432) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_436 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_436) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_413 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_432 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_432) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_436 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_436) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_469 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_469) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_413 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_T_413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_469 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_469) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_409 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_T_409) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_413 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_T_413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_417 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_T_417) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_588 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_588) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_661 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_661) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_670 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_670) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_704[0] & (_T_696 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_696 & _T_2 & ~_T_704[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_714 & (_T_696 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_696 & _T_2 & ~_T_714) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:11)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:11)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[20:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[1:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[6:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {3{`RANDOM}};
+ inflight = _RAND_13[79:0];
+ _RAND_14 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_14[319:0];
+ _RAND_15 = {10{`RANDOM}};
+ inflight_sizes = _RAND_15[319:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[0:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[0:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {3{`RANDOM}};
+ inflight_1 = _RAND_19[79:0];
+ _RAND_20 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[319:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[0:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_13(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [1:0] auto_in_a_bits_size,
+ input [6:0] auto_in_a_bits_source,
+ input [20:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [1:0] auto_in_d_bits_size,
+ output [6:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [20:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [20:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [6:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [20:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [6:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [20:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [6:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [6:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_38 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_15 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_16 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_39(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [20:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [20:0] _GEN_71 = {{15'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [20:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [20:0] _T_56 = io_in_a_bits_address ^ 21'h110000; // @[Parameters.scala 137:31]
+ wire [21:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [21:0] _T_59 = $signed(_T_57) & -22'sh1000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 22'sh0; // @[Parameters.scala 137:67]
+ wire _T_92 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_96 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_97 = _T_96 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_101 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_105 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_159 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_172 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_189 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_197 = _T_189 & _T_60; // @[Parameters.scala 670:56]
+ wire _T_208 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_212 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_220 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_244 = source_ok & _T_197; // @[Monitor.scala 115:71]
+ wire _T_262 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_300 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_301 = io_in_a_bits_mask & _T_300; // @[Monitor.scala 127:31]
+ wire _T_302 = _T_301 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_306 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_376 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_384 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_415 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_427 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_431 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_435 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_439 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_443 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_447 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_451 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_462 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_466 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_479 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_499 = _T_447 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_508 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_525 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_543 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [20:0] address; // @[Monitor.scala 388:22]
+ wire _T_573 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_574 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_578 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_582 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_586 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_590 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_597 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_598 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_602 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_606 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_610 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_614 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_618 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_624 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_627 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_629 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_631 = ~_T_629[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_635 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_637 = ~_T_431; // @[Monitor.scala 671:74]
+ wire _T_638 = io_in_d_valid & d_first_1 & ~_T_431; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_637 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_637 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_624 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_648 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_650 = _T_648[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_655 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_656 = io_in_d_bits_opcode == _GEN_32 | _T_655; // @[Monitor.scala 685:77]
+ wire _T_660 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_667 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_668 = io_in_d_bits_opcode == _GEN_48 | _T_667; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_672 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_682 = _T_635 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_637; // @[Monitor.scala 694:116]
+ wire _T_684 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_691 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_700 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_726 = io_in_d_valid & d_first_2 & _T_431; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_431 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_431 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_734 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_744 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_769 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_92 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_92) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_159 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_159) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_97 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_97) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_105 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_105 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_197 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_172 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_172 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_220 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_220 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_244 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_244) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_208 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_208) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_302 & (io_in_a_valid & _T_262 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_262 & ~reset & ~_T_302) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_337 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_337) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_306 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_306 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_376 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_376) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_345 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_345 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_415 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_415) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_212 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_212) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_101 & (io_in_a_valid & _T_384 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_384 & ~reset & ~_T_101) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_427 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_427) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_439 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_439) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_443 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_443) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_431 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_431 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_462 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_462) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_466 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_466) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_443 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_443) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_451 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_451 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_435 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_435) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_462 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_462) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_466 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_466) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_479 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_479 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_439 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~_T_439) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_443 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~_T_443) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_508 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_508 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_439 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~_T_439) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_525 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_525 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_439 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_439) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_443 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_443) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_447 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_447) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_578 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_578) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_582 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_582) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_586 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_586) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_590 & (_T_573 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_573 & ~reset & ~_T_590) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_598 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_598) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_602 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_602) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_606 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_606) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_610 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_610) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_614 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_614) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_627 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_627 & ~reset & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_638 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_660 & (_T_638 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & same_cycle_resp & _T_2 & ~_T_660) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_668 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_668) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_672 & (_T_638 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_638 & ~same_cycle_resp & _T_2 & ~_T_672) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_684 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_684) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_691 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_691) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_700 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_700) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_734[0] & (_T_726 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_726 & _T_2 & ~_T_734[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_744 & (_T_726 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_726 & _T_2 & ~_T_744) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusWrapper.scala:264:51)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_769 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_769) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:264:51)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[20:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_13(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [20:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [20:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [20:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [20:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [20:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [20:0] _GEN_11 = {{15'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ TLMonitor_39 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Repeater_14 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask),
+ .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:4]; // @[Fragmenter.scala 226:47]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLInterconnectCoupler_23(
+ input clock,
+ input reset,
+ output auto_buffer_in_a_ready,
+ input auto_buffer_in_a_valid,
+ input [2:0] auto_buffer_in_a_bits_opcode,
+ input [2:0] auto_buffer_in_a_bits_param,
+ input [2:0] auto_buffer_in_a_bits_size,
+ input [2:0] auto_buffer_in_a_bits_source,
+ input [20:0] auto_buffer_in_a_bits_address,
+ input [7:0] auto_buffer_in_a_bits_mask,
+ input [63:0] auto_buffer_in_a_bits_data,
+ input auto_buffer_in_a_bits_corrupt,
+ input auto_buffer_in_d_ready,
+ output auto_buffer_in_d_valid,
+ output [2:0] auto_buffer_in_d_bits_opcode,
+ output [1:0] auto_buffer_in_d_bits_param,
+ output [2:0] auto_buffer_in_d_bits_size,
+ output [2:0] auto_buffer_in_d_bits_source,
+ output auto_buffer_in_d_bits_sink,
+ output auto_buffer_in_d_bits_denied,
+ output [63:0] auto_buffer_in_d_bits_data,
+ output auto_buffer_in_d_bits_corrupt,
+ input auto_buffer_out_a_ready,
+ output auto_buffer_out_a_valid,
+ output [2:0] auto_buffer_out_a_bits_opcode,
+ output [2:0] auto_buffer_out_a_bits_param,
+ output [1:0] auto_buffer_out_a_bits_size,
+ output [6:0] auto_buffer_out_a_bits_source,
+ output [20:0] auto_buffer_out_a_bits_address,
+ output [7:0] auto_buffer_out_a_bits_mask,
+ output [63:0] auto_buffer_out_a_bits_data,
+ output auto_buffer_out_a_bits_corrupt,
+ output auto_buffer_out_d_ready,
+ input auto_buffer_out_d_valid,
+ input [2:0] auto_buffer_out_d_bits_opcode,
+ input [1:0] auto_buffer_out_d_bits_size,
+ input [6:0] auto_buffer_out_d_bits_source,
+ input [63:0] auto_buffer_out_d_bits_data
+);
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [20:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [20:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire fragmenter_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [20:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_in_d_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_bits_sink; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_bits_denied; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_in_d_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [20:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_bits_sink; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_bits_denied; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_auto_out_d_bits_corrupt; // @[Fragmenter.scala 333:34]
+ wire buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [20:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [20:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ TLFragmenter_13 fragmenter ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_clock),
+ .reset(fragmenter_reset),
+ .auto_in_a_ready(fragmenter_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fragmenter_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(fragmenter_auto_in_d_bits_param),
+ .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(fragmenter_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(fragmenter_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(fragmenter_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(fragmenter_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fragmenter_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(fragmenter_auto_out_d_bits_param),
+ .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(fragmenter_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(fragmenter_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(fragmenter_auto_out_d_bits_corrupt)
+ );
+ TLBuffer_12 buffer_1 ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_1_auto_in_a_ready),
+ .auto_in_a_valid(buffer_1_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_1_auto_in_d_ready),
+ .auto_in_d_valid(buffer_1_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_1_auto_out_a_ready),
+ .auto_out_a_valid(buffer_1_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_1_auto_out_d_ready),
+ .auto_out_d_valid(buffer_1_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt)
+ );
+ assign auto_buffer_in_a_ready = buffer_1_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_valid = buffer_1_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_buffer_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign auto_buffer_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_buffer_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 311:12]
+ assign buffer_clock = clock;
+ assign buffer_reset = reset;
+ assign buffer_auto_in_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_a_ready = auto_buffer_out_a_ready; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_valid = auto_buffer_out_d_valid; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign fragmenter_clock = clock;
+ assign fragmenter_reset = reset;
+ assign fragmenter_auto_in_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_in_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign fragmenter_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_data = auto_buffer_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 309:16]
+ assign buffer_1_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_param = fragmenter_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_sink = fragmenter_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_denied = fragmenter_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_corrupt = fragmenter_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+endmodule
+module PeripheryBus_1(
+ input auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_ready,
+ output auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_valid,
+ output [2:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_param,
+ output [1:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_size,
+ output [6:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_source,
+ output [20:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_address,
+ output [7:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_mask,
+ output [63:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_data,
+ output auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_corrupt,
+ output auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_ready,
+ input auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_valid,
+ input [2:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_size,
+ input [6:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_source,
+ input [63:0] auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_data,
+ input auto_coupler_to_slave_named_clockgater_buffer_out_a_ready,
+ output auto_coupler_to_slave_named_clockgater_buffer_out_a_valid,
+ output [2:0] auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_param,
+ output [1:0] auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_size,
+ output [6:0] auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_source,
+ output [20:0] auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_address,
+ output [7:0] auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_mask,
+ output [63:0] auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_data,
+ output auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_corrupt,
+ output auto_coupler_to_slave_named_clockgater_buffer_out_d_ready,
+ input auto_coupler_to_slave_named_clockgater_buffer_out_d_valid,
+ input [2:0] auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_size,
+ input [6:0] auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_source,
+ input [63:0] auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_data,
+ input auto_coupler_to_bootrom_fragmenter_out_a_ready,
+ output auto_coupler_to_bootrom_fragmenter_out_a_valid,
+ output [2:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_param,
+ output [1:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_size,
+ output [6:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_source,
+ output [16:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_address,
+ output [7:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_mask,
+ output auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt,
+ output auto_coupler_to_bootrom_fragmenter_out_d_ready,
+ input auto_coupler_to_bootrom_fragmenter_out_d_valid,
+ input [1:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_size,
+ input [6:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_source,
+ input [63:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_data,
+ input auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready,
+ output auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid,
+ output [2:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param,
+ output [2:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size,
+ output [2:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source,
+ output [31:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address,
+ output [7:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data,
+ output auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready,
+ input auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid,
+ input [2:0] auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param,
+ input [2:0] auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size,
+ input [2:0] auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source,
+ input auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink,
+ input auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied,
+ input [63:0] auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data,
+ input auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt,
+ input auto_coupler_to_debug_fragmenter_out_a_ready,
+ output auto_coupler_to_debug_fragmenter_out_a_valid,
+ output [2:0] auto_coupler_to_debug_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_debug_fragmenter_out_a_bits_param,
+ output [1:0] auto_coupler_to_debug_fragmenter_out_a_bits_size,
+ output [6:0] auto_coupler_to_debug_fragmenter_out_a_bits_source,
+ output [11:0] auto_coupler_to_debug_fragmenter_out_a_bits_address,
+ output [7:0] auto_coupler_to_debug_fragmenter_out_a_bits_mask,
+ output [63:0] auto_coupler_to_debug_fragmenter_out_a_bits_data,
+ output auto_coupler_to_debug_fragmenter_out_a_bits_corrupt,
+ output auto_coupler_to_debug_fragmenter_out_d_ready,
+ input auto_coupler_to_debug_fragmenter_out_d_valid,
+ input [2:0] auto_coupler_to_debug_fragmenter_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_debug_fragmenter_out_d_bits_size,
+ input [6:0] auto_coupler_to_debug_fragmenter_out_d_bits_source,
+ input [63:0] auto_coupler_to_debug_fragmenter_out_d_bits_data,
+ input auto_coupler_to_clint_fragmenter_out_a_ready,
+ output auto_coupler_to_clint_fragmenter_out_a_valid,
+ output [2:0] auto_coupler_to_clint_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_clint_fragmenter_out_a_bits_param,
+ output [1:0] auto_coupler_to_clint_fragmenter_out_a_bits_size,
+ output [6:0] auto_coupler_to_clint_fragmenter_out_a_bits_source,
+ output [25:0] auto_coupler_to_clint_fragmenter_out_a_bits_address,
+ output [7:0] auto_coupler_to_clint_fragmenter_out_a_bits_mask,
+ output [63:0] auto_coupler_to_clint_fragmenter_out_a_bits_data,
+ output auto_coupler_to_clint_fragmenter_out_a_bits_corrupt,
+ output auto_coupler_to_clint_fragmenter_out_d_ready,
+ input auto_coupler_to_clint_fragmenter_out_d_valid,
+ input [2:0] auto_coupler_to_clint_fragmenter_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_clint_fragmenter_out_d_bits_size,
+ input [6:0] auto_coupler_to_clint_fragmenter_out_d_bits_source,
+ input [63:0] auto_coupler_to_clint_fragmenter_out_d_bits_data,
+ input auto_coupler_to_plic_fragmenter_out_a_ready,
+ output auto_coupler_to_plic_fragmenter_out_a_valid,
+ output [2:0] auto_coupler_to_plic_fragmenter_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_plic_fragmenter_out_a_bits_param,
+ output [1:0] auto_coupler_to_plic_fragmenter_out_a_bits_size,
+ output [6:0] auto_coupler_to_plic_fragmenter_out_a_bits_source,
+ output [27:0] auto_coupler_to_plic_fragmenter_out_a_bits_address,
+ output [7:0] auto_coupler_to_plic_fragmenter_out_a_bits_mask,
+ output [63:0] auto_coupler_to_plic_fragmenter_out_a_bits_data,
+ output auto_coupler_to_plic_fragmenter_out_a_bits_corrupt,
+ output auto_coupler_to_plic_fragmenter_out_d_ready,
+ input auto_coupler_to_plic_fragmenter_out_d_valid,
+ input [2:0] auto_coupler_to_plic_fragmenter_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_plic_fragmenter_out_d_bits_size,
+ input [6:0] auto_coupler_to_plic_fragmenter_out_d_bits_source,
+ input [63:0] auto_coupler_to_plic_fragmenter_out_d_bits_data,
+ input auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready,
+ output auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid,
+ output [2:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode,
+ output [2:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param,
+ output [2:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size,
+ output [2:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source,
+ output [29:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address,
+ output [7:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask,
+ output [63:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data,
+ output auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt,
+ output auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready,
+ input auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid,
+ input [2:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode,
+ input [1:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param,
+ input [2:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size,
+ input [2:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source,
+ input auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink,
+ input auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied,
+ input [63:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data,
+ input auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt,
+ output auto_fixedClockNode_out_4_clock,
+ output auto_fixedClockNode_out_4_reset,
+ output auto_fixedClockNode_out_3_clock,
+ output auto_fixedClockNode_out_3_reset,
+ output auto_fixedClockNode_out_2_clock,
+ output auto_fixedClockNode_out_2_reset,
+ output auto_fixedClockNode_out_0_clock,
+ output auto_fixedClockNode_out_0_reset,
+ input auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock,
+ input auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset,
+ output auto_bus_xing_in_a_ready,
+ input auto_bus_xing_in_a_valid,
+ input [2:0] auto_bus_xing_in_a_bits_opcode,
+ input [2:0] auto_bus_xing_in_a_bits_param,
+ input [3:0] auto_bus_xing_in_a_bits_size,
+ input [1:0] auto_bus_xing_in_a_bits_source,
+ input [31:0] auto_bus_xing_in_a_bits_address,
+ input [7:0] auto_bus_xing_in_a_bits_mask,
+ input [63:0] auto_bus_xing_in_a_bits_data,
+ input auto_bus_xing_in_a_bits_corrupt,
+ input auto_bus_xing_in_d_ready,
+ output auto_bus_xing_in_d_valid,
+ output [2:0] auto_bus_xing_in_d_bits_opcode,
+ output [1:0] auto_bus_xing_in_d_bits_param,
+ output [3:0] auto_bus_xing_in_d_bits_size,
+ output [1:0] auto_bus_xing_in_d_bits_source,
+ output auto_bus_xing_in_d_bits_sink,
+ output auto_bus_xing_in_d_bits_denied,
+ output [63:0] auto_bus_xing_in_d_bits_data,
+ output auto_bus_xing_in_d_bits_corrupt,
+ input custom_boot,
+ output clock,
+ output reset
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ wire subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_clock; // @[BusWrapper.scala 40:48]
+ wire subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_reset; // @[BusWrapper.scala 40:48]
+ wire subsystem_cbus_clock_groups_auto_out_member_subsystem_cbus_0_clock; // @[BusWrapper.scala 40:48]
+ wire subsystem_cbus_clock_groups_auto_out_member_subsystem_cbus_0_reset; // @[BusWrapper.scala 40:48]
+ wire clockGroup_auto_in_member_subsystem_cbus_0_clock; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_in_member_subsystem_cbus_0_reset; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
+ wire clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
+ wire fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_5_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_5_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_4_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_4_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_3_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_3_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_2_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_2_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_1_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_1_reset; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_0_clock; // @[ClockGroup.scala 106:107]
+ wire fixedClockNode_auto_out_0_reset; // @[ClockGroup.scala 106:107]
+ wire fixer_clock; // @[PeripheryBus.scala 47:33]
+ wire fixer_reset; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_a_ready; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_a_valid; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_a_bits_opcode; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_a_bits_param; // @[PeripheryBus.scala 47:33]
+ wire [3:0] fixer_auto_in_a_bits_size; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_a_bits_source; // @[PeripheryBus.scala 47:33]
+ wire [31:0] fixer_auto_in_a_bits_address; // @[PeripheryBus.scala 47:33]
+ wire [7:0] fixer_auto_in_a_bits_mask; // @[PeripheryBus.scala 47:33]
+ wire [63:0] fixer_auto_in_a_bits_data; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_ready; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_valid; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_d_bits_opcode; // @[PeripheryBus.scala 47:33]
+ wire [1:0] fixer_auto_in_d_bits_param; // @[PeripheryBus.scala 47:33]
+ wire [3:0] fixer_auto_in_d_bits_size; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_in_d_bits_source; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_bits_sink; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_bits_denied; // @[PeripheryBus.scala 47:33]
+ wire [63:0] fixer_auto_in_d_bits_data; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_a_ready; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_a_valid; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_a_bits_opcode; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_a_bits_param; // @[PeripheryBus.scala 47:33]
+ wire [3:0] fixer_auto_out_a_bits_size; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_a_bits_source; // @[PeripheryBus.scala 47:33]
+ wire [31:0] fixer_auto_out_a_bits_address; // @[PeripheryBus.scala 47:33]
+ wire [7:0] fixer_auto_out_a_bits_mask; // @[PeripheryBus.scala 47:33]
+ wire [63:0] fixer_auto_out_a_bits_data; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_ready; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_valid; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_d_bits_opcode; // @[PeripheryBus.scala 47:33]
+ wire [1:0] fixer_auto_out_d_bits_param; // @[PeripheryBus.scala 47:33]
+ wire [3:0] fixer_auto_out_d_bits_size; // @[PeripheryBus.scala 47:33]
+ wire [2:0] fixer_auto_out_d_bits_source; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_bits_sink; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_bits_denied; // @[PeripheryBus.scala 47:33]
+ wire [63:0] fixer_auto_out_d_bits_data; // @[PeripheryBus.scala 47:33]
+ wire fixer_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 47:33]
+ wire in_xbar_clock; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_reset; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_1_a_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_1_a_valid; // @[PeripheryBus.scala 49:29]
+ wire [31:0] in_xbar_auto_in_1_a_bits_address; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_in_1_a_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_1_d_valid; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_0_a_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_0_a_valid; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_0_a_bits_opcode; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_0_a_bits_param; // @[PeripheryBus.scala 49:29]
+ wire [3:0] in_xbar_auto_in_0_a_bits_size; // @[PeripheryBus.scala 49:29]
+ wire [1:0] in_xbar_auto_in_0_a_bits_source; // @[PeripheryBus.scala 49:29]
+ wire [31:0] in_xbar_auto_in_0_a_bits_address; // @[PeripheryBus.scala 49:29]
+ wire [7:0] in_xbar_auto_in_0_a_bits_mask; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_in_0_a_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_0_a_bits_corrupt; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_0_d_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_0_d_valid; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_in_0_d_bits_opcode; // @[PeripheryBus.scala 49:29]
+ wire [1:0] in_xbar_auto_in_0_d_bits_param; // @[PeripheryBus.scala 49:29]
+ wire [3:0] in_xbar_auto_in_0_d_bits_size; // @[PeripheryBus.scala 49:29]
+ wire [1:0] in_xbar_auto_in_0_d_bits_source; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_0_d_bits_sink; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_0_d_bits_denied; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_in_0_d_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_in_0_d_bits_corrupt; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_a_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_a_valid; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_a_bits_opcode; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_a_bits_param; // @[PeripheryBus.scala 49:29]
+ wire [3:0] in_xbar_auto_out_a_bits_size; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_a_bits_source; // @[PeripheryBus.scala 49:29]
+ wire [31:0] in_xbar_auto_out_a_bits_address; // @[PeripheryBus.scala 49:29]
+ wire [7:0] in_xbar_auto_out_a_bits_mask; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_out_a_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_ready; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_valid; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_d_bits_opcode; // @[PeripheryBus.scala 49:29]
+ wire [1:0] in_xbar_auto_out_d_bits_param; // @[PeripheryBus.scala 49:29]
+ wire [3:0] in_xbar_auto_out_d_bits_size; // @[PeripheryBus.scala 49:29]
+ wire [2:0] in_xbar_auto_out_d_bits_source; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_bits_sink; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_bits_denied; // @[PeripheryBus.scala 49:29]
+ wire [63:0] in_xbar_auto_out_d_bits_data; // @[PeripheryBus.scala 49:29]
+ wire in_xbar_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 49:29]
+ wire out_xbar_clock; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_reset; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [3:0] out_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [31:0] out_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [1:0] out_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [3:0] out_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [20:0] out_xbar_auto_out_8_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_8_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_8_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [1:0] out_xbar_auto_out_8_d_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_8_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_d_bits_sink; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_d_bits_denied; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_8_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_8_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [20:0] out_xbar_auto_out_7_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_7_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_7_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [1:0] out_xbar_auto_out_7_d_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_7_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_d_bits_sink; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_d_bits_denied; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_7_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_7_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [16:0] out_xbar_auto_out_6_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_6_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_6_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_6_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_6_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [31:0] out_xbar_auto_out_5_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_5_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_5_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [1:0] out_xbar_auto_out_5_d_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_5_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_d_bits_sink; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_d_bits_denied; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_5_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_5_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [11:0] out_xbar_auto_out_4_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_4_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_4_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_4_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_4_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_4_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [25:0] out_xbar_auto_out_3_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_3_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_3_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_3_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_3_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_3_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [27:0] out_xbar_auto_out_2_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_2_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_2_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_2_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_2_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_2_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [29:0] out_xbar_auto_out_1_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_1_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_1_a_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [1:0] out_xbar_auto_out_1_d_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_1_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_bits_sink; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_bits_denied; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_1_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_1_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_a_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_a_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_a_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_a_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [3:0] out_xbar_auto_out_0_a_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_a_bits_source; // @[PeripheryBus.scala 50:30]
+ wire [13:0] out_xbar_auto_out_0_a_bits_address; // @[PeripheryBus.scala 50:30]
+ wire [7:0] out_xbar_auto_out_0_a_bits_mask; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_d_ready; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_d_valid; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_d_bits_opcode; // @[PeripheryBus.scala 50:30]
+ wire [1:0] out_xbar_auto_out_0_d_bits_param; // @[PeripheryBus.scala 50:30]
+ wire [3:0] out_xbar_auto_out_0_d_bits_size; // @[PeripheryBus.scala 50:30]
+ wire [2:0] out_xbar_auto_out_0_d_bits_source; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_d_bits_sink; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_d_bits_denied; // @[PeripheryBus.scala 50:30]
+ wire [63:0] out_xbar_auto_out_0_d_bits_data; // @[PeripheryBus.scala 50:30]
+ wire out_xbar_auto_out_0_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire atomics_clock; // @[AtomicAutomata.scala 283:29]
+ wire atomics_reset; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_a_ready; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_a_valid; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_a_bits_opcode; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_a_bits_param; // @[AtomicAutomata.scala 283:29]
+ wire [3:0] atomics_auto_in_a_bits_size; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_a_bits_source; // @[AtomicAutomata.scala 283:29]
+ wire [31:0] atomics_auto_in_a_bits_address; // @[AtomicAutomata.scala 283:29]
+ wire [7:0] atomics_auto_in_a_bits_mask; // @[AtomicAutomata.scala 283:29]
+ wire [63:0] atomics_auto_in_a_bits_data; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_ready; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_valid; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala 283:29]
+ wire [1:0] atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala 283:29]
+ wire [3:0] atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala 283:29]
+ wire [63:0] atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_a_ready; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_a_valid; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala 283:29]
+ wire [3:0] atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala 283:29]
+ wire [31:0] atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala 283:29]
+ wire [7:0] atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala 283:29]
+ wire [63:0] atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_ready; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_valid; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_d_bits_opcode; // @[AtomicAutomata.scala 283:29]
+ wire [1:0] atomics_auto_out_d_bits_param; // @[AtomicAutomata.scala 283:29]
+ wire [3:0] atomics_auto_out_d_bits_size; // @[AtomicAutomata.scala 283:29]
+ wire [2:0] atomics_auto_out_d_bits_source; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_bits_sink; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_bits_denied; // @[AtomicAutomata.scala 283:29]
+ wire [63:0] atomics_auto_out_d_bits_data; // @[AtomicAutomata.scala 283:29]
+ wire atomics_auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 283:29]
+ wire wrapped_error_device_clock; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_reset; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_auto_buffer_in_a_ready; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_auto_buffer_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] wrapped_error_device_auto_buffer_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [13:0] wrapped_error_device_auto_buffer_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] wrapped_error_device_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_auto_buffer_in_d_ready; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_auto_buffer_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [3:0] wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [29:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [29:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_plic_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_plic_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [27:0] coupler_to_plic_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_plic_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_plic_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_plic_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_plic_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_plic_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [27:0] coupler_to_plic_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_plic_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_plic_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_plic_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_clint_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_clint_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [25:0] coupler_to_clint_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_clint_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_clint_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_clint_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_clint_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_clint_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [25:0] coupler_to_clint_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_clint_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_clint_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_clint_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_debug_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_debug_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [11:0] coupler_to_debug_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_debug_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_debug_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_debug_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_debug_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_debug_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [11:0] coupler_to_debug_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_debug_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_debug_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_debug_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_slave_clock_xing_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_slave_clock_xing_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_slave_clock_xing_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_slave_clock_xing_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_to_tile_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_tile_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_tile_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_tile_auto_tl_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_tile_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_tile_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_tile_auto_tl_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [16:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bootrom_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bootrom_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bootrom_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bootrom_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [16:0] coupler_to_bootrom_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_bootrom_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [31:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [20:0] coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [20:0] coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_clockgater_auto_buffer_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_clock; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_reset; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [20:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_param; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_source; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_param; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_source; // @[LazyModule.scala 432:27]
+ wire [20:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_address; // @[LazyModule.scala 432:27]
+ wire [7:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_data; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_ready; // @[LazyModule.scala 432:27]
+ wire coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_valid; // @[LazyModule.scala 432:27]
+ wire [2:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 432:27]
+ wire [1:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_size; // @[LazyModule.scala 432:27]
+ wire [6:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_source; // @[LazyModule.scala 432:27]
+ wire [63:0] coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_data; // @[LazyModule.scala 432:27]
+ wire bundleIn_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ reg [2:0] state; // @[CustomBootPin.scala 46:28]
+ wire bundleOut_0_1_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ wire _GEN_19 = 3'h2 == state ? 1'h0 : 3'h3 == state; // @[CustomBootPin.scala 47:20 50:24]
+ wire _GEN_28 = 3'h1 == state | _GEN_19; // @[CustomBootPin.scala 50:24 53:24]
+ wire bundleOut_0_1_a_valid = 3'h0 == state ? 1'h0 : _GEN_28; // @[CustomBootPin.scala 47:20 50:24]
+ wire _T_2 = bundleOut_0_1_a_ready & bundleOut_0_1_a_valid; // @[Decoupled.scala 50:35]
+ wire bundleOut_0_1_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ wire [2:0] _GEN_2 = bundleOut_0_1_d_valid ? 3'h3 : state; // @[CustomBootPin.scala 46:28 62:{58,66}]
+ wire [2:0] _GEN_3 = _T_2 ? 3'h4 : state; // @[CustomBootPin.scala 46:28 71:{30,38}]
+ wire [2:0] _GEN_4 = bundleOut_0_1_d_valid ? 3'h5 : state; // @[CustomBootPin.scala 46:28 73:{50,58}]
+ wire [2:0] _GEN_5 = ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala 46:28 74:{43,51}]
+ wire [2:0] _GEN_6 = 3'h5 == state ? _GEN_5 : state; // @[CustomBootPin.scala 50:24 46:28]
+ wire [2:0] _GEN_7 = 3'h4 == state ? _GEN_4 : _GEN_6; // @[CustomBootPin.scala 50:24]
+ wire [2:0] _GEN_17 = 3'h3 == state ? _GEN_3 : _GEN_7; // @[CustomBootPin.scala 50:24]
+ wire bundleIn_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ ClockGroupAggregator_3 subsystem_cbus_clock_groups ( // @[BusWrapper.scala 40:48]
+ .auto_in_member_subsystem_cbus_0_clock(subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_clock),
+ .auto_in_member_subsystem_cbus_0_reset(subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_reset),
+ .auto_out_member_subsystem_cbus_0_clock(subsystem_cbus_clock_groups_auto_out_member_subsystem_cbus_0_clock),
+ .auto_out_member_subsystem_cbus_0_reset(subsystem_cbus_clock_groups_auto_out_member_subsystem_cbus_0_reset)
+ );
+ ClockGroup_3 clockGroup ( // @[BusWrapper.scala 41:38]
+ .auto_in_member_subsystem_cbus_0_clock(clockGroup_auto_in_member_subsystem_cbus_0_clock),
+ .auto_in_member_subsystem_cbus_0_reset(clockGroup_auto_in_member_subsystem_cbus_0_reset),
+ .auto_out_clock(clockGroup_auto_out_clock),
+ .auto_out_reset(clockGroup_auto_out_reset)
+ );
+ FixedClockBroadcast_1 fixedClockNode ( // @[ClockGroup.scala 106:107]
+ .auto_in_clock(fixedClockNode_auto_in_clock),
+ .auto_in_reset(fixedClockNode_auto_in_reset),
+ .auto_out_5_clock(fixedClockNode_auto_out_5_clock),
+ .auto_out_5_reset(fixedClockNode_auto_out_5_reset),
+ .auto_out_4_clock(fixedClockNode_auto_out_4_clock),
+ .auto_out_4_reset(fixedClockNode_auto_out_4_reset),
+ .auto_out_3_clock(fixedClockNode_auto_out_3_clock),
+ .auto_out_3_reset(fixedClockNode_auto_out_3_reset),
+ .auto_out_2_clock(fixedClockNode_auto_out_2_clock),
+ .auto_out_2_reset(fixedClockNode_auto_out_2_reset),
+ .auto_out_1_clock(fixedClockNode_auto_out_1_clock),
+ .auto_out_1_reset(fixedClockNode_auto_out_1_reset),
+ .auto_out_0_clock(fixedClockNode_auto_out_0_clock),
+ .auto_out_0_reset(fixedClockNode_auto_out_0_reset)
+ );
+ TLFIFOFixer_2 fixer ( // @[PeripheryBus.scala 47:33]
+ .clock(fixer_clock),
+ .reset(fixer_reset),
+ .auto_in_a_ready(fixer_auto_in_a_ready),
+ .auto_in_a_valid(fixer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fixer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fixer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fixer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fixer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fixer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(fixer_auto_in_d_ready),
+ .auto_in_d_valid(fixer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(fixer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(fixer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fixer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(fixer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(fixer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(fixer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(fixer_auto_out_a_ready),
+ .auto_out_a_valid(fixer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fixer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fixer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fixer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fixer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fixer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(fixer_auto_out_d_ready),
+ .auto_out_d_valid(fixer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(fixer_auto_out_d_bits_param),
+ .auto_out_d_bits_size(fixer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fixer_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(fixer_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(fixer_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(fixer_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt)
+ );
+ TLXbar_4 in_xbar ( // @[PeripheryBus.scala 49:29]
+ .clock(in_xbar_clock),
+ .reset(in_xbar_reset),
+ .auto_in_1_a_ready(in_xbar_auto_in_1_a_ready),
+ .auto_in_1_a_valid(in_xbar_auto_in_1_a_valid),
+ .auto_in_1_a_bits_address(in_xbar_auto_in_1_a_bits_address),
+ .auto_in_1_a_bits_data(in_xbar_auto_in_1_a_bits_data),
+ .auto_in_1_d_valid(in_xbar_auto_in_1_d_valid),
+ .auto_in_0_a_ready(in_xbar_auto_in_0_a_ready),
+ .auto_in_0_a_valid(in_xbar_auto_in_0_a_valid),
+ .auto_in_0_a_bits_opcode(in_xbar_auto_in_0_a_bits_opcode),
+ .auto_in_0_a_bits_param(in_xbar_auto_in_0_a_bits_param),
+ .auto_in_0_a_bits_size(in_xbar_auto_in_0_a_bits_size),
+ .auto_in_0_a_bits_source(in_xbar_auto_in_0_a_bits_source),
+ .auto_in_0_a_bits_address(in_xbar_auto_in_0_a_bits_address),
+ .auto_in_0_a_bits_mask(in_xbar_auto_in_0_a_bits_mask),
+ .auto_in_0_a_bits_data(in_xbar_auto_in_0_a_bits_data),
+ .auto_in_0_a_bits_corrupt(in_xbar_auto_in_0_a_bits_corrupt),
+ .auto_in_0_d_ready(in_xbar_auto_in_0_d_ready),
+ .auto_in_0_d_valid(in_xbar_auto_in_0_d_valid),
+ .auto_in_0_d_bits_opcode(in_xbar_auto_in_0_d_bits_opcode),
+ .auto_in_0_d_bits_param(in_xbar_auto_in_0_d_bits_param),
+ .auto_in_0_d_bits_size(in_xbar_auto_in_0_d_bits_size),
+ .auto_in_0_d_bits_source(in_xbar_auto_in_0_d_bits_source),
+ .auto_in_0_d_bits_sink(in_xbar_auto_in_0_d_bits_sink),
+ .auto_in_0_d_bits_denied(in_xbar_auto_in_0_d_bits_denied),
+ .auto_in_0_d_bits_data(in_xbar_auto_in_0_d_bits_data),
+ .auto_in_0_d_bits_corrupt(in_xbar_auto_in_0_d_bits_corrupt),
+ .auto_out_a_ready(in_xbar_auto_out_a_ready),
+ .auto_out_a_valid(in_xbar_auto_out_a_valid),
+ .auto_out_a_bits_opcode(in_xbar_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(in_xbar_auto_out_a_bits_param),
+ .auto_out_a_bits_size(in_xbar_auto_out_a_bits_size),
+ .auto_out_a_bits_source(in_xbar_auto_out_a_bits_source),
+ .auto_out_a_bits_address(in_xbar_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(in_xbar_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(in_xbar_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(in_xbar_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(in_xbar_auto_out_d_ready),
+ .auto_out_d_valid(in_xbar_auto_out_d_valid),
+ .auto_out_d_bits_opcode(in_xbar_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(in_xbar_auto_out_d_bits_param),
+ .auto_out_d_bits_size(in_xbar_auto_out_d_bits_size),
+ .auto_out_d_bits_source(in_xbar_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(in_xbar_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(in_xbar_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(in_xbar_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(in_xbar_auto_out_d_bits_corrupt)
+ );
+ TLXbar_5 out_xbar ( // @[PeripheryBus.scala 50:30]
+ .clock(out_xbar_clock),
+ .reset(out_xbar_reset),
+ .auto_in_a_ready(out_xbar_auto_in_a_ready),
+ .auto_in_a_valid(out_xbar_auto_in_a_valid),
+ .auto_in_a_bits_opcode(out_xbar_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(out_xbar_auto_in_a_bits_param),
+ .auto_in_a_bits_size(out_xbar_auto_in_a_bits_size),
+ .auto_in_a_bits_source(out_xbar_auto_in_a_bits_source),
+ .auto_in_a_bits_address(out_xbar_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(out_xbar_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(out_xbar_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(out_xbar_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(out_xbar_auto_in_d_ready),
+ .auto_in_d_valid(out_xbar_auto_in_d_valid),
+ .auto_in_d_bits_opcode(out_xbar_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(out_xbar_auto_in_d_bits_param),
+ .auto_in_d_bits_size(out_xbar_auto_in_d_bits_size),
+ .auto_in_d_bits_source(out_xbar_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(out_xbar_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(out_xbar_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(out_xbar_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(out_xbar_auto_in_d_bits_corrupt),
+ .auto_out_8_a_ready(out_xbar_auto_out_8_a_ready),
+ .auto_out_8_a_valid(out_xbar_auto_out_8_a_valid),
+ .auto_out_8_a_bits_opcode(out_xbar_auto_out_8_a_bits_opcode),
+ .auto_out_8_a_bits_param(out_xbar_auto_out_8_a_bits_param),
+ .auto_out_8_a_bits_size(out_xbar_auto_out_8_a_bits_size),
+ .auto_out_8_a_bits_source(out_xbar_auto_out_8_a_bits_source),
+ .auto_out_8_a_bits_address(out_xbar_auto_out_8_a_bits_address),
+ .auto_out_8_a_bits_mask(out_xbar_auto_out_8_a_bits_mask),
+ .auto_out_8_a_bits_data(out_xbar_auto_out_8_a_bits_data),
+ .auto_out_8_a_bits_corrupt(out_xbar_auto_out_8_a_bits_corrupt),
+ .auto_out_8_d_ready(out_xbar_auto_out_8_d_ready),
+ .auto_out_8_d_valid(out_xbar_auto_out_8_d_valid),
+ .auto_out_8_d_bits_opcode(out_xbar_auto_out_8_d_bits_opcode),
+ .auto_out_8_d_bits_param(out_xbar_auto_out_8_d_bits_param),
+ .auto_out_8_d_bits_size(out_xbar_auto_out_8_d_bits_size),
+ .auto_out_8_d_bits_source(out_xbar_auto_out_8_d_bits_source),
+ .auto_out_8_d_bits_sink(out_xbar_auto_out_8_d_bits_sink),
+ .auto_out_8_d_bits_denied(out_xbar_auto_out_8_d_bits_denied),
+ .auto_out_8_d_bits_data(out_xbar_auto_out_8_d_bits_data),
+ .auto_out_8_d_bits_corrupt(out_xbar_auto_out_8_d_bits_corrupt),
+ .auto_out_7_a_ready(out_xbar_auto_out_7_a_ready),
+ .auto_out_7_a_valid(out_xbar_auto_out_7_a_valid),
+ .auto_out_7_a_bits_opcode(out_xbar_auto_out_7_a_bits_opcode),
+ .auto_out_7_a_bits_param(out_xbar_auto_out_7_a_bits_param),
+ .auto_out_7_a_bits_size(out_xbar_auto_out_7_a_bits_size),
+ .auto_out_7_a_bits_source(out_xbar_auto_out_7_a_bits_source),
+ .auto_out_7_a_bits_address(out_xbar_auto_out_7_a_bits_address),
+ .auto_out_7_a_bits_mask(out_xbar_auto_out_7_a_bits_mask),
+ .auto_out_7_a_bits_data(out_xbar_auto_out_7_a_bits_data),
+ .auto_out_7_a_bits_corrupt(out_xbar_auto_out_7_a_bits_corrupt),
+ .auto_out_7_d_ready(out_xbar_auto_out_7_d_ready),
+ .auto_out_7_d_valid(out_xbar_auto_out_7_d_valid),
+ .auto_out_7_d_bits_opcode(out_xbar_auto_out_7_d_bits_opcode),
+ .auto_out_7_d_bits_param(out_xbar_auto_out_7_d_bits_param),
+ .auto_out_7_d_bits_size(out_xbar_auto_out_7_d_bits_size),
+ .auto_out_7_d_bits_source(out_xbar_auto_out_7_d_bits_source),
+ .auto_out_7_d_bits_sink(out_xbar_auto_out_7_d_bits_sink),
+ .auto_out_7_d_bits_denied(out_xbar_auto_out_7_d_bits_denied),
+ .auto_out_7_d_bits_data(out_xbar_auto_out_7_d_bits_data),
+ .auto_out_7_d_bits_corrupt(out_xbar_auto_out_7_d_bits_corrupt),
+ .auto_out_6_a_ready(out_xbar_auto_out_6_a_ready),
+ .auto_out_6_a_valid(out_xbar_auto_out_6_a_valid),
+ .auto_out_6_a_bits_opcode(out_xbar_auto_out_6_a_bits_opcode),
+ .auto_out_6_a_bits_param(out_xbar_auto_out_6_a_bits_param),
+ .auto_out_6_a_bits_size(out_xbar_auto_out_6_a_bits_size),
+ .auto_out_6_a_bits_source(out_xbar_auto_out_6_a_bits_source),
+ .auto_out_6_a_bits_address(out_xbar_auto_out_6_a_bits_address),
+ .auto_out_6_a_bits_mask(out_xbar_auto_out_6_a_bits_mask),
+ .auto_out_6_a_bits_corrupt(out_xbar_auto_out_6_a_bits_corrupt),
+ .auto_out_6_d_ready(out_xbar_auto_out_6_d_ready),
+ .auto_out_6_d_valid(out_xbar_auto_out_6_d_valid),
+ .auto_out_6_d_bits_size(out_xbar_auto_out_6_d_bits_size),
+ .auto_out_6_d_bits_source(out_xbar_auto_out_6_d_bits_source),
+ .auto_out_6_d_bits_data(out_xbar_auto_out_6_d_bits_data),
+ .auto_out_5_a_ready(out_xbar_auto_out_5_a_ready),
+ .auto_out_5_a_valid(out_xbar_auto_out_5_a_valid),
+ .auto_out_5_a_bits_opcode(out_xbar_auto_out_5_a_bits_opcode),
+ .auto_out_5_a_bits_param(out_xbar_auto_out_5_a_bits_param),
+ .auto_out_5_a_bits_size(out_xbar_auto_out_5_a_bits_size),
+ .auto_out_5_a_bits_source(out_xbar_auto_out_5_a_bits_source),
+ .auto_out_5_a_bits_address(out_xbar_auto_out_5_a_bits_address),
+ .auto_out_5_a_bits_mask(out_xbar_auto_out_5_a_bits_mask),
+ .auto_out_5_a_bits_data(out_xbar_auto_out_5_a_bits_data),
+ .auto_out_5_d_ready(out_xbar_auto_out_5_d_ready),
+ .auto_out_5_d_valid(out_xbar_auto_out_5_d_valid),
+ .auto_out_5_d_bits_opcode(out_xbar_auto_out_5_d_bits_opcode),
+ .auto_out_5_d_bits_param(out_xbar_auto_out_5_d_bits_param),
+ .auto_out_5_d_bits_size(out_xbar_auto_out_5_d_bits_size),
+ .auto_out_5_d_bits_source(out_xbar_auto_out_5_d_bits_source),
+ .auto_out_5_d_bits_sink(out_xbar_auto_out_5_d_bits_sink),
+ .auto_out_5_d_bits_denied(out_xbar_auto_out_5_d_bits_denied),
+ .auto_out_5_d_bits_data(out_xbar_auto_out_5_d_bits_data),
+ .auto_out_5_d_bits_corrupt(out_xbar_auto_out_5_d_bits_corrupt),
+ .auto_out_4_a_ready(out_xbar_auto_out_4_a_ready),
+ .auto_out_4_a_valid(out_xbar_auto_out_4_a_valid),
+ .auto_out_4_a_bits_opcode(out_xbar_auto_out_4_a_bits_opcode),
+ .auto_out_4_a_bits_param(out_xbar_auto_out_4_a_bits_param),
+ .auto_out_4_a_bits_size(out_xbar_auto_out_4_a_bits_size),
+ .auto_out_4_a_bits_source(out_xbar_auto_out_4_a_bits_source),
+ .auto_out_4_a_bits_address(out_xbar_auto_out_4_a_bits_address),
+ .auto_out_4_a_bits_mask(out_xbar_auto_out_4_a_bits_mask),
+ .auto_out_4_a_bits_data(out_xbar_auto_out_4_a_bits_data),
+ .auto_out_4_a_bits_corrupt(out_xbar_auto_out_4_a_bits_corrupt),
+ .auto_out_4_d_ready(out_xbar_auto_out_4_d_ready),
+ .auto_out_4_d_valid(out_xbar_auto_out_4_d_valid),
+ .auto_out_4_d_bits_opcode(out_xbar_auto_out_4_d_bits_opcode),
+ .auto_out_4_d_bits_size(out_xbar_auto_out_4_d_bits_size),
+ .auto_out_4_d_bits_source(out_xbar_auto_out_4_d_bits_source),
+ .auto_out_4_d_bits_data(out_xbar_auto_out_4_d_bits_data),
+ .auto_out_3_a_ready(out_xbar_auto_out_3_a_ready),
+ .auto_out_3_a_valid(out_xbar_auto_out_3_a_valid),
+ .auto_out_3_a_bits_opcode(out_xbar_auto_out_3_a_bits_opcode),
+ .auto_out_3_a_bits_param(out_xbar_auto_out_3_a_bits_param),
+ .auto_out_3_a_bits_size(out_xbar_auto_out_3_a_bits_size),
+ .auto_out_3_a_bits_source(out_xbar_auto_out_3_a_bits_source),
+ .auto_out_3_a_bits_address(out_xbar_auto_out_3_a_bits_address),
+ .auto_out_3_a_bits_mask(out_xbar_auto_out_3_a_bits_mask),
+ .auto_out_3_a_bits_data(out_xbar_auto_out_3_a_bits_data),
+ .auto_out_3_a_bits_corrupt(out_xbar_auto_out_3_a_bits_corrupt),
+ .auto_out_3_d_ready(out_xbar_auto_out_3_d_ready),
+ .auto_out_3_d_valid(out_xbar_auto_out_3_d_valid),
+ .auto_out_3_d_bits_opcode(out_xbar_auto_out_3_d_bits_opcode),
+ .auto_out_3_d_bits_size(out_xbar_auto_out_3_d_bits_size),
+ .auto_out_3_d_bits_source(out_xbar_auto_out_3_d_bits_source),
+ .auto_out_3_d_bits_data(out_xbar_auto_out_3_d_bits_data),
+ .auto_out_2_a_ready(out_xbar_auto_out_2_a_ready),
+ .auto_out_2_a_valid(out_xbar_auto_out_2_a_valid),
+ .auto_out_2_a_bits_opcode(out_xbar_auto_out_2_a_bits_opcode),
+ .auto_out_2_a_bits_param(out_xbar_auto_out_2_a_bits_param),
+ .auto_out_2_a_bits_size(out_xbar_auto_out_2_a_bits_size),
+ .auto_out_2_a_bits_source(out_xbar_auto_out_2_a_bits_source),
+ .auto_out_2_a_bits_address(out_xbar_auto_out_2_a_bits_address),
+ .auto_out_2_a_bits_mask(out_xbar_auto_out_2_a_bits_mask),
+ .auto_out_2_a_bits_data(out_xbar_auto_out_2_a_bits_data),
+ .auto_out_2_a_bits_corrupt(out_xbar_auto_out_2_a_bits_corrupt),
+ .auto_out_2_d_ready(out_xbar_auto_out_2_d_ready),
+ .auto_out_2_d_valid(out_xbar_auto_out_2_d_valid),
+ .auto_out_2_d_bits_opcode(out_xbar_auto_out_2_d_bits_opcode),
+ .auto_out_2_d_bits_size(out_xbar_auto_out_2_d_bits_size),
+ .auto_out_2_d_bits_source(out_xbar_auto_out_2_d_bits_source),
+ .auto_out_2_d_bits_data(out_xbar_auto_out_2_d_bits_data),
+ .auto_out_1_a_ready(out_xbar_auto_out_1_a_ready),
+ .auto_out_1_a_valid(out_xbar_auto_out_1_a_valid),
+ .auto_out_1_a_bits_opcode(out_xbar_auto_out_1_a_bits_opcode),
+ .auto_out_1_a_bits_param(out_xbar_auto_out_1_a_bits_param),
+ .auto_out_1_a_bits_size(out_xbar_auto_out_1_a_bits_size),
+ .auto_out_1_a_bits_source(out_xbar_auto_out_1_a_bits_source),
+ .auto_out_1_a_bits_address(out_xbar_auto_out_1_a_bits_address),
+ .auto_out_1_a_bits_mask(out_xbar_auto_out_1_a_bits_mask),
+ .auto_out_1_a_bits_data(out_xbar_auto_out_1_a_bits_data),
+ .auto_out_1_a_bits_corrupt(out_xbar_auto_out_1_a_bits_corrupt),
+ .auto_out_1_d_ready(out_xbar_auto_out_1_d_ready),
+ .auto_out_1_d_valid(out_xbar_auto_out_1_d_valid),
+ .auto_out_1_d_bits_opcode(out_xbar_auto_out_1_d_bits_opcode),
+ .auto_out_1_d_bits_param(out_xbar_auto_out_1_d_bits_param),
+ .auto_out_1_d_bits_size(out_xbar_auto_out_1_d_bits_size),
+ .auto_out_1_d_bits_source(out_xbar_auto_out_1_d_bits_source),
+ .auto_out_1_d_bits_sink(out_xbar_auto_out_1_d_bits_sink),
+ .auto_out_1_d_bits_denied(out_xbar_auto_out_1_d_bits_denied),
+ .auto_out_1_d_bits_data(out_xbar_auto_out_1_d_bits_data),
+ .auto_out_1_d_bits_corrupt(out_xbar_auto_out_1_d_bits_corrupt),
+ .auto_out_0_a_ready(out_xbar_auto_out_0_a_ready),
+ .auto_out_0_a_valid(out_xbar_auto_out_0_a_valid),
+ .auto_out_0_a_bits_opcode(out_xbar_auto_out_0_a_bits_opcode),
+ .auto_out_0_a_bits_param(out_xbar_auto_out_0_a_bits_param),
+ .auto_out_0_a_bits_size(out_xbar_auto_out_0_a_bits_size),
+ .auto_out_0_a_bits_source(out_xbar_auto_out_0_a_bits_source),
+ .auto_out_0_a_bits_address(out_xbar_auto_out_0_a_bits_address),
+ .auto_out_0_a_bits_mask(out_xbar_auto_out_0_a_bits_mask),
+ .auto_out_0_a_bits_corrupt(out_xbar_auto_out_0_a_bits_corrupt),
+ .auto_out_0_d_ready(out_xbar_auto_out_0_d_ready),
+ .auto_out_0_d_valid(out_xbar_auto_out_0_d_valid),
+ .auto_out_0_d_bits_opcode(out_xbar_auto_out_0_d_bits_opcode),
+ .auto_out_0_d_bits_param(out_xbar_auto_out_0_d_bits_param),
+ .auto_out_0_d_bits_size(out_xbar_auto_out_0_d_bits_size),
+ .auto_out_0_d_bits_source(out_xbar_auto_out_0_d_bits_source),
+ .auto_out_0_d_bits_sink(out_xbar_auto_out_0_d_bits_sink),
+ .auto_out_0_d_bits_denied(out_xbar_auto_out_0_d_bits_denied),
+ .auto_out_0_d_bits_data(out_xbar_auto_out_0_d_bits_data),
+ .auto_out_0_d_bits_corrupt(out_xbar_auto_out_0_d_bits_corrupt)
+ );
+ TLBuffer_8 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
+ );
+ TLAtomicAutomata_1 atomics ( // @[AtomicAutomata.scala 283:29]
+ .clock(atomics_clock),
+ .reset(atomics_reset),
+ .auto_in_a_ready(atomics_auto_in_a_ready),
+ .auto_in_a_valid(atomics_auto_in_a_valid),
+ .auto_in_a_bits_opcode(atomics_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(atomics_auto_in_a_bits_param),
+ .auto_in_a_bits_size(atomics_auto_in_a_bits_size),
+ .auto_in_a_bits_source(atomics_auto_in_a_bits_source),
+ .auto_in_a_bits_address(atomics_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(atomics_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(atomics_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(atomics_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(atomics_auto_in_d_ready),
+ .auto_in_d_valid(atomics_auto_in_d_valid),
+ .auto_in_d_bits_opcode(atomics_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(atomics_auto_in_d_bits_param),
+ .auto_in_d_bits_size(atomics_auto_in_d_bits_size),
+ .auto_in_d_bits_source(atomics_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(atomics_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(atomics_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(atomics_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(atomics_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(atomics_auto_out_a_ready),
+ .auto_out_a_valid(atomics_auto_out_a_valid),
+ .auto_out_a_bits_opcode(atomics_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(atomics_auto_out_a_bits_param),
+ .auto_out_a_bits_size(atomics_auto_out_a_bits_size),
+ .auto_out_a_bits_source(atomics_auto_out_a_bits_source),
+ .auto_out_a_bits_address(atomics_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(atomics_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(atomics_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(atomics_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(atomics_auto_out_d_ready),
+ .auto_out_d_valid(atomics_auto_out_d_valid),
+ .auto_out_d_bits_opcode(atomics_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(atomics_auto_out_d_bits_param),
+ .auto_out_d_bits_size(atomics_auto_out_d_bits_size),
+ .auto_out_d_bits_source(atomics_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(atomics_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(atomics_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(atomics_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(atomics_auto_out_d_bits_corrupt)
+ );
+ ErrorDeviceWrapper wrapped_error_device ( // @[LazyModule.scala 432:27]
+ .clock(wrapped_error_device_clock),
+ .reset(wrapped_error_device_reset),
+ .auto_buffer_in_a_ready(wrapped_error_device_auto_buffer_in_a_ready),
+ .auto_buffer_in_a_valid(wrapped_error_device_auto_buffer_in_a_valid),
+ .auto_buffer_in_a_bits_opcode(wrapped_error_device_auto_buffer_in_a_bits_opcode),
+ .auto_buffer_in_a_bits_param(wrapped_error_device_auto_buffer_in_a_bits_param),
+ .auto_buffer_in_a_bits_size(wrapped_error_device_auto_buffer_in_a_bits_size),
+ .auto_buffer_in_a_bits_source(wrapped_error_device_auto_buffer_in_a_bits_source),
+ .auto_buffer_in_a_bits_address(wrapped_error_device_auto_buffer_in_a_bits_address),
+ .auto_buffer_in_a_bits_mask(wrapped_error_device_auto_buffer_in_a_bits_mask),
+ .auto_buffer_in_a_bits_corrupt(wrapped_error_device_auto_buffer_in_a_bits_corrupt),
+ .auto_buffer_in_d_ready(wrapped_error_device_auto_buffer_in_d_ready),
+ .auto_buffer_in_d_valid(wrapped_error_device_auto_buffer_in_d_valid),
+ .auto_buffer_in_d_bits_opcode(wrapped_error_device_auto_buffer_in_d_bits_opcode),
+ .auto_buffer_in_d_bits_param(wrapped_error_device_auto_buffer_in_d_bits_param),
+ .auto_buffer_in_d_bits_size(wrapped_error_device_auto_buffer_in_d_bits_size),
+ .auto_buffer_in_d_bits_source(wrapped_error_device_auto_buffer_in_d_bits_source),
+ .auto_buffer_in_d_bits_sink(wrapped_error_device_auto_buffer_in_d_bits_sink),
+ .auto_buffer_in_d_bits_denied(wrapped_error_device_auto_buffer_in_d_bits_denied),
+ .auto_buffer_in_d_bits_data(wrapped_error_device_auto_buffer_in_d_bits_data),
+ .auto_buffer_in_d_bits_corrupt(wrapped_error_device_auto_buffer_in_d_bits_corrupt)
+ );
+ TLBuffer_10 buffer_1 ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_1_auto_in_a_ready),
+ .auto_in_a_valid(buffer_1_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_1_auto_in_d_ready),
+ .auto_in_d_valid(buffer_1_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_1_auto_out_a_ready),
+ .auto_out_a_valid(buffer_1_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_1_auto_out_d_ready),
+ .auto_out_d_valid(buffer_1_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt)
+ );
+ TLInterconnectCoupler_15 coupler_to_bus_named_subsystem_pbus ( // @[LazyModule.scala 432:27]
+ .auto_widget_in_a_ready(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_ready),
+ .auto_widget_in_a_valid(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_valid),
+ .auto_widget_in_a_bits_opcode(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_opcode),
+ .auto_widget_in_a_bits_param(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_param),
+ .auto_widget_in_a_bits_size(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_size),
+ .auto_widget_in_a_bits_source(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_source),
+ .auto_widget_in_a_bits_address(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_address),
+ .auto_widget_in_a_bits_mask(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_mask),
+ .auto_widget_in_a_bits_data(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_data),
+ .auto_widget_in_a_bits_corrupt(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_corrupt),
+ .auto_widget_in_d_ready(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_ready),
+ .auto_widget_in_d_valid(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_valid),
+ .auto_widget_in_d_bits_opcode(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_opcode),
+ .auto_widget_in_d_bits_param(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_param),
+ .auto_widget_in_d_bits_size(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_size),
+ .auto_widget_in_d_bits_source(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_source),
+ .auto_widget_in_d_bits_sink(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_sink),
+ .auto_widget_in_d_bits_denied(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_denied),
+ .auto_widget_in_d_bits_data(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_data),
+ .auto_widget_in_d_bits_corrupt(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_corrupt),
+ .auto_bus_xing_out_a_ready(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_ready),
+ .auto_bus_xing_out_a_valid(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_valid),
+ .auto_bus_xing_out_a_bits_opcode(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_opcode),
+ .auto_bus_xing_out_a_bits_param(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_param),
+ .auto_bus_xing_out_a_bits_size(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_size),
+ .auto_bus_xing_out_a_bits_source(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_source),
+ .auto_bus_xing_out_a_bits_address(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_address),
+ .auto_bus_xing_out_a_bits_mask(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_mask),
+ .auto_bus_xing_out_a_bits_data(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_data),
+ .auto_bus_xing_out_a_bits_corrupt(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_corrupt),
+ .auto_bus_xing_out_d_ready(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_ready),
+ .auto_bus_xing_out_d_valid(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_valid),
+ .auto_bus_xing_out_d_bits_opcode(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_opcode),
+ .auto_bus_xing_out_d_bits_param(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_param),
+ .auto_bus_xing_out_d_bits_size(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_size),
+ .auto_bus_xing_out_d_bits_source(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_source),
+ .auto_bus_xing_out_d_bits_sink(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_sink),
+ .auto_bus_xing_out_d_bits_denied(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_denied),
+ .auto_bus_xing_out_d_bits_data(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_data),
+ .auto_bus_xing_out_d_bits_corrupt(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_corrupt)
+ );
+ TLInterconnectCoupler_16 coupler_to_plic ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_plic_clock),
+ .reset(coupler_to_plic_reset),
+ .auto_fragmenter_out_a_ready(coupler_to_plic_auto_fragmenter_out_a_ready),
+ .auto_fragmenter_out_a_valid(coupler_to_plic_auto_fragmenter_out_a_valid),
+ .auto_fragmenter_out_a_bits_opcode(coupler_to_plic_auto_fragmenter_out_a_bits_opcode),
+ .auto_fragmenter_out_a_bits_param(coupler_to_plic_auto_fragmenter_out_a_bits_param),
+ .auto_fragmenter_out_a_bits_size(coupler_to_plic_auto_fragmenter_out_a_bits_size),
+ .auto_fragmenter_out_a_bits_source(coupler_to_plic_auto_fragmenter_out_a_bits_source),
+ .auto_fragmenter_out_a_bits_address(coupler_to_plic_auto_fragmenter_out_a_bits_address),
+ .auto_fragmenter_out_a_bits_mask(coupler_to_plic_auto_fragmenter_out_a_bits_mask),
+ .auto_fragmenter_out_a_bits_data(coupler_to_plic_auto_fragmenter_out_a_bits_data),
+ .auto_fragmenter_out_a_bits_corrupt(coupler_to_plic_auto_fragmenter_out_a_bits_corrupt),
+ .auto_fragmenter_out_d_ready(coupler_to_plic_auto_fragmenter_out_d_ready),
+ .auto_fragmenter_out_d_valid(coupler_to_plic_auto_fragmenter_out_d_valid),
+ .auto_fragmenter_out_d_bits_opcode(coupler_to_plic_auto_fragmenter_out_d_bits_opcode),
+ .auto_fragmenter_out_d_bits_size(coupler_to_plic_auto_fragmenter_out_d_bits_size),
+ .auto_fragmenter_out_d_bits_source(coupler_to_plic_auto_fragmenter_out_d_bits_source),
+ .auto_fragmenter_out_d_bits_data(coupler_to_plic_auto_fragmenter_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_plic_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_plic_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_plic_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_plic_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_plic_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_plic_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_plic_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_plic_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_plic_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_plic_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_plic_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_plic_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_plic_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(coupler_to_plic_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_plic_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_plic_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_17 coupler_to_clint ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_clint_clock),
+ .reset(coupler_to_clint_reset),
+ .auto_fragmenter_out_a_ready(coupler_to_clint_auto_fragmenter_out_a_ready),
+ .auto_fragmenter_out_a_valid(coupler_to_clint_auto_fragmenter_out_a_valid),
+ .auto_fragmenter_out_a_bits_opcode(coupler_to_clint_auto_fragmenter_out_a_bits_opcode),
+ .auto_fragmenter_out_a_bits_param(coupler_to_clint_auto_fragmenter_out_a_bits_param),
+ .auto_fragmenter_out_a_bits_size(coupler_to_clint_auto_fragmenter_out_a_bits_size),
+ .auto_fragmenter_out_a_bits_source(coupler_to_clint_auto_fragmenter_out_a_bits_source),
+ .auto_fragmenter_out_a_bits_address(coupler_to_clint_auto_fragmenter_out_a_bits_address),
+ .auto_fragmenter_out_a_bits_mask(coupler_to_clint_auto_fragmenter_out_a_bits_mask),
+ .auto_fragmenter_out_a_bits_data(coupler_to_clint_auto_fragmenter_out_a_bits_data),
+ .auto_fragmenter_out_a_bits_corrupt(coupler_to_clint_auto_fragmenter_out_a_bits_corrupt),
+ .auto_fragmenter_out_d_ready(coupler_to_clint_auto_fragmenter_out_d_ready),
+ .auto_fragmenter_out_d_valid(coupler_to_clint_auto_fragmenter_out_d_valid),
+ .auto_fragmenter_out_d_bits_opcode(coupler_to_clint_auto_fragmenter_out_d_bits_opcode),
+ .auto_fragmenter_out_d_bits_size(coupler_to_clint_auto_fragmenter_out_d_bits_size),
+ .auto_fragmenter_out_d_bits_source(coupler_to_clint_auto_fragmenter_out_d_bits_source),
+ .auto_fragmenter_out_d_bits_data(coupler_to_clint_auto_fragmenter_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_clint_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_clint_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_clint_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_clint_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_clint_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_clint_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_clint_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_clint_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_clint_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_clint_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_clint_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_clint_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_clint_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(coupler_to_clint_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_clint_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_clint_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_18 coupler_to_debug ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_debug_clock),
+ .reset(coupler_to_debug_reset),
+ .auto_fragmenter_out_a_ready(coupler_to_debug_auto_fragmenter_out_a_ready),
+ .auto_fragmenter_out_a_valid(coupler_to_debug_auto_fragmenter_out_a_valid),
+ .auto_fragmenter_out_a_bits_opcode(coupler_to_debug_auto_fragmenter_out_a_bits_opcode),
+ .auto_fragmenter_out_a_bits_param(coupler_to_debug_auto_fragmenter_out_a_bits_param),
+ .auto_fragmenter_out_a_bits_size(coupler_to_debug_auto_fragmenter_out_a_bits_size),
+ .auto_fragmenter_out_a_bits_source(coupler_to_debug_auto_fragmenter_out_a_bits_source),
+ .auto_fragmenter_out_a_bits_address(coupler_to_debug_auto_fragmenter_out_a_bits_address),
+ .auto_fragmenter_out_a_bits_mask(coupler_to_debug_auto_fragmenter_out_a_bits_mask),
+ .auto_fragmenter_out_a_bits_data(coupler_to_debug_auto_fragmenter_out_a_bits_data),
+ .auto_fragmenter_out_a_bits_corrupt(coupler_to_debug_auto_fragmenter_out_a_bits_corrupt),
+ .auto_fragmenter_out_d_ready(coupler_to_debug_auto_fragmenter_out_d_ready),
+ .auto_fragmenter_out_d_valid(coupler_to_debug_auto_fragmenter_out_d_valid),
+ .auto_fragmenter_out_d_bits_opcode(coupler_to_debug_auto_fragmenter_out_d_bits_opcode),
+ .auto_fragmenter_out_d_bits_size(coupler_to_debug_auto_fragmenter_out_d_bits_size),
+ .auto_fragmenter_out_d_bits_source(coupler_to_debug_auto_fragmenter_out_d_bits_source),
+ .auto_fragmenter_out_d_bits_data(coupler_to_debug_auto_fragmenter_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_debug_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_debug_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_debug_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_debug_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_debug_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_debug_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_debug_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_debug_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_debug_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(coupler_to_debug_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_debug_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_debug_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_debug_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(coupler_to_debug_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_debug_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_debug_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_19 coupler_to_tile ( // @[LazyModule.scala 432:27]
+ .auto_tl_slave_clock_xing_out_a_ready(coupler_to_tile_auto_tl_slave_clock_xing_out_a_ready),
+ .auto_tl_slave_clock_xing_out_a_valid(coupler_to_tile_auto_tl_slave_clock_xing_out_a_valid),
+ .auto_tl_slave_clock_xing_out_a_bits_opcode(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_opcode),
+ .auto_tl_slave_clock_xing_out_a_bits_param(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_param),
+ .auto_tl_slave_clock_xing_out_a_bits_size(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_size),
+ .auto_tl_slave_clock_xing_out_a_bits_source(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_source),
+ .auto_tl_slave_clock_xing_out_a_bits_address(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_address),
+ .auto_tl_slave_clock_xing_out_a_bits_mask(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_mask),
+ .auto_tl_slave_clock_xing_out_a_bits_data(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_data),
+ .auto_tl_slave_clock_xing_out_d_ready(coupler_to_tile_auto_tl_slave_clock_xing_out_d_ready),
+ .auto_tl_slave_clock_xing_out_d_valid(coupler_to_tile_auto_tl_slave_clock_xing_out_d_valid),
+ .auto_tl_slave_clock_xing_out_d_bits_opcode(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_opcode),
+ .auto_tl_slave_clock_xing_out_d_bits_param(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_param),
+ .auto_tl_slave_clock_xing_out_d_bits_size(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_size),
+ .auto_tl_slave_clock_xing_out_d_bits_source(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_source),
+ .auto_tl_slave_clock_xing_out_d_bits_sink(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_sink),
+ .auto_tl_slave_clock_xing_out_d_bits_denied(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_denied),
+ .auto_tl_slave_clock_xing_out_d_bits_data(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_data),
+ .auto_tl_slave_clock_xing_out_d_bits_corrupt(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_corrupt),
+ .auto_tl_in_a_ready(coupler_to_tile_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_tile_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_tile_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_tile_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_tile_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_tile_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_tile_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_tile_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(coupler_to_tile_auto_tl_in_a_bits_data),
+ .auto_tl_in_d_ready(coupler_to_tile_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_tile_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(coupler_to_tile_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_param(coupler_to_tile_auto_tl_in_d_bits_param),
+ .auto_tl_in_d_bits_size(coupler_to_tile_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_tile_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_sink(coupler_to_tile_auto_tl_in_d_bits_sink),
+ .auto_tl_in_d_bits_denied(coupler_to_tile_auto_tl_in_d_bits_denied),
+ .auto_tl_in_d_bits_data(coupler_to_tile_auto_tl_in_d_bits_data),
+ .auto_tl_in_d_bits_corrupt(coupler_to_tile_auto_tl_in_d_bits_corrupt)
+ );
+ TLInterconnectCoupler_20 coupler_to_bootrom ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_bootrom_clock),
+ .reset(coupler_to_bootrom_reset),
+ .auto_fragmenter_out_a_ready(coupler_to_bootrom_auto_fragmenter_out_a_ready),
+ .auto_fragmenter_out_a_valid(coupler_to_bootrom_auto_fragmenter_out_a_valid),
+ .auto_fragmenter_out_a_bits_opcode(coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode),
+ .auto_fragmenter_out_a_bits_param(coupler_to_bootrom_auto_fragmenter_out_a_bits_param),
+ .auto_fragmenter_out_a_bits_size(coupler_to_bootrom_auto_fragmenter_out_a_bits_size),
+ .auto_fragmenter_out_a_bits_source(coupler_to_bootrom_auto_fragmenter_out_a_bits_source),
+ .auto_fragmenter_out_a_bits_address(coupler_to_bootrom_auto_fragmenter_out_a_bits_address),
+ .auto_fragmenter_out_a_bits_mask(coupler_to_bootrom_auto_fragmenter_out_a_bits_mask),
+ .auto_fragmenter_out_a_bits_corrupt(coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt),
+ .auto_fragmenter_out_d_ready(coupler_to_bootrom_auto_fragmenter_out_d_ready),
+ .auto_fragmenter_out_d_valid(coupler_to_bootrom_auto_fragmenter_out_d_valid),
+ .auto_fragmenter_out_d_bits_size(coupler_to_bootrom_auto_fragmenter_out_d_bits_size),
+ .auto_fragmenter_out_d_bits_source(coupler_to_bootrom_auto_fragmenter_out_d_bits_source),
+ .auto_fragmenter_out_d_bits_data(coupler_to_bootrom_auto_fragmenter_out_d_bits_data),
+ .auto_tl_in_a_ready(coupler_to_bootrom_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_to_bootrom_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(coupler_to_bootrom_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(coupler_to_bootrom_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(coupler_to_bootrom_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(coupler_to_bootrom_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(coupler_to_bootrom_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(coupler_to_bootrom_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_corrupt(coupler_to_bootrom_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(coupler_to_bootrom_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(coupler_to_bootrom_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_size(coupler_to_bootrom_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(coupler_to_bootrom_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(coupler_to_bootrom_auto_tl_in_d_bits_data)
+ );
+ TLInterconnectCoupler_21 coupler_from_port_named_custom_boot_pin ( // @[LazyModule.scala 432:27]
+ .auto_tl_in_a_ready(coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_address(coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_data(coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data),
+ .auto_tl_in_d_valid(coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid),
+ .auto_tl_out_a_ready(coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready),
+ .auto_tl_out_a_valid(coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid),
+ .auto_tl_out_a_bits_address(coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address),
+ .auto_tl_out_a_bits_data(coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data),
+ .auto_tl_out_d_valid(coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid)
+ );
+ TLInterconnectCoupler_22 coupler_to_slave_named_clockgater ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_slave_named_clockgater_clock),
+ .reset(coupler_to_slave_named_clockgater_reset),
+ .auto_buffer_in_a_ready(coupler_to_slave_named_clockgater_auto_buffer_in_a_ready),
+ .auto_buffer_in_a_valid(coupler_to_slave_named_clockgater_auto_buffer_in_a_valid),
+ .auto_buffer_in_a_bits_opcode(coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_opcode),
+ .auto_buffer_in_a_bits_param(coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_param),
+ .auto_buffer_in_a_bits_size(coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_size),
+ .auto_buffer_in_a_bits_source(coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_source),
+ .auto_buffer_in_a_bits_address(coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_address),
+ .auto_buffer_in_a_bits_mask(coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_mask),
+ .auto_buffer_in_a_bits_data(coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_data),
+ .auto_buffer_in_a_bits_corrupt(coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_corrupt),
+ .auto_buffer_in_d_ready(coupler_to_slave_named_clockgater_auto_buffer_in_d_ready),
+ .auto_buffer_in_d_valid(coupler_to_slave_named_clockgater_auto_buffer_in_d_valid),
+ .auto_buffer_in_d_bits_opcode(coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_opcode),
+ .auto_buffer_in_d_bits_param(coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_param),
+ .auto_buffer_in_d_bits_size(coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_size),
+ .auto_buffer_in_d_bits_source(coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_source),
+ .auto_buffer_in_d_bits_sink(coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_sink),
+ .auto_buffer_in_d_bits_denied(coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_denied),
+ .auto_buffer_in_d_bits_data(coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_data),
+ .auto_buffer_in_d_bits_corrupt(coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_corrupt),
+ .auto_buffer_out_a_ready(coupler_to_slave_named_clockgater_auto_buffer_out_a_ready),
+ .auto_buffer_out_a_valid(coupler_to_slave_named_clockgater_auto_buffer_out_a_valid),
+ .auto_buffer_out_a_bits_opcode(coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_opcode),
+ .auto_buffer_out_a_bits_param(coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_param),
+ .auto_buffer_out_a_bits_size(coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_size),
+ .auto_buffer_out_a_bits_source(coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_source),
+ .auto_buffer_out_a_bits_address(coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_address),
+ .auto_buffer_out_a_bits_mask(coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_mask),
+ .auto_buffer_out_a_bits_data(coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_data),
+ .auto_buffer_out_a_bits_corrupt(coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_corrupt),
+ .auto_buffer_out_d_ready(coupler_to_slave_named_clockgater_auto_buffer_out_d_ready),
+ .auto_buffer_out_d_valid(coupler_to_slave_named_clockgater_auto_buffer_out_d_valid),
+ .auto_buffer_out_d_bits_opcode(coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_opcode),
+ .auto_buffer_out_d_bits_size(coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_size),
+ .auto_buffer_out_d_bits_source(coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_source),
+ .auto_buffer_out_d_bits_data(coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_data)
+ );
+ TLInterconnectCoupler_23 coupler_to_slave_named_tileresetsetter ( // @[LazyModule.scala 432:27]
+ .clock(coupler_to_slave_named_tileresetsetter_clock),
+ .reset(coupler_to_slave_named_tileresetsetter_reset),
+ .auto_buffer_in_a_ready(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_ready),
+ .auto_buffer_in_a_valid(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_valid),
+ .auto_buffer_in_a_bits_opcode(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_opcode),
+ .auto_buffer_in_a_bits_param(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_param),
+ .auto_buffer_in_a_bits_size(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_size),
+ .auto_buffer_in_a_bits_source(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_source),
+ .auto_buffer_in_a_bits_address(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_address),
+ .auto_buffer_in_a_bits_mask(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_mask),
+ .auto_buffer_in_a_bits_data(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_data),
+ .auto_buffer_in_a_bits_corrupt(coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_corrupt),
+ .auto_buffer_in_d_ready(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_ready),
+ .auto_buffer_in_d_valid(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_valid),
+ .auto_buffer_in_d_bits_opcode(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_opcode),
+ .auto_buffer_in_d_bits_param(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_param),
+ .auto_buffer_in_d_bits_size(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_size),
+ .auto_buffer_in_d_bits_source(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_source),
+ .auto_buffer_in_d_bits_sink(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_sink),
+ .auto_buffer_in_d_bits_denied(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_denied),
+ .auto_buffer_in_d_bits_data(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_data),
+ .auto_buffer_in_d_bits_corrupt(coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_corrupt),
+ .auto_buffer_out_a_ready(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_ready),
+ .auto_buffer_out_a_valid(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_valid),
+ .auto_buffer_out_a_bits_opcode(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_opcode),
+ .auto_buffer_out_a_bits_param(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_param),
+ .auto_buffer_out_a_bits_size(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_size),
+ .auto_buffer_out_a_bits_source(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_source),
+ .auto_buffer_out_a_bits_address(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_address),
+ .auto_buffer_out_a_bits_mask(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_mask),
+ .auto_buffer_out_a_bits_data(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_data),
+ .auto_buffer_out_a_bits_corrupt(coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_corrupt),
+ .auto_buffer_out_d_ready(coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_ready),
+ .auto_buffer_out_d_valid(coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_valid),
+ .auto_buffer_out_d_bits_opcode(coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_opcode),
+ .auto_buffer_out_d_bits_size(coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_size),
+ .auto_buffer_out_d_bits_source(coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_source),
+ .auto_buffer_out_d_bits_data(coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_data)
+ );
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_valid =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_opcode =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_param =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_size =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_source =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_address =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_mask =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_data =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_corrupt =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_ready =
+ coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_valid =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_opcode =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_param =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_size =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_source =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_address =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_mask =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_data =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_corrupt =
+ coupler_to_slave_named_clockgater_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_slave_named_clockgater_buffer_out_d_ready =
+ coupler_to_slave_named_clockgater_auto_buffer_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_a_valid = coupler_to_bootrom_auto_fragmenter_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode = coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_a_bits_param = coupler_to_bootrom_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_a_bits_size = coupler_to_bootrom_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_a_bits_source = coupler_to_bootrom_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_a_bits_address = coupler_to_bootrom_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_a_bits_mask = coupler_to_bootrom_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt = coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bootrom_fragmenter_out_d_ready = coupler_to_bootrom_auto_fragmenter_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid = coupler_to_tile_auto_tl_slave_clock_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode =
+ coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param =
+ coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size =
+ coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source =
+ coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address =
+ coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask =
+ coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data =
+ coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready = coupler_to_tile_auto_tl_slave_clock_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_valid = coupler_to_debug_auto_fragmenter_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_bits_opcode = coupler_to_debug_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_bits_param = coupler_to_debug_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_bits_size = coupler_to_debug_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_bits_source = coupler_to_debug_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_bits_address = coupler_to_debug_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_bits_mask = coupler_to_debug_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_bits_data = coupler_to_debug_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_a_bits_corrupt = coupler_to_debug_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_debug_fragmenter_out_d_ready = coupler_to_debug_auto_fragmenter_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_valid = coupler_to_clint_auto_fragmenter_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_bits_opcode = coupler_to_clint_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_bits_param = coupler_to_clint_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_bits_size = coupler_to_clint_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_bits_source = coupler_to_clint_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_bits_address = coupler_to_clint_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_bits_mask = coupler_to_clint_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_bits_data = coupler_to_clint_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_a_bits_corrupt = coupler_to_clint_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_clint_fragmenter_out_d_ready = coupler_to_clint_auto_fragmenter_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_valid = coupler_to_plic_auto_fragmenter_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_bits_opcode = coupler_to_plic_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_bits_param = coupler_to_plic_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_bits_size = coupler_to_plic_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_bits_source = coupler_to_plic_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_bits_address = coupler_to_plic_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_bits_mask = coupler_to_plic_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_bits_data = coupler_to_plic_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_a_bits_corrupt = coupler_to_plic_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_plic_fragmenter_out_d_ready = coupler_to_plic_auto_fragmenter_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready =
+ coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_4_clock = fixedClockNode_auto_out_5_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_4_reset = fixedClockNode_auto_out_5_reset; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_3_clock = fixedClockNode_auto_out_4_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_3_reset = fixedClockNode_auto_out_4_reset; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_2_clock = fixedClockNode_auto_out_3_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_2_reset = fixedClockNode_auto_out_3_reset; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_0_clock = fixedClockNode_auto_out_1_clock; // @[LazyModule.scala 311:12]
+ assign auto_fixedClockNode_out_0_reset = fixedClockNode_auto_out_1_reset; // @[LazyModule.scala 311:12]
+ assign auto_bus_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_bus_xing_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_clock =
+ auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock; // @[LazyModule.scala 309:16]
+ assign subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_reset =
+ auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset; // @[LazyModule.scala 309:16]
+ assign clockGroup_auto_in_member_subsystem_cbus_0_clock =
+ subsystem_cbus_clock_groups_auto_out_member_subsystem_cbus_0_clock; // @[LazyModule.scala 298:16]
+ assign clockGroup_auto_in_member_subsystem_cbus_0_reset =
+ subsystem_cbus_clock_groups_auto_out_member_subsystem_cbus_0_reset; // @[LazyModule.scala 298:16]
+ assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
+ assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
+ assign fixer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign fixer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign fixer_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign fixer_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign fixer_auto_out_a_ready = out_xbar_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_valid = out_xbar_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_opcode = out_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_param = out_xbar_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_size = out_xbar_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_source = out_xbar_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_sink = out_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_denied = out_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_data = out_xbar_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign fixer_auto_out_d_bits_corrupt = out_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign in_xbar_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign in_xbar_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign in_xbar_auto_in_1_a_valid = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_1_a_bits_address = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_1_a_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_in_0_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign in_xbar_auto_out_a_ready = atomics_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_valid = atomics_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_opcode = atomics_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_param = atomics_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_size = atomics_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_source = atomics_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_sink = atomics_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_denied = atomics_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_data = atomics_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign in_xbar_auto_out_d_bits_corrupt = atomics_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign out_xbar_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign out_xbar_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_a_ready = coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_valid = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_opcode = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_param = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_size = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_source = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_sink = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_denied = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_data = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_8_d_bits_corrupt = coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_a_ready = coupler_to_slave_named_clockgater_auto_buffer_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_valid = coupler_to_slave_named_clockgater_auto_buffer_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_opcode = coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_param = coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_size = coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_source = coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_sink = coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_denied = coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_data = coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_7_d_bits_corrupt = coupler_to_slave_named_clockgater_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_a_ready = coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_d_valid = coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_d_bits_size = coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_d_bits_source = coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_6_d_bits_data = coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_a_ready = coupler_to_tile_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_valid = coupler_to_tile_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_opcode = coupler_to_tile_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_param = coupler_to_tile_auto_tl_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_size = coupler_to_tile_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_source = coupler_to_tile_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_sink = coupler_to_tile_auto_tl_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_denied = coupler_to_tile_auto_tl_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_data = coupler_to_tile_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_5_d_bits_corrupt = coupler_to_tile_auto_tl_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_a_ready = coupler_to_debug_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_valid = coupler_to_debug_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_bits_opcode = coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_bits_size = coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_bits_source = coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_4_d_bits_data = coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_a_ready = coupler_to_clint_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_valid = coupler_to_clint_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_bits_opcode = coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_bits_size = coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_bits_source = coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_3_d_bits_data = coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_a_ready = coupler_to_plic_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_valid = coupler_to_plic_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_bits_opcode = coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_bits_size = coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_bits_source = coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_2_d_bits_data = coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_a_ready = coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_valid = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_opcode = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_param = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_size = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_source = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_sink = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_denied = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_data = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_1_d_bits_corrupt = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_a_ready = wrapped_error_device_auto_buffer_in_a_ready; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_valid = wrapped_error_device_auto_buffer_in_d_valid; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_opcode = wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_param = wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_size = wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_source = wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_sink = wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_denied = wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_data = wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign out_xbar_auto_out_0_d_bits_corrupt = wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign buffer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_in_a_valid = atomics_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_opcode = atomics_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_param = atomics_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_size = atomics_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_source = atomics_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_address = atomics_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_mask = atomics_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_data = atomics_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_a_bits_corrupt = atomics_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign buffer_auto_in_d_ready = atomics_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign atomics_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign atomics_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign atomics_auto_in_a_valid = in_xbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_opcode = in_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_param = in_xbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_size = in_xbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_source = in_xbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_address = in_xbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_mask = in_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_data = in_xbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_a_bits_corrupt = in_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign atomics_auto_in_d_ready = in_xbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
+ assign atomics_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign atomics_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign wrapped_error_device_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign wrapped_error_device_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign wrapped_error_device_auto_buffer_in_a_valid = out_xbar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
+ assign wrapped_error_device_auto_buffer_in_a_bits_opcode = out_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign wrapped_error_device_auto_buffer_in_a_bits_param = out_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 298:16]
+ assign wrapped_error_device_auto_buffer_in_a_bits_size = out_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 298:16]
+ assign wrapped_error_device_auto_buffer_in_a_bits_source = out_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 298:16]
+ assign wrapped_error_device_auto_buffer_in_a_bits_address = out_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
+ assign wrapped_error_device_auto_buffer_in_a_bits_mask = out_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign wrapped_error_device_auto_buffer_in_a_bits_corrupt = out_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign wrapped_error_device_auto_buffer_in_d_ready = out_xbar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_out_a_ready = in_xbar_auto_in_0_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_valid = in_xbar_auto_in_0_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_opcode = in_xbar_auto_in_0_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_param = in_xbar_auto_in_0_d_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_size = in_xbar_auto_in_0_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_source = in_xbar_auto_in_0_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_sink = in_xbar_auto_in_0_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_denied = in_xbar_auto_in_0_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_data = in_xbar_auto_in_0_d_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_1_auto_out_d_bits_corrupt = in_xbar_auto_in_0_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_valid = out_xbar_auto_out_1_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_opcode = out_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_param = out_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_size = out_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_source = out_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_address = out_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_mask = out_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_data = out_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_corrupt = out_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_ready = out_xbar_auto_out_1_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_ready =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_valid =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_opcode =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_param =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_size =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_source =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_sink =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_denied =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_data =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_corrupt =
+ auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign coupler_to_plic_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_plic_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_plic_auto_fragmenter_out_a_ready = auto_coupler_to_plic_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_plic_auto_fragmenter_out_d_valid = auto_coupler_to_plic_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_plic_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_plic_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_plic_auto_fragmenter_out_d_bits_size = auto_coupler_to_plic_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_plic_auto_fragmenter_out_d_bits_source = auto_coupler_to_plic_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_plic_auto_fragmenter_out_d_bits_data = auto_coupler_to_plic_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_plic_auto_tl_in_a_valid = out_xbar_auto_out_2_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_a_bits_opcode = out_xbar_auto_out_2_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_a_bits_param = out_xbar_auto_out_2_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_a_bits_size = out_xbar_auto_out_2_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_a_bits_source = out_xbar_auto_out_2_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_a_bits_address = out_xbar_auto_out_2_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_a_bits_mask = out_xbar_auto_out_2_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_a_bits_data = out_xbar_auto_out_2_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_2_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_plic_auto_tl_in_d_ready = out_xbar_auto_out_2_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_clint_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_clint_auto_fragmenter_out_a_ready = auto_coupler_to_clint_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_clint_auto_fragmenter_out_d_valid = auto_coupler_to_clint_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_clint_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_clint_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_clint_auto_fragmenter_out_d_bits_size = auto_coupler_to_clint_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_clint_auto_fragmenter_out_d_bits_source = auto_coupler_to_clint_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_clint_auto_fragmenter_out_d_bits_data = auto_coupler_to_clint_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_clint_auto_tl_in_a_valid = out_xbar_auto_out_3_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_a_bits_opcode = out_xbar_auto_out_3_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_a_bits_param = out_xbar_auto_out_3_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_a_bits_size = out_xbar_auto_out_3_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_a_bits_source = out_xbar_auto_out_3_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_a_bits_address = out_xbar_auto_out_3_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_a_bits_mask = out_xbar_auto_out_3_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_a_bits_data = out_xbar_auto_out_3_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_3_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_clint_auto_tl_in_d_ready = out_xbar_auto_out_3_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_debug_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_debug_auto_fragmenter_out_a_ready = auto_coupler_to_debug_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_debug_auto_fragmenter_out_d_valid = auto_coupler_to_debug_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_debug_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_debug_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_debug_auto_fragmenter_out_d_bits_size = auto_coupler_to_debug_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_debug_auto_fragmenter_out_d_bits_source = auto_coupler_to_debug_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_debug_auto_fragmenter_out_d_bits_data = auto_coupler_to_debug_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_debug_auto_tl_in_a_valid = out_xbar_auto_out_4_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_a_bits_opcode = out_xbar_auto_out_4_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_a_bits_param = out_xbar_auto_out_4_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_a_bits_size = out_xbar_auto_out_4_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_a_bits_source = out_xbar_auto_out_4_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_a_bits_address = out_xbar_auto_out_4_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_a_bits_mask = out_xbar_auto_out_4_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_a_bits_data = out_xbar_auto_out_4_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_4_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_debug_auto_tl_in_d_ready = out_xbar_auto_out_4_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_a_ready = auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_valid = auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_opcode =
+ auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_param =
+ auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_size =
+ auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_source =
+ auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_sink =
+ auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_denied =
+ auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_data =
+ auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_corrupt =
+ auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign coupler_to_tile_auto_tl_in_a_valid = out_xbar_auto_out_5_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_in_a_bits_opcode = out_xbar_auto_out_5_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_in_a_bits_param = out_xbar_auto_out_5_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_in_a_bits_size = out_xbar_auto_out_5_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_in_a_bits_source = out_xbar_auto_out_5_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_in_a_bits_address = out_xbar_auto_out_5_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_in_a_bits_mask = out_xbar_auto_out_5_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_in_a_bits_data = out_xbar_auto_out_5_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_tile_auto_tl_in_d_ready = out_xbar_auto_out_5_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_bootrom_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_bootrom_auto_fragmenter_out_a_ready = auto_coupler_to_bootrom_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_bootrom_auto_fragmenter_out_d_valid = auto_coupler_to_bootrom_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_bootrom_auto_fragmenter_out_d_bits_size = auto_coupler_to_bootrom_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_bootrom_auto_fragmenter_out_d_bits_source = auto_coupler_to_bootrom_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_bootrom_auto_fragmenter_out_d_bits_data = auto_coupler_to_bootrom_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_bootrom_auto_tl_in_a_valid = out_xbar_auto_out_6_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_auto_tl_in_a_bits_opcode = out_xbar_auto_out_6_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_auto_tl_in_a_bits_param = out_xbar_auto_out_6_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_auto_tl_in_a_bits_size = out_xbar_auto_out_6_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_auto_tl_in_a_bits_source = out_xbar_auto_out_6_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_auto_tl_in_a_bits_address = out_xbar_auto_out_6_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_auto_tl_in_a_bits_mask = out_xbar_auto_out_6_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_6_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_bootrom_auto_tl_in_d_ready = out_xbar_auto_out_6_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid = 3'h0 == state ? 1'h0 : _GEN_28; // @[CustomBootPin.scala 47:20 50:24]
+ assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address = 3'h1 == state ? 32'h4000 : 32'h2000000; // @[CustomBootPin.scala 50:24 54:23]
+ assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data = 3'h1 == state ? 64'h80000000 : 64'h1; // @[CustomBootPin.scala 50:24 54:23]
+ assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready = in_xbar_auto_in_1_a_ready; // @[LazyModule.scala 296:16]
+ assign coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid = in_xbar_auto_in_1_d_valid; // @[LazyModule.scala 296:16]
+ assign coupler_to_slave_named_clockgater_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_clockgater_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_valid = out_xbar_auto_out_7_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_opcode = out_xbar_auto_out_7_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_param = out_xbar_auto_out_7_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_size = out_xbar_auto_out_7_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_source = out_xbar_auto_out_7_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_address = out_xbar_auto_out_7_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_mask = out_xbar_auto_out_7_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_data = out_xbar_auto_out_7_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_a_bits_corrupt = out_xbar_auto_out_7_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_in_d_ready = out_xbar_auto_out_7_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_clockgater_auto_buffer_out_a_ready =
+ auto_coupler_to_slave_named_clockgater_buffer_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_clockgater_auto_buffer_out_d_valid =
+ auto_coupler_to_slave_named_clockgater_buffer_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_opcode =
+ auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_size =
+ auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_source =
+ auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_clockgater_auto_buffer_out_d_bits_data =
+ auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_tileresetsetter_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_tileresetsetter_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_valid = out_xbar_auto_out_8_a_valid; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_opcode = out_xbar_auto_out_8_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_param = out_xbar_auto_out_8_a_bits_param; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_size = out_xbar_auto_out_8_a_bits_size; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_source = out_xbar_auto_out_8_a_bits_source; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_address = out_xbar_auto_out_8_a_bits_address; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_mask = out_xbar_auto_out_8_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_data = out_xbar_auto_out_8_a_bits_data; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_a_bits_corrupt = out_xbar_auto_out_8_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_in_d_ready = out_xbar_auto_out_8_d_ready; // @[LazyModule.scala 298:16]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_out_a_ready =
+ auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_ready; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_valid =
+ auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_valid; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_opcode =
+ auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_size =
+ auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_source =
+ auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign coupler_to_slave_named_tileresetsetter_auto_buffer_out_d_bits_data =
+ auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_data; // @[LazyModule.scala 311:12]
+ always @(posedge bundleIn_0_clock) begin
+ if (bundleIn_0_reset) begin // @[CustomBootPin.scala 46:28]
+ state <= 3'h0; // @[CustomBootPin.scala 46:28]
+ end else if (3'h0 == state) begin // @[CustomBootPin.scala 50:24]
+ if (custom_boot) begin // @[CustomBootPin.scala 51:46]
+ state <= 3'h1; // @[CustomBootPin.scala 51:54]
+ end
+ end else if (3'h1 == state) begin // @[CustomBootPin.scala 50:24]
+ if (_T_2) begin // @[CustomBootPin.scala 60:30]
+ state <= 3'h2; // @[CustomBootPin.scala 60:38]
+ end
+ end else if (3'h2 == state) begin // @[CustomBootPin.scala 50:24]
+ state <= _GEN_2;
+ end else begin
+ state <= _GEN_17;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ state = _RAND_0[2:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_40(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_17 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire [32:0] _T_26 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_28 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_29 = {1'b0,$signed(_T_28)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_31 = $signed(_T_29) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_32 = $signed(_T_31) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_33 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_36 = $signed(_T_34) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_38 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_39 = {1'b0,$signed(_T_38)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_41 = $signed(_T_39) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_42 = $signed(_T_41) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_43 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_44 = {1'b0,$signed(_T_43)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_46 = $signed(_T_44) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_47 = $signed(_T_46) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_48 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_51 = $signed(_T_49) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_52 = $signed(_T_51) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_53 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_54 = {1'b0,$signed(_T_53)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_56 = $signed(_T_54) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_57 = $signed(_T_56) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_58 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_59 = {1'b0,$signed(_T_58)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_61 = $signed(_T_59) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_62 = $signed(_T_61) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_63 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_66 = $signed(_T_64) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_67 = $signed(_T_66) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_68 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_71 = $signed(_T_69) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_72 = $signed(_T_71) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_73 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_76 = $signed(_T_74) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_77 = $signed(_T_76) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_78 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_79 = {1'b0,$signed(_T_78)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_81 = $signed(_T_79) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_82 = $signed(_T_81) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_191 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_195 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_196 = _T_195 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_204 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_384 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_397 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_416 = _T_17 & _T_32; // @[Parameters.scala 670:56]
+ wire _T_418 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_485 = _T_27 | _T_37 | _T_42 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_77 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_486 = _T_418 & _T_485; // @[Parameters.scala 670:56]
+ wire _T_488 = _T_416 | _T_486; // @[Parameters.scala 672:30]
+ wire _T_498 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_502 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_510 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_577 = _T_27 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_578 = _T_418 & _T_577; // @[Parameters.scala 670:56]
+ wire _T_599 = _T_416 | _T_578; // @[Parameters.scala 672:30]
+ wire _T_601 = _T_17 & _T_599; // @[Monitor.scala 115:71]
+ wire _T_619 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_724 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_725 = io_in_a_bits_mask & _T_724; // @[Monitor.scala 127:31]
+ wire _T_726 = _T_725 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_730 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_738 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_793 = _T_27 | _T_32 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_794 = _T_738 & _T_793; // @[Parameters.scala 670:56]
+ wire _T_816 = _T_17 & _T_794; // @[Monitor.scala 131:74]
+ wire _T_826 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_834 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_930 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_938 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1024 = _T_17 & _T_416; // @[Monitor.scala 147:68]
+ wire _T_1034 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1046 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _T_1050 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1054 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1058 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1062 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1066 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1070 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1081 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1085 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1098 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1118 = _T_1066 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1127 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1144 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1162 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1192 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1193 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1197 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1201 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1209 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1216 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1217 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1221 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1225 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1233 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1237 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_72 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_74 = {{8'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_74 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1243 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1246 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire _T_1250 = ~inflight; // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = _a_first_T & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1254 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1256 = ~_T_1050; // @[Monitor.scala 671:74]
+ wire _T_1257 = io_in_d_valid & d_first_1 & ~_T_1050; // @[Monitor.scala 671:71]
+ wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1050 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_sizes_clr_T_5 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_1256 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1256 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1256 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire _T_1269 = inflight | _T_1243; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1274 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1275 = io_in_d_bits_opcode == _GEN_32 | _T_1274; // @[Monitor.scala 685:77]
+ wire _T_1279 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1286 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1287 = io_in_d_bits_opcode == _GEN_48 | _T_1286; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_76 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1291 = _GEN_76 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1301 = _T_1254 & a_first_1 & io_in_a_valid & _T_1256; // @[Monitor.scala 694:116]
+ wire _T_1303 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set_wo_ready = _GEN_15[0];
+ wire d_clr_wo_ready = _GEN_21[0];
+ wire _T_1310 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [7:0] a_sizes_set = _GEN_20[7:0];
+ wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [7:0] d_sizes_clr = _GEN_24[7:0];
+ wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1319 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _GEN_79 = {{8'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_79 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1345 = io_in_d_valid & d_first_2 & _T_1050; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1050 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1363 = _GEN_76 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
+ wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_191 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_191) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_384 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_384) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_196 & (io_in_a_valid & _T_204 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_204 & ~reset & ~_T_196) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_17 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_17) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_488 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_488) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_510 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_510 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_726 & (io_in_a_valid & _T_619 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_619 & ~reset & ~_T_726) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_826 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_826) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_730 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_730 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_816 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_816) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_930 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_930) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_834 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_834 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1024 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1024) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1034 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_1034) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (io_in_a_valid & _T_938 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_938 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1046 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1046) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1066 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1066) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1193 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1193) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1197 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1197) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1201 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1201) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1209 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1209) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1217 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1217) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1221 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1221) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1225 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1225) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1233 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1237 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1237) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1246 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1246 & ~reset & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1269 & (_T_1257 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_2 & ~_T_1269) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1257 & _T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_1243 & _T_2 & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1279 & (_T_1257 & _T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_1243 & _T_2 & ~_T_1279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1287 & (_T_1257 & ~_T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~_T_1243 & _T_2 & ~_T_1287) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1291 & (_T_1257 & ~_T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~_T_1243 & _T_2 & ~_T_1291) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1303 & (_T_1301 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1301 & _T_2 & ~_T_1303) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1310 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1310) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1319 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1319) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at HellaCache.scala:271:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1363 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1363) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at HellaCache.scala:271:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ address = _RAND_4[31:0];
+ _RAND_5 = {1{`RANDOM}};
+ d_first_counter = _RAND_5[8:0];
+ _RAND_6 = {1{`RANDOM}};
+ opcode_1 = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ param_1 = _RAND_7[1:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[3:0];
+ _RAND_9 = {1{`RANDOM}};
+ sink = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ denied = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_12[3:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight_sizes = _RAND_13[7:0];
+ _RAND_14 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_14[8:0];
+ _RAND_15 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_15[8:0];
+ _RAND_16 = {1{`RANDOM}};
+ watchdog = _RAND_16[31:0];
+ _RAND_17 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[7:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_41(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [31:0] io_in_a_bits_address,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & 32'h3f; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_26 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_27 = $signed(_T_26) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_28 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_29 = {1'b0,$signed(_T_28)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_31 = $signed(_T_29) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_32 = $signed(_T_31) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_33 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_36 = $signed(_T_34) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_38 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_39 = {1'b0,$signed(_T_38)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_41 = $signed(_T_39) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_42 = $signed(_T_41) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_43 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_44 = {1'b0,$signed(_T_43)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_46 = $signed(_T_44) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_47 = $signed(_T_46) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_48 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_51 = $signed(_T_49) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_52 = $signed(_T_51) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_53 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_54 = {1'b0,$signed(_T_53)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_56 = $signed(_T_54) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_57 = $signed(_T_56) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_58 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_59 = {1'b0,$signed(_T_58)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_61 = $signed(_T_59) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_62 = $signed(_T_61) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_63 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_66 = $signed(_T_64) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_67 = $signed(_T_66) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_68 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_71 = $signed(_T_69) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_72 = $signed(_T_71) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_73 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_76 = $signed(_T_74) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_77 = $signed(_T_76) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_78 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_79 = {1'b0,$signed(_T_78)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_81 = $signed(_T_79) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_82 = $signed(_T_81) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_485 = _T_27 | _T_37 | _T_42 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_77 | _T_82; // @[Parameters.scala 671:42]
+ wire _T_488 = _T_32 | _T_485; // @[Parameters.scala 672:30]
+ wire _T_1046 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _T_1050 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1054 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1058 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1062 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1066 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1070 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1081 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1085 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1098 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1118 = _T_1066 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1127 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1144 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1162 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1192 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1209 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1216 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1217 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1221 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1225 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1233 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1237 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{8'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1243 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1246 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? 4'h9 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [4:0] a_sizes_set_interm = a_first_done & a_first_1 ? 5'hd : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire _T_1250 = ~inflight; // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1254 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1256 = ~_T_1050; // @[Monitor.scala 671:74]
+ wire _T_1257 = io_in_d_valid & d_first_1 & ~_T_1050; // @[Monitor.scala 671:71]
+ wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1050 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_sizes_clr_T_5 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [30:0] _GEN_23 = _T_1257 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _T_1257 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire _T_1269 = inflight | _T_1243; // @[Monitor.scala 682:49]
+ wire _T_1275 = _T_1144 | _T_1144; // @[Monitor.scala 685:77]
+ wire _T_1279 = 4'h6 == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1286 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1287 = io_in_d_bits_opcode == _GEN_48 | _T_1286; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_75 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1291 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1301 = _T_1254 & a_first_1 & io_in_a_valid & _T_1256; // @[Monitor.scala 694:116]
+ wire a_set_wo_ready = _GEN_15[0];
+ wire d_clr_wo_ready = _GEN_21[0];
+ wire _T_1310 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire a_set = _GEN_16[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [7:0] a_sizes_set = _GEN_20[7:0];
+ wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [7:0] d_sizes_clr = _GEN_24[7:0];
+ wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1319 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _GEN_78 = {{8'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_78 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1345 = io_in_d_valid & d_first_2 & _T_1050; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_69 = _T_1345 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1363 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
+ wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 9'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (io_in_d_valid & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr_wo_ready; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 9'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | io_in_d_valid) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (io_in_d_valid) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_488 & (io_in_a_valid & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & ~reset & ~_T_488) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Frontend.scala:372:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Frontend.scala:372:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1046 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1046) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1066 & (io_in_d_valid & _T_1050 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1050 & _T_2 & ~_T_1066) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1070 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1070 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1054 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1054) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1081 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1081) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1085 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1085) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1098 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1098 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1127 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1127 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1118 & (io_in_d_valid & _T_1144 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1144 & _T_2 & ~_T_1118) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1058 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1058) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1062 & (io_in_d_valid & _T_1162 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1162 & _T_2 & ~_T_1062) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1209 & (_T_1192 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1192 & ~reset & ~_T_1209) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Frontend.scala:372:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1217 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1217) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1221 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1221) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1225 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1225) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1233 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1233) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1237 & (_T_1216 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1216 & _T_2 & ~_T_1237) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1246 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1246 & ~reset & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Frontend.scala:372:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1269 & (_T_1257 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_2 & ~_T_1269) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1257 & _T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_1243 & _T_2 & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1279 & (_T_1257 & _T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & _T_1243 & _T_2 & ~_T_1279) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1287 & (_T_1257 & ~_T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~_T_1243 & _T_2 & ~_T_1287) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1291 & (_T_1257 & ~_T_1243 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1257 & ~_T_1243 & _T_2 & ~_T_1291) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~io_in_a_ready & (_T_1301 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1301 & _T_2 & ~io_in_a_ready) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1310 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1310) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1319 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1319) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Frontend.scala:372:21)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1363 & (_T_1345 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1345 & _T_2 & ~_T_1363) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Frontend.scala:372:21)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ address = _RAND_1[31:0];
+ _RAND_2 = {1{`RANDOM}};
+ d_first_counter = _RAND_2[8:0];
+ _RAND_3 = {1{`RANDOM}};
+ opcode_1 = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ param_1 = _RAND_4[1:0];
+ _RAND_5 = {1{`RANDOM}};
+ size_1 = _RAND_5[3:0];
+ _RAND_6 = {1{`RANDOM}};
+ sink = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ denied = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ inflight = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_sizes = _RAND_10[7:0];
+ _RAND_11 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_11[8:0];
+ _RAND_12 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_12[8:0];
+ _RAND_13 = {1{`RANDOM}};
+ watchdog = _RAND_13[31:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_14[7:0];
+ _RAND_15 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_15[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLXbar_6(
+ input clock,
+ input reset,
+ output auto_in_1_a_ready,
+ input auto_in_1_a_valid,
+ input [31:0] auto_in_1_a_bits_address,
+ output auto_in_1_d_valid,
+ output [2:0] auto_in_1_d_bits_opcode,
+ output [3:0] auto_in_1_d_bits_size,
+ output [63:0] auto_in_1_d_bits_data,
+ output auto_in_1_d_bits_corrupt,
+ output auto_in_0_a_ready,
+ input auto_in_0_a_valid,
+ input [2:0] auto_in_0_a_bits_opcode,
+ input [2:0] auto_in_0_a_bits_param,
+ input [3:0] auto_in_0_a_bits_size,
+ input [31:0] auto_in_0_a_bits_address,
+ input [7:0] auto_in_0_a_bits_mask,
+ input [63:0] auto_in_0_a_bits_data,
+ input auto_in_0_d_ready,
+ output auto_in_0_d_valid,
+ output [2:0] auto_in_0_d_bits_opcode,
+ output [3:0] auto_in_0_d_bits_size,
+ output auto_in_0_d_bits_denied,
+ output [63:0] auto_in_0_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_clock; // @[Nodes.scala 24:25]
+ wire monitor_1_reset; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire requestDOI_0_1 = ~auto_out_d_bits_source; // @[Parameters.scala 46:9]
+ wire [26:0] _beatsAI_decode_T_1 = 27'hfff << auto_in_0_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] _beatsAI_decode_T_3 = ~_beatsAI_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] beatsAI_decode = _beatsAI_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire beatsAI_opdata = ~auto_in_0_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle = beatsLeft == 9'h0; // @[Arbiter.scala 88:28]
+ wire latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
+ wire [1:0] readys_valid = {auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 31:58]
+ wire _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
+ reg [1:0] readys_mask; // @[Arbiter.scala 23:23]
+ wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
+ wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
+ wire [3:0] readys_filter = {_readys_filter_T_1,auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 31:58]
+ wire [3:0] _GEN_1 = {{1'd0}, readys_filter[3:1]}; // @[package.scala 253:43]
+ wire [3:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
+ wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
+ wire [3:0] _GEN_2 = {{1'd0}, _readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
+ wire [3:0] readys_unready = _GEN_2 | _readys_unready_T_4; // @[Arbiter.scala 25:58]
+ wire [1:0] _readys_readys_T_2 = readys_unready[3:2] & readys_unready[1:0]; // @[Arbiter.scala 26:39]
+ wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
+ wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
+ wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
+ wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[1:0]; // @[package.scala 244:43]
+ wire readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
+ wire readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_0 = readys_0 & auto_in_0_a_valid; // @[Arbiter.scala 97:79]
+ wire earlyWinner_1 = readys_1 & auto_in_1_a_valid; // @[Arbiter.scala 97:79]
+ wire _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
+ wire _T_10 = auto_in_0_a_valid | auto_in_1_a_valid; // @[Arbiter.scala 107:36]
+ wire _T_11 = ~(auto_in_0_a_valid | auto_in_1_a_valid); // @[Arbiter.scala 107:15]
+ reg state_0; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire _out_0_a_earlyValid_T_3 = state_0 & auto_in_0_a_valid | state_1 & auto_in_1_a_valid; // @[Mux.scala 27:73]
+ wire out_2_0_a_earlyValid = idle ? _T_10 : _out_0_a_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_out_a_ready & out_2_0_a_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ wire [8:0] _GEN_3 = {{8'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
+ wire [8:0] _beatsLeft_T_4 = beatsLeft - _GEN_3; // @[Arbiter.scala 113:52]
+ wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
+ wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire [7:0] _T_30 = muxStateEarly_0 ? auto_in_0_a_bits_mask : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _T_31 = muxStateEarly_1 ? 8'hff : 8'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_33 = muxStateEarly_0 ? auto_in_0_a_bits_address : 32'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_34 = muxStateEarly_1 ? auto_in_1_a_bits_address : 32'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_39 = muxStateEarly_0 ? auto_in_0_a_bits_size : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _T_40 = muxStateEarly_1 ? 4'h6 : 4'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_45 = muxStateEarly_0 ? auto_in_0_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_46 = muxStateEarly_1 ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
+ TLMonitor_40 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ TLMonitor_41 monitor_1 ( // @[Nodes.scala 24:25]
+ .clock(monitor_1_clock),
+ .reset(monitor_1_reset),
+ .io_in_a_ready(monitor_1_io_in_a_ready),
+ .io_in_a_valid(monitor_1_io_in_a_valid),
+ .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
+ .io_in_d_valid(monitor_1_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_1_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
+ .io_in_d_bits_sink(monitor_1_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_1_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_1_io_in_d_bits_corrupt)
+ );
+ assign auto_in_1_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign auto_in_1_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
+ assign auto_in_1_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_1_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign auto_in_0_d_valid = auto_out_d_valid & auto_out_d_bits_source; // @[Xbar.scala 179:40]
+ assign auto_in_0_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_0_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = idle ? _T_10 : _out_0_a_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ assign auto_out_a_bits_opcode = _T_45 | _T_46; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_param = muxStateEarly_0 ? auto_in_0_a_bits_param : 3'h0; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_size = _T_39 | _T_40; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_source = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ assign auto_out_a_bits_address = _T_33 | _T_34; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_mask = _T_30 | _T_31; // @[Mux.scala 27:73]
+ assign auto_out_a_bits_data = muxStateEarly_0 ? auto_in_0_a_bits_data : 64'h0; // @[Mux.scala 27:73]
+ assign auto_out_d_ready = auto_out_d_bits_source & auto_in_0_d_ready | requestDOI_0_1; // @[Mux.scala 27:73]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign monitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_out_d_valid & auto_out_d_bits_source; // @[Xbar.scala 179:40]
+ assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_clock = clock;
+ assign monitor_1_reset = reset;
+ assign monitor_1_io_in_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign monitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
+ assign monitor_1_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
+ assign monitor_1_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign monitor_1_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 9'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ if (earlyWinner_0) begin // @[Arbiter.scala 111:73]
+ if (beatsAI_opdata) begin // @[Edges.scala 220:14]
+ beatsLeft <= beatsAI_decode;
+ end else begin
+ beatsLeft <= 9'h0;
+ end
+ end else begin
+ beatsLeft <= 9'h0;
+ end
+ end else begin
+ beatsLeft <= _beatsLeft_T_4;
+ end
+ if (reset) begin // @[Arbiter.scala 23:23]
+ readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
+ end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
+ readys_mask <= _readys_mask_T_3; // @[Arbiter.scala 28:12]
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_0 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_0 <= earlyWinner_0;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~earlyWinner_0 | ~earlyWinner_1) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 105:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
+ ); // @[Arbiter.scala 105:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(auto_in_0_a_valid | auto_in_1_a_valid) | _prefixOR_T) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~(auto_in_0_a_valid | auto_in_1_a_valid) | _prefixOR_T)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_11 | _T_10) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(_T_11 | _T_10)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ beatsLeft = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ readys_mask = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ state_0 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ state_1 = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLXbar_7(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[ReadyValidCancel.scala 21:38]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Xbar.scala 228:69]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[ReadyValidCancel.scala 21:38]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module IntXbar_1(
+ input auto_int_in_2_0,
+ input auto_int_in_1_0,
+ input auto_int_in_1_1,
+ input auto_int_in_0_0,
+ output auto_int_out_0,
+ output auto_int_out_1,
+ output auto_int_out_2,
+ output auto_int_out_3
+);
+ assign auto_int_out_0 = auto_int_in_0_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_1 = auto_int_in_1_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_2 = auto_int_in_1_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_int_out_3 = auto_int_in_2_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module BundleBridgeNexus_4(
+ input auto_in,
+ output auto_out_0
+);
+ assign auto_out_0 = auto_in; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module PMPChecker(
+ input [1:0] io_prv,
+ input io_pmp_0_cfg_l,
+ input [1:0] io_pmp_0_cfg_a,
+ input io_pmp_0_cfg_w,
+ input io_pmp_0_cfg_r,
+ input [29:0] io_pmp_0_addr,
+ input [31:0] io_pmp_0_mask,
+ input io_pmp_1_cfg_l,
+ input [1:0] io_pmp_1_cfg_a,
+ input io_pmp_1_cfg_w,
+ input io_pmp_1_cfg_r,
+ input [29:0] io_pmp_1_addr,
+ input [31:0] io_pmp_1_mask,
+ input io_pmp_2_cfg_l,
+ input [1:0] io_pmp_2_cfg_a,
+ input io_pmp_2_cfg_w,
+ input io_pmp_2_cfg_r,
+ input [29:0] io_pmp_2_addr,
+ input [31:0] io_pmp_2_mask,
+ input io_pmp_3_cfg_l,
+ input [1:0] io_pmp_3_cfg_a,
+ input io_pmp_3_cfg_w,
+ input io_pmp_3_cfg_r,
+ input [29:0] io_pmp_3_addr,
+ input [31:0] io_pmp_3_mask,
+ input io_pmp_4_cfg_l,
+ input [1:0] io_pmp_4_cfg_a,
+ input io_pmp_4_cfg_w,
+ input io_pmp_4_cfg_r,
+ input [29:0] io_pmp_4_addr,
+ input [31:0] io_pmp_4_mask,
+ input io_pmp_5_cfg_l,
+ input [1:0] io_pmp_5_cfg_a,
+ input io_pmp_5_cfg_w,
+ input io_pmp_5_cfg_r,
+ input [29:0] io_pmp_5_addr,
+ input [31:0] io_pmp_5_mask,
+ input io_pmp_6_cfg_l,
+ input [1:0] io_pmp_6_cfg_a,
+ input io_pmp_6_cfg_w,
+ input io_pmp_6_cfg_r,
+ input [29:0] io_pmp_6_addr,
+ input [31:0] io_pmp_6_mask,
+ input io_pmp_7_cfg_l,
+ input [1:0] io_pmp_7_cfg_a,
+ input io_pmp_7_cfg_w,
+ input io_pmp_7_cfg_r,
+ input [29:0] io_pmp_7_addr,
+ input [31:0] io_pmp_7_mask,
+ input [31:0] io_addr,
+ input [1:0] io_size,
+ output io_r,
+ output io_w
+);
+ wire default_ = io_prv > 2'h1; // @[PMP.scala 156:56]
+ wire [5:0] _res_hit_lsbMask_T_1 = 6'h7 << io_size; // @[package.scala 234:77]
+ wire [2:0] _res_hit_lsbMask_T_3 = ~_res_hit_lsbMask_T_1[2:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_0 = {{29'd0}, _res_hit_lsbMask_T_3}; // @[PMP.scala 69:26]
+ wire [31:0] res_hit_lsbMask = io_pmp_7_mask | _GEN_0; // @[PMP.scala 69:26]
+ wire [31:0] _res_hit_msbMatch_T_1 = {io_pmp_7_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_msbMatch_T_3 = _res_hit_msbMatch_T_2 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala 61:27]
+ wire [28:0] _res_hit_msbMatch_T_7 = io_addr[31:3] ^ _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala 64:47]
+ wire [28:0] _res_hit_msbMatch_T_8 = ~io_pmp_7_mask[31:3]; // @[PMP.scala 64:54]
+ wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala 64:52]
+ wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala 64:58]
+ wire [2:0] _res_hit_lsbMatch_T_7 = io_addr[2:0] ^ _res_hit_msbMatch_T_4[2:0]; // @[PMP.scala 64:47]
+ wire [2:0] _res_hit_lsbMatch_T_8 = ~res_hit_lsbMask[2:0]; // @[PMP.scala 64:54]
+ wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala 64:52]
+ wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala 64:58]
+ wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala 72:16]
+ wire [31:0] _res_hit_msbsLess_T_1 = {io_pmp_6_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_msbsLess_T_3 = _res_hit_msbsLess_T_2 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala 61:27]
+ wire res_hit_msbsLess = io_addr[31:3] < _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala 81:39]
+ wire [28:0] _res_hit_msbsEqual_T_6 = io_addr[31:3] ^ _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala 82:41]
+ wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala 82:69]
+ wire [2:0] _res_hit_lsbsLess_T_1 = io_addr[2:0] | _res_hit_lsbMask_T_3; // @[PMP.scala 83:42]
+ wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_msbsLess_T_4[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_8 = res_hit_msbsLess | res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala 84:16]
+ wire _res_hit_T_9 = ~_res_hit_T_8; // @[PMP.scala 89:5]
+ wire res_hit_msbsLess_1 = io_addr[31:3] < _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala 81:39]
+ wire res_hit_msbsEqual_1 = _res_hit_msbMatch_T_7 == 29'h0; // @[PMP.scala 82:69]
+ wire res_hit_lsbsLess_1 = io_addr[2:0] < _res_hit_msbMatch_T_4[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_11 = res_hit_msbsLess_1 | res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala 84:16]
+ wire _res_hit_T_12 = _res_hit_T_9 & _res_hit_T_11; // @[PMP.scala 95:48]
+ wire res_hit = io_pmp_7_cfg_a[1] ? _res_hit_T_1 : io_pmp_7_cfg_a[0] & _res_hit_T_12; // @[PMP.scala 133:8]
+ wire res_ignore = default_ & ~io_pmp_7_cfg_l; // @[PMP.scala 164:26]
+ wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~io_addr[2:0]; // @[PMP.scala 124:125]
+ wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_hit_msbsLess_T_4[2:0] & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala 124:123]
+ wire res_aligned_straddlesLowerBound = res_hit_msbsEqual & _res_aligned_straddlesLowerBound_T_15 != 3'h0; // @[PMP.scala 124:88]
+ wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_hit_msbMatch_T_4[2:0] & _res_hit_lsbsLess_T_1; // @[PMP.scala 125:113]
+ wire res_aligned_straddlesUpperBound = res_hit_msbsEqual_1 & _res_aligned_straddlesUpperBound_T_15 != 3'h0; // @[PMP.scala 125:83]
+ wire res_aligned_rangeAligned = ~(res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound); // @[PMP.scala 126:24]
+ wire [2:0] _res_aligned_pow2Aligned_T_1 = ~io_pmp_7_mask[2:0]; // @[PMP.scala 127:34]
+ wire [2:0] _res_aligned_pow2Aligned_T_2 = _res_hit_lsbMask_T_3 & _res_aligned_pow2Aligned_T_1; // @[PMP.scala 127:32]
+ wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala 127:57]
+ wire res_aligned = io_pmp_7_cfg_a[1] ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala 128:8]
+ wire res_cur_cfg_r = res_aligned & (io_pmp_7_cfg_r | res_ignore); // @[PMP.scala 182:26]
+ wire res_cur_cfg_w = res_aligned & (io_pmp_7_cfg_w | res_ignore); // @[PMP.scala 183:26]
+ wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : default_; // @[PMP.scala 185:8]
+ wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : default_; // @[PMP.scala 185:8]
+ wire [31:0] res_hit_lsbMask_1 = io_pmp_6_mask | _GEN_0; // @[PMP.scala 69:26]
+ wire [28:0] _res_hit_msbMatch_T_18 = ~io_pmp_6_mask[31:3]; // @[PMP.scala 64:54]
+ wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbsEqual_T_6 & _res_hit_msbMatch_T_18; // @[PMP.scala 64:52]
+ wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala 64:58]
+ wire [2:0] _res_hit_lsbMatch_T_17 = io_addr[2:0] ^ _res_hit_msbsLess_T_4[2:0]; // @[PMP.scala 64:47]
+ wire [2:0] _res_hit_lsbMatch_T_18 = ~res_hit_lsbMask_1[2:0]; // @[PMP.scala 64:54]
+ wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala 64:52]
+ wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala 64:58]
+ wire _res_hit_T_15 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala 72:16]
+ wire [31:0] _res_hit_msbsLess_T_13 = {io_pmp_5_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_msbsLess_T_15 = _res_hit_msbsLess_T_14 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala 61:27]
+ wire res_hit_msbsLess_2 = io_addr[31:3] < _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala 81:39]
+ wire [28:0] _res_hit_msbsEqual_T_20 = io_addr[31:3] ^ _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala 82:41]
+ wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala 82:69]
+ wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_1 < _res_hit_msbsLess_T_16[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_22 = res_hit_msbsLess_2 | res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala 84:16]
+ wire _res_hit_T_23 = ~_res_hit_T_22; // @[PMP.scala 89:5]
+ wire res_hit_lsbsLess_3 = io_addr[2:0] < _res_hit_msbsLess_T_4[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_25 = res_hit_msbsLess | res_hit_msbsEqual & res_hit_lsbsLess_3; // @[PMP.scala 84:16]
+ wire _res_hit_T_26 = _res_hit_T_23 & _res_hit_T_25; // @[PMP.scala 95:48]
+ wire res_hit_1 = io_pmp_6_cfg_a[1] ? _res_hit_T_15 : io_pmp_6_cfg_a[0] & _res_hit_T_26; // @[PMP.scala 133:8]
+ wire res_ignore_1 = default_ & ~io_pmp_6_cfg_l; // @[PMP.scala 164:26]
+ wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_hit_msbsLess_T_16[2:0] & _res_aligned_straddlesLowerBound_T_14
+ ; // @[PMP.scala 124:123]
+ wire res_aligned_straddlesLowerBound_1 = res_hit_msbsEqual_2 & _res_aligned_straddlesLowerBound_T_32 != 3'h0; // @[PMP.scala 124:88]
+ wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_hit_msbsLess_T_4[2:0] & _res_hit_lsbsLess_T_1; // @[PMP.scala 125:113]
+ wire res_aligned_straddlesUpperBound_1 = res_hit_msbsEqual & _res_aligned_straddlesUpperBound_T_32 != 3'h0; // @[PMP.scala 125:83]
+ wire res_aligned_rangeAligned_1 = ~(res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1); // @[PMP.scala 126:24]
+ wire [2:0] _res_aligned_pow2Aligned_T_4 = ~io_pmp_6_mask[2:0]; // @[PMP.scala 127:34]
+ wire [2:0] _res_aligned_pow2Aligned_T_5 = _res_hit_lsbMask_T_3 & _res_aligned_pow2Aligned_T_4; // @[PMP.scala 127:32]
+ wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala 127:57]
+ wire res_aligned_1 = io_pmp_6_cfg_a[1] ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala 128:8]
+ wire res_cur_1_cfg_r = res_aligned_1 & (io_pmp_6_cfg_r | res_ignore_1); // @[PMP.scala 182:26]
+ wire res_cur_1_cfg_w = res_aligned_1 & (io_pmp_6_cfg_w | res_ignore_1); // @[PMP.scala 183:26]
+ wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala 185:8]
+ wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala 185:8]
+ wire [31:0] res_hit_lsbMask_2 = io_pmp_5_mask | _GEN_0; // @[PMP.scala 69:26]
+ wire [28:0] _res_hit_msbMatch_T_28 = ~io_pmp_5_mask[31:3]; // @[PMP.scala 64:54]
+ wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbsEqual_T_20 & _res_hit_msbMatch_T_28; // @[PMP.scala 64:52]
+ wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala 64:58]
+ wire [2:0] _res_hit_lsbMatch_T_27 = io_addr[2:0] ^ _res_hit_msbsLess_T_16[2:0]; // @[PMP.scala 64:47]
+ wire [2:0] _res_hit_lsbMatch_T_28 = ~res_hit_lsbMask_2[2:0]; // @[PMP.scala 64:54]
+ wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala 64:52]
+ wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala 64:58]
+ wire _res_hit_T_29 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala 72:16]
+ wire [31:0] _res_hit_msbsLess_T_25 = {io_pmp_4_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_msbsLess_T_27 = _res_hit_msbsLess_T_26 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala 61:27]
+ wire res_hit_msbsLess_4 = io_addr[31:3] < _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala 81:39]
+ wire [28:0] _res_hit_msbsEqual_T_34 = io_addr[31:3] ^ _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala 82:41]
+ wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala 82:69]
+ wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_1 < _res_hit_msbsLess_T_28[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_36 = res_hit_msbsLess_4 | res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala 84:16]
+ wire _res_hit_T_37 = ~_res_hit_T_36; // @[PMP.scala 89:5]
+ wire res_hit_lsbsLess_5 = io_addr[2:0] < _res_hit_msbsLess_T_16[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_39 = res_hit_msbsLess_2 | res_hit_msbsEqual_2 & res_hit_lsbsLess_5; // @[PMP.scala 84:16]
+ wire _res_hit_T_40 = _res_hit_T_37 & _res_hit_T_39; // @[PMP.scala 95:48]
+ wire res_hit_2 = io_pmp_5_cfg_a[1] ? _res_hit_T_29 : io_pmp_5_cfg_a[0] & _res_hit_T_40; // @[PMP.scala 133:8]
+ wire res_ignore_2 = default_ & ~io_pmp_5_cfg_l; // @[PMP.scala 164:26]
+ wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_hit_msbsLess_T_28[2:0] & _res_aligned_straddlesLowerBound_T_14
+ ; // @[PMP.scala 124:123]
+ wire res_aligned_straddlesLowerBound_2 = res_hit_msbsEqual_4 & _res_aligned_straddlesLowerBound_T_49 != 3'h0; // @[PMP.scala 124:88]
+ wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_hit_msbsLess_T_16[2:0] & _res_hit_lsbsLess_T_1; // @[PMP.scala 125:113]
+ wire res_aligned_straddlesUpperBound_2 = res_hit_msbsEqual_2 & _res_aligned_straddlesUpperBound_T_49 != 3'h0; // @[PMP.scala 125:83]
+ wire res_aligned_rangeAligned_2 = ~(res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2); // @[PMP.scala 126:24]
+ wire [2:0] _res_aligned_pow2Aligned_T_7 = ~io_pmp_5_mask[2:0]; // @[PMP.scala 127:34]
+ wire [2:0] _res_aligned_pow2Aligned_T_8 = _res_hit_lsbMask_T_3 & _res_aligned_pow2Aligned_T_7; // @[PMP.scala 127:32]
+ wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala 127:57]
+ wire res_aligned_2 = io_pmp_5_cfg_a[1] ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala 128:8]
+ wire res_cur_2_cfg_r = res_aligned_2 & (io_pmp_5_cfg_r | res_ignore_2); // @[PMP.scala 182:26]
+ wire res_cur_2_cfg_w = res_aligned_2 & (io_pmp_5_cfg_w | res_ignore_2); // @[PMP.scala 183:26]
+ wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala 185:8]
+ wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala 185:8]
+ wire [31:0] res_hit_lsbMask_3 = io_pmp_4_mask | _GEN_0; // @[PMP.scala 69:26]
+ wire [28:0] _res_hit_msbMatch_T_38 = ~io_pmp_4_mask[31:3]; // @[PMP.scala 64:54]
+ wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbsEqual_T_34 & _res_hit_msbMatch_T_38; // @[PMP.scala 64:52]
+ wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala 64:58]
+ wire [2:0] _res_hit_lsbMatch_T_37 = io_addr[2:0] ^ _res_hit_msbsLess_T_28[2:0]; // @[PMP.scala 64:47]
+ wire [2:0] _res_hit_lsbMatch_T_38 = ~res_hit_lsbMask_3[2:0]; // @[PMP.scala 64:54]
+ wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala 64:52]
+ wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala 64:58]
+ wire _res_hit_T_43 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala 72:16]
+ wire [31:0] _res_hit_msbsLess_T_37 = {io_pmp_3_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_msbsLess_T_39 = _res_hit_msbsLess_T_38 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala 61:27]
+ wire res_hit_msbsLess_6 = io_addr[31:3] < _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala 81:39]
+ wire [28:0] _res_hit_msbsEqual_T_48 = io_addr[31:3] ^ _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala 82:41]
+ wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala 82:69]
+ wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_1 < _res_hit_msbsLess_T_40[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_50 = res_hit_msbsLess_6 | res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala 84:16]
+ wire _res_hit_T_51 = ~_res_hit_T_50; // @[PMP.scala 89:5]
+ wire res_hit_lsbsLess_7 = io_addr[2:0] < _res_hit_msbsLess_T_28[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_53 = res_hit_msbsLess_4 | res_hit_msbsEqual_4 & res_hit_lsbsLess_7; // @[PMP.scala 84:16]
+ wire _res_hit_T_54 = _res_hit_T_51 & _res_hit_T_53; // @[PMP.scala 95:48]
+ wire res_hit_3 = io_pmp_4_cfg_a[1] ? _res_hit_T_43 : io_pmp_4_cfg_a[0] & _res_hit_T_54; // @[PMP.scala 133:8]
+ wire res_ignore_3 = default_ & ~io_pmp_4_cfg_l; // @[PMP.scala 164:26]
+ wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_hit_msbsLess_T_40[2:0] & _res_aligned_straddlesLowerBound_T_14
+ ; // @[PMP.scala 124:123]
+ wire res_aligned_straddlesLowerBound_3 = res_hit_msbsEqual_6 & _res_aligned_straddlesLowerBound_T_66 != 3'h0; // @[PMP.scala 124:88]
+ wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_hit_msbsLess_T_28[2:0] & _res_hit_lsbsLess_T_1; // @[PMP.scala 125:113]
+ wire res_aligned_straddlesUpperBound_3 = res_hit_msbsEqual_4 & _res_aligned_straddlesUpperBound_T_66 != 3'h0; // @[PMP.scala 125:83]
+ wire res_aligned_rangeAligned_3 = ~(res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3); // @[PMP.scala 126:24]
+ wire [2:0] _res_aligned_pow2Aligned_T_10 = ~io_pmp_4_mask[2:0]; // @[PMP.scala 127:34]
+ wire [2:0] _res_aligned_pow2Aligned_T_11 = _res_hit_lsbMask_T_3 & _res_aligned_pow2Aligned_T_10; // @[PMP.scala 127:32]
+ wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala 127:57]
+ wire res_aligned_3 = io_pmp_4_cfg_a[1] ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala 128:8]
+ wire res_cur_3_cfg_r = res_aligned_3 & (io_pmp_4_cfg_r | res_ignore_3); // @[PMP.scala 182:26]
+ wire res_cur_3_cfg_w = res_aligned_3 & (io_pmp_4_cfg_w | res_ignore_3); // @[PMP.scala 183:26]
+ wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala 185:8]
+ wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala 185:8]
+ wire [31:0] res_hit_lsbMask_4 = io_pmp_3_mask | _GEN_0; // @[PMP.scala 69:26]
+ wire [28:0] _res_hit_msbMatch_T_48 = ~io_pmp_3_mask[31:3]; // @[PMP.scala 64:54]
+ wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbsEqual_T_48 & _res_hit_msbMatch_T_48; // @[PMP.scala 64:52]
+ wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala 64:58]
+ wire [2:0] _res_hit_lsbMatch_T_47 = io_addr[2:0] ^ _res_hit_msbsLess_T_40[2:0]; // @[PMP.scala 64:47]
+ wire [2:0] _res_hit_lsbMatch_T_48 = ~res_hit_lsbMask_4[2:0]; // @[PMP.scala 64:54]
+ wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala 64:52]
+ wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala 64:58]
+ wire _res_hit_T_57 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala 72:16]
+ wire [31:0] _res_hit_msbsLess_T_49 = {io_pmp_2_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_msbsLess_T_51 = _res_hit_msbsLess_T_50 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala 61:27]
+ wire res_hit_msbsLess_8 = io_addr[31:3] < _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala 81:39]
+ wire [28:0] _res_hit_msbsEqual_T_62 = io_addr[31:3] ^ _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala 82:41]
+ wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala 82:69]
+ wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_1 < _res_hit_msbsLess_T_52[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_64 = res_hit_msbsLess_8 | res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala 84:16]
+ wire _res_hit_T_65 = ~_res_hit_T_64; // @[PMP.scala 89:5]
+ wire res_hit_lsbsLess_9 = io_addr[2:0] < _res_hit_msbsLess_T_40[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_67 = res_hit_msbsLess_6 | res_hit_msbsEqual_6 & res_hit_lsbsLess_9; // @[PMP.scala 84:16]
+ wire _res_hit_T_68 = _res_hit_T_65 & _res_hit_T_67; // @[PMP.scala 95:48]
+ wire res_hit_4 = io_pmp_3_cfg_a[1] ? _res_hit_T_57 : io_pmp_3_cfg_a[0] & _res_hit_T_68; // @[PMP.scala 133:8]
+ wire res_ignore_4 = default_ & ~io_pmp_3_cfg_l; // @[PMP.scala 164:26]
+ wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_hit_msbsLess_T_52[2:0] & _res_aligned_straddlesLowerBound_T_14
+ ; // @[PMP.scala 124:123]
+ wire res_aligned_straddlesLowerBound_4 = res_hit_msbsEqual_8 & _res_aligned_straddlesLowerBound_T_83 != 3'h0; // @[PMP.scala 124:88]
+ wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_hit_msbsLess_T_40[2:0] & _res_hit_lsbsLess_T_1; // @[PMP.scala 125:113]
+ wire res_aligned_straddlesUpperBound_4 = res_hit_msbsEqual_6 & _res_aligned_straddlesUpperBound_T_83 != 3'h0; // @[PMP.scala 125:83]
+ wire res_aligned_rangeAligned_4 = ~(res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4); // @[PMP.scala 126:24]
+ wire [2:0] _res_aligned_pow2Aligned_T_13 = ~io_pmp_3_mask[2:0]; // @[PMP.scala 127:34]
+ wire [2:0] _res_aligned_pow2Aligned_T_14 = _res_hit_lsbMask_T_3 & _res_aligned_pow2Aligned_T_13; // @[PMP.scala 127:32]
+ wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala 127:57]
+ wire res_aligned_4 = io_pmp_3_cfg_a[1] ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala 128:8]
+ wire res_cur_4_cfg_r = res_aligned_4 & (io_pmp_3_cfg_r | res_ignore_4); // @[PMP.scala 182:26]
+ wire res_cur_4_cfg_w = res_aligned_4 & (io_pmp_3_cfg_w | res_ignore_4); // @[PMP.scala 183:26]
+ wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala 185:8]
+ wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala 185:8]
+ wire [31:0] res_hit_lsbMask_5 = io_pmp_2_mask | _GEN_0; // @[PMP.scala 69:26]
+ wire [28:0] _res_hit_msbMatch_T_58 = ~io_pmp_2_mask[31:3]; // @[PMP.scala 64:54]
+ wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbsEqual_T_62 & _res_hit_msbMatch_T_58; // @[PMP.scala 64:52]
+ wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala 64:58]
+ wire [2:0] _res_hit_lsbMatch_T_57 = io_addr[2:0] ^ _res_hit_msbsLess_T_52[2:0]; // @[PMP.scala 64:47]
+ wire [2:0] _res_hit_lsbMatch_T_58 = ~res_hit_lsbMask_5[2:0]; // @[PMP.scala 64:54]
+ wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala 64:52]
+ wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala 64:58]
+ wire _res_hit_T_71 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala 72:16]
+ wire [31:0] _res_hit_msbsLess_T_61 = {io_pmp_1_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_msbsLess_T_63 = _res_hit_msbsLess_T_62 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala 61:27]
+ wire res_hit_msbsLess_10 = io_addr[31:3] < _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala 81:39]
+ wire [28:0] _res_hit_msbsEqual_T_76 = io_addr[31:3] ^ _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala 82:41]
+ wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala 82:69]
+ wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_1 < _res_hit_msbsLess_T_64[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_78 = res_hit_msbsLess_10 | res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala 84:16]
+ wire _res_hit_T_79 = ~_res_hit_T_78; // @[PMP.scala 89:5]
+ wire res_hit_lsbsLess_11 = io_addr[2:0] < _res_hit_msbsLess_T_52[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_81 = res_hit_msbsLess_8 | res_hit_msbsEqual_8 & res_hit_lsbsLess_11; // @[PMP.scala 84:16]
+ wire _res_hit_T_82 = _res_hit_T_79 & _res_hit_T_81; // @[PMP.scala 95:48]
+ wire res_hit_5 = io_pmp_2_cfg_a[1] ? _res_hit_T_71 : io_pmp_2_cfg_a[0] & _res_hit_T_82; // @[PMP.scala 133:8]
+ wire res_ignore_5 = default_ & ~io_pmp_2_cfg_l; // @[PMP.scala 164:26]
+ wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_hit_msbsLess_T_64[2:0] &
+ _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala 124:123]
+ wire res_aligned_straddlesLowerBound_5 = res_hit_msbsEqual_10 & _res_aligned_straddlesLowerBound_T_100 != 3'h0; // @[PMP.scala 124:88]
+ wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_hit_msbsLess_T_52[2:0] & _res_hit_lsbsLess_T_1; // @[PMP.scala 125:113]
+ wire res_aligned_straddlesUpperBound_5 = res_hit_msbsEqual_8 & _res_aligned_straddlesUpperBound_T_100 != 3'h0; // @[PMP.scala 125:83]
+ wire res_aligned_rangeAligned_5 = ~(res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5); // @[PMP.scala 126:24]
+ wire [2:0] _res_aligned_pow2Aligned_T_16 = ~io_pmp_2_mask[2:0]; // @[PMP.scala 127:34]
+ wire [2:0] _res_aligned_pow2Aligned_T_17 = _res_hit_lsbMask_T_3 & _res_aligned_pow2Aligned_T_16; // @[PMP.scala 127:32]
+ wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala 127:57]
+ wire res_aligned_5 = io_pmp_2_cfg_a[1] ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala 128:8]
+ wire res_cur_5_cfg_r = res_aligned_5 & (io_pmp_2_cfg_r | res_ignore_5); // @[PMP.scala 182:26]
+ wire res_cur_5_cfg_w = res_aligned_5 & (io_pmp_2_cfg_w | res_ignore_5); // @[PMP.scala 183:26]
+ wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala 185:8]
+ wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala 185:8]
+ wire [31:0] res_hit_lsbMask_6 = io_pmp_1_mask | _GEN_0; // @[PMP.scala 69:26]
+ wire [28:0] _res_hit_msbMatch_T_68 = ~io_pmp_1_mask[31:3]; // @[PMP.scala 64:54]
+ wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbsEqual_T_76 & _res_hit_msbMatch_T_68; // @[PMP.scala 64:52]
+ wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala 64:58]
+ wire [2:0] _res_hit_lsbMatch_T_67 = io_addr[2:0] ^ _res_hit_msbsLess_T_64[2:0]; // @[PMP.scala 64:47]
+ wire [2:0] _res_hit_lsbMatch_T_68 = ~res_hit_lsbMask_6[2:0]; // @[PMP.scala 64:54]
+ wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala 64:52]
+ wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala 64:58]
+ wire _res_hit_T_85 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala 72:16]
+ wire [31:0] _res_hit_msbsLess_T_73 = {io_pmp_0_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_msbsLess_T_75 = _res_hit_msbsLess_T_74 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala 61:27]
+ wire res_hit_msbsLess_12 = io_addr[31:3] < _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala 81:39]
+ wire [28:0] _res_hit_msbsEqual_T_90 = io_addr[31:3] ^ _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala 82:41]
+ wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala 82:69]
+ wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_1 < _res_hit_msbsLess_T_76[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_92 = res_hit_msbsLess_12 | res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala 84:16]
+ wire _res_hit_T_93 = ~_res_hit_T_92; // @[PMP.scala 89:5]
+ wire res_hit_lsbsLess_13 = io_addr[2:0] < _res_hit_msbsLess_T_64[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_95 = res_hit_msbsLess_10 | res_hit_msbsEqual_10 & res_hit_lsbsLess_13; // @[PMP.scala 84:16]
+ wire _res_hit_T_96 = _res_hit_T_93 & _res_hit_T_95; // @[PMP.scala 95:48]
+ wire res_hit_6 = io_pmp_1_cfg_a[1] ? _res_hit_T_85 : io_pmp_1_cfg_a[0] & _res_hit_T_96; // @[PMP.scala 133:8]
+ wire res_ignore_6 = default_ & ~io_pmp_1_cfg_l; // @[PMP.scala 164:26]
+ wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_hit_msbsLess_T_76[2:0] &
+ _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala 124:123]
+ wire res_aligned_straddlesLowerBound_6 = res_hit_msbsEqual_12 & _res_aligned_straddlesLowerBound_T_117 != 3'h0; // @[PMP.scala 124:88]
+ wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_hit_msbsLess_T_64[2:0] & _res_hit_lsbsLess_T_1; // @[PMP.scala 125:113]
+ wire res_aligned_straddlesUpperBound_6 = res_hit_msbsEqual_10 & _res_aligned_straddlesUpperBound_T_117 != 3'h0; // @[PMP.scala 125:83]
+ wire res_aligned_rangeAligned_6 = ~(res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6); // @[PMP.scala 126:24]
+ wire [2:0] _res_aligned_pow2Aligned_T_19 = ~io_pmp_1_mask[2:0]; // @[PMP.scala 127:34]
+ wire [2:0] _res_aligned_pow2Aligned_T_20 = _res_hit_lsbMask_T_3 & _res_aligned_pow2Aligned_T_19; // @[PMP.scala 127:32]
+ wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala 127:57]
+ wire res_aligned_6 = io_pmp_1_cfg_a[1] ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala 128:8]
+ wire res_cur_6_cfg_r = res_aligned_6 & (io_pmp_1_cfg_r | res_ignore_6); // @[PMP.scala 182:26]
+ wire res_cur_6_cfg_w = res_aligned_6 & (io_pmp_1_cfg_w | res_ignore_6); // @[PMP.scala 183:26]
+ wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala 185:8]
+ wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala 185:8]
+ wire [31:0] res_hit_lsbMask_7 = io_pmp_0_mask | _GEN_0; // @[PMP.scala 69:26]
+ wire [28:0] _res_hit_msbMatch_T_78 = ~io_pmp_0_mask[31:3]; // @[PMP.scala 64:54]
+ wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbsEqual_T_90 & _res_hit_msbMatch_T_78; // @[PMP.scala 64:52]
+ wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala 64:58]
+ wire [2:0] _res_hit_lsbMatch_T_77 = io_addr[2:0] ^ _res_hit_msbsLess_T_76[2:0]; // @[PMP.scala 64:47]
+ wire [2:0] _res_hit_lsbMatch_T_78 = ~res_hit_lsbMask_7[2:0]; // @[PMP.scala 64:54]
+ wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala 64:52]
+ wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala 64:58]
+ wire _res_hit_T_99 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala 72:16]
+ wire res_hit_lsbsLess_15 = io_addr[2:0] < _res_hit_msbsLess_T_76[2:0]; // @[PMP.scala 83:53]
+ wire _res_hit_T_109 = res_hit_msbsLess_12 | res_hit_msbsEqual_12 & res_hit_lsbsLess_15; // @[PMP.scala 84:16]
+ wire res_hit_7 = io_pmp_0_cfg_a[1] ? _res_hit_T_99 : io_pmp_0_cfg_a[0] & _res_hit_T_109; // @[PMP.scala 133:8]
+ wire res_ignore_7 = default_ & ~io_pmp_0_cfg_l; // @[PMP.scala 164:26]
+ wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_hit_msbsLess_T_76[2:0] & _res_hit_lsbsLess_T_1; // @[PMP.scala 125:113]
+ wire res_aligned_straddlesUpperBound_7 = res_hit_msbsEqual_12 & _res_aligned_straddlesUpperBound_T_134 != 3'h0; // @[PMP.scala 125:83]
+ wire res_aligned_rangeAligned_7 = ~res_aligned_straddlesUpperBound_7; // @[PMP.scala 126:24]
+ wire [2:0] _res_aligned_pow2Aligned_T_22 = ~io_pmp_0_mask[2:0]; // @[PMP.scala 127:34]
+ wire [2:0] _res_aligned_pow2Aligned_T_23 = _res_hit_lsbMask_T_3 & _res_aligned_pow2Aligned_T_22; // @[PMP.scala 127:32]
+ wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala 127:57]
+ wire res_aligned_7 = io_pmp_0_cfg_a[1] ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala 128:8]
+ wire res_cur_7_cfg_r = res_aligned_7 & (io_pmp_0_cfg_r | res_ignore_7); // @[PMP.scala 182:26]
+ wire res_cur_7_cfg_w = res_aligned_7 & (io_pmp_0_cfg_w | res_ignore_7); // @[PMP.scala 183:26]
+ assign io_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala 185:8]
+ assign io_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala 185:8]
+endmodule
+module TLB(
+ input io_req_valid,
+ input [33:0] io_req_bits_vaddr,
+ input [1:0] io_req_bits_size,
+ input [4:0] io_req_bits_cmd,
+ input [1:0] io_req_bits_prv,
+ output [31:0] io_resp_paddr,
+ output io_resp_pf_ld,
+ output io_resp_pf_st,
+ output io_resp_ae_ld,
+ output io_resp_ae_st,
+ output io_resp_ma_ld,
+ output io_resp_ma_st,
+ input io_ptw_status_debug,
+ input io_ptw_pmp_0_cfg_l,
+ input [1:0] io_ptw_pmp_0_cfg_a,
+ input io_ptw_pmp_0_cfg_w,
+ input io_ptw_pmp_0_cfg_r,
+ input [29:0] io_ptw_pmp_0_addr,
+ input [31:0] io_ptw_pmp_0_mask,
+ input io_ptw_pmp_1_cfg_l,
+ input [1:0] io_ptw_pmp_1_cfg_a,
+ input io_ptw_pmp_1_cfg_w,
+ input io_ptw_pmp_1_cfg_r,
+ input [29:0] io_ptw_pmp_1_addr,
+ input [31:0] io_ptw_pmp_1_mask,
+ input io_ptw_pmp_2_cfg_l,
+ input [1:0] io_ptw_pmp_2_cfg_a,
+ input io_ptw_pmp_2_cfg_w,
+ input io_ptw_pmp_2_cfg_r,
+ input [29:0] io_ptw_pmp_2_addr,
+ input [31:0] io_ptw_pmp_2_mask,
+ input io_ptw_pmp_3_cfg_l,
+ input [1:0] io_ptw_pmp_3_cfg_a,
+ input io_ptw_pmp_3_cfg_w,
+ input io_ptw_pmp_3_cfg_r,
+ input [29:0] io_ptw_pmp_3_addr,
+ input [31:0] io_ptw_pmp_3_mask,
+ input io_ptw_pmp_4_cfg_l,
+ input [1:0] io_ptw_pmp_4_cfg_a,
+ input io_ptw_pmp_4_cfg_w,
+ input io_ptw_pmp_4_cfg_r,
+ input [29:0] io_ptw_pmp_4_addr,
+ input [31:0] io_ptw_pmp_4_mask,
+ input io_ptw_pmp_5_cfg_l,
+ input [1:0] io_ptw_pmp_5_cfg_a,
+ input io_ptw_pmp_5_cfg_w,
+ input io_ptw_pmp_5_cfg_r,
+ input [29:0] io_ptw_pmp_5_addr,
+ input [31:0] io_ptw_pmp_5_mask,
+ input io_ptw_pmp_6_cfg_l,
+ input [1:0] io_ptw_pmp_6_cfg_a,
+ input io_ptw_pmp_6_cfg_w,
+ input io_ptw_pmp_6_cfg_r,
+ input [29:0] io_ptw_pmp_6_addr,
+ input [31:0] io_ptw_pmp_6_mask,
+ input io_ptw_pmp_7_cfg_l,
+ input [1:0] io_ptw_pmp_7_cfg_a,
+ input io_ptw_pmp_7_cfg_w,
+ input io_ptw_pmp_7_cfg_r,
+ input [29:0] io_ptw_pmp_7_addr,
+ input [31:0] io_ptw_pmp_7_mask
+);
+ wire [1:0] pmp_io_prv; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_0_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_0_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_0_cfg_w; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_0_cfg_r; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_0_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_0_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_1_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_1_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_1_cfg_w; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_1_cfg_r; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_1_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_1_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_2_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_2_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_2_cfg_w; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_2_cfg_r; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_2_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_2_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_3_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_3_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_3_cfg_w; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_3_cfg_r; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_3_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_3_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_4_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_4_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_4_cfg_w; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_4_cfg_r; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_4_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_4_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_5_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_5_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_5_cfg_w; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_5_cfg_r; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_5_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_5_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_6_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_6_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_6_cfg_w; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_6_cfg_r; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_6_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_6_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_7_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_7_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_7_cfg_w; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_7_cfg_r; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_7_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_7_mask; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_addr; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_size; // @[TLB.scala 233:19]
+ wire pmp_io_r; // @[TLB.scala 233:19]
+ wire pmp_io_w; // @[TLB.scala 233:19]
+ wire [20:0] vpn = io_req_bits_vaddr[32:12]; // @[TLB.scala 187:30]
+ wire [21:0] mpu_ppn = io_req_bits_vaddr[33:12]; // @[TLB.scala 230:144]
+ wire [33:0] mpu_physaddr = {mpu_ppn,io_req_bits_vaddr[11:0]}; // @[Cat.scala 31:58]
+ wire [2:0] mpu_priv = {io_ptw_status_debug,io_req_bits_prv}; // @[Cat.scala 31:58]
+ wire [33:0] _legal_address_T = mpu_physaddr ^ 34'h3000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_1 = {1'b0,$signed(_legal_address_T)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_3 = $signed(_legal_address_T_1) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_4 = $signed(_legal_address_T_3) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_5 = mpu_physaddr ^ 34'h4000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_6 = {1'b0,$signed(_legal_address_T_5)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_8 = $signed(_legal_address_T_6) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_9 = $signed(_legal_address_T_8) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_10 = mpu_physaddr ^ 34'h10000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_11 = {1'b0,$signed(_legal_address_T_10)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_13 = $signed(_legal_address_T_11) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_14 = $signed(_legal_address_T_13) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_15 = mpu_physaddr ^ 34'h20000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_16 = {1'b0,$signed(_legal_address_T_15)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_18 = $signed(_legal_address_T_16) & -35'sh10000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_19 = $signed(_legal_address_T_18) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_20 = mpu_physaddr ^ 34'h10010000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_21 = {1'b0,$signed(_legal_address_T_20)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_23 = $signed(_legal_address_T_21) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_24 = $signed(_legal_address_T_23) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_25 = mpu_physaddr ^ 34'h10011000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_26 = {1'b0,$signed(_legal_address_T_25)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_28 = $signed(_legal_address_T_26) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_29 = $signed(_legal_address_T_28) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_30 = mpu_physaddr ^ 34'h10012000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_31 = {1'b0,$signed(_legal_address_T_30)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_33 = $signed(_legal_address_T_31) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_34 = $signed(_legal_address_T_33) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_35 = mpu_physaddr ^ 34'h10013000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_36 = {1'b0,$signed(_legal_address_T_35)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_38 = $signed(_legal_address_T_36) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_39 = $signed(_legal_address_T_38) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_40 = mpu_physaddr ^ 34'h20000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_41 = {1'b0,$signed(_legal_address_T_40)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_43 = $signed(_legal_address_T_41) & -35'sh10000000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_44 = $signed(_legal_address_T_43) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_45 = mpu_physaddr ^ 34'h10014000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_46 = {1'b0,$signed(_legal_address_T_45)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_48 = $signed(_legal_address_T_46) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_49 = $signed(_legal_address_T_48) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_50 = mpu_physaddr ^ 34'h30000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_51 = {1'b0,$signed(_legal_address_T_50)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_53 = $signed(_legal_address_T_51) & -35'sh10000000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_54 = $signed(_legal_address_T_53) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_55 = mpu_physaddr ^ 34'hc000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_56 = {1'b0,$signed(_legal_address_T_55)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_58 = $signed(_legal_address_T_56) & -35'sh4000000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_59 = $signed(_legal_address_T_58) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_60 = mpu_physaddr ^ 34'h2000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_61 = {1'b0,$signed(_legal_address_T_60)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_63 = $signed(_legal_address_T_61) & -35'sh10000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_64 = $signed(_legal_address_T_63) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _legal_address_T_66 = {1'b0,$signed(mpu_physaddr)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_68 = $signed(_legal_address_T_66) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_69 = $signed(_legal_address_T_68) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_70 = mpu_physaddr ^ 34'h80000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_71 = {1'b0,$signed(_legal_address_T_70)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_73 = $signed(_legal_address_T_71) & -35'sh4000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_74 = $signed(_legal_address_T_73) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_75 = mpu_physaddr ^ 34'h10000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_76 = {1'b0,$signed(_legal_address_T_75)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_78 = $signed(_legal_address_T_76) & -35'sh10000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_79 = $signed(_legal_address_T_78) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_80 = mpu_physaddr ^ 34'h100000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_81 = {1'b0,$signed(_legal_address_T_80)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_83 = $signed(_legal_address_T_81) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_84 = $signed(_legal_address_T_83) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_85 = mpu_physaddr ^ 34'h110000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_86 = {1'b0,$signed(_legal_address_T_85)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_88 = $signed(_legal_address_T_86) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_89 = $signed(_legal_address_T_88) == 35'sh0; // @[Parameters.scala 137:67]
+ wire legal_address = _legal_address_T_4 | _legal_address_T_9 | _legal_address_T_14 | _legal_address_T_19 |
+ _legal_address_T_24 | _legal_address_T_29 | _legal_address_T_34 | _legal_address_T_39 | _legal_address_T_44 |
+ _legal_address_T_49 | _legal_address_T_54 | _legal_address_T_59 | _legal_address_T_64 | _legal_address_T_69 |
+ _legal_address_T_74 | _legal_address_T_79 | _legal_address_T_84 | _legal_address_T_89; // @[TLB.scala 238:67]
+ wire deny_access_to_debug = mpu_priv <= 3'h3 & _legal_address_T_69; // @[TLB.scala 243:48]
+ wire _prot_r_T_6 = ~deny_access_to_debug; // @[TLB.scala 244:44]
+ wire prot_r = legal_address & ~deny_access_to_debug & pmp_io_r; // @[TLB.scala 244:66]
+ wire [34:0] _prot_w_T_3 = $signed(_legal_address_T_66) & 35'sh38130000; // @[Parameters.scala 137:52]
+ wire _prot_w_T_4 = $signed(_prot_w_T_3) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _prot_w_T_8 = $signed(_legal_address_T_81) & 35'shb8120000; // @[Parameters.scala 137:52]
+ wire _prot_w_T_9 = $signed(_prot_w_T_8) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _prot_w_T_10 = mpu_physaddr ^ 34'h8000000; // @[Parameters.scala 137:31]
+ wire [34:0] _prot_w_T_11 = {1'b0,$signed(_prot_w_T_10)}; // @[Parameters.scala 137:49]
+ wire [34:0] _prot_w_T_13 = $signed(_prot_w_T_11) & 35'shb8000000; // @[Parameters.scala 137:52]
+ wire _prot_w_T_14 = $signed(_prot_w_T_13) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _prot_w_T_18 = $signed(_legal_address_T_11) & 35'shb8120000; // @[Parameters.scala 137:52]
+ wire _prot_w_T_19 = $signed(_prot_w_T_18) == 35'sh0; // @[Parameters.scala 137:67]
+ wire _prot_w_T_22 = _prot_w_T_4 | _prot_w_T_9 | _prot_w_T_14 | _prot_w_T_19; // @[Parameters.scala 615:89]
+ wire _prot_w_T_43 = legal_address & _prot_w_T_22; // @[TLB.scala 240:19]
+ wire prot_w = _prot_w_T_43 & _prot_r_T_6 & pmp_io_w; // @[TLB.scala 245:70]
+ wire [34:0] _prot_x_T_42 = $signed(_legal_address_T_61) & 35'shba130000; // @[Parameters.scala 137:52]
+ wire _prot_x_T_43 = $signed(_prot_x_T_42) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _prot_eff_T_38 = $signed(_legal_address_T_66) & 35'shba132000; // @[Parameters.scala 137:52]
+ wire _prot_eff_T_39 = $signed(_prot_eff_T_38) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _prot_eff_T_43 = $signed(_legal_address_T_81) & 35'shba122000; // @[Parameters.scala 137:52]
+ wire _prot_eff_T_44 = $signed(_prot_eff_T_43) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _prot_eff_T_58 = $signed(_legal_address_T_21) & 35'shba130000; // @[Parameters.scala 137:52]
+ wire _prot_eff_T_59 = $signed(_prot_eff_T_58) == 35'sh0; // @[Parameters.scala 137:67]
+ wire _prot_eff_T_63 = _prot_eff_T_39 | _prot_eff_T_44 | _prot_x_T_43 | _prot_w_T_14 | _prot_eff_T_59; // @[Parameters.scala 615:89]
+ wire prot_eff = legal_address & _prot_eff_T_63; // @[TLB.scala 240:19]
+ wire [19:0] ppn = vpn[19:0]; // @[TLB.scala 310:125]
+ wire [1:0] _pr_array_T_1 = prot_r ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
+ wire [6:0] pr_array = {_pr_array_T_1,5'h0}; // @[Cat.scala 31:58]
+ wire [1:0] _pw_array_T_1 = prot_w ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
+ wire [6:0] pw_array = {_pw_array_T_1,5'h0}; // @[Cat.scala 31:58]
+ wire [1:0] _eff_array_T_1 = prot_eff ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
+ wire [6:0] eff_array = {_eff_array_T_1,5'h0}; // @[Cat.scala 31:58]
+ wire [1:0] _ppp_array_T_1 = _prot_w_T_43 ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
+ wire [6:0] ppp_array = {_ppp_array_T_1,5'h0}; // @[Cat.scala 31:58]
+ wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size; // @[OneHot.scala 57:35]
+ wire [3:0] _misaligned_T_2 = _misaligned_T - 4'h1; // @[TLB.scala 341:69]
+ wire [33:0] _GEN_144 = {{30'd0}, _misaligned_T_2}; // @[TLB.scala 341:39]
+ wire [33:0] _misaligned_T_3 = io_req_bits_vaddr & _GEN_144; // @[TLB.scala 341:39]
+ wire misaligned = |_misaligned_T_3; // @[TLB.scala 341:75]
+ wire _cmd_lrsc_T = io_req_bits_cmd == 5'h6; // @[package.scala 15:47]
+ wire _cmd_lrsc_T_1 = io_req_bits_cmd == 5'h7; // @[package.scala 15:47]
+ wire cmd_lrsc = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala 72:59]
+ wire _cmd_amo_logical_T = io_req_bits_cmd == 5'h4; // @[package.scala 15:47]
+ wire _cmd_amo_logical_T_1 = io_req_bits_cmd == 5'h9; // @[package.scala 15:47]
+ wire _cmd_amo_logical_T_2 = io_req_bits_cmd == 5'ha; // @[package.scala 15:47]
+ wire _cmd_amo_logical_T_3 = io_req_bits_cmd == 5'hb; // @[package.scala 15:47]
+ wire cmd_amo_logical = _cmd_amo_logical_T | _cmd_amo_logical_T_1 | _cmd_amo_logical_T_2 | _cmd_amo_logical_T_3; // @[package.scala 72:59]
+ wire _cmd_amo_arithmetic_T = io_req_bits_cmd == 5'h8; // @[package.scala 15:47]
+ wire _cmd_amo_arithmetic_T_1 = io_req_bits_cmd == 5'hc; // @[package.scala 15:47]
+ wire _cmd_amo_arithmetic_T_2 = io_req_bits_cmd == 5'hd; // @[package.scala 15:47]
+ wire _cmd_amo_arithmetic_T_3 = io_req_bits_cmd == 5'he; // @[package.scala 15:47]
+ wire _cmd_amo_arithmetic_T_4 = io_req_bits_cmd == 5'hf; // @[package.scala 15:47]
+ wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1 | _cmd_amo_arithmetic_T_2 |
+ _cmd_amo_arithmetic_T_3 | _cmd_amo_arithmetic_T_4; // @[package.scala 72:59]
+ wire cmd_put_partial = io_req_bits_cmd == 5'h11; // @[TLB.scala 364:41]
+ wire _cmd_read_T = io_req_bits_cmd == 5'h0; // @[package.scala 15:47]
+ wire _cmd_read_T_1 = io_req_bits_cmd == 5'h10; // @[package.scala 15:47]
+ wire _cmd_read_T_6 = _cmd_read_T | _cmd_read_T_1 | _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala 72:59]
+ wire _cmd_read_T_23 = cmd_amo_logical | cmd_amo_arithmetic; // @[Consts.scala 82:44]
+ wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[Consts.scala 84:68]
+ wire cmd_write = io_req_bits_cmd == 5'h1 | cmd_put_partial | _cmd_lrsc_T_1 | _cmd_read_T_23; // @[Consts.scala 85:76]
+ wire _cmd_write_perms_T = io_req_bits_cmd == 5'h5; // @[package.scala 15:47]
+ wire _cmd_write_perms_T_1 = io_req_bits_cmd == 5'h17; // @[package.scala 15:47]
+ wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala 72:59]
+ wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[TLB.scala 368:35]
+ wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala 373:8]
+ wire [6:0] _ae_array_T_2 = cmd_lrsc ? 7'h7f : 7'h0; // @[TLB.scala 374:8]
+ wire [6:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala 373:37]
+ wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala 375:46]
+ wire [6:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala 375:44]
+ wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala 375:24]
+ wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala 377:37]
+ wire [6:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala 377:35]
+ wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala 377:8]
+ wire [6:0] _ae_st_array_T_3 = ~ppp_array; // @[TLB.scala 378:26]
+ wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala 378:8]
+ wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala 377:53]
+ wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala 379:8]
+ wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala 378:53]
+ wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala 380:8]
+ wire [6:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala 379:53]
+ wire [6:0] pf_ld_array = cmd_read ? 7'h3f : 7'h0; // @[TLB.scala 386:24]
+ wire [6:0] pf_st_array = cmd_write_perms ? 7'h3f : 7'h0; // @[TLB.scala 387:24]
+ wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & 7'h40; // @[TLB.scala 419:57]
+ wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & 7'h40; // @[TLB.scala 420:64]
+ wire [6:0] _io_resp_ae_ld_T = ae_ld_array & 7'h40; // @[TLB.scala 425:33]
+ wire [6:0] _io_resp_ae_st_T = ae_st_array & 7'h40; // @[TLB.scala 426:33]
+ PMPChecker pmp ( // @[TLB.scala 233:19]
+ .io_prv(pmp_io_prv),
+ .io_pmp_0_cfg_l(pmp_io_pmp_0_cfg_l),
+ .io_pmp_0_cfg_a(pmp_io_pmp_0_cfg_a),
+ .io_pmp_0_cfg_w(pmp_io_pmp_0_cfg_w),
+ .io_pmp_0_cfg_r(pmp_io_pmp_0_cfg_r),
+ .io_pmp_0_addr(pmp_io_pmp_0_addr),
+ .io_pmp_0_mask(pmp_io_pmp_0_mask),
+ .io_pmp_1_cfg_l(pmp_io_pmp_1_cfg_l),
+ .io_pmp_1_cfg_a(pmp_io_pmp_1_cfg_a),
+ .io_pmp_1_cfg_w(pmp_io_pmp_1_cfg_w),
+ .io_pmp_1_cfg_r(pmp_io_pmp_1_cfg_r),
+ .io_pmp_1_addr(pmp_io_pmp_1_addr),
+ .io_pmp_1_mask(pmp_io_pmp_1_mask),
+ .io_pmp_2_cfg_l(pmp_io_pmp_2_cfg_l),
+ .io_pmp_2_cfg_a(pmp_io_pmp_2_cfg_a),
+ .io_pmp_2_cfg_w(pmp_io_pmp_2_cfg_w),
+ .io_pmp_2_cfg_r(pmp_io_pmp_2_cfg_r),
+ .io_pmp_2_addr(pmp_io_pmp_2_addr),
+ .io_pmp_2_mask(pmp_io_pmp_2_mask),
+ .io_pmp_3_cfg_l(pmp_io_pmp_3_cfg_l),
+ .io_pmp_3_cfg_a(pmp_io_pmp_3_cfg_a),
+ .io_pmp_3_cfg_w(pmp_io_pmp_3_cfg_w),
+ .io_pmp_3_cfg_r(pmp_io_pmp_3_cfg_r),
+ .io_pmp_3_addr(pmp_io_pmp_3_addr),
+ .io_pmp_3_mask(pmp_io_pmp_3_mask),
+ .io_pmp_4_cfg_l(pmp_io_pmp_4_cfg_l),
+ .io_pmp_4_cfg_a(pmp_io_pmp_4_cfg_a),
+ .io_pmp_4_cfg_w(pmp_io_pmp_4_cfg_w),
+ .io_pmp_4_cfg_r(pmp_io_pmp_4_cfg_r),
+ .io_pmp_4_addr(pmp_io_pmp_4_addr),
+ .io_pmp_4_mask(pmp_io_pmp_4_mask),
+ .io_pmp_5_cfg_l(pmp_io_pmp_5_cfg_l),
+ .io_pmp_5_cfg_a(pmp_io_pmp_5_cfg_a),
+ .io_pmp_5_cfg_w(pmp_io_pmp_5_cfg_w),
+ .io_pmp_5_cfg_r(pmp_io_pmp_5_cfg_r),
+ .io_pmp_5_addr(pmp_io_pmp_5_addr),
+ .io_pmp_5_mask(pmp_io_pmp_5_mask),
+ .io_pmp_6_cfg_l(pmp_io_pmp_6_cfg_l),
+ .io_pmp_6_cfg_a(pmp_io_pmp_6_cfg_a),
+ .io_pmp_6_cfg_w(pmp_io_pmp_6_cfg_w),
+ .io_pmp_6_cfg_r(pmp_io_pmp_6_cfg_r),
+ .io_pmp_6_addr(pmp_io_pmp_6_addr),
+ .io_pmp_6_mask(pmp_io_pmp_6_mask),
+ .io_pmp_7_cfg_l(pmp_io_pmp_7_cfg_l),
+ .io_pmp_7_cfg_a(pmp_io_pmp_7_cfg_a),
+ .io_pmp_7_cfg_w(pmp_io_pmp_7_cfg_w),
+ .io_pmp_7_cfg_r(pmp_io_pmp_7_cfg_r),
+ .io_pmp_7_addr(pmp_io_pmp_7_addr),
+ .io_pmp_7_mask(pmp_io_pmp_7_mask),
+ .io_addr(pmp_io_addr),
+ .io_size(pmp_io_size),
+ .io_r(pmp_io_r),
+ .io_w(pmp_io_w)
+ );
+ assign io_resp_paddr = {ppn,io_req_bits_vaddr[11:0]}; // @[Cat.scala 31:58]
+ assign io_resp_pf_ld = |_io_resp_pf_ld_T_1; // @[TLB.scala 419:65]
+ assign io_resp_pf_st = |_io_resp_pf_st_T_1; // @[TLB.scala 420:72]
+ assign io_resp_ae_ld = |_io_resp_ae_ld_T; // @[TLB.scala 425:41]
+ assign io_resp_ae_st = |_io_resp_ae_st_T; // @[TLB.scala 426:41]
+ assign io_resp_ma_ld = misaligned & cmd_read; // @[TLB.scala 428:31]
+ assign io_resp_ma_st = misaligned & cmd_write; // @[TLB.scala 429:31]
+ assign pmp_io_prv = mpu_priv[1:0]; // @[TLB.scala 237:14]
+ assign pmp_io_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_addr = io_ptw_pmp_0_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_mask = io_ptw_pmp_0_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_addr = io_ptw_pmp_1_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_mask = io_ptw_pmp_1_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_addr = io_ptw_pmp_2_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_mask = io_ptw_pmp_2_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_addr = io_ptw_pmp_3_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_mask = io_ptw_pmp_3_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_addr = io_ptw_pmp_4_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_mask = io_ptw_pmp_4_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_addr = io_ptw_pmp_5_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_mask = io_ptw_pmp_5_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_addr = io_ptw_pmp_6_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_mask = io_ptw_pmp_6_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_addr = io_ptw_pmp_7_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_mask = io_ptw_pmp_7_mask; // @[TLB.scala 236:14]
+ assign pmp_io_addr = mpu_physaddr[31:0]; // @[TLB.scala 234:15]
+ assign pmp_io_size = io_req_bits_size; // @[TLB.scala 235:15]
+endmodule
+module DCacheModuleImpl_Anon_1(
+ input io_in_2_valid,
+ input [33:0] io_in_2_bits_addr,
+ input io_in_3_valid,
+ input [33:0] io_in_3_bits_addr,
+ output io_in_5_ready,
+ input io_in_5_valid,
+ output io_in_7_ready,
+ input io_in_7_valid,
+ input [33:0] io_in_7_bits_addr,
+ output io_out_valid,
+ output io_out_bits_write,
+ output [33:0] io_out_bits_addr
+);
+ wire [33:0] _GEN_22 = io_in_3_valid ? io_in_3_bits_addr : io_in_7_bits_addr; // @[Arbiter.scala 141:26 143:19]
+ wire _GEN_29 = io_in_2_valid | io_in_3_valid; // @[Arbiter.scala 141:26 143:19]
+ wire grant_4 = ~_GEN_29; // @[Arbiter.scala 46:78]
+ assign io_in_5_ready = ~_GEN_29; // @[Arbiter.scala 46:78]
+ assign io_in_7_ready = ~_GEN_29; // @[Arbiter.scala 46:78]
+ assign io_out_valid = ~grant_4 | io_in_7_valid; // @[Arbiter.scala 150:31]
+ assign io_out_bits_write = io_in_2_valid | io_in_3_valid; // @[Arbiter.scala 141:26 143:19]
+ assign io_out_bits_addr = io_in_2_valid ? io_in_2_bits_addr : _GEN_22; // @[Arbiter.scala 141:26 143:19]
+endmodule
+module DCacheDataArray(
+ input clock,
+ input io_req_valid,
+ input [13:0] io_req_bits_addr,
+ input io_req_bits_write,
+ input [63:0] io_req_bits_wdata,
+ input [7:0] io_req_bits_eccMask,
+ output [63:0] io_resp_0
+);
+ wire [10:0] data_arrays_0_RW0_addr; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_en; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_clk; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmode; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_wdata_0; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_wdata_1; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_wdata_2; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_wdata_3; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_wdata_4; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_wdata_5; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_wdata_6; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_wdata_7; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_rdata_0; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_rdata_1; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_rdata_2; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_rdata_3; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_rdata_4; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_rdata_5; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_rdata_6; // @[DescribedSRAM.scala 19:26]
+ wire [7:0] data_arrays_0_RW0_rdata_7; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmask_0; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmask_1; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmask_2; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmask_3; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmask_4; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmask_5; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmask_6; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmask_7; // @[DescribedSRAM.scala 19:26]
+ wire _rdata_T = io_req_valid & io_req_bits_write; // @[DCache.scala 66:17]
+ wire _rdata_data_T_1 = io_req_valid & ~io_req_bits_write; // @[DCache.scala 71:39]
+ wire [31:0] rdata_lo = {data_arrays_0_RW0_rdata_3,data_arrays_0_RW0_rdata_2,data_arrays_0_RW0_rdata_1,
+ data_arrays_0_RW0_rdata_0}; // @[Cat.scala 31:58]
+ wire [31:0] rdata_hi = {data_arrays_0_RW0_rdata_7,data_arrays_0_RW0_rdata_6,data_arrays_0_RW0_rdata_5,
+ data_arrays_0_RW0_rdata_4}; // @[Cat.scala 31:58]
+ data_arrays_0 data_arrays_0 ( // @[DescribedSRAM.scala 19:26]
+ .RW0_addr(data_arrays_0_RW0_addr),
+ .RW0_en(data_arrays_0_RW0_en),
+ .RW0_clk(data_arrays_0_RW0_clk),
+ .RW0_wmode(data_arrays_0_RW0_wmode),
+ .RW0_wdata_0(data_arrays_0_RW0_wdata_0),
+ .RW0_wdata_1(data_arrays_0_RW0_wdata_1),
+ .RW0_wdata_2(data_arrays_0_RW0_wdata_2),
+ .RW0_wdata_3(data_arrays_0_RW0_wdata_3),
+ .RW0_wdata_4(data_arrays_0_RW0_wdata_4),
+ .RW0_wdata_5(data_arrays_0_RW0_wdata_5),
+ .RW0_wdata_6(data_arrays_0_RW0_wdata_6),
+ .RW0_wdata_7(data_arrays_0_RW0_wdata_7),
+ .RW0_rdata_0(data_arrays_0_RW0_rdata_0),
+ .RW0_rdata_1(data_arrays_0_RW0_rdata_1),
+ .RW0_rdata_2(data_arrays_0_RW0_rdata_2),
+ .RW0_rdata_3(data_arrays_0_RW0_rdata_3),
+ .RW0_rdata_4(data_arrays_0_RW0_rdata_4),
+ .RW0_rdata_5(data_arrays_0_RW0_rdata_5),
+ .RW0_rdata_6(data_arrays_0_RW0_rdata_6),
+ .RW0_rdata_7(data_arrays_0_RW0_rdata_7),
+ .RW0_wmask_0(data_arrays_0_RW0_wmask_0),
+ .RW0_wmask_1(data_arrays_0_RW0_wmask_1),
+ .RW0_wmask_2(data_arrays_0_RW0_wmask_2),
+ .RW0_wmask_3(data_arrays_0_RW0_wmask_3),
+ .RW0_wmask_4(data_arrays_0_RW0_wmask_4),
+ .RW0_wmask_5(data_arrays_0_RW0_wmask_5),
+ .RW0_wmask_6(data_arrays_0_RW0_wmask_6),
+ .RW0_wmask_7(data_arrays_0_RW0_wmask_7)
+ );
+ assign io_resp_0 = {rdata_hi,rdata_lo}; // @[Cat.scala 31:58]
+ assign data_arrays_0_RW0_clk = clock; // @[DCache.scala 66:39]
+ assign data_arrays_0_RW0_wdata_0 = io_req_bits_wdata[7:0]; // @[package.scala 202:50]
+ assign data_arrays_0_RW0_wdata_1 = io_req_bits_wdata[15:8]; // @[package.scala 202:50]
+ assign data_arrays_0_RW0_wdata_2 = io_req_bits_wdata[23:16]; // @[package.scala 202:50]
+ assign data_arrays_0_RW0_wdata_3 = io_req_bits_wdata[31:24]; // @[package.scala 202:50]
+ assign data_arrays_0_RW0_wdata_4 = io_req_bits_wdata[39:32]; // @[package.scala 202:50]
+ assign data_arrays_0_RW0_wdata_5 = io_req_bits_wdata[47:40]; // @[package.scala 202:50]
+ assign data_arrays_0_RW0_wdata_6 = io_req_bits_wdata[55:48]; // @[package.scala 202:50]
+ assign data_arrays_0_RW0_wdata_7 = io_req_bits_wdata[63:56]; // @[package.scala 202:50]
+ assign data_arrays_0_RW0_wmask_0 = io_req_bits_eccMask[0]; // @[DCache.scala 50:82]
+ assign data_arrays_0_RW0_wmask_1 = io_req_bits_eccMask[1]; // @[DCache.scala 50:82]
+ assign data_arrays_0_RW0_wmask_2 = io_req_bits_eccMask[2]; // @[DCache.scala 50:82]
+ assign data_arrays_0_RW0_wmask_3 = io_req_bits_eccMask[3]; // @[DCache.scala 50:82]
+ assign data_arrays_0_RW0_wmask_4 = io_req_bits_eccMask[4]; // @[DCache.scala 50:82]
+ assign data_arrays_0_RW0_wmask_5 = io_req_bits_eccMask[5]; // @[DCache.scala 50:82]
+ assign data_arrays_0_RW0_wmask_6 = io_req_bits_eccMask[6]; // @[DCache.scala 50:82]
+ assign data_arrays_0_RW0_wmask_7 = io_req_bits_eccMask[7]; // @[DCache.scala 50:82]
+ assign data_arrays_0_RW0_en = _rdata_data_T_1 | _rdata_T;
+ assign data_arrays_0_RW0_wmode = io_req_bits_write;
+ assign data_arrays_0_RW0_addr = io_req_bits_addr[13:3]; // @[DCache.scala 53:31]
+endmodule
+module DCacheModuleImpl_Anon_2(
+ input io_in_0_valid,
+ input [13:0] io_in_0_bits_addr,
+ input io_in_0_bits_write,
+ input [63:0] io_in_0_bits_wdata,
+ input [7:0] io_in_0_bits_eccMask,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [13:0] io_in_1_bits_addr,
+ input io_in_1_bits_write,
+ input [63:0] io_in_1_bits_wdata,
+ input [7:0] io_in_1_bits_eccMask,
+ output io_in_3_ready,
+ input io_in_3_valid,
+ input [13:0] io_in_3_bits_addr,
+ input [63:0] io_in_3_bits_wdata,
+ input io_in_3_bits_wordMask,
+ output io_out_valid,
+ output [13:0] io_out_bits_addr,
+ output io_out_bits_write,
+ output [63:0] io_out_bits_wdata,
+ output [7:0] io_out_bits_eccMask
+);
+ wire [7:0] _GEN_9 = io_in_1_valid ? io_in_1_bits_eccMask : 8'hff; // @[Arbiter.scala 141:26 143:19]
+ wire [63:0] _GEN_11 = io_in_1_valid ? io_in_1_bits_wdata : io_in_3_bits_wdata; // @[Arbiter.scala 141:26 143:19]
+ wire [13:0] _GEN_13 = io_in_1_valid ? io_in_1_bits_addr : io_in_3_bits_addr; // @[Arbiter.scala 141:26 143:19]
+ wire grant_2 = ~(io_in_0_valid | io_in_1_valid); // @[Arbiter.scala 46:78]
+ assign io_in_1_ready = ~io_in_0_valid; // @[Arbiter.scala 46:78]
+ assign io_in_3_ready = ~(io_in_0_valid | io_in_1_valid); // @[Arbiter.scala 46:78]
+ assign io_out_valid = ~grant_2 | io_in_3_valid; // @[Arbiter.scala 150:31]
+ assign io_out_bits_addr = io_in_0_valid ? io_in_0_bits_addr : _GEN_13; // @[Arbiter.scala 141:26 143:19]
+ assign io_out_bits_write = io_in_0_valid ? io_in_0_bits_write : io_in_1_valid & io_in_1_bits_write; // @[Arbiter.scala 141:26 143:19]
+ assign io_out_bits_wdata = io_in_0_valid ? io_in_0_bits_wdata : _GEN_11; // @[Arbiter.scala 141:26 143:19]
+ assign io_out_bits_eccMask = io_in_0_valid ? io_in_0_bits_eccMask : _GEN_9; // @[Arbiter.scala 141:26 143:19]
+endmodule
+module AMOALU(
+ input [7:0] io_mask,
+ input [4:0] io_cmd,
+ input [63:0] io_lhs,
+ input [63:0] io_rhs,
+ output [63:0] io_out_unmasked
+);
+ wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
+ wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
+ wire add = io_cmd == 5'h8; // @[AMOALU.scala 66:20]
+ wire _logic_and_T = io_cmd == 5'ha; // @[AMOALU.scala 67:26]
+ wire logic_and = io_cmd == 5'ha | io_cmd == 5'hb; // @[AMOALU.scala 67:38]
+ wire logic_xor = io_cmd == 5'h9 | _logic_and_T; // @[AMOALU.scala 68:39]
+ wire _adder_out_mask_T_1 = ~io_mask[3]; // @[AMOALU.scala 72:63]
+ wire [31:0] _adder_out_mask_T_2 = {_adder_out_mask_T_1, 31'h0}; // @[AMOALU.scala 72:79]
+ wire [63:0] _adder_out_mask_T_3 = {{32'd0}, _adder_out_mask_T_2}; // @[AMOALU.scala 72:98]
+ wire [63:0] adder_out_mask = ~_adder_out_mask_T_3; // @[AMOALU.scala 72:16]
+ wire [63:0] _adder_out_T = io_lhs & adder_out_mask; // @[AMOALU.scala 73:13]
+ wire [63:0] _adder_out_T_1 = io_rhs & adder_out_mask; // @[AMOALU.scala 73:31]
+ wire [63:0] adder_out = _adder_out_T + _adder_out_T_1; // @[AMOALU.scala 73:21]
+ wire [4:0] _less_signed_T = io_cmd & 5'h2; // @[AMOALU.scala 86:17]
+ wire less_signed = _less_signed_T == 5'h0; // @[AMOALU.scala 86:25]
+ wire _less_T_12 = io_lhs[31:0] < io_rhs[31:0]; // @[AMOALU.scala 79:35]
+ wire _less_T_14 = io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32] & _less_T_12; // @[AMOALU.scala 80:38]
+ wire _less_T_17 = less_signed ? io_lhs[63] : io_rhs[63]; // @[AMOALU.scala 88:58]
+ wire _less_T_18 = io_lhs[63] == io_rhs[63] ? _less_T_14 : _less_T_17; // @[AMOALU.scala 88:10]
+ wire _less_T_28 = less_signed ? io_lhs[31] : io_rhs[31]; // @[AMOALU.scala 88:58]
+ wire _less_T_29 = io_lhs[31] == io_rhs[31] ? _less_T_12 : _less_T_28; // @[AMOALU.scala 88:10]
+ wire less = io_mask[4] ? _less_T_18 : _less_T_29; // @[Mux.scala 47:70]
+ wire _minmax_T = less ? min : max; // @[AMOALU.scala 94:23]
+ wire [63:0] minmax = _minmax_T ? io_lhs : io_rhs; // @[AMOALU.scala 94:19]
+ wire [63:0] _logic_T = io_lhs & io_rhs; // @[AMOALU.scala 96:27]
+ wire [63:0] _logic_T_1 = logic_and ? _logic_T : 64'h0; // @[AMOALU.scala 96:8]
+ wire [63:0] _logic_T_2 = io_lhs ^ io_rhs; // @[AMOALU.scala 97:27]
+ wire [63:0] _logic_T_3 = logic_xor ? _logic_T_2 : 64'h0; // @[AMOALU.scala 97:8]
+ wire [63:0] logic_ = _logic_T_1 | _logic_T_3; // @[AMOALU.scala 96:42]
+ wire [63:0] _out_T_1 = logic_and | logic_xor ? logic_ : minmax; // @[AMOALU.scala 100:8]
+ assign io_out_unmasked = add ? adder_out : _out_T_1; // @[AMOALU.scala 99:8]
+endmodule
+module DCache(
+ input clock,
+ input reset,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [3:0] auto_out_d_bits_size,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ output io_cpu_req_ready,
+ input io_cpu_req_valid,
+ input [33:0] io_cpu_req_bits_addr,
+ input [6:0] io_cpu_req_bits_tag,
+ input [4:0] io_cpu_req_bits_cmd,
+ input [1:0] io_cpu_req_bits_size,
+ input io_cpu_req_bits_signed,
+ input [1:0] io_cpu_req_bits_dprv,
+ input io_cpu_req_bits_no_xcpt,
+ input io_cpu_s1_kill,
+ input [63:0] io_cpu_s1_data_data,
+ input [7:0] io_cpu_s1_data_mask,
+ output io_cpu_s2_nack,
+ output io_cpu_resp_valid,
+ output [33:0] io_cpu_resp_bits_addr,
+ output [6:0] io_cpu_resp_bits_tag,
+ output [4:0] io_cpu_resp_bits_cmd,
+ output [1:0] io_cpu_resp_bits_size,
+ output io_cpu_resp_bits_signed,
+ output [1:0] io_cpu_resp_bits_dprv,
+ output io_cpu_resp_bits_dv,
+ output [63:0] io_cpu_resp_bits_data,
+ output [7:0] io_cpu_resp_bits_mask,
+ output io_cpu_resp_bits_replay,
+ output io_cpu_resp_bits_has_data,
+ output [63:0] io_cpu_resp_bits_data_word_bypass,
+ output [63:0] io_cpu_resp_bits_data_raw,
+ output [63:0] io_cpu_resp_bits_store_data,
+ output io_cpu_replay_next,
+ output io_cpu_s2_xcpt_ma_ld,
+ output io_cpu_s2_xcpt_ma_st,
+ output io_cpu_s2_xcpt_pf_ld,
+ output io_cpu_s2_xcpt_pf_st,
+ output io_cpu_s2_xcpt_gf_ld,
+ output io_cpu_s2_xcpt_gf_st,
+ output io_cpu_s2_xcpt_ae_ld,
+ output io_cpu_s2_xcpt_ae_st,
+ output io_cpu_ordered,
+ output io_cpu_perf_grant,
+ input io_ptw_status_debug,
+ input io_ptw_pmp_0_cfg_l,
+ input [1:0] io_ptw_pmp_0_cfg_a,
+ input io_ptw_pmp_0_cfg_w,
+ input io_ptw_pmp_0_cfg_r,
+ input [29:0] io_ptw_pmp_0_addr,
+ input [31:0] io_ptw_pmp_0_mask,
+ input io_ptw_pmp_1_cfg_l,
+ input [1:0] io_ptw_pmp_1_cfg_a,
+ input io_ptw_pmp_1_cfg_w,
+ input io_ptw_pmp_1_cfg_r,
+ input [29:0] io_ptw_pmp_1_addr,
+ input [31:0] io_ptw_pmp_1_mask,
+ input io_ptw_pmp_2_cfg_l,
+ input [1:0] io_ptw_pmp_2_cfg_a,
+ input io_ptw_pmp_2_cfg_w,
+ input io_ptw_pmp_2_cfg_r,
+ input [29:0] io_ptw_pmp_2_addr,
+ input [31:0] io_ptw_pmp_2_mask,
+ input io_ptw_pmp_3_cfg_l,
+ input [1:0] io_ptw_pmp_3_cfg_a,
+ input io_ptw_pmp_3_cfg_w,
+ input io_ptw_pmp_3_cfg_r,
+ input [29:0] io_ptw_pmp_3_addr,
+ input [31:0] io_ptw_pmp_3_mask,
+ input io_ptw_pmp_4_cfg_l,
+ input [1:0] io_ptw_pmp_4_cfg_a,
+ input io_ptw_pmp_4_cfg_w,
+ input io_ptw_pmp_4_cfg_r,
+ input [29:0] io_ptw_pmp_4_addr,
+ input [31:0] io_ptw_pmp_4_mask,
+ input io_ptw_pmp_5_cfg_l,
+ input [1:0] io_ptw_pmp_5_cfg_a,
+ input io_ptw_pmp_5_cfg_w,
+ input io_ptw_pmp_5_cfg_r,
+ input [29:0] io_ptw_pmp_5_addr,
+ input [31:0] io_ptw_pmp_5_mask,
+ input io_ptw_pmp_6_cfg_l,
+ input [1:0] io_ptw_pmp_6_cfg_a,
+ input io_ptw_pmp_6_cfg_w,
+ input io_ptw_pmp_6_cfg_r,
+ input [29:0] io_ptw_pmp_6_addr,
+ input [31:0] io_ptw_pmp_6_mask,
+ input io_ptw_pmp_7_cfg_l,
+ input [1:0] io_ptw_pmp_7_cfg_a,
+ input io_ptw_pmp_7_cfg_w,
+ input io_ptw_pmp_7_cfg_r,
+ input [29:0] io_ptw_pmp_7_addr,
+ input [31:0] io_ptw_pmp_7_mask
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [63:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [63:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [63:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [63:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [63:0] _RAND_30;
+ reg [31:0] _RAND_31;
+ reg [31:0] _RAND_32;
+ reg [31:0] _RAND_33;
+ reg [31:0] _RAND_34;
+ reg [31:0] _RAND_35;
+ reg [31:0] _RAND_36;
+ reg [31:0] _RAND_37;
+ reg [31:0] _RAND_38;
+ reg [31:0] _RAND_39;
+ reg [31:0] _RAND_40;
+ reg [31:0] _RAND_41;
+ reg [63:0] _RAND_42;
+ reg [63:0] _RAND_43;
+ reg [31:0] _RAND_44;
+ reg [31:0] _RAND_45;
+ reg [31:0] _RAND_46;
+ reg [63:0] _RAND_47;
+ reg [31:0] _RAND_48;
+ reg [63:0] _RAND_49;
+ reg [31:0] _RAND_50;
+ reg [31:0] _RAND_51;
+ reg [31:0] _RAND_52;
+ reg [31:0] _RAND_53;
+ reg [31:0] _RAND_54;
+ reg [31:0] _RAND_55;
+ reg [31:0] _RAND_56;
+ reg [31:0] _RAND_57;
+ reg [31:0] _RAND_58;
+ reg [31:0] _RAND_59;
+ reg [31:0] _RAND_60;
+ reg [31:0] _RAND_61;
+`endif // RANDOMIZE_REG_INIT
+ wire tlb_io_req_valid; // @[DCache.scala 117:19]
+ wire [33:0] tlb_io_req_bits_vaddr; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_req_bits_size; // @[DCache.scala 117:19]
+ wire [4:0] tlb_io_req_bits_cmd; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_req_bits_prv; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_resp_paddr; // @[DCache.scala 117:19]
+ wire tlb_io_resp_pf_ld; // @[DCache.scala 117:19]
+ wire tlb_io_resp_pf_st; // @[DCache.scala 117:19]
+ wire tlb_io_resp_ae_ld; // @[DCache.scala 117:19]
+ wire tlb_io_resp_ae_st; // @[DCache.scala 117:19]
+ wire tlb_io_resp_ma_ld; // @[DCache.scala 117:19]
+ wire tlb_io_resp_ma_st; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_status_debug; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_0_cfg_l; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_ptw_pmp_0_cfg_a; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_0_cfg_w; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_0_cfg_r; // @[DCache.scala 117:19]
+ wire [29:0] tlb_io_ptw_pmp_0_addr; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_ptw_pmp_0_mask; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_1_cfg_l; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_ptw_pmp_1_cfg_a; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_1_cfg_w; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_1_cfg_r; // @[DCache.scala 117:19]
+ wire [29:0] tlb_io_ptw_pmp_1_addr; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_ptw_pmp_1_mask; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_2_cfg_l; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_ptw_pmp_2_cfg_a; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_2_cfg_w; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_2_cfg_r; // @[DCache.scala 117:19]
+ wire [29:0] tlb_io_ptw_pmp_2_addr; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_ptw_pmp_2_mask; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_3_cfg_l; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_ptw_pmp_3_cfg_a; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_3_cfg_w; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_3_cfg_r; // @[DCache.scala 117:19]
+ wire [29:0] tlb_io_ptw_pmp_3_addr; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_ptw_pmp_3_mask; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_4_cfg_l; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_ptw_pmp_4_cfg_a; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_4_cfg_w; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_4_cfg_r; // @[DCache.scala 117:19]
+ wire [29:0] tlb_io_ptw_pmp_4_addr; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_ptw_pmp_4_mask; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_5_cfg_l; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_ptw_pmp_5_cfg_a; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_5_cfg_w; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_5_cfg_r; // @[DCache.scala 117:19]
+ wire [29:0] tlb_io_ptw_pmp_5_addr; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_ptw_pmp_5_mask; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_6_cfg_l; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_ptw_pmp_6_cfg_a; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_6_cfg_w; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_6_cfg_r; // @[DCache.scala 117:19]
+ wire [29:0] tlb_io_ptw_pmp_6_addr; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_ptw_pmp_6_mask; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_7_cfg_l; // @[DCache.scala 117:19]
+ wire [1:0] tlb_io_ptw_pmp_7_cfg_a; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_7_cfg_w; // @[DCache.scala 117:19]
+ wire tlb_io_ptw_pmp_7_cfg_r; // @[DCache.scala 117:19]
+ wire [29:0] tlb_io_ptw_pmp_7_addr; // @[DCache.scala 117:19]
+ wire [31:0] tlb_io_ptw_pmp_7_mask; // @[DCache.scala 117:19]
+ wire pma_checker_io_req_valid; // @[DCache.scala 118:27]
+ wire [33:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala 118:27]
+ wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala 118:27]
+ wire pma_checker_io_resp_pf_ld; // @[DCache.scala 118:27]
+ wire pma_checker_io_resp_pf_st; // @[DCache.scala 118:27]
+ wire pma_checker_io_resp_ae_ld; // @[DCache.scala 118:27]
+ wire pma_checker_io_resp_ae_st; // @[DCache.scala 118:27]
+ wire pma_checker_io_resp_ma_ld; // @[DCache.scala 118:27]
+ wire pma_checker_io_resp_ma_st; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_status_debug; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_0_cfg_l; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_0_cfg_w; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_0_cfg_r; // @[DCache.scala 118:27]
+ wire [29:0] pma_checker_io_ptw_pmp_0_addr; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_ptw_pmp_0_mask; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_1_cfg_l; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_1_cfg_w; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_1_cfg_r; // @[DCache.scala 118:27]
+ wire [29:0] pma_checker_io_ptw_pmp_1_addr; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_ptw_pmp_1_mask; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_2_cfg_l; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_2_cfg_w; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_2_cfg_r; // @[DCache.scala 118:27]
+ wire [29:0] pma_checker_io_ptw_pmp_2_addr; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_ptw_pmp_2_mask; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_3_cfg_l; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_3_cfg_w; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_3_cfg_r; // @[DCache.scala 118:27]
+ wire [29:0] pma_checker_io_ptw_pmp_3_addr; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_ptw_pmp_3_mask; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_4_cfg_l; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_4_cfg_w; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_4_cfg_r; // @[DCache.scala 118:27]
+ wire [29:0] pma_checker_io_ptw_pmp_4_addr; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_ptw_pmp_4_mask; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_5_cfg_l; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_5_cfg_w; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_5_cfg_r; // @[DCache.scala 118:27]
+ wire [29:0] pma_checker_io_ptw_pmp_5_addr; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_ptw_pmp_5_mask; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_6_cfg_l; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_6_cfg_w; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_6_cfg_r; // @[DCache.scala 118:27]
+ wire [29:0] pma_checker_io_ptw_pmp_6_addr; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_ptw_pmp_6_mask; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_7_cfg_l; // @[DCache.scala 118:27]
+ wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_7_cfg_w; // @[DCache.scala 118:27]
+ wire pma_checker_io_ptw_pmp_7_cfg_r; // @[DCache.scala 118:27]
+ wire [29:0] pma_checker_io_ptw_pmp_7_addr; // @[DCache.scala 118:27]
+ wire [31:0] pma_checker_io_ptw_pmp_7_mask; // @[DCache.scala 118:27]
+ wire metaArb_io_in_2_valid; // @[DCache.scala 122:23]
+ wire [33:0] metaArb_io_in_2_bits_addr; // @[DCache.scala 122:23]
+ wire metaArb_io_in_3_valid; // @[DCache.scala 122:23]
+ wire [33:0] metaArb_io_in_3_bits_addr; // @[DCache.scala 122:23]
+ wire metaArb_io_in_5_ready; // @[DCache.scala 122:23]
+ wire metaArb_io_in_5_valid; // @[DCache.scala 122:23]
+ wire metaArb_io_in_7_ready; // @[DCache.scala 122:23]
+ wire metaArb_io_in_7_valid; // @[DCache.scala 122:23]
+ wire [33:0] metaArb_io_in_7_bits_addr; // @[DCache.scala 122:23]
+ wire metaArb_io_out_valid; // @[DCache.scala 122:23]
+ wire metaArb_io_out_bits_write; // @[DCache.scala 122:23]
+ wire [33:0] metaArb_io_out_bits_addr; // @[DCache.scala 122:23]
+ wire data_clock; // @[DCache.scala 132:20]
+ wire data_io_req_valid; // @[DCache.scala 132:20]
+ wire [13:0] data_io_req_bits_addr; // @[DCache.scala 132:20]
+ wire data_io_req_bits_write; // @[DCache.scala 132:20]
+ wire [63:0] data_io_req_bits_wdata; // @[DCache.scala 132:20]
+ wire [7:0] data_io_req_bits_eccMask; // @[DCache.scala 132:20]
+ wire [63:0] data_io_resp_0; // @[DCache.scala 132:20]
+ wire dataArb_io_in_0_valid; // @[DCache.scala 133:23]
+ wire [13:0] dataArb_io_in_0_bits_addr; // @[DCache.scala 133:23]
+ wire dataArb_io_in_0_bits_write; // @[DCache.scala 133:23]
+ wire [63:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala 133:23]
+ wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala 133:23]
+ wire dataArb_io_in_1_ready; // @[DCache.scala 133:23]
+ wire dataArb_io_in_1_valid; // @[DCache.scala 133:23]
+ wire [13:0] dataArb_io_in_1_bits_addr; // @[DCache.scala 133:23]
+ wire dataArb_io_in_1_bits_write; // @[DCache.scala 133:23]
+ wire [63:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala 133:23]
+ wire [7:0] dataArb_io_in_1_bits_eccMask; // @[DCache.scala 133:23]
+ wire dataArb_io_in_3_ready; // @[DCache.scala 133:23]
+ wire dataArb_io_in_3_valid; // @[DCache.scala 133:23]
+ wire [13:0] dataArb_io_in_3_bits_addr; // @[DCache.scala 133:23]
+ wire [63:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala 133:23]
+ wire dataArb_io_in_3_bits_wordMask; // @[DCache.scala 133:23]
+ wire dataArb_io_out_valid; // @[DCache.scala 133:23]
+ wire [13:0] dataArb_io_out_bits_addr; // @[DCache.scala 133:23]
+ wire dataArb_io_out_bits_write; // @[DCache.scala 133:23]
+ wire [63:0] dataArb_io_out_bits_wdata; // @[DCache.scala 133:23]
+ wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala 133:23]
+ wire [7:0] amoalu_io_mask; // @[DCache.scala 956:26]
+ wire [4:0] amoalu_io_cmd; // @[DCache.scala 956:26]
+ wire [63:0] amoalu_io_lhs; // @[DCache.scala 956:26]
+ wire [63:0] amoalu_io_rhs; // @[DCache.scala 956:26]
+ wire [63:0] amoalu_io_out_unmasked; // @[DCache.scala 956:26]
+ wire s1_valid_x12 = io_cpu_req_ready & io_cpu_req_valid; // @[Decoupled.scala 50:35]
+ reg s1_valid; // @[DCache.scala 162:21]
+ wire s1_valid_masked = s1_valid & ~io_cpu_s1_kill; // @[DCache.scala 166:34]
+ reg [4:0] s1_req_cmd; // @[Reg.scala 16:16]
+ wire _s1_read_T = s1_req_cmd == 5'h0; // @[package.scala 15:47]
+ wire _s1_read_T_1 = s1_req_cmd == 5'h10; // @[package.scala 15:47]
+ wire _s1_read_T_2 = s1_req_cmd == 5'h6; // @[package.scala 15:47]
+ wire _s1_read_T_3 = s1_req_cmd == 5'h7; // @[package.scala 15:47]
+ wire _s1_read_T_6 = _s1_read_T | _s1_read_T_1 | _s1_read_T_2 | _s1_read_T_3; // @[package.scala 72:59]
+ wire _s1_read_T_7 = s1_req_cmd == 5'h4; // @[package.scala 15:47]
+ wire _s1_read_T_8 = s1_req_cmd == 5'h9; // @[package.scala 15:47]
+ wire _s1_read_T_9 = s1_req_cmd == 5'ha; // @[package.scala 15:47]
+ wire _s1_read_T_10 = s1_req_cmd == 5'hb; // @[package.scala 15:47]
+ wire _s1_read_T_13 = _s1_read_T_7 | _s1_read_T_8 | _s1_read_T_9 | _s1_read_T_10; // @[package.scala 72:59]
+ wire _s1_read_T_14 = s1_req_cmd == 5'h8; // @[package.scala 15:47]
+ wire _s1_read_T_15 = s1_req_cmd == 5'hc; // @[package.scala 15:47]
+ wire _s1_read_T_16 = s1_req_cmd == 5'hd; // @[package.scala 15:47]
+ wire _s1_read_T_17 = s1_req_cmd == 5'he; // @[package.scala 15:47]
+ wire _s1_read_T_18 = s1_req_cmd == 5'hf; // @[package.scala 15:47]
+ wire _s1_read_T_22 = _s1_read_T_14 | _s1_read_T_15 | _s1_read_T_16 | _s1_read_T_17 | _s1_read_T_18; // @[package.scala 72:59]
+ wire _s1_read_T_23 = _s1_read_T_13 | _s1_read_T_22; // @[Consts.scala 82:44]
+ wire s1_read = _s1_read_T_6 | _s1_read_T_23; // @[Consts.scala 84:68]
+ reg s2_valid; // @[DCache.scala 306:21]
+ reg [4:0] s2_req_cmd; // @[DCache.scala 314:19]
+ wire _s2_write_T_1 = s2_req_cmd == 5'h11; // @[Consts.scala 85:49]
+ wire _s2_write_T_3 = s2_req_cmd == 5'h7; // @[Consts.scala 85:66]
+ wire _s2_write_T_5 = s2_req_cmd == 5'h4; // @[package.scala 15:47]
+ wire _s2_write_T_6 = s2_req_cmd == 5'h9; // @[package.scala 15:47]
+ wire _s2_write_T_7 = s2_req_cmd == 5'ha; // @[package.scala 15:47]
+ wire _s2_write_T_8 = s2_req_cmd == 5'hb; // @[package.scala 15:47]
+ wire _s2_write_T_11 = _s2_write_T_5 | _s2_write_T_6 | _s2_write_T_7 | _s2_write_T_8; // @[package.scala 72:59]
+ wire _s2_write_T_12 = s2_req_cmd == 5'h8; // @[package.scala 15:47]
+ wire _s2_write_T_13 = s2_req_cmd == 5'hc; // @[package.scala 15:47]
+ wire _s2_write_T_14 = s2_req_cmd == 5'hd; // @[package.scala 15:47]
+ wire _s2_write_T_15 = s2_req_cmd == 5'he; // @[package.scala 15:47]
+ wire _s2_write_T_16 = s2_req_cmd == 5'hf; // @[package.scala 15:47]
+ wire _s2_write_T_20 = _s2_write_T_12 | _s2_write_T_13 | _s2_write_T_14 | _s2_write_T_15 | _s2_write_T_16; // @[package.scala 72:59]
+ wire _s2_write_T_21 = _s2_write_T_11 | _s2_write_T_20; // @[Consts.scala 82:44]
+ wire s2_write = s2_req_cmd == 5'h1 | s2_req_cmd == 5'h11 | s2_req_cmd == 5'h7 | _s2_write_T_21; // @[Consts.scala 85:76]
+ reg pstore1_held; // @[DCache.scala 479:29]
+ wire pstore1_valid_likely = s2_valid & s2_write | pstore1_held; // @[DCache.scala 480:51]
+ reg [33:0] pstore1_addr; // @[Reg.scala 16:16]
+ reg [33:0] s1_req_addr; // @[Reg.scala 16:16]
+ wire [33:0] s1_vaddr = {s1_req_addr[33:14],s1_req_addr[13:0]}; // @[Cat.scala 31:58]
+ wire _s1_write_T_1 = s1_req_cmd == 5'h11; // @[Consts.scala 85:49]
+ wire s1_write = s1_req_cmd == 5'h1 | s1_req_cmd == 5'h11 | _s1_read_T_3 | _s1_read_T_23; // @[Consts.scala 85:76]
+ reg [7:0] pstore1_mask; // @[Reg.scala 16:16]
+ wire _s1_hazard_T_18 = |pstore1_mask[7]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_17 = |pstore1_mask[6]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_16 = |pstore1_mask[5]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_15 = |pstore1_mask[4]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_14 = |pstore1_mask[3]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_13 = |pstore1_mask[2]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_12 = |pstore1_mask[1]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_11 = |pstore1_mask[0]; // @[DCache.scala 1155:66]
+ wire [7:0] _s1_hazard_T_19 = {_s1_hazard_T_18,_s1_hazard_T_17,_s1_hazard_T_16,_s1_hazard_T_15,_s1_hazard_T_14,
+ _s1_hazard_T_13,_s1_hazard_T_12,_s1_hazard_T_11}; // @[Cat.scala 31:58]
+ wire [7:0] _s1_hazard_T_28 = {_s1_hazard_T_19[7],_s1_hazard_T_19[6],_s1_hazard_T_19[5],_s1_hazard_T_19[4],
+ _s1_hazard_T_19[3],_s1_hazard_T_19[2],_s1_hazard_T_19[1],_s1_hazard_T_19[0]}; // @[Cat.scala 31:58]
+ reg [1:0] s1_req_size; // @[Reg.scala 16:16]
+ wire s1_mask_xwr_upper = s1_req_addr[0] | s1_req_size >= 2'h1; // @[AMOALU.scala 17:46]
+ wire s1_mask_xwr_lower = s1_req_addr[0] ? 1'h0 : 1'h1; // @[AMOALU.scala 18:22]
+ wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper,s1_mask_xwr_lower}; // @[Cat.scala 31:58]
+ wire [1:0] _s1_mask_xwr_upper_T_5 = s1_req_addr[1] ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala 17:22]
+ wire [1:0] _s1_mask_xwr_upper_T_7 = s1_req_size >= 2'h2 ? 2'h3 : 2'h0; // @[AMOALU.scala 17:51]
+ wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 | _s1_mask_xwr_upper_T_7; // @[AMOALU.scala 17:46]
+ wire [1:0] s1_mask_xwr_lower_1 = s1_req_addr[1] ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala 18:22]
+ wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1,s1_mask_xwr_lower_1}; // @[Cat.scala 31:58]
+ wire [3:0] _s1_mask_xwr_upper_T_9 = s1_req_addr[2] ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala 17:22]
+ wire [3:0] _s1_mask_xwr_upper_T_11 = s1_req_size >= 2'h3 ? 4'hf : 4'h0; // @[AMOALU.scala 17:51]
+ wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 | _s1_mask_xwr_upper_T_11; // @[AMOALU.scala 17:46]
+ wire [3:0] s1_mask_xwr_lower_2 = s1_req_addr[2] ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala 18:22]
+ wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2,s1_mask_xwr_lower_2}; // @[Cat.scala 31:58]
+ wire _s1_hazard_T_44 = |s1_mask_xwr[7]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_43 = |s1_mask_xwr[6]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_42 = |s1_mask_xwr[5]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_41 = |s1_mask_xwr[4]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_40 = |s1_mask_xwr[3]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_39 = |s1_mask_xwr[2]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_38 = |s1_mask_xwr[1]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_37 = |s1_mask_xwr[0]; // @[DCache.scala 1155:66]
+ wire [7:0] _s1_hazard_T_45 = {_s1_hazard_T_44,_s1_hazard_T_43,_s1_hazard_T_42,_s1_hazard_T_41,_s1_hazard_T_40,
+ _s1_hazard_T_39,_s1_hazard_T_38,_s1_hazard_T_37}; // @[Cat.scala 31:58]
+ wire [7:0] _s1_hazard_T_54 = {_s1_hazard_T_45[7],_s1_hazard_T_45[6],_s1_hazard_T_45[5],_s1_hazard_T_45[4],
+ _s1_hazard_T_45[3],_s1_hazard_T_45[2],_s1_hazard_T_45[1],_s1_hazard_T_45[0]}; // @[Cat.scala 31:58]
+ wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala 537:38]
+ wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala 537:77]
+ wire _s1_hazard_T_59 = s1_write ? |_s1_hazard_T_55 : |_s1_hazard_T_57; // @[DCache.scala 537:8]
+ wire _s1_hazard_T_60 = pstore1_addr[13:3] == s1_vaddr[13:3] & _s1_hazard_T_59; // @[DCache.scala 536:65]
+ reg pstore2_valid; // @[DCache.scala 476:30]
+ reg [33:0] pstore2_addr; // @[Reg.scala 16:16]
+ reg [7:0] mask; // @[DCache.scala 506:19]
+ wire _s1_hazard_T_80 = |mask[7]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_79 = |mask[6]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_78 = |mask[5]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_77 = |mask[4]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_76 = |mask[3]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_75 = |mask[2]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_74 = |mask[1]; // @[DCache.scala 1155:66]
+ wire _s1_hazard_T_73 = |mask[0]; // @[DCache.scala 1155:66]
+ wire [7:0] _s1_hazard_T_81 = {_s1_hazard_T_80,_s1_hazard_T_79,_s1_hazard_T_78,_s1_hazard_T_77,_s1_hazard_T_76,
+ _s1_hazard_T_75,_s1_hazard_T_74,_s1_hazard_T_73}; // @[Cat.scala 31:58]
+ wire [7:0] _s1_hazard_T_90 = {_s1_hazard_T_81[7],_s1_hazard_T_81[6],_s1_hazard_T_81[5],_s1_hazard_T_81[4],
+ _s1_hazard_T_81[3],_s1_hazard_T_81[2],_s1_hazard_T_81[1],_s1_hazard_T_81[0]}; // @[Cat.scala 31:58]
+ wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_54; // @[DCache.scala 537:38]
+ wire [7:0] _s1_hazard_T_119 = mask & s1_mask_xwr; // @[DCache.scala 537:77]
+ wire _s1_hazard_T_121 = s1_write ? |_s1_hazard_T_117 : |_s1_hazard_T_119; // @[DCache.scala 537:8]
+ wire _s1_hazard_T_122 = pstore2_addr[13:3] == s1_vaddr[13:3] & _s1_hazard_T_121; // @[DCache.scala 536:65]
+ wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala 540:21]
+ wire s1_hazard = pstore1_valid_likely & _s1_hazard_T_60 | _s1_hazard_T_123; // @[DCache.scala 539:69]
+ wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala 541:31]
+ wire [7:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ma_ld,io_cpu_s2_xcpt_ma_st,io_cpu_s2_xcpt_pf_ld,io_cpu_s2_xcpt_pf_st,
+ io_cpu_s2_xcpt_gf_ld,io_cpu_s2_xcpt_gf_st,io_cpu_s2_xcpt_ae_ld,io_cpu_s2_xcpt_ae_st}; // @[DCache.scala 307:54]
+ wire s2_valid_no_xcpt = s2_valid & ~(|_s2_valid_no_xcpt_T); // @[DCache.scala 307:35]
+ reg s2_not_nacked_in_s1; // @[DCache.scala 310:36]
+ wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala 312:42]
+ wire _c_cat_T_48 = s2_req_cmd == 5'h6; // @[Consts.scala 86:71]
+ wire _c_cat_T_49 = s2_write | s2_req_cmd == 5'h3 | s2_req_cmd == 5'h6; // @[Consts.scala 86:64]
+ reg [1:0] s2_hit_state_state; // @[Reg.scala 16:16]
+ wire [3:0] _T_35 = {s2_write,_c_cat_T_49,s2_hit_state_state}; // @[Cat.scala 31:58]
+ wire _T_93 = 4'h3 == _T_35; // @[Misc.scala 48:20]
+ wire _T_90 = 4'h2 == _T_35; // @[Misc.scala 48:20]
+ wire _T_87 = 4'h1 == _T_35; // @[Misc.scala 48:20]
+ wire _T_84 = 4'h7 == _T_35; // @[Misc.scala 48:20]
+ wire _T_81 = 4'h6 == _T_35; // @[Misc.scala 48:20]
+ wire _T_78 = 4'hf == _T_35; // @[Misc.scala 48:20]
+ wire _T_75 = 4'he == _T_35; // @[Misc.scala 48:20]
+ wire _T_72 = 4'h0 == _T_35; // @[Misc.scala 48:20]
+ wire _T_69 = 4'h5 == _T_35; // @[Misc.scala 48:20]
+ wire _T_66 = 4'h4 == _T_35; // @[Misc.scala 48:20]
+ wire _T_63 = 4'hd == _T_35; // @[Misc.scala 48:20]
+ wire _T_60 = 4'hc == _T_35; // @[Misc.scala 48:20]
+ wire s2_hit = _T_93 | (_T_90 | (_T_87 | (_T_84 | (_T_81 | (_T_78 | _T_75))))); // @[Misc.scala 34:9]
+ wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked & s2_hit; // @[DCache.scala 372:89]
+ wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala 15:47]
+ wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala 15:47]
+ wire _s2_read_T_6 = _s2_read_T | _s2_read_T_1 | _c_cat_T_48 | _s2_write_T_3; // @[package.scala 72:59]
+ wire s2_read = _s2_read_T_6 | _s2_write_T_21; // @[Consts.scala 84:68]
+ wire s2_readwrite = s2_read | s2_write; // @[DCache.scala 329:30]
+ wire s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala 393:89]
+ wire [1:0] _T_62 = _T_60 ? 2'h1 : 2'h0; // @[Misc.scala 34:36]
+ wire [1:0] _T_65 = _T_63 ? 2'h2 : _T_62; // @[Misc.scala 34:36]
+ wire [1:0] _T_68 = _T_66 ? 2'h1 : _T_65; // @[Misc.scala 34:36]
+ wire [1:0] _T_71 = _T_69 ? 2'h2 : _T_68; // @[Misc.scala 34:36]
+ wire [1:0] _T_74 = _T_72 ? 2'h0 : _T_71; // @[Misc.scala 34:36]
+ wire [1:0] _T_77 = _T_75 ? 2'h3 : _T_74; // @[Misc.scala 34:36]
+ wire [1:0] _T_80 = _T_78 ? 2'h3 : _T_77; // @[Misc.scala 34:36]
+ wire [1:0] _T_83 = _T_81 ? 2'h2 : _T_80; // @[Misc.scala 34:36]
+ wire [1:0] _T_86 = _T_84 ? 2'h3 : _T_83; // @[Misc.scala 34:36]
+ wire [1:0] _T_89 = _T_87 ? 2'h1 : _T_86; // @[Misc.scala 34:36]
+ wire [1:0] _T_92 = _T_90 ? 2'h2 : _T_89; // @[Misc.scala 34:36]
+ wire [1:0] s2_grow_param = _T_93 ? 2'h3 : _T_92; // @[Misc.scala 34:36]
+ wire _s2_update_meta_T = s2_hit_state_state == s2_grow_param; // @[Metadata.scala 45:46]
+ wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala 46:40]
+ wire _T_227 = io_cpu_s2_nack | s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[DCache.scala 421:24]
+ reg s1_req_no_xcpt; // @[Reg.scala 16:16]
+ wire s1_readwrite = s1_read | s1_write; // @[DCache.scala 192:30]
+ wire s1_flush_line = s1_req_cmd == 5'h5 & s1_req_size[0]; // @[DCache.scala 194:50]
+ wire s1_cmd_uses_tlb = s1_readwrite | s1_flush_line | s1_req_cmd == 5'h17; // @[DCache.scala 250:55]
+ wire s1_nack = s1_valid & s1_raw_hazard | _T_227; // @[DCache.scala 546:{36,46}]
+ wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala 167:41]
+ wire s1_valid_not_nacked = s1_valid & ~s1_nack; // @[DCache.scala 167:38]
+ wire s0_clk_en = metaArb_io_out_valid & ~metaArb_io_out_bits_write; // @[DCache.scala 170:40]
+ wire [33:0] s0_req_addr = {metaArb_io_out_bits_addr[33:6],io_cpu_req_bits_addr[5:0]}; // @[Cat.scala 31:58]
+ wire _T = ~metaArb_io_in_7_ready; // @[DCache.scala 175:9]
+ reg [6:0] s1_req_tag; // @[Reg.scala 16:16]
+ reg s1_req_signed; // @[Reg.scala 16:16]
+ reg [1:0] s1_req_dprv; // @[Reg.scala 16:16]
+ reg [33:0] s1_tlb_req_vaddr; // @[Reg.scala 16:16]
+ reg [1:0] s1_tlb_req_size; // @[Reg.scala 16:16]
+ reg [4:0] s1_tlb_req_cmd; // @[Reg.scala 16:16]
+ reg [1:0] s1_tlb_req_prv; // @[Reg.scala 16:16]
+ wire s1_sfence = s1_req_cmd == 5'h14 | s1_req_cmd == 5'h15 | s1_req_cmd == 5'h16; // @[DCache.scala 193:71]
+ reg s1_flush_valid; // @[DCache.scala 195:27]
+ reg uncachedInFlight_0; // @[DCache.scala 216:33]
+ reg [33:0] uncachedReqs_0_addr; // @[DCache.scala 217:25]
+ reg [6:0] uncachedReqs_0_tag; // @[DCache.scala 217:25]
+ reg [1:0] uncachedReqs_0_size; // @[DCache.scala 217:25]
+ reg uncachedReqs_0_signed; // @[DCache.scala 217:25]
+ wire _s0_read_T = io_cpu_req_bits_cmd == 5'h0; // @[package.scala 15:47]
+ wire _s0_read_T_1 = io_cpu_req_bits_cmd == 5'h10; // @[package.scala 15:47]
+ wire _s0_read_T_2 = io_cpu_req_bits_cmd == 5'h6; // @[package.scala 15:47]
+ wire _s0_read_T_3 = io_cpu_req_bits_cmd == 5'h7; // @[package.scala 15:47]
+ wire _s0_read_T_6 = _s0_read_T | _s0_read_T_1 | _s0_read_T_2 | _s0_read_T_3; // @[package.scala 72:59]
+ wire _s0_read_T_7 = io_cpu_req_bits_cmd == 5'h4; // @[package.scala 15:47]
+ wire _s0_read_T_8 = io_cpu_req_bits_cmd == 5'h9; // @[package.scala 15:47]
+ wire _s0_read_T_9 = io_cpu_req_bits_cmd == 5'ha; // @[package.scala 15:47]
+ wire _s0_read_T_10 = io_cpu_req_bits_cmd == 5'hb; // @[package.scala 15:47]
+ wire _s0_read_T_13 = _s0_read_T_7 | _s0_read_T_8 | _s0_read_T_9 | _s0_read_T_10; // @[package.scala 72:59]
+ wire _s0_read_T_14 = io_cpu_req_bits_cmd == 5'h8; // @[package.scala 15:47]
+ wire _s0_read_T_15 = io_cpu_req_bits_cmd == 5'hc; // @[package.scala 15:47]
+ wire _s0_read_T_16 = io_cpu_req_bits_cmd == 5'hd; // @[package.scala 15:47]
+ wire _s0_read_T_17 = io_cpu_req_bits_cmd == 5'he; // @[package.scala 15:47]
+ wire _s0_read_T_18 = io_cpu_req_bits_cmd == 5'hf; // @[package.scala 15:47]
+ wire _s0_read_T_22 = _s0_read_T_14 | _s0_read_T_15 | _s0_read_T_16 | _s0_read_T_17 | _s0_read_T_18; // @[package.scala 72:59]
+ wire _s0_read_T_23 = _s0_read_T_13 | _s0_read_T_22; // @[Consts.scala 82:44]
+ wire s0_read = _s0_read_T_6 | _s0_read_T_23; // @[Consts.scala 84:68]
+ wire _dataArb_io_in_3_valid_res_T = io_cpu_req_bits_cmd == 5'h1; // @[package.scala 15:47]
+ wire _dataArb_io_in_3_valid_res_T_1 = io_cpu_req_bits_cmd == 5'h3; // @[package.scala 15:47]
+ wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T | _dataArb_io_in_3_valid_res_T_1; // @[package.scala 72:59]
+ wire res = ~_dataArb_io_in_3_valid_res_T_2; // @[DCache.scala 1159:15]
+ wire _dataArb_io_in_3_valid_T_26 = io_cpu_req_bits_cmd == 5'h11; // @[Consts.scala 85:49]
+ wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_res_T | io_cpu_req_bits_cmd == 5'h11 | _s0_read_T_3 |
+ _s0_read_T_23; // @[Consts.scala 85:76]
+ wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_26; // @[DCache.scala 1165:23]
+ wire _dataArb_io_in_3_valid_T_52 = s0_read | _dataArb_io_in_3_valid_T_51; // @[DCache.scala 1164:21]
+ wire _dataArb_io_in_3_valid_T_56 = ~reset; // @[DCache.scala 1160:11]
+ wire _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid & res; // @[DCache.scala 222:46]
+ wire [33:0] _dataArb_io_in_3_bits_addr_T_2 = {io_cpu_req_bits_addr[33:14],io_cpu_req_bits_addr[13:0]}; // @[Cat.scala 31:58]
+ wire _GEN_33 = ~dataArb_io_in_3_ready & s0_read ? 1'h0 : _s1_valid_not_nacked_T; // @[DCache.scala 213:20 238:{45,64}]
+ wire _s1_did_read_T_54 = dataArb_io_in_3_ready & (io_cpu_req_valid & _dataArb_io_in_3_valid_T_52); // @[DCache.scala 239:54]
+ reg s1_did_read; // @[Reg.scala 16:16]
+ reg s1_read_mask; // @[Reg.scala 16:16]
+ wire _GEN_36 = _T ? 1'h0 : _GEN_33; // @[DCache.scala 247:{34,53}]
+ wire [31:0] s1_paddr = {tlb_io_resp_paddr[31:12],s1_req_addr[11:0]}; // @[Cat.scala 31:58]
+ wire inScratchpad = s1_paddr >= 32'h80000000 & s1_paddr < 32'h80004000; // @[DCache.scala 278:47]
+ wire [63:0] _tl_d_data_encoded_T_8 = {auto_out_d_bits_data[63:56],auto_out_d_bits_data[55:48],auto_out_d_bits_data[47:
+ 40],auto_out_d_bits_data[39:32],auto_out_d_bits_data[31:24],auto_out_d_bits_data[23:16],auto_out_d_bits_data[15:8],
+ auto_out_d_bits_data[7:0]}; // @[Cat.scala 31:58]
+ wire [7:0] _T_27 = ~io_cpu_s1_data_mask; // @[DCache.scala 304:71]
+ wire [7:0] _T_28 = s1_mask_xwr | _T_27; // @[DCache.scala 304:69]
+ wire s2_valid_x44 = s1_valid_masked & ~s1_sfence; // @[DCache.scala 306:43]
+ reg [33:0] s2_req_addr; // @[DCache.scala 314:19]
+ reg [6:0] s2_req_tag; // @[DCache.scala 314:19]
+ reg [1:0] s2_req_size; // @[DCache.scala 314:19]
+ reg s2_req_signed; // @[DCache.scala 314:19]
+ reg [1:0] s2_req_dprv; // @[DCache.scala 314:19]
+ reg s2_req_no_xcpt; // @[DCache.scala 314:19]
+ reg s2_tlb_xcpt_pf_ld; // @[DCache.scala 317:24]
+ reg s2_tlb_xcpt_pf_st; // @[DCache.scala 317:24]
+ reg s2_tlb_xcpt_ae_ld; // @[DCache.scala 317:24]
+ reg s2_tlb_xcpt_ae_st; // @[DCache.scala 317:24]
+ reg s2_tlb_xcpt_ma_ld; // @[DCache.scala 317:24]
+ reg s2_tlb_xcpt_ma_st; // @[DCache.scala 317:24]
+ reg [33:0] s2_uncached_resp_addr; // @[DCache.scala 319:34]
+ wire _T_34 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala 320:29]
+ wire [33:0] _GEN_40 = s1_valid_not_nacked | s1_flush_valid ? {{2'd0}, s1_paddr} : s2_req_addr; // @[DCache.scala 320:48 322:17 314:19]
+ wire [6:0] _GEN_41 = s1_valid_not_nacked | s1_flush_valid ? s1_req_tag : s2_req_tag; // @[DCache.scala 320:48 321:12 314:19]
+ wire [4:0] _GEN_42 = s1_valid_not_nacked | s1_flush_valid ? s1_req_cmd : s2_req_cmd; // @[DCache.scala 320:48 321:12 314:19]
+ wire [1:0] _GEN_43 = s1_valid_not_nacked | s1_flush_valid ? s1_req_size : s2_req_size; // @[DCache.scala 320:48 321:12 314:19]
+ wire _GEN_44 = s1_valid_not_nacked | s1_flush_valid ? s1_req_signed : s2_req_signed; // @[DCache.scala 320:48 321:12 314:19]
+ reg [33:0] s2_vaddr_r; // @[Reg.scala 16:16]
+ wire [33:0] s2_vaddr = {s2_vaddr_r[33:14],s2_req_addr[13:0]}; // @[Cat.scala 31:58]
+ reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala 330:43]
+ wire en = s1_valid | io_cpu_replay_next; // @[DCache.scala 341:38]
+ wire word_en = s1_did_read & s1_read_mask; // @[DCache.scala 342:63]
+ wire [63:0] s1_all_data_ways_0 = data_io_resp_0; // @[DCache.scala 300:{29,29}]
+ wire s1_word_en = ~io_cpu_replay_next ? word_en : 1'h1; // @[DCache.scala 352:27]
+ wire [1:0] opc = auto_out_d_bits_opcode[1:0]; // @[DCache.scala 631:26]
+ wire [1:0] _T_261 = opc & 2'h1; // @[Decode.scala 14:65]
+ wire data_1 = _T_261 == 2'h1; // @[Decode.scala 14:121]
+ reg blockUncachedGrant; // @[DCache.scala 725:33]
+ wire [2:0] _GEN_248 = {{1'd0}, opc}; // @[DCache.scala 641:29]
+ wire grantIsRefill = _GEN_248 == 3'h5; // @[DCache.scala 641:29]
+ wire _T_288 = ~dataArb_io_in_1_ready; // @[DCache.scala 697:26]
+ wire _grantIsCached_T = _GEN_248 == 3'h4; // @[package.scala 15:47]
+ wire grantIsCached = _grantIsCached_T | grantIsRefill; // @[package.scala 72:59]
+ reg [8:0] counter; // @[Edges.scala 228:27]
+ wire d_first = counter == 9'h0; // @[Edges.scala 230:25]
+ wire _bundleOut_0_d_ready_T_3 = grantIsCached ? ~d_first : 1'h1; // @[DCache.scala 646:24]
+ wire _GEN_227 = grantIsRefill & ~dataArb_io_in_1_ready ? 1'h0 : _bundleOut_0_d_ready_T_3; // @[DCache.scala 646:18 697:51 699:20]
+ wire tl_out__d_ready = data_1 & (blockUncachedGrant | s1_valid) ? 1'h0 : _GEN_227; // @[DCache.scala 727:68 728:22]
+ wire _T_265 = tl_out__d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [1:0] _GEN_184 = data_1 ? 2'h2 : 2'h1; // @[DCache.scala 666:34 669:25]
+ wire [1:0] _GEN_206 = grantIsCached ? 2'h1 : _GEN_184; // @[DCache.scala 650:26]
+ wire [1:0] s1_data_way = _T_265 ? _GEN_206 : 2'h1; // @[DCache.scala 649:26]
+ wire [1:0] _s2_data_T_1 = s1_word_en ? s1_data_way : 2'h0; // @[DCache.scala 354:28]
+ wire [63:0] _s2_data_T_4 = _s2_data_T_1[0] ? s1_all_data_ways_0 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _s2_data_T_5 = _s2_data_T_1[1] ? _tl_d_data_encoded_T_8 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _s2_data_T_6 = _s2_data_T_4 | _s2_data_T_5; // @[Mux.scala 27:73]
+ reg [63:0] s2_data; // @[Reg.scala 16:16]
+ wire s2_hit_valid = s2_hit_state_state > 2'h0; // @[Metadata.scala 49:45]
+ wire [31:0] s2_data_corrected_lo = {s2_data[31:24],s2_data[23:16],s2_data[15:8],s2_data[7:0]}; // @[Cat.scala 31:58]
+ wire [31:0] s2_data_corrected_hi = {s2_data[63:56],s2_data[55:48],s2_data[47:40],s2_data[39:32]}; // @[Cat.scala 31:58]
+ wire [63:0] s2_data_corrected = {s2_data[63:56],s2_data[55:48],s2_data[47:40],s2_data[39:32],s2_data[31:24],s2_data[23
+ :16],s2_data[15:8],s2_data[7:0]}; // @[Cat.scala 31:58]
+ wire s2_valid_miss = s2_valid_masked & s2_readwrite & ~s2_hit; // @[DCache.scala 398:73]
+ wire _s2_valid_cached_miss_T_2 = |uncachedInFlight_0; // @[DCache.scala 400:88]
+ wire s2_valid_cached_miss = 1'h0; // @[DCache.scala 400:60]
+ wire _s2_cannot_victimize_T = ~s2_flush_valid_pre_tag_ecc; // @[DCache.scala 403:29]
+ wire s2_valid_uncached_pending = s2_valid_miss & ~(&uncachedInFlight_0); // @[DCache.scala 405:64]
+ wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : 2'h0; // @[DCache.scala 409:28]
+ wire [3:0] _T_167 = {2'h2,s2_victim_state_state}; // @[Cat.scala 31:58]
+ wire _T_192 = 4'hb == _T_167; // @[Misc.scala 55:20]
+ wire _T_196 = 4'h4 == _T_167; // @[Misc.scala 55:20]
+ wire _T_197 = _T_196 ? 1'h0 : _T_192; // @[Misc.scala 37:9]
+ wire _T_200 = 4'h5 == _T_167; // @[Misc.scala 55:20]
+ wire _T_201 = _T_200 ? 1'h0 : _T_197; // @[Misc.scala 37:9]
+ wire _T_204 = 4'h6 == _T_167; // @[Misc.scala 55:20]
+ wire _T_205 = _T_204 ? 1'h0 : _T_201; // @[Misc.scala 37:9]
+ wire _T_208 = 4'h7 == _T_167; // @[Misc.scala 55:20]
+ wire _T_212 = 4'h0 == _T_167; // @[Misc.scala 55:20]
+ wire _T_213 = _T_212 ? 1'h0 : _T_208 | _T_205; // @[Misc.scala 37:9]
+ wire _T_216 = 4'h1 == _T_167; // @[Misc.scala 55:20]
+ wire _T_217 = _T_216 ? 1'h0 : _T_213; // @[Misc.scala 37:9]
+ wire _T_220 = 4'h2 == _T_167; // @[Misc.scala 55:20]
+ wire _T_221 = _T_220 ? 1'h0 : _T_217; // @[Misc.scala 37:9]
+ wire _T_224 = 4'h3 == _T_167; // @[Misc.scala 55:20]
+ wire s2_victim_dirty = _T_224 | _T_221; // @[Misc.scala 37:9]
+ wire s2_dont_nack_uncached = s2_valid_uncached_pending & auto_out_a_ready; // @[DCache.scala 415:57]
+ wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala 419:17]
+ wire s2_dont_nack_misc = s2_valid_masked & _s2_dont_nack_misc_T_10; // @[DCache.scala 416:61]
+ wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala 420:89]
+ wire _pstore1_cmd_T = s1_valid_not_nacked & s1_write; // @[DCache.scala 467:63]
+ reg [4:0] pstore1_cmd; // @[Reg.scala 16:16]
+ reg [63:0] pstore1_data; // @[Reg.scala 16:16]
+ wire _pstore1_rmw_T_51 = s1_write & _s1_write_T_1; // @[DCache.scala 1165:23]
+ wire _pstore1_rmw_T_52 = s1_read | _pstore1_rmw_T_51; // @[DCache.scala 1164:21]
+ reg pstore1_rmw_r; // @[Reg.scala 16:16]
+ wire _pstore1_merge_T = s2_valid_hit_pre_data_ecc_and_waw & s2_write; // @[DCache.scala 465:46]
+ wire pstore_drain_opportunistic = ~_dataArb_io_in_3_valid_T_58; // @[DCache.scala 477:36]
+ reg pstore_drain_on_miss_REG; // @[DCache.scala 478:56]
+ wire pstore1_valid = _pstore1_merge_T | pstore1_held; // @[DCache.scala 482:38]
+ wire pstore_drain_structural = pstore1_valid_likely & pstore2_valid & (s1_valid & s1_write | pstore1_rmw_r); // @[DCache.scala 484:71]
+ wire _pstore_drain_T_10 = (pstore1_valid & ~pstore1_rmw_r | pstore2_valid) & (pstore_drain_opportunistic |
+ pstore_drain_on_miss_REG); // @[DCache.scala 493:76]
+ wire pstore_drain = pstore_drain_structural | _pstore_drain_T_10; // @[DCache.scala 492:48]
+ wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala 496:91]
+ wire advance_pstore1 = pstore1_valid & pstore2_valid == pstore_drain; // @[DCache.scala 497:61]
+ wire [7:0] _pstore1_storegen_data_mask_T_24 = pstore1_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _pstore1_storegen_data_mask_T_22 = pstore1_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _pstore1_storegen_data_mask_T_20 = pstore1_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _pstore1_storegen_data_mask_T_18 = pstore1_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _pstore1_storegen_data_mask_T_16 = pstore1_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _pstore1_storegen_data_mask_T_14 = pstore1_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _pstore1_storegen_data_mask_T_12 = pstore1_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _pstore1_storegen_data_mask_T_10 = pstore1_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] mask_1 = {_pstore1_storegen_data_mask_T_24,_pstore1_storegen_data_mask_T_22,
+ _pstore1_storegen_data_mask_T_20,_pstore1_storegen_data_mask_T_18,_pstore1_storegen_data_mask_T_16,
+ _pstore1_storegen_data_mask_T_14,_pstore1_storegen_data_mask_T_12,_pstore1_storegen_data_mask_T_10}; // @[Cat.scala 31:58]
+ wire [63:0] _pstore1_storegen_data_T = amoalu_io_out_unmasked & mask_1; // @[DCache.scala 965:45]
+ wire [63:0] _pstore1_storegen_data_T_1 = ~mask_1; // @[DCache.scala 965:79]
+ wire [63:0] _pstore1_storegen_data_T_2 = s2_data_corrected & _pstore1_storegen_data_T_1; // @[DCache.scala 965:77]
+ wire [63:0] pstore1_storegen_data = _pstore1_storegen_data_T | _pstore1_storegen_data_T_2; // @[DCache.scala 965:52]
+ reg [7:0] pstore2_storegen_data_r; // @[Reg.scala 16:16]
+ reg [7:0] pstore2_storegen_data_r_1; // @[Reg.scala 16:16]
+ reg [7:0] pstore2_storegen_data_r_2; // @[Reg.scala 16:16]
+ reg [7:0] pstore2_storegen_data_r_3; // @[Reg.scala 16:16]
+ reg [7:0] pstore2_storegen_data_r_4; // @[Reg.scala 16:16]
+ reg [7:0] pstore2_storegen_data_r_5; // @[Reg.scala 16:16]
+ reg [7:0] pstore2_storegen_data_r_6; // @[Reg.scala 16:16]
+ reg [7:0] pstore2_storegen_data_r_7; // @[Reg.scala 16:16]
+ wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_r_7,pstore2_storegen_data_r_6,pstore2_storegen_data_r_5,
+ pstore2_storegen_data_r_4,pstore2_storegen_data_r_3,pstore2_storegen_data_r_2,pstore2_storegen_data_r_1,
+ pstore2_storegen_data_r}; // @[Cat.scala 31:58]
+ wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore1_mask; // @[DCache.scala 509:37]
+ wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T; // @[DCache.scala 509:15]
+ wire [33:0] _dataArb_io_in_0_bits_addr_T = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala 524:36]
+ wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[DCache.scala 526:63]
+ wire [31:0] dataArb_io_in_0_bits_wdata_lo = {_dataArb_io_in_0_bits_wdata_T[31:24],_dataArb_io_in_0_bits_wdata_T[23:16]
+ ,_dataArb_io_in_0_bits_wdata_T[15:8],_dataArb_io_in_0_bits_wdata_T[7:0]}; // @[Cat.scala 31:58]
+ wire [31:0] dataArb_io_in_0_bits_wdata_hi = {_dataArb_io_in_0_bits_wdata_T[63:56],_dataArb_io_in_0_bits_wdata_T[55:48]
+ ,_dataArb_io_in_0_bits_wdata_T[47:40],_dataArb_io_in_0_bits_wdata_T[39:32]}; // @[Cat.scala 31:58]
+ wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? mask : pstore1_mask; // @[DCache.scala 532:47]
+ wire _dataArb_io_in_0_bits_eccMask_T_9 = |_dataArb_io_in_0_bits_eccMask_T[0]; // @[DCache.scala 1155:66]
+ wire _dataArb_io_in_0_bits_eccMask_T_10 = |_dataArb_io_in_0_bits_eccMask_T[1]; // @[DCache.scala 1155:66]
+ wire _dataArb_io_in_0_bits_eccMask_T_11 = |_dataArb_io_in_0_bits_eccMask_T[2]; // @[DCache.scala 1155:66]
+ wire _dataArb_io_in_0_bits_eccMask_T_12 = |_dataArb_io_in_0_bits_eccMask_T[3]; // @[DCache.scala 1155:66]
+ wire _dataArb_io_in_0_bits_eccMask_T_13 = |_dataArb_io_in_0_bits_eccMask_T[4]; // @[DCache.scala 1155:66]
+ wire _dataArb_io_in_0_bits_eccMask_T_14 = |_dataArb_io_in_0_bits_eccMask_T[5]; // @[DCache.scala 1155:66]
+ wire _dataArb_io_in_0_bits_eccMask_T_15 = |_dataArb_io_in_0_bits_eccMask_T[6]; // @[DCache.scala 1155:66]
+ wire _dataArb_io_in_0_bits_eccMask_T_16 = |_dataArb_io_in_0_bits_eccMask_T[7]; // @[DCache.scala 1155:66]
+ wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {_dataArb_io_in_0_bits_eccMask_T_12,_dataArb_io_in_0_bits_eccMask_T_11,
+ _dataArb_io_in_0_bits_eccMask_T_10,_dataArb_io_in_0_bits_eccMask_T_9}; // @[Cat.scala 31:58]
+ wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {_dataArb_io_in_0_bits_eccMask_T_16,_dataArb_io_in_0_bits_eccMask_T_15,
+ _dataArb_io_in_0_bits_eccMask_T_14,_dataArb_io_in_0_bits_eccMask_T_13}; // @[Cat.scala 31:58]
+ wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala 552:34]
+ wire [22:0] a_mask = {{15'd0}, pstore1_mask}; // @[DCache.scala 557:29]
+ wire [2:0] _get_a_mask_sizeOH_T = {{1'd0}, s2_req_size}; // @[Misc.scala 201:34]
+ wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] get_a_mask_sizeOH = _get_a_mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _get_a_mask_T = s2_req_size >= 2'h3; // @[Misc.scala 205:21]
+ wire get_a_mask_size = get_a_mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire get_a_mask_bit = s2_req_addr[2]; // @[Misc.scala 209:26]
+ wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala 210:20]
+ wire get_a_mask_acc = _get_a_mask_T | get_a_mask_size & get_a_mask_nbit; // @[Misc.scala 214:29]
+ wire get_a_mask_acc_1 = _get_a_mask_T | get_a_mask_size & get_a_mask_bit; // @[Misc.scala 214:29]
+ wire get_a_mask_size_1 = get_a_mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire get_a_mask_bit_1 = s2_req_addr[1]; // @[Misc.scala 209:26]
+ wire get_a_mask_nbit_1 = ~get_a_mask_bit_1; // @[Misc.scala 210:20]
+ wire get_a_mask_eq_2 = get_a_mask_nbit & get_a_mask_nbit_1; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_2 = get_a_mask_acc | get_a_mask_size_1 & get_a_mask_eq_2; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_3 = get_a_mask_nbit & get_a_mask_bit_1; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_3 = get_a_mask_acc | get_a_mask_size_1 & get_a_mask_eq_3; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_4 = get_a_mask_bit & get_a_mask_nbit_1; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_4 = get_a_mask_acc_1 | get_a_mask_size_1 & get_a_mask_eq_4; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_5 = get_a_mask_bit & get_a_mask_bit_1; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_5 = get_a_mask_acc_1 | get_a_mask_size_1 & get_a_mask_eq_5; // @[Misc.scala 214:29]
+ wire get_a_mask_size_2 = get_a_mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire get_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala 209:26]
+ wire get_a_mask_nbit_2 = ~get_a_mask_bit_2; // @[Misc.scala 210:20]
+ wire get_a_mask_eq_6 = get_a_mask_eq_2 & get_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_6 = get_a_mask_acc_2 | get_a_mask_size_2 & get_a_mask_eq_6; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_7 = get_a_mask_eq_2 & get_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_7 = get_a_mask_acc_2 | get_a_mask_size_2 & get_a_mask_eq_7; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_8 = get_a_mask_eq_3 & get_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_8 = get_a_mask_acc_3 | get_a_mask_size_2 & get_a_mask_eq_8; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_9 = get_a_mask_eq_3 & get_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_9 = get_a_mask_acc_3 | get_a_mask_size_2 & get_a_mask_eq_9; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_10 = get_a_mask_eq_4 & get_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_10 = get_a_mask_acc_4 | get_a_mask_size_2 & get_a_mask_eq_10; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_11 = get_a_mask_eq_4 & get_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_11 = get_a_mask_acc_4 | get_a_mask_size_2 & get_a_mask_eq_11; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_12 = get_a_mask_eq_5 & get_a_mask_nbit_2; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_12 = get_a_mask_acc_5 | get_a_mask_size_2 & get_a_mask_eq_12; // @[Misc.scala 214:29]
+ wire get_a_mask_eq_13 = get_a_mask_eq_5 & get_a_mask_bit_2; // @[Misc.scala 213:27]
+ wire get_a_mask_acc_13 = get_a_mask_acc_5 | get_a_mask_size_2 & get_a_mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] get_mask = {get_a_mask_acc_13,get_a_mask_acc_12,get_a_mask_acc_11,get_a_mask_acc_10,get_a_mask_acc_9,
+ get_a_mask_acc_8,get_a_mask_acc_7,get_a_mask_acc_6}; // @[Cat.scala 31:58]
+ wire [2:0] _atomics_T_1_opcode = 5'h4 == s2_req_cmd ? 3'h3 : 3'h0; // @[Mux.scala 81:58]
+ wire [3:0] atomics_a_size = {{2'd0}, s2_req_size}; // @[Edges.scala 513:17 516:15]
+ wire [3:0] _atomics_T_1_size = 5'h4 == s2_req_cmd ? atomics_a_size : 4'h0; // @[Mux.scala 81:58]
+ wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala 513:17 518:15]
+ wire [31:0] _atomics_T_1_address = 5'h4 == s2_req_cmd ? atomics_a_address : 32'h0; // @[Mux.scala 81:58]
+ wire [7:0] _atomics_T_1_mask = 5'h4 == s2_req_cmd ? get_mask : 8'h0; // @[Mux.scala 81:58]
+ wire [63:0] _atomics_T_1_data = 5'h4 == s2_req_cmd ? pstore1_data : 64'h0; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_3_opcode = 5'h9 == s2_req_cmd ? 3'h3 : _atomics_T_1_opcode; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_3_param = 5'h9 == s2_req_cmd ? 3'h0 : _atomics_T_1_opcode; // @[Mux.scala 81:58]
+ wire [3:0] _atomics_T_3_size = 5'h9 == s2_req_cmd ? atomics_a_size : _atomics_T_1_size; // @[Mux.scala 81:58]
+ wire [31:0] _atomics_T_3_address = 5'h9 == s2_req_cmd ? atomics_a_address : _atomics_T_1_address; // @[Mux.scala 81:58]
+ wire [7:0] _atomics_T_3_mask = 5'h9 == s2_req_cmd ? get_mask : _atomics_T_1_mask; // @[Mux.scala 81:58]
+ wire [63:0] _atomics_T_3_data = 5'h9 == s2_req_cmd ? pstore1_data : _atomics_T_1_data; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_5_opcode = 5'ha == s2_req_cmd ? 3'h3 : _atomics_T_3_opcode; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_5_param = 5'ha == s2_req_cmd ? 3'h1 : _atomics_T_3_param; // @[Mux.scala 81:58]
+ wire [3:0] _atomics_T_5_size = 5'ha == s2_req_cmd ? atomics_a_size : _atomics_T_3_size; // @[Mux.scala 81:58]
+ wire [31:0] _atomics_T_5_address = 5'ha == s2_req_cmd ? atomics_a_address : _atomics_T_3_address; // @[Mux.scala 81:58]
+ wire [7:0] _atomics_T_5_mask = 5'ha == s2_req_cmd ? get_mask : _atomics_T_3_mask; // @[Mux.scala 81:58]
+ wire [63:0] _atomics_T_5_data = 5'ha == s2_req_cmd ? pstore1_data : _atomics_T_3_data; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_7_opcode = 5'hb == s2_req_cmd ? 3'h3 : _atomics_T_5_opcode; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_7_param = 5'hb == s2_req_cmd ? 3'h2 : _atomics_T_5_param; // @[Mux.scala 81:58]
+ wire [3:0] _atomics_T_7_size = 5'hb == s2_req_cmd ? atomics_a_size : _atomics_T_5_size; // @[Mux.scala 81:58]
+ wire [31:0] _atomics_T_7_address = 5'hb == s2_req_cmd ? atomics_a_address : _atomics_T_5_address; // @[Mux.scala 81:58]
+ wire [7:0] _atomics_T_7_mask = 5'hb == s2_req_cmd ? get_mask : _atomics_T_5_mask; // @[Mux.scala 81:58]
+ wire [63:0] _atomics_T_7_data = 5'hb == s2_req_cmd ? pstore1_data : _atomics_T_5_data; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_9_opcode = 5'h8 == s2_req_cmd ? 3'h2 : _atomics_T_7_opcode; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_9_param = 5'h8 == s2_req_cmd ? 3'h4 : _atomics_T_7_param; // @[Mux.scala 81:58]
+ wire [3:0] _atomics_T_9_size = 5'h8 == s2_req_cmd ? atomics_a_size : _atomics_T_7_size; // @[Mux.scala 81:58]
+ wire [31:0] _atomics_T_9_address = 5'h8 == s2_req_cmd ? atomics_a_address : _atomics_T_7_address; // @[Mux.scala 81:58]
+ wire [7:0] _atomics_T_9_mask = 5'h8 == s2_req_cmd ? get_mask : _atomics_T_7_mask; // @[Mux.scala 81:58]
+ wire [63:0] _atomics_T_9_data = 5'h8 == s2_req_cmd ? pstore1_data : _atomics_T_7_data; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_11_opcode = 5'hc == s2_req_cmd ? 3'h2 : _atomics_T_9_opcode; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_11_param = 5'hc == s2_req_cmd ? 3'h0 : _atomics_T_9_param; // @[Mux.scala 81:58]
+ wire [3:0] _atomics_T_11_size = 5'hc == s2_req_cmd ? atomics_a_size : _atomics_T_9_size; // @[Mux.scala 81:58]
+ wire [31:0] _atomics_T_11_address = 5'hc == s2_req_cmd ? atomics_a_address : _atomics_T_9_address; // @[Mux.scala 81:58]
+ wire [7:0] _atomics_T_11_mask = 5'hc == s2_req_cmd ? get_mask : _atomics_T_9_mask; // @[Mux.scala 81:58]
+ wire [63:0] _atomics_T_11_data = 5'hc == s2_req_cmd ? pstore1_data : _atomics_T_9_data; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_13_opcode = 5'hd == s2_req_cmd ? 3'h2 : _atomics_T_11_opcode; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_13_param = 5'hd == s2_req_cmd ? 3'h1 : _atomics_T_11_param; // @[Mux.scala 81:58]
+ wire [3:0] _atomics_T_13_size = 5'hd == s2_req_cmd ? atomics_a_size : _atomics_T_11_size; // @[Mux.scala 81:58]
+ wire [31:0] _atomics_T_13_address = 5'hd == s2_req_cmd ? atomics_a_address : _atomics_T_11_address; // @[Mux.scala 81:58]
+ wire [7:0] _atomics_T_13_mask = 5'hd == s2_req_cmd ? get_mask : _atomics_T_11_mask; // @[Mux.scala 81:58]
+ wire [63:0] _atomics_T_13_data = 5'hd == s2_req_cmd ? pstore1_data : _atomics_T_11_data; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_15_opcode = 5'he == s2_req_cmd ? 3'h2 : _atomics_T_13_opcode; // @[Mux.scala 81:58]
+ wire [2:0] _atomics_T_15_param = 5'he == s2_req_cmd ? 3'h2 : _atomics_T_13_param; // @[Mux.scala 81:58]
+ wire [3:0] _atomics_T_15_size = 5'he == s2_req_cmd ? atomics_a_size : _atomics_T_13_size; // @[Mux.scala 81:58]
+ wire [31:0] _atomics_T_15_address = 5'he == s2_req_cmd ? atomics_a_address : _atomics_T_13_address; // @[Mux.scala 81:58]
+ wire [7:0] _atomics_T_15_mask = 5'he == s2_req_cmd ? get_mask : _atomics_T_13_mask; // @[Mux.scala 81:58]
+ wire [63:0] _atomics_T_15_data = 5'he == s2_req_cmd ? pstore1_data : _atomics_T_13_data; // @[Mux.scala 81:58]
+ wire [2:0] atomics_opcode = 5'hf == s2_req_cmd ? 3'h2 : _atomics_T_15_opcode; // @[Mux.scala 81:58]
+ wire [2:0] atomics_param = 5'hf == s2_req_cmd ? 3'h3 : _atomics_T_15_param; // @[Mux.scala 81:58]
+ wire [3:0] atomics_size = 5'hf == s2_req_cmd ? atomics_a_size : _atomics_T_15_size; // @[Mux.scala 81:58]
+ wire [31:0] atomics_address = 5'hf == s2_req_cmd ? atomics_a_address : _atomics_T_15_address; // @[Mux.scala 81:58]
+ wire [7:0] atomics_mask = 5'hf == s2_req_cmd ? get_mask : _atomics_T_15_mask; // @[Mux.scala 81:58]
+ wire [63:0] atomics_data = 5'hf == s2_req_cmd ? pstore1_data : _atomics_T_15_data; // @[Mux.scala 81:58]
+ wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[DCache.scala 582:89]
+ wire _tl_out_a_valid_T_12 = 1'h0 & _tl_out_a_valid_T_10; // @[DCache.scala 581:125]
+ wire tl_out_a_valid = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala 579:32]
+ wire [2:0] _tl_out_a_bits_T_4_opcode = ~s2_read ? 3'h0 : atomics_opcode; // @[DCache.scala 586:8]
+ wire [2:0] _tl_out_a_bits_T_4_param = ~s2_read ? 3'h0 : atomics_param; // @[DCache.scala 586:8]
+ wire [3:0] _tl_out_a_bits_T_4_size = ~s2_read ? atomics_a_size : atomics_size; // @[DCache.scala 586:8]
+ wire [31:0] _tl_out_a_bits_T_4_address = ~s2_read ? atomics_a_address : atomics_address; // @[DCache.scala 586:8]
+ wire [7:0] _tl_out_a_bits_T_4_mask = ~s2_read ? get_mask : atomics_mask; // @[DCache.scala 586:8]
+ wire [63:0] _tl_out_a_bits_T_4_data = ~s2_read ? pstore1_data : atomics_data; // @[DCache.scala 586:8]
+ wire [2:0] _tl_out_a_bits_T_5_opcode = _s2_write_T_1 ? 3'h1 : _tl_out_a_bits_T_4_opcode; // @[DCache.scala 585:8]
+ wire [2:0] _tl_out_a_bits_T_5_param = _s2_write_T_1 ? 3'h0 : _tl_out_a_bits_T_4_param; // @[DCache.scala 585:8]
+ wire [3:0] _tl_out_a_bits_T_5_size = _s2_write_T_1 ? atomics_a_size : _tl_out_a_bits_T_4_size; // @[DCache.scala 585:8]
+ wire [31:0] _tl_out_a_bits_T_5_address = _s2_write_T_1 ? atomics_a_address : _tl_out_a_bits_T_4_address; // @[DCache.scala 585:8]
+ wire [7:0] putpartial_mask = a_mask[7:0]; // @[Edges.scala 483:17 489:15]
+ wire [7:0] _tl_out_a_bits_T_5_mask = _s2_write_T_1 ? putpartial_mask : _tl_out_a_bits_T_4_mask; // @[DCache.scala 585:8]
+ wire [63:0] _tl_out_a_bits_T_5_data = _s2_write_T_1 ? pstore1_data : _tl_out_a_bits_T_4_data; // @[DCache.scala 585:8]
+ wire _T_248 = auto_out_a_ready & tl_out_a_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_162 = _T_248 | uncachedInFlight_0; // @[DCache.scala 606:26 216:33]
+ wire [26:0] _beats1_decode_T_1 = 27'hfff << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] beats1_decode = _beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire beats1_opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [8:0] beats1 = beats1_opdata ? beats1_decode : 9'h0; // @[Edges.scala 220:14]
+ wire [8:0] counter1 = counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_last = counter == 9'h1 | beats1 == 9'h0; // @[Edges.scala 231:37]
+ wire d_done = d_last & _T_265; // @[Edges.scala 232:22]
+ wire _T_252 = auto_out_d_bits_opcode == 3'h1; // @[package.scala 15:47]
+ wire _T_253 = auto_out_d_bits_opcode == 3'h0; // @[package.scala 15:47]
+ wire _T_254 = auto_out_d_bits_opcode == 3'h2; // @[package.scala 15:47]
+ wire _T_256 = _T_252 | _T_253 | _T_254; // @[package.scala 72:59]
+ wire [31:0] dontCareBits = {s1_paddr[31:3], 3'h0}; // @[DCache.scala 676:55]
+ wire [31:0] _GEN_253 = {{29'd0}, uncachedReqs_0_addr[2:0]}; // @[DCache.scala 677:26]
+ wire [31:0] _s2_req_addr_T_1 = dontCareBits | _GEN_253; // @[DCache.scala 677:26]
+ wire _GEN_228 = auto_out_d_valid ? 1'h0 : _GEN_36; // @[DCache.scala 730:29 731:26]
+ wire _GEN_229 = auto_out_d_valid | auto_out_d_valid & grantIsRefill; // @[DCache.scala 696:26 730:29 732:32]
+ wire _GEN_230 = auto_out_d_valid ? 1'h0 : dataArb_io_in_0_bits_write; // @[DCache.scala 709:27 730:29 733:37]
+ wire _io_cpu_ordered_T = ~s1_req_no_xcpt; // @[DCache.scala 904:35]
+ reg io_cpu_s2_xcpt_REG; // @[DCache.scala 907:32]
+ wire _T_303 = _c_cat_T_48 | _s2_write_T_3; // @[package.scala 72:59]
+ reg doUncachedResp; // @[DCache.scala 922:27]
+ wire [31:0] io_cpu_resp_bits_data_shifted = get_a_mask_bit ? s2_data_corrected[63:32] : s2_data_corrected[31:0]; // @[AMOALU.scala 39:24]
+ wire _io_cpu_resp_bits_data_T_3 = s2_req_signed & io_cpu_resp_bits_data_shifted[31]; // @[AMOALU.scala 42:76]
+ wire [31:0] _io_cpu_resp_bits_data_T_5 = _io_cpu_resp_bits_data_T_3 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 74:12]
+ wire [31:0] _io_cpu_resp_bits_data_T_7 = s2_req_size == 2'h2 ? _io_cpu_resp_bits_data_T_5 : s2_data_corrected[63:32]; // @[AMOALU.scala 42:20]
+ wire [63:0] _io_cpu_resp_bits_data_T_8 = {_io_cpu_resp_bits_data_T_7,io_cpu_resp_bits_data_shifted}; // @[Cat.scala 31:58]
+ wire [15:0] io_cpu_resp_bits_data_shifted_1 = get_a_mask_bit_1 ? _io_cpu_resp_bits_data_T_8[31:16] :
+ _io_cpu_resp_bits_data_T_8[15:0]; // @[AMOALU.scala 39:24]
+ wire _io_cpu_resp_bits_data_T_12 = s2_req_signed & io_cpu_resp_bits_data_shifted_1[15]; // @[AMOALU.scala 42:76]
+ wire [47:0] _io_cpu_resp_bits_data_T_14 = _io_cpu_resp_bits_data_T_12 ? 48'hffffffffffff : 48'h0; // @[Bitwise.scala 74:12]
+ wire [47:0] _io_cpu_resp_bits_data_T_16 = s2_req_size == 2'h1 ? _io_cpu_resp_bits_data_T_14 :
+ _io_cpu_resp_bits_data_T_8[63:16]; // @[AMOALU.scala 42:20]
+ wire [63:0] _io_cpu_resp_bits_data_T_17 = {_io_cpu_resp_bits_data_T_16,io_cpu_resp_bits_data_shifted_1}; // @[Cat.scala 31:58]
+ wire [7:0] io_cpu_resp_bits_data_shifted_2 = get_a_mask_bit_2 ? _io_cpu_resp_bits_data_T_17[15:8] :
+ _io_cpu_resp_bits_data_T_17[7:0]; // @[AMOALU.scala 39:24]
+ wire _io_cpu_resp_bits_data_T_21 = s2_req_signed & io_cpu_resp_bits_data_shifted_2[7]; // @[AMOALU.scala 42:76]
+ wire [55:0] _io_cpu_resp_bits_data_T_23 = _io_cpu_resp_bits_data_T_21 ? 56'hffffffffffffff : 56'h0; // @[Bitwise.scala 74:12]
+ wire [55:0] _io_cpu_resp_bits_data_T_25 = s2_req_size == 2'h0 ? _io_cpu_resp_bits_data_T_23 :
+ _io_cpu_resp_bits_data_T_17[63:8]; // @[AMOALU.scala 42:20]
+ wire _s1_flush_valid_T = metaArb_io_in_5_ready & metaArb_io_in_5_valid; // @[Decoupled.scala 50:35]
+ wire _T_318 = ~grantIsCached; // @[DCache.scala 1107:35]
+ TLB tlb ( // @[DCache.scala 117:19]
+ .io_req_valid(tlb_io_req_valid),
+ .io_req_bits_vaddr(tlb_io_req_bits_vaddr),
+ .io_req_bits_size(tlb_io_req_bits_size),
+ .io_req_bits_cmd(tlb_io_req_bits_cmd),
+ .io_req_bits_prv(tlb_io_req_bits_prv),
+ .io_resp_paddr(tlb_io_resp_paddr),
+ .io_resp_pf_ld(tlb_io_resp_pf_ld),
+ .io_resp_pf_st(tlb_io_resp_pf_st),
+ .io_resp_ae_ld(tlb_io_resp_ae_ld),
+ .io_resp_ae_st(tlb_io_resp_ae_st),
+ .io_resp_ma_ld(tlb_io_resp_ma_ld),
+ .io_resp_ma_st(tlb_io_resp_ma_st),
+ .io_ptw_status_debug(tlb_io_ptw_status_debug),
+ .io_ptw_pmp_0_cfg_l(tlb_io_ptw_pmp_0_cfg_l),
+ .io_ptw_pmp_0_cfg_a(tlb_io_ptw_pmp_0_cfg_a),
+ .io_ptw_pmp_0_cfg_w(tlb_io_ptw_pmp_0_cfg_w),
+ .io_ptw_pmp_0_cfg_r(tlb_io_ptw_pmp_0_cfg_r),
+ .io_ptw_pmp_0_addr(tlb_io_ptw_pmp_0_addr),
+ .io_ptw_pmp_0_mask(tlb_io_ptw_pmp_0_mask),
+ .io_ptw_pmp_1_cfg_l(tlb_io_ptw_pmp_1_cfg_l),
+ .io_ptw_pmp_1_cfg_a(tlb_io_ptw_pmp_1_cfg_a),
+ .io_ptw_pmp_1_cfg_w(tlb_io_ptw_pmp_1_cfg_w),
+ .io_ptw_pmp_1_cfg_r(tlb_io_ptw_pmp_1_cfg_r),
+ .io_ptw_pmp_1_addr(tlb_io_ptw_pmp_1_addr),
+ .io_ptw_pmp_1_mask(tlb_io_ptw_pmp_1_mask),
+ .io_ptw_pmp_2_cfg_l(tlb_io_ptw_pmp_2_cfg_l),
+ .io_ptw_pmp_2_cfg_a(tlb_io_ptw_pmp_2_cfg_a),
+ .io_ptw_pmp_2_cfg_w(tlb_io_ptw_pmp_2_cfg_w),
+ .io_ptw_pmp_2_cfg_r(tlb_io_ptw_pmp_2_cfg_r),
+ .io_ptw_pmp_2_addr(tlb_io_ptw_pmp_2_addr),
+ .io_ptw_pmp_2_mask(tlb_io_ptw_pmp_2_mask),
+ .io_ptw_pmp_3_cfg_l(tlb_io_ptw_pmp_3_cfg_l),
+ .io_ptw_pmp_3_cfg_a(tlb_io_ptw_pmp_3_cfg_a),
+ .io_ptw_pmp_3_cfg_w(tlb_io_ptw_pmp_3_cfg_w),
+ .io_ptw_pmp_3_cfg_r(tlb_io_ptw_pmp_3_cfg_r),
+ .io_ptw_pmp_3_addr(tlb_io_ptw_pmp_3_addr),
+ .io_ptw_pmp_3_mask(tlb_io_ptw_pmp_3_mask),
+ .io_ptw_pmp_4_cfg_l(tlb_io_ptw_pmp_4_cfg_l),
+ .io_ptw_pmp_4_cfg_a(tlb_io_ptw_pmp_4_cfg_a),
+ .io_ptw_pmp_4_cfg_w(tlb_io_ptw_pmp_4_cfg_w),
+ .io_ptw_pmp_4_cfg_r(tlb_io_ptw_pmp_4_cfg_r),
+ .io_ptw_pmp_4_addr(tlb_io_ptw_pmp_4_addr),
+ .io_ptw_pmp_4_mask(tlb_io_ptw_pmp_4_mask),
+ .io_ptw_pmp_5_cfg_l(tlb_io_ptw_pmp_5_cfg_l),
+ .io_ptw_pmp_5_cfg_a(tlb_io_ptw_pmp_5_cfg_a),
+ .io_ptw_pmp_5_cfg_w(tlb_io_ptw_pmp_5_cfg_w),
+ .io_ptw_pmp_5_cfg_r(tlb_io_ptw_pmp_5_cfg_r),
+ .io_ptw_pmp_5_addr(tlb_io_ptw_pmp_5_addr),
+ .io_ptw_pmp_5_mask(tlb_io_ptw_pmp_5_mask),
+ .io_ptw_pmp_6_cfg_l(tlb_io_ptw_pmp_6_cfg_l),
+ .io_ptw_pmp_6_cfg_a(tlb_io_ptw_pmp_6_cfg_a),
+ .io_ptw_pmp_6_cfg_w(tlb_io_ptw_pmp_6_cfg_w),
+ .io_ptw_pmp_6_cfg_r(tlb_io_ptw_pmp_6_cfg_r),
+ .io_ptw_pmp_6_addr(tlb_io_ptw_pmp_6_addr),
+ .io_ptw_pmp_6_mask(tlb_io_ptw_pmp_6_mask),
+ .io_ptw_pmp_7_cfg_l(tlb_io_ptw_pmp_7_cfg_l),
+ .io_ptw_pmp_7_cfg_a(tlb_io_ptw_pmp_7_cfg_a),
+ .io_ptw_pmp_7_cfg_w(tlb_io_ptw_pmp_7_cfg_w),
+ .io_ptw_pmp_7_cfg_r(tlb_io_ptw_pmp_7_cfg_r),
+ .io_ptw_pmp_7_addr(tlb_io_ptw_pmp_7_addr),
+ .io_ptw_pmp_7_mask(tlb_io_ptw_pmp_7_mask)
+ );
+ TLB pma_checker ( // @[DCache.scala 118:27]
+ .io_req_valid(pma_checker_io_req_valid),
+ .io_req_bits_vaddr(pma_checker_io_req_bits_vaddr),
+ .io_req_bits_size(pma_checker_io_req_bits_size),
+ .io_req_bits_cmd(pma_checker_io_req_bits_cmd),
+ .io_req_bits_prv(pma_checker_io_req_bits_prv),
+ .io_resp_paddr(pma_checker_io_resp_paddr),
+ .io_resp_pf_ld(pma_checker_io_resp_pf_ld),
+ .io_resp_pf_st(pma_checker_io_resp_pf_st),
+ .io_resp_ae_ld(pma_checker_io_resp_ae_ld),
+ .io_resp_ae_st(pma_checker_io_resp_ae_st),
+ .io_resp_ma_ld(pma_checker_io_resp_ma_ld),
+ .io_resp_ma_st(pma_checker_io_resp_ma_st),
+ .io_ptw_status_debug(pma_checker_io_ptw_status_debug),
+ .io_ptw_pmp_0_cfg_l(pma_checker_io_ptw_pmp_0_cfg_l),
+ .io_ptw_pmp_0_cfg_a(pma_checker_io_ptw_pmp_0_cfg_a),
+ .io_ptw_pmp_0_cfg_w(pma_checker_io_ptw_pmp_0_cfg_w),
+ .io_ptw_pmp_0_cfg_r(pma_checker_io_ptw_pmp_0_cfg_r),
+ .io_ptw_pmp_0_addr(pma_checker_io_ptw_pmp_0_addr),
+ .io_ptw_pmp_0_mask(pma_checker_io_ptw_pmp_0_mask),
+ .io_ptw_pmp_1_cfg_l(pma_checker_io_ptw_pmp_1_cfg_l),
+ .io_ptw_pmp_1_cfg_a(pma_checker_io_ptw_pmp_1_cfg_a),
+ .io_ptw_pmp_1_cfg_w(pma_checker_io_ptw_pmp_1_cfg_w),
+ .io_ptw_pmp_1_cfg_r(pma_checker_io_ptw_pmp_1_cfg_r),
+ .io_ptw_pmp_1_addr(pma_checker_io_ptw_pmp_1_addr),
+ .io_ptw_pmp_1_mask(pma_checker_io_ptw_pmp_1_mask),
+ .io_ptw_pmp_2_cfg_l(pma_checker_io_ptw_pmp_2_cfg_l),
+ .io_ptw_pmp_2_cfg_a(pma_checker_io_ptw_pmp_2_cfg_a),
+ .io_ptw_pmp_2_cfg_w(pma_checker_io_ptw_pmp_2_cfg_w),
+ .io_ptw_pmp_2_cfg_r(pma_checker_io_ptw_pmp_2_cfg_r),
+ .io_ptw_pmp_2_addr(pma_checker_io_ptw_pmp_2_addr),
+ .io_ptw_pmp_2_mask(pma_checker_io_ptw_pmp_2_mask),
+ .io_ptw_pmp_3_cfg_l(pma_checker_io_ptw_pmp_3_cfg_l),
+ .io_ptw_pmp_3_cfg_a(pma_checker_io_ptw_pmp_3_cfg_a),
+ .io_ptw_pmp_3_cfg_w(pma_checker_io_ptw_pmp_3_cfg_w),
+ .io_ptw_pmp_3_cfg_r(pma_checker_io_ptw_pmp_3_cfg_r),
+ .io_ptw_pmp_3_addr(pma_checker_io_ptw_pmp_3_addr),
+ .io_ptw_pmp_3_mask(pma_checker_io_ptw_pmp_3_mask),
+ .io_ptw_pmp_4_cfg_l(pma_checker_io_ptw_pmp_4_cfg_l),
+ .io_ptw_pmp_4_cfg_a(pma_checker_io_ptw_pmp_4_cfg_a),
+ .io_ptw_pmp_4_cfg_w(pma_checker_io_ptw_pmp_4_cfg_w),
+ .io_ptw_pmp_4_cfg_r(pma_checker_io_ptw_pmp_4_cfg_r),
+ .io_ptw_pmp_4_addr(pma_checker_io_ptw_pmp_4_addr),
+ .io_ptw_pmp_4_mask(pma_checker_io_ptw_pmp_4_mask),
+ .io_ptw_pmp_5_cfg_l(pma_checker_io_ptw_pmp_5_cfg_l),
+ .io_ptw_pmp_5_cfg_a(pma_checker_io_ptw_pmp_5_cfg_a),
+ .io_ptw_pmp_5_cfg_w(pma_checker_io_ptw_pmp_5_cfg_w),
+ .io_ptw_pmp_5_cfg_r(pma_checker_io_ptw_pmp_5_cfg_r),
+ .io_ptw_pmp_5_addr(pma_checker_io_ptw_pmp_5_addr),
+ .io_ptw_pmp_5_mask(pma_checker_io_ptw_pmp_5_mask),
+ .io_ptw_pmp_6_cfg_l(pma_checker_io_ptw_pmp_6_cfg_l),
+ .io_ptw_pmp_6_cfg_a(pma_checker_io_ptw_pmp_6_cfg_a),
+ .io_ptw_pmp_6_cfg_w(pma_checker_io_ptw_pmp_6_cfg_w),
+ .io_ptw_pmp_6_cfg_r(pma_checker_io_ptw_pmp_6_cfg_r),
+ .io_ptw_pmp_6_addr(pma_checker_io_ptw_pmp_6_addr),
+ .io_ptw_pmp_6_mask(pma_checker_io_ptw_pmp_6_mask),
+ .io_ptw_pmp_7_cfg_l(pma_checker_io_ptw_pmp_7_cfg_l),
+ .io_ptw_pmp_7_cfg_a(pma_checker_io_ptw_pmp_7_cfg_a),
+ .io_ptw_pmp_7_cfg_w(pma_checker_io_ptw_pmp_7_cfg_w),
+ .io_ptw_pmp_7_cfg_r(pma_checker_io_ptw_pmp_7_cfg_r),
+ .io_ptw_pmp_7_addr(pma_checker_io_ptw_pmp_7_addr),
+ .io_ptw_pmp_7_mask(pma_checker_io_ptw_pmp_7_mask)
+ );
+ DCacheModuleImpl_Anon_1 metaArb ( // @[DCache.scala 122:23]
+ .io_in_2_valid(metaArb_io_in_2_valid),
+ .io_in_2_bits_addr(metaArb_io_in_2_bits_addr),
+ .io_in_3_valid(metaArb_io_in_3_valid),
+ .io_in_3_bits_addr(metaArb_io_in_3_bits_addr),
+ .io_in_5_ready(metaArb_io_in_5_ready),
+ .io_in_5_valid(metaArb_io_in_5_valid),
+ .io_in_7_ready(metaArb_io_in_7_ready),
+ .io_in_7_valid(metaArb_io_in_7_valid),
+ .io_in_7_bits_addr(metaArb_io_in_7_bits_addr),
+ .io_out_valid(metaArb_io_out_valid),
+ .io_out_bits_write(metaArb_io_out_bits_write),
+ .io_out_bits_addr(metaArb_io_out_bits_addr)
+ );
+ DCacheDataArray data ( // @[DCache.scala 132:20]
+ .clock(data_clock),
+ .io_req_valid(data_io_req_valid),
+ .io_req_bits_addr(data_io_req_bits_addr),
+ .io_req_bits_write(data_io_req_bits_write),
+ .io_req_bits_wdata(data_io_req_bits_wdata),
+ .io_req_bits_eccMask(data_io_req_bits_eccMask),
+ .io_resp_0(data_io_resp_0)
+ );
+ DCacheModuleImpl_Anon_2 dataArb ( // @[DCache.scala 133:23]
+ .io_in_0_valid(dataArb_io_in_0_valid),
+ .io_in_0_bits_addr(dataArb_io_in_0_bits_addr),
+ .io_in_0_bits_write(dataArb_io_in_0_bits_write),
+ .io_in_0_bits_wdata(dataArb_io_in_0_bits_wdata),
+ .io_in_0_bits_eccMask(dataArb_io_in_0_bits_eccMask),
+ .io_in_1_ready(dataArb_io_in_1_ready),
+ .io_in_1_valid(dataArb_io_in_1_valid),
+ .io_in_1_bits_addr(dataArb_io_in_1_bits_addr),
+ .io_in_1_bits_write(dataArb_io_in_1_bits_write),
+ .io_in_1_bits_wdata(dataArb_io_in_1_bits_wdata),
+ .io_in_1_bits_eccMask(dataArb_io_in_1_bits_eccMask),
+ .io_in_3_ready(dataArb_io_in_3_ready),
+ .io_in_3_valid(dataArb_io_in_3_valid),
+ .io_in_3_bits_addr(dataArb_io_in_3_bits_addr),
+ .io_in_3_bits_wdata(dataArb_io_in_3_bits_wdata),
+ .io_in_3_bits_wordMask(dataArb_io_in_3_bits_wordMask),
+ .io_out_valid(dataArb_io_out_valid),
+ .io_out_bits_addr(dataArb_io_out_bits_addr),
+ .io_out_bits_write(dataArb_io_out_bits_write),
+ .io_out_bits_wdata(dataArb_io_out_bits_wdata),
+ .io_out_bits_eccMask(dataArb_io_out_bits_eccMask)
+ );
+ AMOALU amoalu ( // @[DCache.scala 956:26]
+ .io_mask(amoalu_io_mask),
+ .io_cmd(amoalu_io_cmd),
+ .io_lhs(amoalu_io_lhs),
+ .io_rhs(amoalu_io_rhs),
+ .io_out_unmasked(amoalu_io_out_unmasked)
+ );
+ assign auto_out_a_valid = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala 579:32]
+ assign auto_out_a_bits_opcode = ~s2_write ? 3'h4 : _tl_out_a_bits_T_5_opcode; // @[DCache.scala 584:8]
+ assign auto_out_a_bits_param = ~s2_write ? 3'h0 : _tl_out_a_bits_T_5_param; // @[DCache.scala 584:8]
+ assign auto_out_a_bits_size = ~s2_write ? atomics_a_size : _tl_out_a_bits_T_5_size; // @[DCache.scala 584:8]
+ assign auto_out_a_bits_address = ~s2_write ? atomics_a_address : _tl_out_a_bits_T_5_address; // @[DCache.scala 584:8]
+ assign auto_out_a_bits_mask = ~s2_write ? get_mask : _tl_out_a_bits_T_5_mask; // @[DCache.scala 584:8]
+ assign auto_out_a_bits_data = ~s2_write ? 64'h0 : _tl_out_a_bits_T_5_data; // @[DCache.scala 584:8]
+ assign auto_out_d_ready = data_1 & (blockUncachedGrant | s1_valid) ? 1'h0 : _GEN_227; // @[DCache.scala 727:68 728:22]
+ assign io_cpu_req_ready = data_1 & (blockUncachedGrant | s1_valid) ? _GEN_228 : _GEN_36; // @[DCache.scala 727:68]
+ assign io_cpu_s2_nack = s2_valid_no_xcpt & ~s2_dont_nack_uncached & ~s2_dont_nack_misc & ~
+ s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala 420:86]
+ assign io_cpu_resp_valid = s2_valid_hit_pre_data_ecc_and_waw | doUncachedResp; // @[DCache.scala 923:51]
+ assign io_cpu_resp_bits_addr = doUncachedResp ? s2_uncached_resp_addr : s2_req_addr; // @[DCache.scala 892:20 925:25 928:27]
+ assign io_cpu_resp_bits_tag = s2_req_tag; // @[DCache.scala 892:20]
+ assign io_cpu_resp_bits_cmd = s2_req_cmd; // @[DCache.scala 892:20]
+ assign io_cpu_resp_bits_size = s2_req_size; // @[DCache.scala 892:20]
+ assign io_cpu_resp_bits_signed = s2_req_signed; // @[DCache.scala 892:20]
+ assign io_cpu_resp_bits_dprv = s2_req_dprv; // @[DCache.scala 892:20]
+ assign io_cpu_resp_bits_dv = 1'h0; // @[DCache.scala 892:20]
+ assign io_cpu_resp_bits_data = {_io_cpu_resp_bits_data_T_25,io_cpu_resp_bits_data_shifted_2}; // @[Cat.scala 31:58]
+ assign io_cpu_resp_bits_mask = 8'h0; // @[DCache.scala 892:20]
+ assign io_cpu_resp_bits_replay = doUncachedResp; // @[DCache.scala 925:25 894:27 927:29]
+ assign io_cpu_resp_bits_has_data = _s2_read_T_6 | _s2_write_T_21; // @[Consts.scala 84:68]
+ assign io_cpu_resp_bits_data_word_bypass = {_io_cpu_resp_bits_data_T_7,io_cpu_resp_bits_data_shifted}; // @[Cat.scala 31:58]
+ assign io_cpu_resp_bits_data_raw = {s2_data_corrected_hi,s2_data_corrected_lo}; // @[Cat.scala 31:58]
+ assign io_cpu_resp_bits_store_data = pstore1_data; // @[DCache.scala 951:31]
+ assign io_cpu_replay_next = _T_265 & data_1; // @[DCache.scala 924:41]
+ assign io_cpu_s2_xcpt_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala 907:24]
+ assign io_cpu_s2_xcpt_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala 907:24]
+ assign io_cpu_s2_xcpt_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala 907:24]
+ assign io_cpu_s2_xcpt_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala 907:24]
+ assign io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala 907:24]
+ assign io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala 907:24]
+ assign io_cpu_s2_xcpt_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala 907:24]
+ assign io_cpu_s2_xcpt_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala 907:24]
+ assign io_cpu_ordered = ~(s1_valid & ~s1_req_no_xcpt | s2_valid & ~s2_req_no_xcpt | _s2_valid_cached_miss_T_2); // @[DCache.scala 904:21]
+ assign io_cpu_perf_grant = auto_out_d_valid & d_last; // @[DCache.scala 1052:39]
+ assign tlb_io_req_valid = s1_valid_masked & s1_cmd_uses_tlb; // @[DCache.scala 253:71]
+ assign tlb_io_req_bits_vaddr = s1_tlb_req_vaddr; // @[DCache.scala 254:19]
+ assign tlb_io_req_bits_size = s1_tlb_req_size; // @[DCache.scala 254:19]
+ assign tlb_io_req_bits_cmd = s1_tlb_req_cmd; // @[DCache.scala 254:19]
+ assign tlb_io_req_bits_prv = s1_tlb_req_prv; // @[DCache.scala 254:19]
+ assign tlb_io_ptw_status_debug = io_ptw_status_debug; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_0_addr = io_ptw_pmp_0_addr; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_0_mask = io_ptw_pmp_0_mask; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_1_addr = io_ptw_pmp_1_addr; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_1_mask = io_ptw_pmp_1_mask; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_2_addr = io_ptw_pmp_2_addr; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_2_mask = io_ptw_pmp_2_mask; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_3_addr = io_ptw_pmp_3_addr; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_3_mask = io_ptw_pmp_3_mask; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_4_addr = io_ptw_pmp_4_addr; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_4_mask = io_ptw_pmp_4_mask; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_5_addr = io_ptw_pmp_5_addr; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_5_mask = io_ptw_pmp_5_mask; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_6_addr = io_ptw_pmp_6_addr; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_6_mask = io_ptw_pmp_6_mask; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_7_addr = io_ptw_pmp_7_addr; // @[DCache.scala 251:10]
+ assign tlb_io_ptw_pmp_7_mask = io_ptw_pmp_7_mask; // @[DCache.scala 251:10]
+ assign pma_checker_io_req_valid = 1'h0;
+ assign pma_checker_io_req_bits_vaddr = 34'h0;
+ assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala 271:27]
+ assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala 271:27]
+ assign pma_checker_io_req_bits_prv = 2'h0;
+ assign pma_checker_io_ptw_status_debug = 1'h0;
+ assign pma_checker_io_ptw_pmp_0_cfg_l = 1'h0;
+ assign pma_checker_io_ptw_pmp_0_cfg_a = 2'h0;
+ assign pma_checker_io_ptw_pmp_0_cfg_w = 1'h0;
+ assign pma_checker_io_ptw_pmp_0_cfg_r = 1'h0;
+ assign pma_checker_io_ptw_pmp_0_addr = 30'h0;
+ assign pma_checker_io_ptw_pmp_0_mask = 32'h0;
+ assign pma_checker_io_ptw_pmp_1_cfg_l = 1'h0;
+ assign pma_checker_io_ptw_pmp_1_cfg_a = 2'h0;
+ assign pma_checker_io_ptw_pmp_1_cfg_w = 1'h0;
+ assign pma_checker_io_ptw_pmp_1_cfg_r = 1'h0;
+ assign pma_checker_io_ptw_pmp_1_addr = 30'h0;
+ assign pma_checker_io_ptw_pmp_1_mask = 32'h0;
+ assign pma_checker_io_ptw_pmp_2_cfg_l = 1'h0;
+ assign pma_checker_io_ptw_pmp_2_cfg_a = 2'h0;
+ assign pma_checker_io_ptw_pmp_2_cfg_w = 1'h0;
+ assign pma_checker_io_ptw_pmp_2_cfg_r = 1'h0;
+ assign pma_checker_io_ptw_pmp_2_addr = 30'h0;
+ assign pma_checker_io_ptw_pmp_2_mask = 32'h0;
+ assign pma_checker_io_ptw_pmp_3_cfg_l = 1'h0;
+ assign pma_checker_io_ptw_pmp_3_cfg_a = 2'h0;
+ assign pma_checker_io_ptw_pmp_3_cfg_w = 1'h0;
+ assign pma_checker_io_ptw_pmp_3_cfg_r = 1'h0;
+ assign pma_checker_io_ptw_pmp_3_addr = 30'h0;
+ assign pma_checker_io_ptw_pmp_3_mask = 32'h0;
+ assign pma_checker_io_ptw_pmp_4_cfg_l = 1'h0;
+ assign pma_checker_io_ptw_pmp_4_cfg_a = 2'h0;
+ assign pma_checker_io_ptw_pmp_4_cfg_w = 1'h0;
+ assign pma_checker_io_ptw_pmp_4_cfg_r = 1'h0;
+ assign pma_checker_io_ptw_pmp_4_addr = 30'h0;
+ assign pma_checker_io_ptw_pmp_4_mask = 32'h0;
+ assign pma_checker_io_ptw_pmp_5_cfg_l = 1'h0;
+ assign pma_checker_io_ptw_pmp_5_cfg_a = 2'h0;
+ assign pma_checker_io_ptw_pmp_5_cfg_w = 1'h0;
+ assign pma_checker_io_ptw_pmp_5_cfg_r = 1'h0;
+ assign pma_checker_io_ptw_pmp_5_addr = 30'h0;
+ assign pma_checker_io_ptw_pmp_5_mask = 32'h0;
+ assign pma_checker_io_ptw_pmp_6_cfg_l = 1'h0;
+ assign pma_checker_io_ptw_pmp_6_cfg_a = 2'h0;
+ assign pma_checker_io_ptw_pmp_6_cfg_w = 1'h0;
+ assign pma_checker_io_ptw_pmp_6_cfg_r = 1'h0;
+ assign pma_checker_io_ptw_pmp_6_addr = 30'h0;
+ assign pma_checker_io_ptw_pmp_6_mask = 32'h0;
+ assign pma_checker_io_ptw_pmp_7_cfg_l = 1'h0;
+ assign pma_checker_io_ptw_pmp_7_cfg_a = 2'h0;
+ assign pma_checker_io_ptw_pmp_7_cfg_w = 1'h0;
+ assign pma_checker_io_ptw_pmp_7_cfg_r = 1'h0;
+ assign pma_checker_io_ptw_pmp_7_addr = 30'h0;
+ assign pma_checker_io_ptw_pmp_7_mask = 32'h0;
+ assign metaArb_io_in_2_valid = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[DCache.scala 437:63]
+ assign metaArb_io_in_2_bits_addr = {io_cpu_req_bits_addr[33:14],s2_vaddr[13:0]}; // @[Cat.scala 31:58]
+ assign metaArb_io_in_3_valid = grantIsCached & d_done & ~auto_out_d_bits_denied; // @[DCache.scala 716:53]
+ assign metaArb_io_in_3_bits_addr = {io_cpu_req_bits_addr[33:14],s2_vaddr[13:0]}; // @[Cat.scala 31:58]
+ assign metaArb_io_in_5_valid = 1'h0; // @[DCache.scala 989:38]
+ assign metaArb_io_in_7_valid = io_cpu_req_valid; // @[DCache.scala 241:26]
+ assign metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr; // @[DCache.scala 244:30]
+ assign data_clock = clock;
+ assign data_io_req_valid = dataArb_io_out_valid; // @[DCache.scala 135:15]
+ assign data_io_req_bits_addr = dataArb_io_out_bits_addr; // @[DCache.scala 135:15]
+ assign data_io_req_bits_write = dataArb_io_out_bits_write; // @[DCache.scala 135:15]
+ assign data_io_req_bits_wdata = dataArb_io_out_bits_wdata; // @[DCache.scala 135:15]
+ assign data_io_req_bits_eccMask = dataArb_io_out_bits_eccMask; // @[DCache.scala 135:15]
+ assign dataArb_io_in_0_valid = pstore_drain_structural | _pstore_drain_T_10; // @[DCache.scala 492:48]
+ assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[13:0]; // @[DCache.scala 524:30]
+ assign dataArb_io_in_0_bits_write = pstore_drain_structural | _pstore_drain_T_10; // @[DCache.scala 492:48]
+ assign dataArb_io_in_0_bits_wdata = {dataArb_io_in_0_bits_wdata_hi,dataArb_io_in_0_bits_wdata_lo}; // @[Cat.scala 31:58]
+ assign dataArb_io_in_0_bits_eccMask = {dataArb_io_in_0_bits_eccMask_hi,dataArb_io_in_0_bits_eccMask_lo}; // @[Cat.scala 31:58]
+ assign dataArb_io_in_1_valid = data_1 & (blockUncachedGrant | s1_valid) ? _GEN_229 : auto_out_d_valid & grantIsRefill; // @[DCache.scala 696:26 727:68]
+ assign dataArb_io_in_1_bits_addr = dataArb_io_in_0_bits_addr; // @[DCache.scala 709:27]
+ assign dataArb_io_in_1_bits_write = data_1 & (blockUncachedGrant | s1_valid) ? _GEN_230 : dataArb_io_in_0_bits_write; // @[DCache.scala 709:27 727:68]
+ assign dataArb_io_in_1_bits_wdata = dataArb_io_in_0_bits_wdata; // @[DCache.scala 709:27]
+ assign dataArb_io_in_1_bits_eccMask = dataArb_io_in_0_bits_eccMask; // @[DCache.scala 709:27]
+ assign dataArb_io_in_3_valid = io_cpu_req_valid & res; // @[DCache.scala 222:46]
+ assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[13:0]; // @[DCache.scala 225:30]
+ assign dataArb_io_in_3_bits_wdata = dataArb_io_in_1_bits_wdata; // @[DCache.scala 223:25]
+ assign dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala 226:34]
+ assign amoalu_io_mask = pstore1_mask; // @[DCache.scala 957:38]
+ assign amoalu_io_cmd = pstore1_cmd; // @[DCache.scala 958:21]
+ assign amoalu_io_lhs = {s2_data_corrected_hi,s2_data_corrected_lo}; // @[Cat.scala 31:58]
+ assign amoalu_io_rhs = pstore1_data; // @[DCache.scala 960:37]
+ always @(posedge clock) begin
+ if (reset) begin // @[DCache.scala 162:21]
+ s1_valid <= 1'h0; // @[DCache.scala 162:21]
+ end else begin
+ s1_valid <= s1_valid_x12; // @[DCache.scala 162:21]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_req_cmd <= io_cpu_req_bits_cmd; // @[Reg.scala 17:22]
+ end
+ if (reset) begin // @[DCache.scala 306:21]
+ s2_valid <= 1'h0; // @[DCache.scala 306:21]
+ end else begin
+ s2_valid <= s2_valid_x44; // @[DCache.scala 306:21]
+ end
+ if (_T_265) begin // @[DCache.scala 649:26]
+ if (grantIsCached) begin // @[DCache.scala 650:26]
+ s2_req_cmd <= _GEN_42;
+ end else if (data_1) begin // @[DCache.scala 666:34]
+ s2_req_cmd <= 5'h0; // @[DCache.scala 670:22]
+ end else begin
+ s2_req_cmd <= _GEN_42;
+ end
+ end else begin
+ s2_req_cmd <= _GEN_42;
+ end
+ if (reset) begin // @[DCache.scala 479:29]
+ pstore1_held <= 1'h0; // @[DCache.scala 479:29]
+ end else begin
+ pstore1_held <= pstore1_valid & pstore2_valid & ~pstore_drain; // @[DCache.scala 496:16]
+ end
+ if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
+ pstore1_addr <= s1_vaddr; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_req_addr <= s0_req_addr; // @[Reg.scala 17:22]
+ end
+ if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
+ if (_s1_write_T_1) begin // @[DCache.scala 302:20]
+ pstore1_mask <= io_cpu_s1_data_mask;
+ end else begin
+ pstore1_mask <= s1_mask_xwr;
+ end
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_req_size <= io_cpu_req_bits_size; // @[Reg.scala 17:22]
+ end
+ if (reset) begin // @[DCache.scala 476:30]
+ pstore2_valid <= 1'h0; // @[DCache.scala 476:30]
+ end else begin
+ pstore2_valid <= pstore2_valid & _pstore1_held_T_9 | advance_pstore1; // @[DCache.scala 498:17]
+ end
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_addr <= pstore1_addr; // @[Reg.scala 17:22]
+ end
+ if (advance_pstore1) begin // @[DCache.scala 507:45]
+ mask <= _pstore2_storegen_mask_mask_T_2; // @[DCache.scala 509:12]
+ end
+ s2_not_nacked_in_s1 <= ~s1_nack; // @[DCache.scala 310:37]
+ if (_T_34) begin // @[Reg.scala 17:18]
+ if (inScratchpad) begin // @[DCache.scala 279:25]
+ s2_hit_state_state <= 2'h3;
+ end else begin
+ s2_hit_state_state <= 2'h0;
+ end
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_req_no_xcpt <= io_cpu_req_bits_no_xcpt; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_req_tag <= io_cpu_req_bits_tag; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_req_signed <= io_cpu_req_bits_signed; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_req_dprv <= io_cpu_req_bits_dprv; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_tlb_req_vaddr <= s0_req_addr; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_tlb_req_size <= io_cpu_req_bits_size; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_tlb_req_cmd <= io_cpu_req_bits_cmd; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_tlb_req_prv <= io_cpu_req_bits_dprv; // @[Reg.scala 17:22]
+ end
+ s1_flush_valid <= _s1_flush_valid_T & ~s1_flush_valid & _s2_cannot_victimize_T; // @[DCache.scala 988:64]
+ if (reset) begin // @[DCache.scala 216:33]
+ uncachedInFlight_0 <= 1'h0; // @[DCache.scala 216:33]
+ end else if (_T_265) begin // @[DCache.scala 649:26]
+ if (grantIsCached) begin // @[DCache.scala 650:26]
+ uncachedInFlight_0 <= _GEN_162;
+ end else if (d_last) begin // @[DCache.scala 661:28]
+ uncachedInFlight_0 <= 1'h0; // @[DCache.scala 663:13]
+ end else begin
+ uncachedInFlight_0 <= _GEN_162;
+ end
+ end else begin
+ uncachedInFlight_0 <= _GEN_162;
+ end
+ if (_T_248) begin // @[DCache.scala 606:26]
+ uncachedReqs_0_addr <= s2_req_addr;
+ end
+ if (_T_248) begin // @[DCache.scala 606:26]
+ uncachedReqs_0_tag <= s2_req_tag;
+ end
+ if (_T_248) begin // @[DCache.scala 606:26]
+ uncachedReqs_0_size <= s2_req_size;
+ end
+ if (_T_248) begin // @[DCache.scala 606:26]
+ uncachedReqs_0_signed <= s2_req_signed;
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_did_read <= _s1_did_read_T_54; // @[Reg.scala 17:22]
+ end
+ if (s0_clk_en) begin // @[Reg.scala 17:18]
+ s1_read_mask <= dataArb_io_in_3_bits_wordMask; // @[Reg.scala 17:22]
+ end
+ if (_T_265) begin // @[DCache.scala 649:26]
+ if (grantIsCached) begin // @[DCache.scala 650:26]
+ s2_req_addr <= _GEN_40;
+ end else if (data_1) begin // @[DCache.scala 666:34]
+ s2_req_addr <= {{2'd0}, _s2_req_addr_T_1}; // @[DCache.scala 674:23]
+ end else begin
+ s2_req_addr <= _GEN_40;
+ end
+ end else begin
+ s2_req_addr <= _GEN_40;
+ end
+ if (_T_265) begin // @[DCache.scala 649:26]
+ if (grantIsCached) begin // @[DCache.scala 650:26]
+ s2_req_tag <= _GEN_41;
+ end else if (data_1) begin // @[DCache.scala 666:34]
+ s2_req_tag <= uncachedReqs_0_tag; // @[DCache.scala 673:22]
+ end else begin
+ s2_req_tag <= _GEN_41;
+ end
+ end else begin
+ s2_req_tag <= _GEN_41;
+ end
+ if (_T_265) begin // @[DCache.scala 649:26]
+ if (grantIsCached) begin // @[DCache.scala 650:26]
+ s2_req_size <= _GEN_43;
+ end else if (data_1) begin // @[DCache.scala 666:34]
+ s2_req_size <= uncachedReqs_0_size; // @[DCache.scala 671:23]
+ end else begin
+ s2_req_size <= _GEN_43;
+ end
+ end else begin
+ s2_req_size <= _GEN_43;
+ end
+ if (_T_265) begin // @[DCache.scala 649:26]
+ if (grantIsCached) begin // @[DCache.scala 650:26]
+ s2_req_signed <= _GEN_44;
+ end else if (data_1) begin // @[DCache.scala 666:34]
+ s2_req_signed <= uncachedReqs_0_signed; // @[DCache.scala 672:25]
+ end else begin
+ s2_req_signed <= _GEN_44;
+ end
+ end else begin
+ s2_req_signed <= _GEN_44;
+ end
+ if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
+ s2_req_dprv <= s1_req_dprv; // @[DCache.scala 321:12]
+ end
+ if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
+ s2_req_no_xcpt <= s1_req_no_xcpt; // @[DCache.scala 321:12]
+ end
+ if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
+ s2_tlb_xcpt_pf_ld <= tlb_io_resp_pf_ld; // @[DCache.scala 323:17]
+ end
+ if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
+ s2_tlb_xcpt_pf_st <= tlb_io_resp_pf_st; // @[DCache.scala 323:17]
+ end
+ if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
+ s2_tlb_xcpt_ae_ld <= tlb_io_resp_ae_ld; // @[DCache.scala 323:17]
+ end
+ if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
+ s2_tlb_xcpt_ae_st <= tlb_io_resp_ae_st; // @[DCache.scala 323:17]
+ end
+ if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
+ s2_tlb_xcpt_ma_ld <= tlb_io_resp_ma_ld; // @[DCache.scala 323:17]
+ end
+ if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
+ s2_tlb_xcpt_ma_st <= tlb_io_resp_ma_st; // @[DCache.scala 323:17]
+ end
+ if (_T_265) begin // @[DCache.scala 649:26]
+ if (!(grantIsCached)) begin // @[DCache.scala 650:26]
+ if (data_1) begin // @[DCache.scala 666:34]
+ s2_uncached_resp_addr <= uncachedReqs_0_addr; // @[DCache.scala 679:33]
+ end
+ end
+ end
+ if (_T_34) begin // @[Reg.scala 17:18]
+ s2_vaddr_r <= s1_vaddr; // @[Reg.scala 17:22]
+ end
+ s2_flush_valid_pre_tag_ecc <= s1_flush_valid; // @[DCache.scala 330:43]
+ if (data_1 & (blockUncachedGrant | s1_valid)) begin // @[DCache.scala 727:68]
+ if (auto_out_d_valid) begin // @[DCache.scala 730:29]
+ blockUncachedGrant <= _T_288; // @[DCache.scala 734:28]
+ end else begin
+ blockUncachedGrant <= dataArb_io_out_valid; // @[DCache.scala 726:24]
+ end
+ end else begin
+ blockUncachedGrant <= dataArb_io_out_valid; // @[DCache.scala 726:24]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_T_265) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (beats1_opdata) begin // @[Edges.scala 220:14]
+ counter <= beats1_decode;
+ end else begin
+ counter <= 9'h0;
+ end
+ end else begin
+ counter <= counter1;
+ end
+ end
+ if (en) begin // @[Reg.scala 17:18]
+ s2_data <= _s2_data_T_6; // @[Reg.scala 17:22]
+ end
+ if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
+ pstore1_cmd <= s1_req_cmd; // @[Reg.scala 17:22]
+ end
+ if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
+ pstore1_data <= io_cpu_s1_data_data; // @[Reg.scala 17:22]
+ end
+ if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
+ pstore1_rmw_r <= _pstore1_rmw_T_52; // @[Reg.scala 17:22]
+ end
+ pstore_drain_on_miss_REG <= io_cpu_s2_nack; // @[DCache.scala 478:56]
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_storegen_data_r <= pstore1_storegen_data[7:0]; // @[Reg.scala 17:22]
+ end
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_storegen_data_r_1 <= pstore1_storegen_data[15:8]; // @[Reg.scala 17:22]
+ end
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_storegen_data_r_2 <= pstore1_storegen_data[23:16]; // @[Reg.scala 17:22]
+ end
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_storegen_data_r_3 <= pstore1_storegen_data[31:24]; // @[Reg.scala 17:22]
+ end
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_storegen_data_r_4 <= pstore1_storegen_data[39:32]; // @[Reg.scala 17:22]
+ end
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_storegen_data_r_5 <= pstore1_storegen_data[47:40]; // @[Reg.scala 17:22]
+ end
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_storegen_data_r_6 <= pstore1_storegen_data[55:48]; // @[Reg.scala 17:22]
+ end
+ if (advance_pstore1) begin // @[Reg.scala 17:18]
+ pstore2_storegen_data_r_7 <= pstore1_storegen_data[63:56]; // @[Reg.scala 17:22]
+ end
+ io_cpu_s2_xcpt_REG <= tlb_io_req_valid & _io_cpu_ordered_T & _s1_valid_not_nacked_T; // @[DCache.scala 906:65]
+ doUncachedResp <= io_cpu_replay_next; // @[DCache.scala 922:27]
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~_dataArb_io_in_3_valid_T_52 | res) & ~reset) begin
+ $fatal; // @[DCache.scala 1160:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~_dataArb_io_in_3_valid_T_52 | res)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:1160 assert(!needsRead(req) || res)\n"); // @[DCache.scala 1160:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(s1_valid_masked & _s1_write_T_1) | &_T_28) & _dataArb_io_in_3_valid_T_56) begin
+ $fatal; // @[DCache.scala 304:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_dataArb_io_in_3_valid_T_56 & ~(~(s1_valid_masked & _s1_write_T_1) | &_T_28)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at DCache.scala:304 assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)\n"
+ ); // @[DCache.scala 304:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~_dataArb_io_in_3_valid_T_52 | res) & ~reset) begin
+ $fatal; // @[DCache.scala 1160:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~_dataArb_io_in_3_valid_T_52 | res)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:1160 assert(!needsRead(req) || res)\n"); // @[DCache.scala 1160:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(pstore1_rmw_r | pstore1_valid == pstore1_valid) & _dataArb_io_in_3_valid_T_56) begin
+ $fatal; // @[DCache.scala 485:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_dataArb_io_in_3_valid_T_56 & ~(pstore1_rmw_r | pstore1_valid == pstore1_valid)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at DCache.scala:485 assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)\n"
+ ); // @[DCache.scala 485:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~auto_out_d_valid | _T_256) & _dataArb_io_in_3_valid_T_56) begin
+ $fatal; // @[DCache.scala 629:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_dataArb_io_in_3_valid_T_56 & ~(~auto_out_d_valid | _T_256)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at DCache.scala:629 assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes))\n"
+ ); // @[DCache.scala 629:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_265 & grantIsCached & _dataArb_io_in_3_valid_T_56) begin
+ $fatal; // @[DCache.scala 652:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_265 & grantIsCached & _dataArb_io_in_3_valid_T_56) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: A GrantData was unexpected by the dcache.\n at DCache.scala:652 assert(cached_grant_wait, \"A GrantData was unexpected by the dcache.\")\n"
+ ); // @[DCache.scala 652:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_a_source_T & (_T_265 & _T_318 & d_last & _dataArb_io_in_3_valid_T_56)) begin
+ $fatal; // @[DCache.scala 662:17]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_265 & _T_318 & d_last & _dataArb_io_in_3_valid_T_56 & _a_source_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: An AccessAck was unexpected by the dcache.\n at DCache.scala:662 assert(f, \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n"
+ ); // @[DCache.scala 662:17]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(_T_265 & d_first & grantIsCached)) & _dataArb_io_in_3_valid_T_56) begin
+ $fatal; // @[DCache.scala 691:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_dataArb_io_in_3_valid_T_56 & ~(~(_T_265 & d_first & grantIsCached))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at DCache.scala:691 assert(tl_out.e.fire() === (tl_out.d.fire() && d_first && grantIsCached))\n"
+ ); // @[DCache.scala 691:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(s2_valid_masked & _T_303)) & _dataArb_io_in_3_valid_T_56) begin
+ $fatal; // @[DCache.scala 910:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_dataArb_io_in_3_valid_T_56 & ~(~(s2_valid_masked & _T_303))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at DCache.scala:910 assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))\n"
+ ); // @[DCache.scala 910:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_io_cpu_s2_nack_T_4 & (doUncachedResp & _dataArb_io_in_3_valid_T_56)) begin
+ $fatal; // @[DCache.scala 926:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (doUncachedResp & _dataArb_io_in_3_valid_T_56 & ~_io_cpu_s2_nack_T_4) begin
+ $fwrite(32'h80000002,"Assertion failed\n at DCache.scala:926 assert(!s2_valid_hit)\n"); // @[DCache.scala 926:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ s1_valid = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ s1_req_cmd = _RAND_1[4:0];
+ _RAND_2 = {1{`RANDOM}};
+ s2_valid = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ s2_req_cmd = _RAND_3[4:0];
+ _RAND_4 = {1{`RANDOM}};
+ pstore1_held = _RAND_4[0:0];
+ _RAND_5 = {2{`RANDOM}};
+ pstore1_addr = _RAND_5[33:0];
+ _RAND_6 = {2{`RANDOM}};
+ s1_req_addr = _RAND_6[33:0];
+ _RAND_7 = {1{`RANDOM}};
+ pstore1_mask = _RAND_7[7:0];
+ _RAND_8 = {1{`RANDOM}};
+ s1_req_size = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ pstore2_valid = _RAND_9[0:0];
+ _RAND_10 = {2{`RANDOM}};
+ pstore2_addr = _RAND_10[33:0];
+ _RAND_11 = {1{`RANDOM}};
+ mask = _RAND_11[7:0];
+ _RAND_12 = {1{`RANDOM}};
+ s2_not_nacked_in_s1 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ s2_hit_state_state = _RAND_13[1:0];
+ _RAND_14 = {1{`RANDOM}};
+ s1_req_no_xcpt = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ s1_req_tag = _RAND_15[6:0];
+ _RAND_16 = {1{`RANDOM}};
+ s1_req_signed = _RAND_16[0:0];
+ _RAND_17 = {1{`RANDOM}};
+ s1_req_dprv = _RAND_17[1:0];
+ _RAND_18 = {2{`RANDOM}};
+ s1_tlb_req_vaddr = _RAND_18[33:0];
+ _RAND_19 = {1{`RANDOM}};
+ s1_tlb_req_size = _RAND_19[1:0];
+ _RAND_20 = {1{`RANDOM}};
+ s1_tlb_req_cmd = _RAND_20[4:0];
+ _RAND_21 = {1{`RANDOM}};
+ s1_tlb_req_prv = _RAND_21[1:0];
+ _RAND_22 = {1{`RANDOM}};
+ s1_flush_valid = _RAND_22[0:0];
+ _RAND_23 = {1{`RANDOM}};
+ uncachedInFlight_0 = _RAND_23[0:0];
+ _RAND_24 = {2{`RANDOM}};
+ uncachedReqs_0_addr = _RAND_24[33:0];
+ _RAND_25 = {1{`RANDOM}};
+ uncachedReqs_0_tag = _RAND_25[6:0];
+ _RAND_26 = {1{`RANDOM}};
+ uncachedReqs_0_size = _RAND_26[1:0];
+ _RAND_27 = {1{`RANDOM}};
+ uncachedReqs_0_signed = _RAND_27[0:0];
+ _RAND_28 = {1{`RANDOM}};
+ s1_did_read = _RAND_28[0:0];
+ _RAND_29 = {1{`RANDOM}};
+ s1_read_mask = _RAND_29[0:0];
+ _RAND_30 = {2{`RANDOM}};
+ s2_req_addr = _RAND_30[33:0];
+ _RAND_31 = {1{`RANDOM}};
+ s2_req_tag = _RAND_31[6:0];
+ _RAND_32 = {1{`RANDOM}};
+ s2_req_size = _RAND_32[1:0];
+ _RAND_33 = {1{`RANDOM}};
+ s2_req_signed = _RAND_33[0:0];
+ _RAND_34 = {1{`RANDOM}};
+ s2_req_dprv = _RAND_34[1:0];
+ _RAND_35 = {1{`RANDOM}};
+ s2_req_no_xcpt = _RAND_35[0:0];
+ _RAND_36 = {1{`RANDOM}};
+ s2_tlb_xcpt_pf_ld = _RAND_36[0:0];
+ _RAND_37 = {1{`RANDOM}};
+ s2_tlb_xcpt_pf_st = _RAND_37[0:0];
+ _RAND_38 = {1{`RANDOM}};
+ s2_tlb_xcpt_ae_ld = _RAND_38[0:0];
+ _RAND_39 = {1{`RANDOM}};
+ s2_tlb_xcpt_ae_st = _RAND_39[0:0];
+ _RAND_40 = {1{`RANDOM}};
+ s2_tlb_xcpt_ma_ld = _RAND_40[0:0];
+ _RAND_41 = {1{`RANDOM}};
+ s2_tlb_xcpt_ma_st = _RAND_41[0:0];
+ _RAND_42 = {2{`RANDOM}};
+ s2_uncached_resp_addr = _RAND_42[33:0];
+ _RAND_43 = {2{`RANDOM}};
+ s2_vaddr_r = _RAND_43[33:0];
+ _RAND_44 = {1{`RANDOM}};
+ s2_flush_valid_pre_tag_ecc = _RAND_44[0:0];
+ _RAND_45 = {1{`RANDOM}};
+ blockUncachedGrant = _RAND_45[0:0];
+ _RAND_46 = {1{`RANDOM}};
+ counter = _RAND_46[8:0];
+ _RAND_47 = {2{`RANDOM}};
+ s2_data = _RAND_47[63:0];
+ _RAND_48 = {1{`RANDOM}};
+ pstore1_cmd = _RAND_48[4:0];
+ _RAND_49 = {2{`RANDOM}};
+ pstore1_data = _RAND_49[63:0];
+ _RAND_50 = {1{`RANDOM}};
+ pstore1_rmw_r = _RAND_50[0:0];
+ _RAND_51 = {1{`RANDOM}};
+ pstore_drain_on_miss_REG = _RAND_51[0:0];
+ _RAND_52 = {1{`RANDOM}};
+ pstore2_storegen_data_r = _RAND_52[7:0];
+ _RAND_53 = {1{`RANDOM}};
+ pstore2_storegen_data_r_1 = _RAND_53[7:0];
+ _RAND_54 = {1{`RANDOM}};
+ pstore2_storegen_data_r_2 = _RAND_54[7:0];
+ _RAND_55 = {1{`RANDOM}};
+ pstore2_storegen_data_r_3 = _RAND_55[7:0];
+ _RAND_56 = {1{`RANDOM}};
+ pstore2_storegen_data_r_4 = _RAND_56[7:0];
+ _RAND_57 = {1{`RANDOM}};
+ pstore2_storegen_data_r_5 = _RAND_57[7:0];
+ _RAND_58 = {1{`RANDOM}};
+ pstore2_storegen_data_r_6 = _RAND_58[7:0];
+ _RAND_59 = {1{`RANDOM}};
+ pstore2_storegen_data_r_7 = _RAND_59[7:0];
+ _RAND_60 = {1{`RANDOM}};
+ io_cpu_s2_xcpt_REG = _RAND_60[0:0];
+ _RAND_61 = {1{`RANDOM}};
+ doUncachedResp = _RAND_61[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ICache(
+ input clock,
+ input reset,
+ input auto_master_out_a_ready,
+ output auto_master_out_a_valid,
+ output [31:0] auto_master_out_a_bits_address,
+ input auto_master_out_d_valid,
+ input [2:0] auto_master_out_d_bits_opcode,
+ input [3:0] auto_master_out_d_bits_size,
+ input [63:0] auto_master_out_d_bits_data,
+ input auto_master_out_d_bits_corrupt,
+ output io_req_ready,
+ input io_req_valid,
+ input [32:0] io_req_bits_addr,
+ input [31:0] io_s1_paddr,
+ input io_s1_kill,
+ input io_s2_kill,
+ output io_resp_valid,
+ output [31:0] io_resp_bits_data,
+ output io_resp_bits_ae,
+ input io_invalidate
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [63:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+`endif // RANDOMIZE_REG_INIT
+ wire [5:0] tag_array_RW0_addr; // @[DescribedSRAM.scala 19:26]
+ wire tag_array_RW0_en; // @[DescribedSRAM.scala 19:26]
+ wire tag_array_RW0_clk; // @[DescribedSRAM.scala 19:26]
+ wire tag_array_RW0_wmode; // @[DescribedSRAM.scala 19:26]
+ wire [20:0] tag_array_RW0_wdata_0; // @[DescribedSRAM.scala 19:26]
+ wire [20:0] tag_array_RW0_rdata_0; // @[DescribedSRAM.scala 19:26]
+ wire [8:0] data_arrays_0_RW0_addr; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_en; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_clk; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_0_RW0_wmode; // @[DescribedSRAM.scala 19:26]
+ wire [31:0] data_arrays_0_RW0_wdata_0; // @[DescribedSRAM.scala 19:26]
+ wire [31:0] data_arrays_0_RW0_rdata_0; // @[DescribedSRAM.scala 19:26]
+ wire [8:0] data_arrays_1_RW0_addr; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_1_RW0_en; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_1_RW0_clk; // @[DescribedSRAM.scala 19:26]
+ wire data_arrays_1_RW0_wmode; // @[DescribedSRAM.scala 19:26]
+ wire [31:0] data_arrays_1_RW0_wdata_0; // @[DescribedSRAM.scala 19:26]
+ wire [31:0] data_arrays_1_RW0_rdata_0; // @[DescribedSRAM.scala 19:26]
+ wire s0_valid = io_req_ready & io_req_valid; // @[Decoupled.scala 50:35]
+ reg s1_valid; // @[ICache.scala 168:21]
+ reg [63:0] vb_array; // @[ICache.scala 230:21]
+ wire [5:0] s1_idx = io_s1_paddr[11:6]; // @[ICache.scala 485:21]
+ wire [6:0] _s1_vb_T = {1'h0,s1_idx}; // @[Cat.scala 31:58]
+ wire [63:0] _s1_vb_T_1 = vb_array >> _s1_vb_T; // @[ICache.scala 258:25]
+ wire s1_vb = _s1_vb_T_1[0]; // @[ICache.scala 258:25]
+ wire [19:0] tag = tag_array_RW0_rdata_0[19:0]; // @[package.scala 154:13]
+ wire [19:0] s1_tag = io_s1_paddr[31:12]; // @[ICache.scala 253:30]
+ wire tagMatch = s1_vb & tag == s1_tag; // @[ICache.scala 261:26]
+ wire _s1_tag_hit_0_T = tagMatch; // @[ICache.scala 261:26]
+ wire s1_hit = tagMatch; // @[ICache.scala 261:26]
+ reg s2_valid; // @[ICache.scala 173:25]
+ reg s2_hit; // @[ICache.scala 174:23]
+ reg invalidated; // @[ICache.scala 176:24]
+ reg refill_valid; // @[ICache.scala 177:29]
+ wire s2_miss = s2_valid & ~s2_hit & ~io_s2_kill; // @[ICache.scala 181:37]
+ reg s2_request_refill_REG; // @[ICache.scala 183:45]
+ wire s2_request_refill = s2_miss & s2_request_refill_REG; // @[ICache.scala 183:35]
+ wire refill_fire = auto_master_out_a_ready & s2_request_refill; // @[Decoupled.scala 50:35]
+ wire s1_can_request_refill = ~(s2_miss | refill_valid); // @[ICache.scala 182:31]
+ wire _refill_paddr_T = s1_valid & s1_can_request_refill; // @[ICache.scala 184:54]
+ reg [31:0] refill_paddr; // @[Reg.scala 16:16]
+ wire [19:0] refill_tag = refill_paddr[31:12]; // @[ICache.scala 186:33]
+ wire [5:0] refill_idx = refill_paddr[11:6]; // @[ICache.scala 485:21]
+ wire refill_one_beat_opdata = auto_master_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire refill_one_beat = auto_master_out_d_valid & refill_one_beat_opdata; // @[ICache.scala 188:41]
+ wire [26:0] _beats1_decode_T_1 = 27'hfff << auto_master_out_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] beats1_decode = _beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire [8:0] beats1 = refill_one_beat_opdata ? beats1_decode : 9'h0; // @[Edges.scala 220:14]
+ reg [8:0] counter; // @[Edges.scala 228:27]
+ wire [8:0] counter1 = counter - 9'h1; // @[Edges.scala 229:28]
+ wire first = counter == 9'h0; // @[Edges.scala 230:25]
+ wire last = counter == 9'h1 | beats1 == 9'h0; // @[Edges.scala 231:37]
+ wire d_done = last & auto_master_out_d_valid; // @[Edges.scala 232:22]
+ wire [8:0] _count_T = ~counter1; // @[Edges.scala 233:27]
+ wire [8:0] refill_cnt = beats1 & _count_T; // @[Edges.scala 233:25]
+ wire refill_done = refill_one_beat & d_done; // @[ICache.scala 194:37]
+ wire _tag_rdata_T_2 = ~refill_done & s0_valid; // @[ICache.scala 217:83]
+ reg accruedRefillError; // @[ICache.scala 218:31]
+ wire refillError = auto_master_out_d_bits_corrupt | refill_cnt > 9'h0 & accruedRefillError; // @[ICache.scala 219:43]
+ wire [6:0] _vb_array_T = {1'h0,refill_idx}; // @[Cat.scala 31:58]
+ wire _vb_array_T_1 = ~invalidated; // @[ICache.scala 234:75]
+ wire [127:0] _vb_array_T_3 = 128'h1 << _vb_array_T; // @[ICache.scala 234:32]
+ wire [127:0] _GEN_52 = {{64'd0}, vb_array}; // @[ICache.scala 234:32]
+ wire [127:0] _vb_array_T_4 = _GEN_52 | _vb_array_T_3; // @[ICache.scala 234:32]
+ wire [63:0] _vb_array_T_5 = ~vb_array; // @[ICache.scala 234:32]
+ wire [127:0] _GEN_53 = {{64'd0}, _vb_array_T_5}; // @[ICache.scala 234:32]
+ wire [127:0] _vb_array_T_6 = _GEN_53 | _vb_array_T_3; // @[ICache.scala 234:32]
+ wire [127:0] _vb_array_T_7 = ~_vb_array_T_6; // @[ICache.scala 234:32]
+ wire [127:0] _vb_array_T_8 = refill_done & ~invalidated ? _vb_array_T_4 : _vb_array_T_7; // @[ICache.scala 234:32]
+ wire [127:0] _GEN_16 = refill_one_beat ? _vb_array_T_8 : {{64'd0}, vb_array}; // @[ICache.scala 231:26 234:14 230:21]
+ wire [127:0] _GEN_17 = io_invalidate ? 128'h0 : _GEN_16; // @[ICache.scala 237:21 238:14]
+ wire _GEN_18 = io_invalidate | invalidated; // @[ICache.scala 237:21 239:17 176:24]
+ wire tl_error = tag_array_RW0_rdata_0[20]; // @[package.scala 154:13]
+ wire s1_tl_error_0 = tagMatch & tl_error; // @[ICache.scala 263:32]
+ wire _s0_ren_T_1 = ~io_req_bits_addr[2]; // @[ICache.scala 281:111]
+ wire s0_ren = s0_valid & _s0_ren_T_1; // @[ICache.scala 283:28]
+ wire wen = refill_one_beat & _vb_array_T_1; // @[ICache.scala 284:32]
+ wire [8:0] _mem_idx_T = {refill_idx, 3'h0}; // @[ICache.scala 285:52]
+ wire [8:0] _mem_idx_T_1 = _mem_idx_T | refill_cnt; // @[ICache.scala 285:79]
+ wire _dout_T_1 = ~wen & s0_ren; // @[ICache.scala 294:46]
+ wire [31:0] _GEN_30 = data_arrays_0_RW0_rdata_0; // @[ICache.scala 295:71 296:15]
+ wire s0_ren_1 = s0_valid & io_req_bits_addr[2]; // @[ICache.scala 283:28]
+ wire _dout_T_5 = ~wen & s0_ren_1; // @[ICache.scala 294:46]
+ reg [31:0] s2_dout_0; // @[Reg.scala 16:16]
+ wire _s2_tl_error_T = |s1_tl_error_0; // @[ICache.scala 312:50]
+ reg s2_tl_error; // @[Reg.scala 16:16]
+ wire _GEN_50 = refill_fire | refill_valid; // @[ICache.scala 476:22 177:29 476:37]
+ tag_array tag_array ( // @[DescribedSRAM.scala 19:26]
+ .RW0_addr(tag_array_RW0_addr),
+ .RW0_en(tag_array_RW0_en),
+ .RW0_clk(tag_array_RW0_clk),
+ .RW0_wmode(tag_array_RW0_wmode),
+ .RW0_wdata_0(tag_array_RW0_wdata_0),
+ .RW0_rdata_0(tag_array_RW0_rdata_0)
+ );
+ data_arrays_0_0 data_arrays_0 ( // @[DescribedSRAM.scala 19:26]
+ .RW0_addr(data_arrays_0_RW0_addr),
+ .RW0_en(data_arrays_0_RW0_en),
+ .RW0_clk(data_arrays_0_RW0_clk),
+ .RW0_wmode(data_arrays_0_RW0_wmode),
+ .RW0_wdata_0(data_arrays_0_RW0_wdata_0),
+ .RW0_rdata_0(data_arrays_0_RW0_rdata_0)
+ );
+ data_arrays_0_0 data_arrays_1 ( // @[DescribedSRAM.scala 19:26]
+ .RW0_addr(data_arrays_1_RW0_addr),
+ .RW0_en(data_arrays_1_RW0_en),
+ .RW0_clk(data_arrays_1_RW0_clk),
+ .RW0_wmode(data_arrays_1_RW0_wmode),
+ .RW0_wdata_0(data_arrays_1_RW0_wdata_0),
+ .RW0_rdata_0(data_arrays_1_RW0_rdata_0)
+ );
+ assign auto_master_out_a_valid = s2_miss & s2_request_refill_REG; // @[ICache.scala 183:35]
+ assign auto_master_out_a_bits_address = {refill_paddr[31:6], 6'h0}; // @[ICache.scala 420:64]
+ assign io_req_ready = ~refill_one_beat; // @[ICache.scala 190:19]
+ assign io_resp_valid = s2_valid & s2_hit; // @[ICache.scala 338:33]
+ assign io_resp_bits_data = s2_dout_0; // @[ICache.scala 335:25]
+ assign io_resp_bits_ae = s2_tl_error; // @[ICache.scala 336:23]
+ assign tag_array_RW0_clk = clock; // @[ICache.scala 220:22]
+ assign tag_array_RW0_wdata_0 = {refillError,refill_tag}; // @[Cat.scala 31:58]
+ assign data_arrays_0_RW0_clk = clock; // @[ICache.scala 289:16]
+ assign data_arrays_0_RW0_wdata_0 = auto_master_out_d_bits_data[31:0]; // @[ICache.scala 290:71]
+ assign data_arrays_1_RW0_clk = clock; // @[ICache.scala 289:16]
+ assign data_arrays_1_RW0_wdata_0 = auto_master_out_d_bits_data[63:32]; // @[ICache.scala 290:71]
+ assign tag_array_RW0_en = _tag_rdata_T_2 | refill_done;
+ assign tag_array_RW0_wmode = refill_one_beat & d_done; // @[ICache.scala 194:37]
+ assign tag_array_RW0_addr = refill_done ? refill_idx : io_req_bits_addr[11:6];
+ assign data_arrays_0_RW0_en = _dout_T_1 | wen;
+ assign data_arrays_0_RW0_wmode = refill_one_beat & _vb_array_T_1; // @[ICache.scala 284:32]
+ assign data_arrays_0_RW0_addr = refill_one_beat ? _mem_idx_T_1 : io_req_bits_addr[11:3]; // @[ICache.scala 285:22]
+ assign data_arrays_1_RW0_en = _dout_T_5 | wen;
+ assign data_arrays_1_RW0_wmode = refill_one_beat & _vb_array_T_1; // @[ICache.scala 284:32]
+ assign data_arrays_1_RW0_addr = refill_one_beat ? _mem_idx_T_1 : io_req_bits_addr[11:3]; // @[ICache.scala 285:22]
+ always @(posedge clock) begin
+ if (reset) begin // @[ICache.scala 168:21]
+ s1_valid <= 1'h0; // @[ICache.scala 168:21]
+ end else begin
+ s1_valid <= s0_valid; // @[ICache.scala 191:12]
+ end
+ if (reset) begin // @[ICache.scala 230:21]
+ vb_array <= 64'h0; // @[ICache.scala 230:21]
+ end else begin
+ vb_array <= _GEN_17[63:0];
+ end
+ if (reset) begin // @[ICache.scala 173:25]
+ s2_valid <= 1'h0; // @[ICache.scala 173:25]
+ end else begin
+ s2_valid <= s1_valid & ~io_s1_kill; // @[ICache.scala 173:25]
+ end
+ s2_hit <= _s1_tag_hit_0_T; // @[ICache.scala 174:23]
+ if (~refill_valid) begin // @[ICache.scala 475:24]
+ invalidated <= 1'h0; // @[ICache.scala 475:38]
+ end else begin
+ invalidated <= _GEN_18;
+ end
+ if (reset) begin // @[ICache.scala 177:29]
+ refill_valid <= 1'h0; // @[ICache.scala 177:29]
+ end else if (refill_done) begin // @[ICache.scala 477:22]
+ refill_valid <= 1'h0; // @[ICache.scala 477:37]
+ end else begin
+ refill_valid <= _GEN_50;
+ end
+ s2_request_refill_REG <= ~(s2_miss | refill_valid); // @[ICache.scala 182:31]
+ if (_refill_paddr_T) begin // @[Reg.scala 17:18]
+ refill_paddr <= io_s1_paddr; // @[Reg.scala 17:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (auto_master_out_d_valid) begin // @[Edges.scala 234:17]
+ if (first) begin // @[Edges.scala 235:21]
+ if (refill_one_beat_opdata) begin // @[Edges.scala 220:14]
+ counter <= beats1_decode;
+ end else begin
+ counter <= 9'h0;
+ end
+ end else begin
+ counter <= counter1;
+ end
+ end
+ if (refill_one_beat) begin // @[ICache.scala 231:26]
+ accruedRefillError <= refillError; // @[ICache.scala 232:24]
+ end
+ if (s1_valid) begin // @[Reg.scala 17:18]
+ if (io_s1_paddr[2]) begin // @[ICache.scala 295:71]
+ s2_dout_0 <= data_arrays_1_RW0_rdata_0; // @[ICache.scala 296:15]
+ end else begin
+ s2_dout_0 <= _GEN_30;
+ end
+ end
+ if (s1_valid) begin // @[Reg.scala 17:18]
+ s2_tl_error <= _s2_tl_error_T; // @[Reg.scala 17:22]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ s1_valid = _RAND_0[0:0];
+ _RAND_1 = {2{`RANDOM}};
+ vb_array = _RAND_1[63:0];
+ _RAND_2 = {1{`RANDOM}};
+ s2_valid = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ s2_hit = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ invalidated = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ refill_valid = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ s2_request_refill_REG = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ refill_paddr = _RAND_7[31:0];
+ _RAND_8 = {1{`RANDOM}};
+ counter = _RAND_8[8:0];
+ _RAND_9 = {1{`RANDOM}};
+ accruedRefillError = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ s2_dout_0 = _RAND_10[31:0];
+ _RAND_11 = {1{`RANDOM}};
+ s2_tl_error = _RAND_11[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ShiftQueue(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [33:0] io_enq_bits_pc,
+ input [31:0] io_enq_bits_data,
+ input io_enq_bits_xcpt_ae_inst,
+ input io_enq_bits_replay,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [33:0] io_deq_bits_pc,
+ output [31:0] io_deq_bits_data,
+ output io_deq_bits_xcpt_ae_inst,
+ output io_deq_bits_replay,
+ output [4:0] io_mask
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [63:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [63:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [63:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [63:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [63:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+`endif // RANDOMIZE_REG_INIT
+ reg valid_0; // @[ShiftQueue.scala 21:30]
+ reg valid_1; // @[ShiftQueue.scala 21:30]
+ reg valid_2; // @[ShiftQueue.scala 21:30]
+ reg valid_3; // @[ShiftQueue.scala 21:30]
+ reg valid_4; // @[ShiftQueue.scala 21:30]
+ reg [33:0] elts_0_pc; // @[ShiftQueue.scala 22:25]
+ reg [31:0] elts_0_data; // @[ShiftQueue.scala 22:25]
+ reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
+ reg elts_0_replay; // @[ShiftQueue.scala 22:25]
+ reg [33:0] elts_1_pc; // @[ShiftQueue.scala 22:25]
+ reg [31:0] elts_1_data; // @[ShiftQueue.scala 22:25]
+ reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
+ reg elts_1_replay; // @[ShiftQueue.scala 22:25]
+ reg [33:0] elts_2_pc; // @[ShiftQueue.scala 22:25]
+ reg [31:0] elts_2_data; // @[ShiftQueue.scala 22:25]
+ reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
+ reg elts_2_replay; // @[ShiftQueue.scala 22:25]
+ reg [33:0] elts_3_pc; // @[ShiftQueue.scala 22:25]
+ reg [31:0] elts_3_data; // @[ShiftQueue.scala 22:25]
+ reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
+ reg elts_3_replay; // @[ShiftQueue.scala 22:25]
+ reg [33:0] elts_4_pc; // @[ShiftQueue.scala 22:25]
+ reg [31:0] elts_4_data; // @[ShiftQueue.scala 22:25]
+ reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
+ reg elts_4_replay; // @[ShiftQueue.scala 22:25]
+ wire _wen_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _wen_T_2 = _wen_T & valid_0; // @[ShiftQueue.scala 30:45]
+ wire _wen_T_3 = valid_1 | _wen_T & valid_0; // @[ShiftQueue.scala 30:28]
+ wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala 31:48]
+ wire _wen_T_7 = _wen_T & ~valid_0; // @[ShiftQueue.scala 31:45]
+ wire wen = io_deq_ready ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala 29:10]
+ wire _valid_0_T_6 = _wen_T | valid_0; // @[ShiftQueue.scala 37:45]
+ wire _wen_T_10 = _wen_T & valid_1; // @[ShiftQueue.scala 30:45]
+ wire _wen_T_11 = valid_2 | _wen_T & valid_1; // @[ShiftQueue.scala 30:28]
+ wire _wen_T_15 = _wen_T_2 & ~valid_1; // @[ShiftQueue.scala 31:45]
+ wire wen_1 = io_deq_ready ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala 29:10]
+ wire _valid_1_T_6 = _wen_T_2 | valid_1; // @[ShiftQueue.scala 37:45]
+ wire _wen_T_18 = _wen_T & valid_2; // @[ShiftQueue.scala 30:45]
+ wire _wen_T_19 = valid_3 | _wen_T & valid_2; // @[ShiftQueue.scala 30:28]
+ wire _wen_T_23 = _wen_T_10 & ~valid_2; // @[ShiftQueue.scala 31:45]
+ wire wen_2 = io_deq_ready ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala 29:10]
+ wire _valid_2_T_6 = _wen_T_10 | valid_2; // @[ShiftQueue.scala 37:45]
+ wire _wen_T_26 = _wen_T & valid_3; // @[ShiftQueue.scala 30:45]
+ wire _wen_T_27 = valid_4 | _wen_T & valid_3; // @[ShiftQueue.scala 30:28]
+ wire _wen_T_31 = _wen_T_18 & ~valid_3; // @[ShiftQueue.scala 31:45]
+ wire wen_3 = io_deq_ready ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala 29:10]
+ wire _valid_3_T_6 = _wen_T_18 | valid_3; // @[ShiftQueue.scala 37:45]
+ wire _wen_T_34 = _wen_T & valid_4; // @[ShiftQueue.scala 30:45]
+ wire _wen_T_39 = _wen_T_26 & ~valid_4; // @[ShiftQueue.scala 31:45]
+ wire wen_4 = io_deq_ready ? _wen_T_34 : _wen_T_39; // @[ShiftQueue.scala 29:10]
+ wire _valid_4_T_6 = _wen_T_26 | valid_4; // @[ShiftQueue.scala 37:45]
+ wire [1:0] io_mask_lo = {valid_1,valid_0}; // @[ShiftQueue.scala 53:20]
+ wire [2:0] io_mask_hi = {valid_4,valid_3,valid_2}; // @[ShiftQueue.scala 53:20]
+ assign io_enq_ready = ~valid_4; // @[ShiftQueue.scala 40:19]
+ assign io_deq_valid = io_enq_valid | valid_0; // @[ShiftQueue.scala 41:16 45:{25,40}]
+ assign io_deq_bits_pc = _wen_T_6 ? io_enq_bits_pc : elts_0_pc; // @[ShiftQueue.scala 42:15 46:{22,36}]
+ assign io_deq_bits_data = _wen_T_6 ? io_enq_bits_data : elts_0_data; // @[ShiftQueue.scala 42:15 46:{22,36}]
+ assign io_deq_bits_xcpt_ae_inst = _wen_T_6 ? io_enq_bits_xcpt_ae_inst : elts_0_xcpt_ae_inst; // @[ShiftQueue.scala 42:15 46:{22,36}]
+ assign io_deq_bits_replay = _wen_T_6 ? io_enq_bits_replay : elts_0_replay; // @[ShiftQueue.scala 42:15 46:{22,36}]
+ assign io_mask = {io_mask_hi,io_mask_lo}; // @[ShiftQueue.scala 53:20]
+ always @(posedge clock) begin
+ if (reset) begin // @[ShiftQueue.scala 21:30]
+ valid_0 <= 1'h0; // @[ShiftQueue.scala 21:30]
+ end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
+ valid_0 <= _wen_T_3;
+ end else begin
+ valid_0 <= _valid_0_T_6;
+ end
+ if (reset) begin // @[ShiftQueue.scala 21:30]
+ valid_1 <= 1'h0; // @[ShiftQueue.scala 21:30]
+ end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
+ valid_1 <= _wen_T_11;
+ end else begin
+ valid_1 <= _valid_1_T_6;
+ end
+ if (reset) begin // @[ShiftQueue.scala 21:30]
+ valid_2 <= 1'h0; // @[ShiftQueue.scala 21:30]
+ end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
+ valid_2 <= _wen_T_19;
+ end else begin
+ valid_2 <= _valid_2_T_6;
+ end
+ if (reset) begin // @[ShiftQueue.scala 21:30]
+ valid_3 <= 1'h0; // @[ShiftQueue.scala 21:30]
+ end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
+ valid_3 <= _wen_T_27;
+ end else begin
+ valid_3 <= _valid_3_T_6;
+ end
+ if (reset) begin // @[ShiftQueue.scala 21:30]
+ valid_4 <= 1'h0; // @[ShiftQueue.scala 21:30]
+ end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
+ valid_4 <= _wen_T_34;
+ end else begin
+ valid_4 <= _valid_4_T_6;
+ end
+ if (wen) begin // @[ShiftQueue.scala 32:16]
+ if (valid_1) begin // @[ShiftQueue.scala 27:57]
+ elts_0_pc <= elts_1_pc;
+ end else begin
+ elts_0_pc <= io_enq_bits_pc;
+ end
+ end
+ if (wen) begin // @[ShiftQueue.scala 32:16]
+ if (valid_1) begin // @[ShiftQueue.scala 27:57]
+ elts_0_data <= elts_1_data;
+ end else begin
+ elts_0_data <= io_enq_bits_data;
+ end
+ end
+ if (wen) begin // @[ShiftQueue.scala 32:16]
+ if (valid_1) begin // @[ShiftQueue.scala 27:57]
+ elts_0_xcpt_ae_inst <= elts_1_xcpt_ae_inst;
+ end else begin
+ elts_0_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
+ end
+ end
+ if (wen) begin // @[ShiftQueue.scala 32:16]
+ if (valid_1) begin // @[ShiftQueue.scala 27:57]
+ elts_0_replay <= elts_1_replay;
+ end else begin
+ elts_0_replay <= io_enq_bits_replay;
+ end
+ end
+ if (wen_1) begin // @[ShiftQueue.scala 32:16]
+ if (valid_2) begin // @[ShiftQueue.scala 27:57]
+ elts_1_pc <= elts_2_pc;
+ end else begin
+ elts_1_pc <= io_enq_bits_pc;
+ end
+ end
+ if (wen_1) begin // @[ShiftQueue.scala 32:16]
+ if (valid_2) begin // @[ShiftQueue.scala 27:57]
+ elts_1_data <= elts_2_data;
+ end else begin
+ elts_1_data <= io_enq_bits_data;
+ end
+ end
+ if (wen_1) begin // @[ShiftQueue.scala 32:16]
+ if (valid_2) begin // @[ShiftQueue.scala 27:57]
+ elts_1_xcpt_ae_inst <= elts_2_xcpt_ae_inst;
+ end else begin
+ elts_1_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
+ end
+ end
+ if (wen_1) begin // @[ShiftQueue.scala 32:16]
+ if (valid_2) begin // @[ShiftQueue.scala 27:57]
+ elts_1_replay <= elts_2_replay;
+ end else begin
+ elts_1_replay <= io_enq_bits_replay;
+ end
+ end
+ if (wen_2) begin // @[ShiftQueue.scala 32:16]
+ if (valid_3) begin // @[ShiftQueue.scala 27:57]
+ elts_2_pc <= elts_3_pc;
+ end else begin
+ elts_2_pc <= io_enq_bits_pc;
+ end
+ end
+ if (wen_2) begin // @[ShiftQueue.scala 32:16]
+ if (valid_3) begin // @[ShiftQueue.scala 27:57]
+ elts_2_data <= elts_3_data;
+ end else begin
+ elts_2_data <= io_enq_bits_data;
+ end
+ end
+ if (wen_2) begin // @[ShiftQueue.scala 32:16]
+ if (valid_3) begin // @[ShiftQueue.scala 27:57]
+ elts_2_xcpt_ae_inst <= elts_3_xcpt_ae_inst;
+ end else begin
+ elts_2_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
+ end
+ end
+ if (wen_2) begin // @[ShiftQueue.scala 32:16]
+ if (valid_3) begin // @[ShiftQueue.scala 27:57]
+ elts_2_replay <= elts_3_replay;
+ end else begin
+ elts_2_replay <= io_enq_bits_replay;
+ end
+ end
+ if (wen_3) begin // @[ShiftQueue.scala 32:16]
+ if (valid_4) begin // @[ShiftQueue.scala 27:57]
+ elts_3_pc <= elts_4_pc;
+ end else begin
+ elts_3_pc <= io_enq_bits_pc;
+ end
+ end
+ if (wen_3) begin // @[ShiftQueue.scala 32:16]
+ if (valid_4) begin // @[ShiftQueue.scala 27:57]
+ elts_3_data <= elts_4_data;
+ end else begin
+ elts_3_data <= io_enq_bits_data;
+ end
+ end
+ if (wen_3) begin // @[ShiftQueue.scala 32:16]
+ if (valid_4) begin // @[ShiftQueue.scala 27:57]
+ elts_3_xcpt_ae_inst <= elts_4_xcpt_ae_inst;
+ end else begin
+ elts_3_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
+ end
+ end
+ if (wen_3) begin // @[ShiftQueue.scala 32:16]
+ if (valid_4) begin // @[ShiftQueue.scala 27:57]
+ elts_3_replay <= elts_4_replay;
+ end else begin
+ elts_3_replay <= io_enq_bits_replay;
+ end
+ end
+ if (wen_4) begin // @[ShiftQueue.scala 32:16]
+ elts_4_pc <= io_enq_bits_pc; // @[ShiftQueue.scala 32:26]
+ end
+ if (wen_4) begin // @[ShiftQueue.scala 32:16]
+ elts_4_data <= io_enq_bits_data; // @[ShiftQueue.scala 32:26]
+ end
+ if (wen_4) begin // @[ShiftQueue.scala 32:16]
+ elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala 32:26]
+ end
+ if (wen_4) begin // @[ShiftQueue.scala 32:16]
+ elts_4_replay <= io_enq_bits_replay; // @[ShiftQueue.scala 32:26]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ valid_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ valid_1 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ valid_2 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ valid_3 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ valid_4 = _RAND_4[0:0];
+ _RAND_5 = {2{`RANDOM}};
+ elts_0_pc = _RAND_5[33:0];
+ _RAND_6 = {1{`RANDOM}};
+ elts_0_data = _RAND_6[31:0];
+ _RAND_7 = {1{`RANDOM}};
+ elts_0_xcpt_ae_inst = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ elts_0_replay = _RAND_8[0:0];
+ _RAND_9 = {2{`RANDOM}};
+ elts_1_pc = _RAND_9[33:0];
+ _RAND_10 = {1{`RANDOM}};
+ elts_1_data = _RAND_10[31:0];
+ _RAND_11 = {1{`RANDOM}};
+ elts_1_xcpt_ae_inst = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ elts_1_replay = _RAND_12[0:0];
+ _RAND_13 = {2{`RANDOM}};
+ elts_2_pc = _RAND_13[33:0];
+ _RAND_14 = {1{`RANDOM}};
+ elts_2_data = _RAND_14[31:0];
+ _RAND_15 = {1{`RANDOM}};
+ elts_2_xcpt_ae_inst = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ elts_2_replay = _RAND_16[0:0];
+ _RAND_17 = {2{`RANDOM}};
+ elts_3_pc = _RAND_17[33:0];
+ _RAND_18 = {1{`RANDOM}};
+ elts_3_data = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ elts_3_xcpt_ae_inst = _RAND_19[0:0];
+ _RAND_20 = {1{`RANDOM}};
+ elts_3_replay = _RAND_20[0:0];
+ _RAND_21 = {2{`RANDOM}};
+ elts_4_pc = _RAND_21[33:0];
+ _RAND_22 = {1{`RANDOM}};
+ elts_4_data = _RAND_22[31:0];
+ _RAND_23 = {1{`RANDOM}};
+ elts_4_xcpt_ae_inst = _RAND_23[0:0];
+ _RAND_24 = {1{`RANDOM}};
+ elts_4_replay = _RAND_24[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module PMPChecker_2(
+ input [1:0] io_prv,
+ input io_pmp_0_cfg_l,
+ input [1:0] io_pmp_0_cfg_a,
+ input io_pmp_0_cfg_x,
+ input [29:0] io_pmp_0_addr,
+ input [31:0] io_pmp_0_mask,
+ input io_pmp_1_cfg_l,
+ input [1:0] io_pmp_1_cfg_a,
+ input io_pmp_1_cfg_x,
+ input [29:0] io_pmp_1_addr,
+ input [31:0] io_pmp_1_mask,
+ input io_pmp_2_cfg_l,
+ input [1:0] io_pmp_2_cfg_a,
+ input io_pmp_2_cfg_x,
+ input [29:0] io_pmp_2_addr,
+ input [31:0] io_pmp_2_mask,
+ input io_pmp_3_cfg_l,
+ input [1:0] io_pmp_3_cfg_a,
+ input io_pmp_3_cfg_x,
+ input [29:0] io_pmp_3_addr,
+ input [31:0] io_pmp_3_mask,
+ input io_pmp_4_cfg_l,
+ input [1:0] io_pmp_4_cfg_a,
+ input io_pmp_4_cfg_x,
+ input [29:0] io_pmp_4_addr,
+ input [31:0] io_pmp_4_mask,
+ input io_pmp_5_cfg_l,
+ input [1:0] io_pmp_5_cfg_a,
+ input io_pmp_5_cfg_x,
+ input [29:0] io_pmp_5_addr,
+ input [31:0] io_pmp_5_mask,
+ input io_pmp_6_cfg_l,
+ input [1:0] io_pmp_6_cfg_a,
+ input io_pmp_6_cfg_x,
+ input [29:0] io_pmp_6_addr,
+ input [31:0] io_pmp_6_mask,
+ input io_pmp_7_cfg_l,
+ input [1:0] io_pmp_7_cfg_a,
+ input io_pmp_7_cfg_x,
+ input [29:0] io_pmp_7_addr,
+ input [31:0] io_pmp_7_mask,
+ input [31:0] io_addr,
+ output io_x
+);
+ wire default_ = io_prv > 2'h1; // @[PMP.scala 156:56]
+ wire [31:0] _res_hit_T_1 = {io_pmp_7_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_T_2 = ~_res_hit_T_1; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_T_3 = _res_hit_T_2 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_T_4 = ~_res_hit_T_3; // @[PMP.scala 61:27]
+ wire [31:0] _res_hit_T_5 = io_addr ^ _res_hit_T_4; // @[PMP.scala 64:47]
+ wire [31:0] _res_hit_T_6 = ~io_pmp_7_mask; // @[PMP.scala 64:54]
+ wire [31:0] _res_hit_T_7 = _res_hit_T_5 & _res_hit_T_6; // @[PMP.scala 64:52]
+ wire _res_hit_T_8 = _res_hit_T_7 == 32'h0; // @[PMP.scala 64:58]
+ wire [31:0] _res_hit_T_14 = {io_pmp_6_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_T_15 = ~_res_hit_T_14; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_T_16 = _res_hit_T_15 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_T_17 = ~_res_hit_T_16; // @[PMP.scala 61:27]
+ wire _res_hit_T_18 = io_addr < _res_hit_T_17; // @[PMP.scala 78:9]
+ wire _res_hit_T_19 = ~_res_hit_T_18; // @[PMP.scala 89:5]
+ wire _res_hit_T_24 = io_addr < _res_hit_T_4; // @[PMP.scala 78:9]
+ wire _res_hit_T_25 = _res_hit_T_19 & _res_hit_T_24; // @[PMP.scala 95:48]
+ wire res_hit = io_pmp_7_cfg_a[1] ? _res_hit_T_8 : io_pmp_7_cfg_a[0] & _res_hit_T_25; // @[PMP.scala 133:8]
+ wire res_ignore = default_ & ~io_pmp_7_cfg_l; // @[PMP.scala 164:26]
+ wire res_cur_cfg_x = io_pmp_7_cfg_x | res_ignore; // @[PMP.scala 184:40]
+ wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : default_; // @[PMP.scala 185:8]
+ wire [31:0] _res_hit_T_32 = io_addr ^ _res_hit_T_17; // @[PMP.scala 64:47]
+ wire [31:0] _res_hit_T_33 = ~io_pmp_6_mask; // @[PMP.scala 64:54]
+ wire [31:0] _res_hit_T_34 = _res_hit_T_32 & _res_hit_T_33; // @[PMP.scala 64:52]
+ wire _res_hit_T_35 = _res_hit_T_34 == 32'h0; // @[PMP.scala 64:58]
+ wire [31:0] _res_hit_T_41 = {io_pmp_5_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_T_42 = ~_res_hit_T_41; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_T_43 = _res_hit_T_42 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_T_44 = ~_res_hit_T_43; // @[PMP.scala 61:27]
+ wire _res_hit_T_45 = io_addr < _res_hit_T_44; // @[PMP.scala 78:9]
+ wire _res_hit_T_46 = ~_res_hit_T_45; // @[PMP.scala 89:5]
+ wire _res_hit_T_52 = _res_hit_T_46 & _res_hit_T_18; // @[PMP.scala 95:48]
+ wire res_hit_1 = io_pmp_6_cfg_a[1] ? _res_hit_T_35 : io_pmp_6_cfg_a[0] & _res_hit_T_52; // @[PMP.scala 133:8]
+ wire res_ignore_1 = default_ & ~io_pmp_6_cfg_l; // @[PMP.scala 164:26]
+ wire res_cur_1_cfg_x = io_pmp_6_cfg_x | res_ignore_1; // @[PMP.scala 184:40]
+ wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala 185:8]
+ wire [31:0] _res_hit_T_59 = io_addr ^ _res_hit_T_44; // @[PMP.scala 64:47]
+ wire [31:0] _res_hit_T_60 = ~io_pmp_5_mask; // @[PMP.scala 64:54]
+ wire [31:0] _res_hit_T_61 = _res_hit_T_59 & _res_hit_T_60; // @[PMP.scala 64:52]
+ wire _res_hit_T_62 = _res_hit_T_61 == 32'h0; // @[PMP.scala 64:58]
+ wire [31:0] _res_hit_T_68 = {io_pmp_4_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_T_69 = ~_res_hit_T_68; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_T_70 = _res_hit_T_69 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_T_71 = ~_res_hit_T_70; // @[PMP.scala 61:27]
+ wire _res_hit_T_72 = io_addr < _res_hit_T_71; // @[PMP.scala 78:9]
+ wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala 89:5]
+ wire _res_hit_T_79 = _res_hit_T_73 & _res_hit_T_45; // @[PMP.scala 95:48]
+ wire res_hit_2 = io_pmp_5_cfg_a[1] ? _res_hit_T_62 : io_pmp_5_cfg_a[0] & _res_hit_T_79; // @[PMP.scala 133:8]
+ wire res_ignore_2 = default_ & ~io_pmp_5_cfg_l; // @[PMP.scala 164:26]
+ wire res_cur_2_cfg_x = io_pmp_5_cfg_x | res_ignore_2; // @[PMP.scala 184:40]
+ wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala 185:8]
+ wire [31:0] _res_hit_T_86 = io_addr ^ _res_hit_T_71; // @[PMP.scala 64:47]
+ wire [31:0] _res_hit_T_87 = ~io_pmp_4_mask; // @[PMP.scala 64:54]
+ wire [31:0] _res_hit_T_88 = _res_hit_T_86 & _res_hit_T_87; // @[PMP.scala 64:52]
+ wire _res_hit_T_89 = _res_hit_T_88 == 32'h0; // @[PMP.scala 64:58]
+ wire [31:0] _res_hit_T_95 = {io_pmp_3_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_T_96 = ~_res_hit_T_95; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_T_97 = _res_hit_T_96 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_T_98 = ~_res_hit_T_97; // @[PMP.scala 61:27]
+ wire _res_hit_T_99 = io_addr < _res_hit_T_98; // @[PMP.scala 78:9]
+ wire _res_hit_T_100 = ~_res_hit_T_99; // @[PMP.scala 89:5]
+ wire _res_hit_T_106 = _res_hit_T_100 & _res_hit_T_72; // @[PMP.scala 95:48]
+ wire res_hit_3 = io_pmp_4_cfg_a[1] ? _res_hit_T_89 : io_pmp_4_cfg_a[0] & _res_hit_T_106; // @[PMP.scala 133:8]
+ wire res_ignore_3 = default_ & ~io_pmp_4_cfg_l; // @[PMP.scala 164:26]
+ wire res_cur_3_cfg_x = io_pmp_4_cfg_x | res_ignore_3; // @[PMP.scala 184:40]
+ wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala 185:8]
+ wire [31:0] _res_hit_T_113 = io_addr ^ _res_hit_T_98; // @[PMP.scala 64:47]
+ wire [31:0] _res_hit_T_114 = ~io_pmp_3_mask; // @[PMP.scala 64:54]
+ wire [31:0] _res_hit_T_115 = _res_hit_T_113 & _res_hit_T_114; // @[PMP.scala 64:52]
+ wire _res_hit_T_116 = _res_hit_T_115 == 32'h0; // @[PMP.scala 64:58]
+ wire [31:0] _res_hit_T_122 = {io_pmp_2_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_T_123 = ~_res_hit_T_122; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_T_124 = _res_hit_T_123 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_T_125 = ~_res_hit_T_124; // @[PMP.scala 61:27]
+ wire _res_hit_T_126 = io_addr < _res_hit_T_125; // @[PMP.scala 78:9]
+ wire _res_hit_T_127 = ~_res_hit_T_126; // @[PMP.scala 89:5]
+ wire _res_hit_T_133 = _res_hit_T_127 & _res_hit_T_99; // @[PMP.scala 95:48]
+ wire res_hit_4 = io_pmp_3_cfg_a[1] ? _res_hit_T_116 : io_pmp_3_cfg_a[0] & _res_hit_T_133; // @[PMP.scala 133:8]
+ wire res_ignore_4 = default_ & ~io_pmp_3_cfg_l; // @[PMP.scala 164:26]
+ wire res_cur_4_cfg_x = io_pmp_3_cfg_x | res_ignore_4; // @[PMP.scala 184:40]
+ wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala 185:8]
+ wire [31:0] _res_hit_T_140 = io_addr ^ _res_hit_T_125; // @[PMP.scala 64:47]
+ wire [31:0] _res_hit_T_141 = ~io_pmp_2_mask; // @[PMP.scala 64:54]
+ wire [31:0] _res_hit_T_142 = _res_hit_T_140 & _res_hit_T_141; // @[PMP.scala 64:52]
+ wire _res_hit_T_143 = _res_hit_T_142 == 32'h0; // @[PMP.scala 64:58]
+ wire [31:0] _res_hit_T_149 = {io_pmp_1_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_T_150 = ~_res_hit_T_149; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_T_151 = _res_hit_T_150 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_T_152 = ~_res_hit_T_151; // @[PMP.scala 61:27]
+ wire _res_hit_T_153 = io_addr < _res_hit_T_152; // @[PMP.scala 78:9]
+ wire _res_hit_T_154 = ~_res_hit_T_153; // @[PMP.scala 89:5]
+ wire _res_hit_T_160 = _res_hit_T_154 & _res_hit_T_126; // @[PMP.scala 95:48]
+ wire res_hit_5 = io_pmp_2_cfg_a[1] ? _res_hit_T_143 : io_pmp_2_cfg_a[0] & _res_hit_T_160; // @[PMP.scala 133:8]
+ wire res_ignore_5 = default_ & ~io_pmp_2_cfg_l; // @[PMP.scala 164:26]
+ wire res_cur_5_cfg_x = io_pmp_2_cfg_x | res_ignore_5; // @[PMP.scala 184:40]
+ wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala 185:8]
+ wire [31:0] _res_hit_T_167 = io_addr ^ _res_hit_T_152; // @[PMP.scala 64:47]
+ wire [31:0] _res_hit_T_168 = ~io_pmp_1_mask; // @[PMP.scala 64:54]
+ wire [31:0] _res_hit_T_169 = _res_hit_T_167 & _res_hit_T_168; // @[PMP.scala 64:52]
+ wire _res_hit_T_170 = _res_hit_T_169 == 32'h0; // @[PMP.scala 64:58]
+ wire [31:0] _res_hit_T_176 = {io_pmp_0_addr, 2'h0}; // @[PMP.scala 61:36]
+ wire [31:0] _res_hit_T_177 = ~_res_hit_T_176; // @[PMP.scala 61:29]
+ wire [31:0] _res_hit_T_178 = _res_hit_T_177 | 32'h3; // @[PMP.scala 61:48]
+ wire [31:0] _res_hit_T_179 = ~_res_hit_T_178; // @[PMP.scala 61:27]
+ wire _res_hit_T_180 = io_addr < _res_hit_T_179; // @[PMP.scala 78:9]
+ wire _res_hit_T_181 = ~_res_hit_T_180; // @[PMP.scala 89:5]
+ wire _res_hit_T_187 = _res_hit_T_181 & _res_hit_T_153; // @[PMP.scala 95:48]
+ wire res_hit_6 = io_pmp_1_cfg_a[1] ? _res_hit_T_170 : io_pmp_1_cfg_a[0] & _res_hit_T_187; // @[PMP.scala 133:8]
+ wire res_ignore_6 = default_ & ~io_pmp_1_cfg_l; // @[PMP.scala 164:26]
+ wire res_cur_6_cfg_x = io_pmp_1_cfg_x | res_ignore_6; // @[PMP.scala 184:40]
+ wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala 185:8]
+ wire [31:0] _res_hit_T_194 = io_addr ^ _res_hit_T_179; // @[PMP.scala 64:47]
+ wire [31:0] _res_hit_T_195 = ~io_pmp_0_mask; // @[PMP.scala 64:54]
+ wire [31:0] _res_hit_T_196 = _res_hit_T_194 & _res_hit_T_195; // @[PMP.scala 64:52]
+ wire _res_hit_T_197 = _res_hit_T_196 == 32'h0; // @[PMP.scala 64:58]
+ wire res_hit_7 = io_pmp_0_cfg_a[1] ? _res_hit_T_197 : io_pmp_0_cfg_a[0] & _res_hit_T_180; // @[PMP.scala 133:8]
+ wire res_ignore_7 = default_ & ~io_pmp_0_cfg_l; // @[PMP.scala 164:26]
+ wire res_cur_7_cfg_x = io_pmp_0_cfg_x | res_ignore_7; // @[PMP.scala 184:40]
+ assign io_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala 185:8]
+endmodule
+module TLB_1(
+ input [33:0] io_req_bits_vaddr,
+ output [31:0] io_resp_paddr,
+ output io_resp_ae_inst,
+ input io_ptw_status_debug,
+ input io_ptw_pmp_0_cfg_l,
+ input [1:0] io_ptw_pmp_0_cfg_a,
+ input io_ptw_pmp_0_cfg_x,
+ input [29:0] io_ptw_pmp_0_addr,
+ input [31:0] io_ptw_pmp_0_mask,
+ input io_ptw_pmp_1_cfg_l,
+ input [1:0] io_ptw_pmp_1_cfg_a,
+ input io_ptw_pmp_1_cfg_x,
+ input [29:0] io_ptw_pmp_1_addr,
+ input [31:0] io_ptw_pmp_1_mask,
+ input io_ptw_pmp_2_cfg_l,
+ input [1:0] io_ptw_pmp_2_cfg_a,
+ input io_ptw_pmp_2_cfg_x,
+ input [29:0] io_ptw_pmp_2_addr,
+ input [31:0] io_ptw_pmp_2_mask,
+ input io_ptw_pmp_3_cfg_l,
+ input [1:0] io_ptw_pmp_3_cfg_a,
+ input io_ptw_pmp_3_cfg_x,
+ input [29:0] io_ptw_pmp_3_addr,
+ input [31:0] io_ptw_pmp_3_mask,
+ input io_ptw_pmp_4_cfg_l,
+ input [1:0] io_ptw_pmp_4_cfg_a,
+ input io_ptw_pmp_4_cfg_x,
+ input [29:0] io_ptw_pmp_4_addr,
+ input [31:0] io_ptw_pmp_4_mask,
+ input io_ptw_pmp_5_cfg_l,
+ input [1:0] io_ptw_pmp_5_cfg_a,
+ input io_ptw_pmp_5_cfg_x,
+ input [29:0] io_ptw_pmp_5_addr,
+ input [31:0] io_ptw_pmp_5_mask,
+ input io_ptw_pmp_6_cfg_l,
+ input [1:0] io_ptw_pmp_6_cfg_a,
+ input io_ptw_pmp_6_cfg_x,
+ input [29:0] io_ptw_pmp_6_addr,
+ input [31:0] io_ptw_pmp_6_mask,
+ input io_ptw_pmp_7_cfg_l,
+ input [1:0] io_ptw_pmp_7_cfg_a,
+ input io_ptw_pmp_7_cfg_x,
+ input [29:0] io_ptw_pmp_7_addr,
+ input [31:0] io_ptw_pmp_7_mask
+);
+ wire [1:0] pmp_io_prv; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_0_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_0_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_0_cfg_x; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_0_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_0_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_1_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_1_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_1_cfg_x; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_1_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_1_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_2_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_2_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_2_cfg_x; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_2_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_2_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_3_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_3_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_3_cfg_x; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_3_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_3_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_4_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_4_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_4_cfg_x; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_4_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_4_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_5_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_5_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_5_cfg_x; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_5_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_5_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_6_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_6_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_6_cfg_x; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_6_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_6_mask; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_7_cfg_l; // @[TLB.scala 233:19]
+ wire [1:0] pmp_io_pmp_7_cfg_a; // @[TLB.scala 233:19]
+ wire pmp_io_pmp_7_cfg_x; // @[TLB.scala 233:19]
+ wire [29:0] pmp_io_pmp_7_addr; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_pmp_7_mask; // @[TLB.scala 233:19]
+ wire [31:0] pmp_io_addr; // @[TLB.scala 233:19]
+ wire pmp_io_x; // @[TLB.scala 233:19]
+ wire [20:0] vpn = io_req_bits_vaddr[32:12]; // @[TLB.scala 187:30]
+ wire [21:0] mpu_ppn = io_req_bits_vaddr[33:12]; // @[TLB.scala 230:144]
+ wire [33:0] mpu_physaddr = {mpu_ppn,io_req_bits_vaddr[11:0]}; // @[Cat.scala 31:58]
+ wire [2:0] mpu_priv = {io_ptw_status_debug,2'h3}; // @[Cat.scala 31:58]
+ wire [33:0] _legal_address_T = mpu_physaddr ^ 34'h3000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_1 = {1'b0,$signed(_legal_address_T)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_3 = $signed(_legal_address_T_1) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_4 = $signed(_legal_address_T_3) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_5 = mpu_physaddr ^ 34'h4000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_6 = {1'b0,$signed(_legal_address_T_5)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_8 = $signed(_legal_address_T_6) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_9 = $signed(_legal_address_T_8) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_10 = mpu_physaddr ^ 34'h10000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_11 = {1'b0,$signed(_legal_address_T_10)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_13 = $signed(_legal_address_T_11) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_14 = $signed(_legal_address_T_13) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_15 = mpu_physaddr ^ 34'h20000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_16 = {1'b0,$signed(_legal_address_T_15)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_18 = $signed(_legal_address_T_16) & -35'sh10000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_19 = $signed(_legal_address_T_18) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_20 = mpu_physaddr ^ 34'h10010000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_21 = {1'b0,$signed(_legal_address_T_20)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_23 = $signed(_legal_address_T_21) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_24 = $signed(_legal_address_T_23) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_25 = mpu_physaddr ^ 34'h10011000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_26 = {1'b0,$signed(_legal_address_T_25)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_28 = $signed(_legal_address_T_26) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_29 = $signed(_legal_address_T_28) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_30 = mpu_physaddr ^ 34'h10012000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_31 = {1'b0,$signed(_legal_address_T_30)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_33 = $signed(_legal_address_T_31) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_34 = $signed(_legal_address_T_33) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_35 = mpu_physaddr ^ 34'h10013000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_36 = {1'b0,$signed(_legal_address_T_35)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_38 = $signed(_legal_address_T_36) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_39 = $signed(_legal_address_T_38) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_40 = mpu_physaddr ^ 34'h20000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_41 = {1'b0,$signed(_legal_address_T_40)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_43 = $signed(_legal_address_T_41) & -35'sh10000000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_44 = $signed(_legal_address_T_43) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_45 = mpu_physaddr ^ 34'h10014000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_46 = {1'b0,$signed(_legal_address_T_45)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_48 = $signed(_legal_address_T_46) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_49 = $signed(_legal_address_T_48) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_50 = mpu_physaddr ^ 34'h30000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_51 = {1'b0,$signed(_legal_address_T_50)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_53 = $signed(_legal_address_T_51) & -35'sh10000000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_54 = $signed(_legal_address_T_53) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_55 = mpu_physaddr ^ 34'hc000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_56 = {1'b0,$signed(_legal_address_T_55)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_58 = $signed(_legal_address_T_56) & -35'sh4000000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_59 = $signed(_legal_address_T_58) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_60 = mpu_physaddr ^ 34'h2000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_61 = {1'b0,$signed(_legal_address_T_60)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_63 = $signed(_legal_address_T_61) & -35'sh10000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_64 = $signed(_legal_address_T_63) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _legal_address_T_66 = {1'b0,$signed(mpu_physaddr)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_68 = $signed(_legal_address_T_66) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_69 = $signed(_legal_address_T_68) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_70 = mpu_physaddr ^ 34'h80000000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_71 = {1'b0,$signed(_legal_address_T_70)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_73 = $signed(_legal_address_T_71) & -35'sh4000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_74 = $signed(_legal_address_T_73) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_75 = mpu_physaddr ^ 34'h10000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_76 = {1'b0,$signed(_legal_address_T_75)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_78 = $signed(_legal_address_T_76) & -35'sh10000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_79 = $signed(_legal_address_T_78) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_80 = mpu_physaddr ^ 34'h100000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_81 = {1'b0,$signed(_legal_address_T_80)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_83 = $signed(_legal_address_T_81) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_84 = $signed(_legal_address_T_83) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [33:0] _legal_address_T_85 = mpu_physaddr ^ 34'h110000; // @[Parameters.scala 137:31]
+ wire [34:0] _legal_address_T_86 = {1'b0,$signed(_legal_address_T_85)}; // @[Parameters.scala 137:49]
+ wire [34:0] _legal_address_T_88 = $signed(_legal_address_T_86) & -35'sh1000; // @[Parameters.scala 137:52]
+ wire _legal_address_T_89 = $signed(_legal_address_T_88) == 35'sh0; // @[Parameters.scala 137:67]
+ wire legal_address = _legal_address_T_4 | _legal_address_T_9 | _legal_address_T_14 | _legal_address_T_19 |
+ _legal_address_T_24 | _legal_address_T_29 | _legal_address_T_34 | _legal_address_T_39 | _legal_address_T_44 |
+ _legal_address_T_49 | _legal_address_T_54 | _legal_address_T_59 | _legal_address_T_64 | _legal_address_T_69 |
+ _legal_address_T_74 | _legal_address_T_79 | _legal_address_T_84 | _legal_address_T_89; // @[TLB.scala 238:67]
+ wire [34:0] _homogeneous_T_75 = $signed(_legal_address_T_76) & 35'shba130000; // @[Parameters.scala 137:52]
+ wire _homogeneous_T_76 = $signed(_homogeneous_T_75) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _homogeneous_T_80 = $signed(_legal_address_T_16) & 35'shba130000; // @[Parameters.scala 137:52]
+ wire _homogeneous_T_81 = $signed(_homogeneous_T_80) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _homogeneous_T_85 = $signed(_legal_address_T_41) & 35'sha0000000; // @[Parameters.scala 137:52]
+ wire _homogeneous_T_86 = $signed(_homogeneous_T_85) == 35'sh0; // @[Parameters.scala 137:67]
+ wire deny_access_to_debug = mpu_priv <= 3'h3 & _legal_address_T_69; // @[TLB.scala 243:48]
+ wire _prot_r_T_6 = ~deny_access_to_debug; // @[TLB.scala 244:44]
+ wire [34:0] _prot_x_T_3 = $signed(_legal_address_T_66) & 35'sh3a134000; // @[Parameters.scala 137:52]
+ wire _prot_x_T_4 = $signed(_prot_x_T_3) == 35'sh0; // @[Parameters.scala 137:67]
+ wire [34:0] _prot_x_T_18 = $signed(_legal_address_T_11) & 35'shba136000; // @[Parameters.scala 137:52]
+ wire _prot_x_T_19 = $signed(_prot_x_T_18) == 35'sh0; // @[Parameters.scala 137:67]
+ wire _prot_x_T_28 = _prot_x_T_4 | _homogeneous_T_76 | _homogeneous_T_81 | _prot_x_T_19 | _homogeneous_T_86; // @[Parameters.scala 615:89]
+ wire _prot_x_T_67 = legal_address & _prot_x_T_28; // @[TLB.scala 240:19]
+ wire prot_x = _prot_x_T_67 & _prot_r_T_6 & pmp_io_x; // @[TLB.scala 249:65]
+ wire [19:0] ppn = vpn[19:0]; // @[TLB.scala 310:125]
+ wire [1:0] _px_array_T_1 = prot_x ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
+ wire [6:0] px_array = {_px_array_T_1,5'h0}; // @[Cat.scala 31:58]
+ wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala 427:23]
+ wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & 7'h40; // @[TLB.scala 427:33]
+ PMPChecker_2 pmp ( // @[TLB.scala 233:19]
+ .io_prv(pmp_io_prv),
+ .io_pmp_0_cfg_l(pmp_io_pmp_0_cfg_l),
+ .io_pmp_0_cfg_a(pmp_io_pmp_0_cfg_a),
+ .io_pmp_0_cfg_x(pmp_io_pmp_0_cfg_x),
+ .io_pmp_0_addr(pmp_io_pmp_0_addr),
+ .io_pmp_0_mask(pmp_io_pmp_0_mask),
+ .io_pmp_1_cfg_l(pmp_io_pmp_1_cfg_l),
+ .io_pmp_1_cfg_a(pmp_io_pmp_1_cfg_a),
+ .io_pmp_1_cfg_x(pmp_io_pmp_1_cfg_x),
+ .io_pmp_1_addr(pmp_io_pmp_1_addr),
+ .io_pmp_1_mask(pmp_io_pmp_1_mask),
+ .io_pmp_2_cfg_l(pmp_io_pmp_2_cfg_l),
+ .io_pmp_2_cfg_a(pmp_io_pmp_2_cfg_a),
+ .io_pmp_2_cfg_x(pmp_io_pmp_2_cfg_x),
+ .io_pmp_2_addr(pmp_io_pmp_2_addr),
+ .io_pmp_2_mask(pmp_io_pmp_2_mask),
+ .io_pmp_3_cfg_l(pmp_io_pmp_3_cfg_l),
+ .io_pmp_3_cfg_a(pmp_io_pmp_3_cfg_a),
+ .io_pmp_3_cfg_x(pmp_io_pmp_3_cfg_x),
+ .io_pmp_3_addr(pmp_io_pmp_3_addr),
+ .io_pmp_3_mask(pmp_io_pmp_3_mask),
+ .io_pmp_4_cfg_l(pmp_io_pmp_4_cfg_l),
+ .io_pmp_4_cfg_a(pmp_io_pmp_4_cfg_a),
+ .io_pmp_4_cfg_x(pmp_io_pmp_4_cfg_x),
+ .io_pmp_4_addr(pmp_io_pmp_4_addr),
+ .io_pmp_4_mask(pmp_io_pmp_4_mask),
+ .io_pmp_5_cfg_l(pmp_io_pmp_5_cfg_l),
+ .io_pmp_5_cfg_a(pmp_io_pmp_5_cfg_a),
+ .io_pmp_5_cfg_x(pmp_io_pmp_5_cfg_x),
+ .io_pmp_5_addr(pmp_io_pmp_5_addr),
+ .io_pmp_5_mask(pmp_io_pmp_5_mask),
+ .io_pmp_6_cfg_l(pmp_io_pmp_6_cfg_l),
+ .io_pmp_6_cfg_a(pmp_io_pmp_6_cfg_a),
+ .io_pmp_6_cfg_x(pmp_io_pmp_6_cfg_x),
+ .io_pmp_6_addr(pmp_io_pmp_6_addr),
+ .io_pmp_6_mask(pmp_io_pmp_6_mask),
+ .io_pmp_7_cfg_l(pmp_io_pmp_7_cfg_l),
+ .io_pmp_7_cfg_a(pmp_io_pmp_7_cfg_a),
+ .io_pmp_7_cfg_x(pmp_io_pmp_7_cfg_x),
+ .io_pmp_7_addr(pmp_io_pmp_7_addr),
+ .io_pmp_7_mask(pmp_io_pmp_7_mask),
+ .io_addr(pmp_io_addr),
+ .io_x(pmp_io_x)
+ );
+ assign io_resp_paddr = {ppn,io_req_bits_vaddr[11:0]}; // @[Cat.scala 31:58]
+ assign io_resp_ae_inst = |_io_resp_ae_inst_T_1; // @[TLB.scala 427:41]
+ assign pmp_io_prv = mpu_priv[1:0]; // @[TLB.scala 237:14]
+ assign pmp_io_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_addr = io_ptw_pmp_0_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_0_mask = io_ptw_pmp_0_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_addr = io_ptw_pmp_1_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_1_mask = io_ptw_pmp_1_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_addr = io_ptw_pmp_2_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_2_mask = io_ptw_pmp_2_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_addr = io_ptw_pmp_3_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_3_mask = io_ptw_pmp_3_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_addr = io_ptw_pmp_4_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_4_mask = io_ptw_pmp_4_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_addr = io_ptw_pmp_5_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_5_mask = io_ptw_pmp_5_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_addr = io_ptw_pmp_6_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_6_mask = io_ptw_pmp_6_mask; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_addr = io_ptw_pmp_7_addr; // @[TLB.scala 236:14]
+ assign pmp_io_pmp_7_mask = io_ptw_pmp_7_mask; // @[TLB.scala 236:14]
+ assign pmp_io_addr = mpu_physaddr[31:0]; // @[TLB.scala 234:15]
+endmodule
+module Frontend(
+ input clock,
+ input reset,
+ input auto_icache_master_out_a_ready,
+ output auto_icache_master_out_a_valid,
+ output [31:0] auto_icache_master_out_a_bits_address,
+ input auto_icache_master_out_d_valid,
+ input [2:0] auto_icache_master_out_d_bits_opcode,
+ input [3:0] auto_icache_master_out_d_bits_size,
+ input [63:0] auto_icache_master_out_d_bits_data,
+ input auto_icache_master_out_d_bits_corrupt,
+ input io_cpu_might_request,
+ input io_cpu_req_valid,
+ input [33:0] io_cpu_req_bits_pc,
+ input io_cpu_req_bits_speculative,
+ input io_cpu_resp_ready,
+ output io_cpu_resp_valid,
+ output [33:0] io_cpu_resp_bits_pc,
+ output [31:0] io_cpu_resp_bits_data,
+ output io_cpu_resp_bits_xcpt_ae_inst,
+ output io_cpu_resp_bits_replay,
+ input io_cpu_btb_update_valid,
+ input io_cpu_bht_update_valid,
+ input io_cpu_flush_icache,
+ output [33:0] io_cpu_npc,
+ input io_ptw_status_debug,
+ input io_ptw_pmp_0_cfg_l,
+ input [1:0] io_ptw_pmp_0_cfg_a,
+ input io_ptw_pmp_0_cfg_x,
+ input [29:0] io_ptw_pmp_0_addr,
+ input [31:0] io_ptw_pmp_0_mask,
+ input io_ptw_pmp_1_cfg_l,
+ input [1:0] io_ptw_pmp_1_cfg_a,
+ input io_ptw_pmp_1_cfg_x,
+ input [29:0] io_ptw_pmp_1_addr,
+ input [31:0] io_ptw_pmp_1_mask,
+ input io_ptw_pmp_2_cfg_l,
+ input [1:0] io_ptw_pmp_2_cfg_a,
+ input io_ptw_pmp_2_cfg_x,
+ input [29:0] io_ptw_pmp_2_addr,
+ input [31:0] io_ptw_pmp_2_mask,
+ input io_ptw_pmp_3_cfg_l,
+ input [1:0] io_ptw_pmp_3_cfg_a,
+ input io_ptw_pmp_3_cfg_x,
+ input [29:0] io_ptw_pmp_3_addr,
+ input [31:0] io_ptw_pmp_3_mask,
+ input io_ptw_pmp_4_cfg_l,
+ input [1:0] io_ptw_pmp_4_cfg_a,
+ input io_ptw_pmp_4_cfg_x,
+ input [29:0] io_ptw_pmp_4_addr,
+ input [31:0] io_ptw_pmp_4_mask,
+ input io_ptw_pmp_5_cfg_l,
+ input [1:0] io_ptw_pmp_5_cfg_a,
+ input io_ptw_pmp_5_cfg_x,
+ input [29:0] io_ptw_pmp_5_addr,
+ input [31:0] io_ptw_pmp_5_mask,
+ input io_ptw_pmp_6_cfg_l,
+ input [1:0] io_ptw_pmp_6_cfg_a,
+ input io_ptw_pmp_6_cfg_x,
+ input [29:0] io_ptw_pmp_6_addr,
+ input [31:0] io_ptw_pmp_6_mask,
+ input io_ptw_pmp_7_cfg_l,
+ input [1:0] io_ptw_pmp_7_cfg_a,
+ input io_ptw_pmp_7_cfg_x,
+ input [29:0] io_ptw_pmp_7_addr,
+ input [31:0] io_ptw_pmp_7_mask,
+ input [63:0] io_ptw_customCSRs_csrs_0_value
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [63:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [63:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+`endif // RANDOMIZE_REG_INIT
+ wire icache_clock; // @[Frontend.scala 66:26]
+ wire icache_reset; // @[Frontend.scala 66:26]
+ wire icache_auto_master_out_a_ready; // @[Frontend.scala 66:26]
+ wire icache_auto_master_out_a_valid; // @[Frontend.scala 66:26]
+ wire [31:0] icache_auto_master_out_a_bits_address; // @[Frontend.scala 66:26]
+ wire icache_auto_master_out_d_valid; // @[Frontend.scala 66:26]
+ wire [2:0] icache_auto_master_out_d_bits_opcode; // @[Frontend.scala 66:26]
+ wire [3:0] icache_auto_master_out_d_bits_size; // @[Frontend.scala 66:26]
+ wire [63:0] icache_auto_master_out_d_bits_data; // @[Frontend.scala 66:26]
+ wire icache_auto_master_out_d_bits_corrupt; // @[Frontend.scala 66:26]
+ wire icache_io_req_ready; // @[Frontend.scala 66:26]
+ wire icache_io_req_valid; // @[Frontend.scala 66:26]
+ wire [32:0] icache_io_req_bits_addr; // @[Frontend.scala 66:26]
+ wire [31:0] icache_io_s1_paddr; // @[Frontend.scala 66:26]
+ wire icache_io_s1_kill; // @[Frontend.scala 66:26]
+ wire icache_io_s2_kill; // @[Frontend.scala 66:26]
+ wire icache_io_resp_valid; // @[Frontend.scala 66:26]
+ wire [31:0] icache_io_resp_bits_data; // @[Frontend.scala 66:26]
+ wire icache_io_resp_bits_ae; // @[Frontend.scala 66:26]
+ wire icache_io_invalidate; // @[Frontend.scala 66:26]
+ wire fq_clock; // @[Frontend.scala 88:57]
+ wire fq_reset; // @[Frontend.scala 88:57]
+ wire fq_io_enq_ready; // @[Frontend.scala 88:57]
+ wire fq_io_enq_valid; // @[Frontend.scala 88:57]
+ wire [33:0] fq_io_enq_bits_pc; // @[Frontend.scala 88:57]
+ wire [31:0] fq_io_enq_bits_data; // @[Frontend.scala 88:57]
+ wire fq_io_enq_bits_xcpt_ae_inst; // @[Frontend.scala 88:57]
+ wire fq_io_enq_bits_replay; // @[Frontend.scala 88:57]
+ wire fq_io_deq_ready; // @[Frontend.scala 88:57]
+ wire fq_io_deq_valid; // @[Frontend.scala 88:57]
+ wire [33:0] fq_io_deq_bits_pc; // @[Frontend.scala 88:57]
+ wire [31:0] fq_io_deq_bits_data; // @[Frontend.scala 88:57]
+ wire fq_io_deq_bits_xcpt_ae_inst; // @[Frontend.scala 88:57]
+ wire fq_io_deq_bits_replay; // @[Frontend.scala 88:57]
+ wire [4:0] fq_io_mask; // @[Frontend.scala 88:57]
+ wire [33:0] tlb_io_req_bits_vaddr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_resp_paddr; // @[Frontend.scala 102:19]
+ wire tlb_io_resp_ae_inst; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_status_debug; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_0_cfg_l; // @[Frontend.scala 102:19]
+ wire [1:0] tlb_io_ptw_pmp_0_cfg_a; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_0_cfg_x; // @[Frontend.scala 102:19]
+ wire [29:0] tlb_io_ptw_pmp_0_addr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_ptw_pmp_0_mask; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_1_cfg_l; // @[Frontend.scala 102:19]
+ wire [1:0] tlb_io_ptw_pmp_1_cfg_a; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_1_cfg_x; // @[Frontend.scala 102:19]
+ wire [29:0] tlb_io_ptw_pmp_1_addr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_ptw_pmp_1_mask; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_2_cfg_l; // @[Frontend.scala 102:19]
+ wire [1:0] tlb_io_ptw_pmp_2_cfg_a; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_2_cfg_x; // @[Frontend.scala 102:19]
+ wire [29:0] tlb_io_ptw_pmp_2_addr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_ptw_pmp_2_mask; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_3_cfg_l; // @[Frontend.scala 102:19]
+ wire [1:0] tlb_io_ptw_pmp_3_cfg_a; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_3_cfg_x; // @[Frontend.scala 102:19]
+ wire [29:0] tlb_io_ptw_pmp_3_addr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_ptw_pmp_3_mask; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_4_cfg_l; // @[Frontend.scala 102:19]
+ wire [1:0] tlb_io_ptw_pmp_4_cfg_a; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_4_cfg_x; // @[Frontend.scala 102:19]
+ wire [29:0] tlb_io_ptw_pmp_4_addr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_ptw_pmp_4_mask; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_5_cfg_l; // @[Frontend.scala 102:19]
+ wire [1:0] tlb_io_ptw_pmp_5_cfg_a; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_5_cfg_x; // @[Frontend.scala 102:19]
+ wire [29:0] tlb_io_ptw_pmp_5_addr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_ptw_pmp_5_mask; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_6_cfg_l; // @[Frontend.scala 102:19]
+ wire [1:0] tlb_io_ptw_pmp_6_cfg_a; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_6_cfg_x; // @[Frontend.scala 102:19]
+ wire [29:0] tlb_io_ptw_pmp_6_addr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_ptw_pmp_6_mask; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_7_cfg_l; // @[Frontend.scala 102:19]
+ wire [1:0] tlb_io_ptw_pmp_7_cfg_a; // @[Frontend.scala 102:19]
+ wire tlb_io_ptw_pmp_7_cfg_x; // @[Frontend.scala 102:19]
+ wire [29:0] tlb_io_ptw_pmp_7_addr; // @[Frontend.scala 102:19]
+ wire [31:0] tlb_io_ptw_pmp_7_mask; // @[Frontend.scala 102:19]
+ wire _T_9 = ~reset; // @[Frontend.scala 93:9]
+ reg s1_valid; // @[Frontend.scala 104:21]
+ reg s2_valid; // @[Frontend.scala 105:25]
+ wire _s0_fq_has_space_T_4 = ~s1_valid; // @[Frontend.scala 108:45]
+ wire _s0_fq_has_space_T_5 = ~s2_valid; // @[Frontend.scala 108:58]
+ wire _s0_fq_has_space_T_7 = ~fq_io_mask[3] & (~s1_valid | ~s2_valid); // @[Frontend.scala 108:41]
+ wire _s0_fq_has_space_T_8 = ~fq_io_mask[2] | _s0_fq_has_space_T_7; // @[Frontend.scala 107:40]
+ wire _s0_fq_has_space_T_14 = ~fq_io_mask[4] & (_s0_fq_has_space_T_4 & _s0_fq_has_space_T_5); // @[Frontend.scala 109:41]
+ wire s0_fq_has_space = _s0_fq_has_space_T_8 | _s0_fq_has_space_T_14; // @[Frontend.scala 108:70]
+ wire s0_valid = io_cpu_req_valid | s0_fq_has_space; // @[Frontend.scala 110:35]
+ reg [33:0] s1_pc; // @[Frontend.scala 112:18]
+ reg s1_speculative; // @[Frontend.scala 113:27]
+ reg [33:0] s2_pc; // @[Frontend.scala 114:22]
+ reg s2_tlb_resp_ae_inst; // @[Frontend.scala 118:24]
+ reg s2_speculative; // @[Frontend.scala 120:27]
+ wire [33:0] _s1_base_pc_T = ~s1_pc; // @[Frontend.scala 125:22]
+ wire [33:0] _s1_base_pc_T_1 = _s1_base_pc_T | 34'h3; // @[Frontend.scala 125:29]
+ wire [33:0] s1_base_pc = ~_s1_base_pc_T_1; // @[Frontend.scala 125:20]
+ wire [33:0] ntpc = s1_base_pc + 34'h4; // @[Frontend.scala 126:25]
+ wire _s2_replay_T = fq_io_enq_ready & fq_io_enq_valid; // @[Decoupled.scala 50:35]
+ reg s2_replay_REG; // @[Frontend.scala 131:58]
+ wire s2_replay = s2_valid & ~_s2_replay_T | s2_replay_REG; // @[Frontend.scala 131:48]
+ wire [33:0] npc = s2_replay ? s2_pc : ntpc; // @[Frontend.scala 132:16]
+ wire s0_speculative = s1_speculative | s2_valid & ~s2_speculative; // @[Frontend.scala 138:41]
+ wire _GEN_0 = ~s2_replay & ~io_cpu_req_valid; // @[Frontend.scala 143:12 144:21 145:14]
+ reg fq_io_enq_valid_REG; // @[Frontend.scala 171:29]
+ wire [33:0] _io_cpu_npc_T = io_cpu_req_valid ? io_cpu_req_bits_pc : npc; // @[Frontend.scala 173:28]
+ wire [33:0] _io_cpu_npc_T_1 = ~_io_cpu_npc_T; // @[Frontend.scala 362:29]
+ wire [33:0] _io_cpu_npc_T_2 = _io_cpu_npc_T_1 | 34'h1; // @[Frontend.scala 362:33]
+ ICache icache ( // @[Frontend.scala 66:26]
+ .clock(icache_clock),
+ .reset(icache_reset),
+ .auto_master_out_a_ready(icache_auto_master_out_a_ready),
+ .auto_master_out_a_valid(icache_auto_master_out_a_valid),
+ .auto_master_out_a_bits_address(icache_auto_master_out_a_bits_address),
+ .auto_master_out_d_valid(icache_auto_master_out_d_valid),
+ .auto_master_out_d_bits_opcode(icache_auto_master_out_d_bits_opcode),
+ .auto_master_out_d_bits_size(icache_auto_master_out_d_bits_size),
+ .auto_master_out_d_bits_data(icache_auto_master_out_d_bits_data),
+ .auto_master_out_d_bits_corrupt(icache_auto_master_out_d_bits_corrupt),
+ .io_req_ready(icache_io_req_ready),
+ .io_req_valid(icache_io_req_valid),
+ .io_req_bits_addr(icache_io_req_bits_addr),
+ .io_s1_paddr(icache_io_s1_paddr),
+ .io_s1_kill(icache_io_s1_kill),
+ .io_s2_kill(icache_io_s2_kill),
+ .io_resp_valid(icache_io_resp_valid),
+ .io_resp_bits_data(icache_io_resp_bits_data),
+ .io_resp_bits_ae(icache_io_resp_bits_ae),
+ .io_invalidate(icache_io_invalidate)
+ );
+ ShiftQueue fq ( // @[Frontend.scala 88:57]
+ .clock(fq_clock),
+ .reset(fq_reset),
+ .io_enq_ready(fq_io_enq_ready),
+ .io_enq_valid(fq_io_enq_valid),
+ .io_enq_bits_pc(fq_io_enq_bits_pc),
+ .io_enq_bits_data(fq_io_enq_bits_data),
+ .io_enq_bits_xcpt_ae_inst(fq_io_enq_bits_xcpt_ae_inst),
+ .io_enq_bits_replay(fq_io_enq_bits_replay),
+ .io_deq_ready(fq_io_deq_ready),
+ .io_deq_valid(fq_io_deq_valid),
+ .io_deq_bits_pc(fq_io_deq_bits_pc),
+ .io_deq_bits_data(fq_io_deq_bits_data),
+ .io_deq_bits_xcpt_ae_inst(fq_io_deq_bits_xcpt_ae_inst),
+ .io_deq_bits_replay(fq_io_deq_bits_replay),
+ .io_mask(fq_io_mask)
+ );
+ TLB_1 tlb ( // @[Frontend.scala 102:19]
+ .io_req_bits_vaddr(tlb_io_req_bits_vaddr),
+ .io_resp_paddr(tlb_io_resp_paddr),
+ .io_resp_ae_inst(tlb_io_resp_ae_inst),
+ .io_ptw_status_debug(tlb_io_ptw_status_debug),
+ .io_ptw_pmp_0_cfg_l(tlb_io_ptw_pmp_0_cfg_l),
+ .io_ptw_pmp_0_cfg_a(tlb_io_ptw_pmp_0_cfg_a),
+ .io_ptw_pmp_0_cfg_x(tlb_io_ptw_pmp_0_cfg_x),
+ .io_ptw_pmp_0_addr(tlb_io_ptw_pmp_0_addr),
+ .io_ptw_pmp_0_mask(tlb_io_ptw_pmp_0_mask),
+ .io_ptw_pmp_1_cfg_l(tlb_io_ptw_pmp_1_cfg_l),
+ .io_ptw_pmp_1_cfg_a(tlb_io_ptw_pmp_1_cfg_a),
+ .io_ptw_pmp_1_cfg_x(tlb_io_ptw_pmp_1_cfg_x),
+ .io_ptw_pmp_1_addr(tlb_io_ptw_pmp_1_addr),
+ .io_ptw_pmp_1_mask(tlb_io_ptw_pmp_1_mask),
+ .io_ptw_pmp_2_cfg_l(tlb_io_ptw_pmp_2_cfg_l),
+ .io_ptw_pmp_2_cfg_a(tlb_io_ptw_pmp_2_cfg_a),
+ .io_ptw_pmp_2_cfg_x(tlb_io_ptw_pmp_2_cfg_x),
+ .io_ptw_pmp_2_addr(tlb_io_ptw_pmp_2_addr),
+ .io_ptw_pmp_2_mask(tlb_io_ptw_pmp_2_mask),
+ .io_ptw_pmp_3_cfg_l(tlb_io_ptw_pmp_3_cfg_l),
+ .io_ptw_pmp_3_cfg_a(tlb_io_ptw_pmp_3_cfg_a),
+ .io_ptw_pmp_3_cfg_x(tlb_io_ptw_pmp_3_cfg_x),
+ .io_ptw_pmp_3_addr(tlb_io_ptw_pmp_3_addr),
+ .io_ptw_pmp_3_mask(tlb_io_ptw_pmp_3_mask),
+ .io_ptw_pmp_4_cfg_l(tlb_io_ptw_pmp_4_cfg_l),
+ .io_ptw_pmp_4_cfg_a(tlb_io_ptw_pmp_4_cfg_a),
+ .io_ptw_pmp_4_cfg_x(tlb_io_ptw_pmp_4_cfg_x),
+ .io_ptw_pmp_4_addr(tlb_io_ptw_pmp_4_addr),
+ .io_ptw_pmp_4_mask(tlb_io_ptw_pmp_4_mask),
+ .io_ptw_pmp_5_cfg_l(tlb_io_ptw_pmp_5_cfg_l),
+ .io_ptw_pmp_5_cfg_a(tlb_io_ptw_pmp_5_cfg_a),
+ .io_ptw_pmp_5_cfg_x(tlb_io_ptw_pmp_5_cfg_x),
+ .io_ptw_pmp_5_addr(tlb_io_ptw_pmp_5_addr),
+ .io_ptw_pmp_5_mask(tlb_io_ptw_pmp_5_mask),
+ .io_ptw_pmp_6_cfg_l(tlb_io_ptw_pmp_6_cfg_l),
+ .io_ptw_pmp_6_cfg_a(tlb_io_ptw_pmp_6_cfg_a),
+ .io_ptw_pmp_6_cfg_x(tlb_io_ptw_pmp_6_cfg_x),
+ .io_ptw_pmp_6_addr(tlb_io_ptw_pmp_6_addr),
+ .io_ptw_pmp_6_mask(tlb_io_ptw_pmp_6_mask),
+ .io_ptw_pmp_7_cfg_l(tlb_io_ptw_pmp_7_cfg_l),
+ .io_ptw_pmp_7_cfg_a(tlb_io_ptw_pmp_7_cfg_a),
+ .io_ptw_pmp_7_cfg_x(tlb_io_ptw_pmp_7_cfg_x),
+ .io_ptw_pmp_7_addr(tlb_io_ptw_pmp_7_addr),
+ .io_ptw_pmp_7_mask(tlb_io_ptw_pmp_7_mask)
+ );
+ assign auto_icache_master_out_a_valid = icache_auto_master_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_icache_master_out_a_bits_address = icache_auto_master_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign io_cpu_resp_valid = fq_io_deq_valid; // @[Frontend.scala 331:15]
+ assign io_cpu_resp_bits_pc = fq_io_deq_bits_pc; // @[Frontend.scala 331:15]
+ assign io_cpu_resp_bits_data = fq_io_deq_bits_data; // @[Frontend.scala 331:15]
+ assign io_cpu_resp_bits_xcpt_ae_inst = fq_io_deq_bits_xcpt_ae_inst; // @[Frontend.scala 331:15]
+ assign io_cpu_resp_bits_replay = fq_io_deq_bits_replay; // @[Frontend.scala 331:15]
+ assign io_cpu_npc = ~_io_cpu_npc_T_2; // @[Frontend.scala 362:27]
+ assign icache_clock = clock; // @[Frontend.scala 98:16]
+ assign icache_reset = reset;
+ assign icache_auto_master_out_a_ready = auto_icache_master_out_a_ready; // @[LazyModule.scala 311:12]
+ assign icache_auto_master_out_d_valid = auto_icache_master_out_d_valid; // @[LazyModule.scala 311:12]
+ assign icache_auto_master_out_d_bits_opcode = auto_icache_master_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign icache_auto_master_out_d_bits_size = auto_icache_master_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign icache_auto_master_out_d_bits_data = auto_icache_master_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign icache_auto_master_out_d_bits_corrupt = auto_icache_master_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign icache_io_req_valid = io_cpu_req_valid | s0_fq_has_space; // @[Frontend.scala 110:35]
+ assign icache_io_req_bits_addr = io_cpu_npc[32:0]; // @[Frontend.scala 162:27]
+ assign icache_io_s1_paddr = tlb_io_resp_paddr; // @[Frontend.scala 164:22]
+ assign icache_io_s1_kill = io_cpu_req_valid | s2_replay; // @[Frontend.scala 166:56]
+ assign icache_io_s2_kill = s2_speculative | s2_tlb_resp_ae_inst; // @[Frontend.scala 168:71]
+ assign icache_io_invalidate = io_cpu_flush_icache; // @[Frontend.scala 163:24]
+ assign fq_clock = clock;
+ assign fq_reset = reset | io_cpu_req_valid; // @[Frontend.scala 88:28]
+ assign fq_io_enq_valid = fq_io_enq_valid_REG & s2_valid & (icache_io_resp_valid | icache_io_s2_kill); // @[Frontend.scala 171:52]
+ assign fq_io_enq_bits_pc = s2_pc; // @[Frontend.scala 172:21]
+ assign fq_io_enq_bits_data = icache_io_resp_bits_data; // @[Frontend.scala 175:23]
+ assign fq_io_enq_bits_xcpt_ae_inst = icache_io_resp_valid & icache_io_resp_bits_ae | s2_tlb_resp_ae_inst; // @[Frontend.scala 180:23 182:{57,87}]
+ assign fq_io_enq_bits_replay = icache_io_s2_kill & ~icache_io_resp_valid & ~s2_tlb_resp_ae_inst; // @[Frontend.scala 177:101]
+ assign fq_io_deq_ready = io_cpu_resp_ready; // @[Frontend.scala 331:15]
+ assign tlb_io_req_bits_vaddr = s1_pc; // @[Frontend.scala 153:25]
+ assign tlb_io_ptw_status_debug = io_ptw_status_debug; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_0_addr = io_ptw_pmp_0_addr; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_0_mask = io_ptw_pmp_0_mask; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_1_addr = io_ptw_pmp_1_addr; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_1_mask = io_ptw_pmp_1_mask; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_2_addr = io_ptw_pmp_2_addr; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_2_mask = io_ptw_pmp_2_mask; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_3_addr = io_ptw_pmp_3_addr; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_3_mask = io_ptw_pmp_3_mask; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_4_addr = io_ptw_pmp_4_addr; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_4_mask = io_ptw_pmp_4_mask; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_5_addr = io_ptw_pmp_5_addr; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_5_mask = io_ptw_pmp_5_mask; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_6_addr = io_ptw_pmp_6_addr; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_6_mask = io_ptw_pmp_6_mask; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_7_addr = io_ptw_pmp_7_addr; // @[Frontend.scala 151:10]
+ assign tlb_io_ptw_pmp_7_mask = io_ptw_pmp_7_mask; // @[Frontend.scala 151:10]
+ always @(posedge clock) begin
+ s1_valid <= io_cpu_req_valid | s0_fq_has_space; // @[Frontend.scala 110:35]
+ if (reset) begin // @[Frontend.scala 105:25]
+ s2_valid <= 1'h0; // @[Frontend.scala 105:25]
+ end else begin
+ s2_valid <= _GEN_0;
+ end
+ s1_pc <= io_cpu_npc; // @[Frontend.scala 134:9]
+ if (io_cpu_req_valid) begin // @[Frontend.scala 140:24]
+ s1_speculative <= io_cpu_req_bits_speculative;
+ end else if (s2_replay) begin // @[Frontend.scala 140:75]
+ s1_speculative <= s2_speculative;
+ end else begin
+ s1_speculative <= s0_speculative;
+ end
+ if (reset) begin // @[Frontend.scala 114:22]
+ s2_pc <= 34'h10040; // @[Frontend.scala 114:22]
+ end else if (~s2_replay) begin // @[Frontend.scala 144:21]
+ s2_pc <= s1_pc; // @[Frontend.scala 146:11]
+ end
+ if (~s2_replay) begin // @[Frontend.scala 144:21]
+ s2_tlb_resp_ae_inst <= tlb_io_resp_ae_inst; // @[Frontend.scala 148:17]
+ end
+ if (reset) begin // @[Frontend.scala 120:27]
+ s2_speculative <= 1'h0; // @[Frontend.scala 120:27]
+ end else if (~s2_replay) begin // @[Frontend.scala 144:21]
+ s2_speculative <= s1_speculative; // @[Frontend.scala 147:20]
+ end
+ s2_replay_REG <= reset | s2_replay & ~s0_valid; // @[Frontend.scala 131:{58,58,58}]
+ fq_io_enq_valid_REG <= s1_valid; // @[Frontend.scala 171:29]
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(io_cpu_req_valid | io_cpu_flush_icache | io_cpu_bht_update_valid | io_cpu_btb_update_valid) |
+ io_cpu_might_request) & ~reset) begin
+ $fatal; // @[Frontend.scala 93:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~(io_cpu_req_valid | io_cpu_flush_icache | io_cpu_bht_update_valid | io_cpu_btb_update_valid) |
+ io_cpu_might_request)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Frontend.scala:93 assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)\n"
+ ); // @[Frontend.scala 93:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(s2_speculative & io_ptw_customCSRs_csrs_0_value[3] & ~icache_io_s2_kill)) & _T_9) begin
+ $fatal; // @[Frontend.scala 181:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_9 & ~(~(s2_speculative & io_ptw_customCSRs_csrs_0_value[3] & ~icache_io_s2_kill))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Frontend.scala:181 assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill))\n"
+ ); // @[Frontend.scala 181:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ s1_valid = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ s2_valid = _RAND_1[0:0];
+ _RAND_2 = {2{`RANDOM}};
+ s1_pc = _RAND_2[33:0];
+ _RAND_3 = {1{`RANDOM}};
+ s1_speculative = _RAND_3[0:0];
+ _RAND_4 = {2{`RANDOM}};
+ s2_pc = _RAND_4[33:0];
+ _RAND_5 = {1{`RANDOM}};
+ s2_tlb_resp_ae_inst = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ s2_speculative = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ s2_replay_REG = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ fq_io_enq_valid_REG = _RAND_8[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ScratchpadSlavePort(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [1:0] auto_in_a_bits_size,
+ input [7:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_size,
+ output [7:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input io_dmem_req_ready,
+ output io_dmem_req_valid,
+ output [33:0] io_dmem_req_bits_addr,
+ output [4:0] io_dmem_req_bits_cmd,
+ output [1:0] io_dmem_req_bits_size,
+ output io_dmem_s1_kill,
+ output [63:0] io_dmem_s1_data_data,
+ output [7:0] io_dmem_s1_data_mask,
+ input io_dmem_s2_nack,
+ input io_dmem_resp_valid,
+ input [63:0] io_dmem_resp_bits_data_raw
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [63:0] _RAND_7;
+ reg [63:0] _RAND_8;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] state; // @[ScratchpadSlavePort.scala 45:20]
+ wire [2:0] _GEN_0 = state == 3'h1 ? 3'h2 : state; // @[ScratchpadSlavePort.scala 45:20 47:{30,38}]
+ wire _T_1 = state == 3'h4; // @[ScratchpadSlavePort.scala 48:17]
+ wire [2:0] _GEN_1 = state == 3'h4 & auto_in_a_valid ? 3'h0 : _GEN_0; // @[ScratchpadSlavePort.scala 48:{46,54}]
+ wire [2:0] _GEN_2 = io_dmem_resp_valid ? 3'h5 : _GEN_1; // @[ScratchpadSlavePort.scala 49:{31,39}]
+ wire tl_in_d_valid = io_dmem_resp_valid | state == 3'h5; // @[ScratchpadSlavePort.scala 110:41]
+ wire _T_3 = auto_in_d_ready & tl_in_d_valid; // @[Decoupled.scala 50:35]
+ wire _ready_T = state == 3'h0; // @[ScratchpadSlavePort.scala 98:23]
+ wire _ready_T_1 = state == 3'h2; // @[ScratchpadSlavePort.scala 98:44]
+ wire ready = state == 3'h0 | state == 3'h2 & io_dmem_resp_valid & auto_in_d_ready; // @[ScratchpadSlavePort.scala 98:35]
+ wire _dmem_req_valid_T_1 = state == 3'h3; // @[ScratchpadSlavePort.scala 99:57]
+ wire dmem_req_valid = auto_in_a_valid & ready | state == 3'h3; // @[ScratchpadSlavePort.scala 99:48]
+ reg [2:0] acq_opcode; // @[ScratchpadSlavePort.scala 54:18]
+ reg [2:0] acq_param; // @[ScratchpadSlavePort.scala 54:18]
+ reg [1:0] acq_size; // @[ScratchpadSlavePort.scala 54:18]
+ reg [7:0] acq_source; // @[ScratchpadSlavePort.scala 54:18]
+ reg [31:0] acq_address; // @[ScratchpadSlavePort.scala 54:18]
+ reg [7:0] acq_mask; // @[ScratchpadSlavePort.scala 54:18]
+ reg [63:0] acq_data; // @[ScratchpadSlavePort.scala 54:18]
+ wire tl_in_a_ready = io_dmem_req_ready & ready; // @[ScratchpadSlavePort.scala 103:40]
+ wire _T_5 = tl_in_a_ready & auto_in_a_valid; // @[Decoupled.scala 50:35]
+ wire ready_likely = _ready_T | _ready_T_1; // @[package.scala 72:59]
+ wire [2:0] _io_dmem_req_bits_T_1_opcode = _dmem_req_valid_T_1 ? acq_opcode : auto_in_a_bits_opcode; // @[ScratchpadSlavePort.scala 104:41]
+ wire [2:0] _io_dmem_req_bits_T_1_param = _dmem_req_valid_T_1 ? acq_param : auto_in_a_bits_param; // @[ScratchpadSlavePort.scala 104:41]
+ wire [1:0] io_dmem_req_bits_mask_full_desired_mask_size = _dmem_req_valid_T_1 ? acq_size : auto_in_a_bits_size; // @[ScratchpadSlavePort.scala 104:41]
+ wire [31:0] _io_dmem_req_bits_T_1_address = _dmem_req_valid_T_1 ? acq_address : auto_in_a_bits_address; // @[ScratchpadSlavePort.scala 104:41]
+ wire [7:0] _io_dmem_req_bits_T_1_mask = _dmem_req_valid_T_1 ? acq_mask : auto_in_a_bits_mask; // @[ScratchpadSlavePort.scala 104:41]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_1 = 3'h0 == _io_dmem_req_bits_T_1_param ? 4'hc : 4'h0; // @[Mux.scala 81:58]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_3 = 3'h1 == _io_dmem_req_bits_T_1_param ? 4'hd : _io_dmem_req_bits_req_cmd_T_1; // @[Mux.scala 81:58]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_5 = 3'h2 == _io_dmem_req_bits_T_1_param ? 4'he : _io_dmem_req_bits_req_cmd_T_3; // @[Mux.scala 81:58]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_7 = 3'h3 == _io_dmem_req_bits_T_1_param ? 4'hf : _io_dmem_req_bits_req_cmd_T_5; // @[Mux.scala 81:58]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_9 = 3'h4 == _io_dmem_req_bits_T_1_param ? 4'h8 : _io_dmem_req_bits_req_cmd_T_7; // @[Mux.scala 81:58]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_11 = 3'h0 == _io_dmem_req_bits_T_1_param ? 4'h9 : 4'h0; // @[Mux.scala 81:58]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_13 = 3'h1 == _io_dmem_req_bits_T_1_param ? 4'ha :
+ _io_dmem_req_bits_req_cmd_T_11; // @[Mux.scala 81:58]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_15 = 3'h2 == _io_dmem_req_bits_T_1_param ? 4'hb :
+ _io_dmem_req_bits_req_cmd_T_13; // @[Mux.scala 81:58]
+ wire [3:0] _io_dmem_req_bits_req_cmd_T_17 = 3'h3 == _io_dmem_req_bits_T_1_param ? 4'h4 :
+ _io_dmem_req_bits_req_cmd_T_15; // @[Mux.scala 81:58]
+ wire [4:0] _io_dmem_req_bits_req_cmd_T_21 = 3'h1 == _io_dmem_req_bits_T_1_opcode ? 5'h11 : {{4'd0}, 3'h0 ==
+ _io_dmem_req_bits_T_1_opcode}; // @[Mux.scala 81:58]
+ wire [4:0] _io_dmem_req_bits_req_cmd_T_23 = 3'h2 == _io_dmem_req_bits_T_1_opcode ? {{1'd0},
+ _io_dmem_req_bits_req_cmd_T_9} : _io_dmem_req_bits_req_cmd_T_21; // @[Mux.scala 81:58]
+ wire [4:0] _io_dmem_req_bits_req_cmd_T_25 = 3'h3 == _io_dmem_req_bits_T_1_opcode ? {{1'd0},
+ _io_dmem_req_bits_req_cmd_T_17} : _io_dmem_req_bits_req_cmd_T_23; // @[Mux.scala 81:58]
+ wire [4:0] _io_dmem_req_bits_req_cmd_T_27 = 3'h4 == _io_dmem_req_bits_T_1_opcode ? 5'h0 :
+ _io_dmem_req_bits_req_cmd_T_25; // @[Mux.scala 81:58]
+ wire io_dmem_req_bits_mask_full_desired_mask_upper = _io_dmem_req_bits_T_1_address[0] |
+ io_dmem_req_bits_mask_full_desired_mask_size >= 2'h1; // @[AMOALU.scala 17:46]
+ wire io_dmem_req_bits_mask_full_desired_mask_lower = _io_dmem_req_bits_T_1_address[0] ? 1'h0 : 1'h1; // @[AMOALU.scala 18:22]
+ wire [1:0] _io_dmem_req_bits_mask_full_desired_mask_T = {io_dmem_req_bits_mask_full_desired_mask_upper,
+ io_dmem_req_bits_mask_full_desired_mask_lower}; // @[Cat.scala 31:58]
+ wire [1:0] _io_dmem_req_bits_mask_full_desired_mask_upper_T_5 = _io_dmem_req_bits_T_1_address[1] ?
+ _io_dmem_req_bits_mask_full_desired_mask_T : 2'h0; // @[AMOALU.scala 17:22]
+ wire [1:0] _io_dmem_req_bits_mask_full_desired_mask_upper_T_7 = io_dmem_req_bits_mask_full_desired_mask_size >= 2'h2
+ ? 2'h3 : 2'h0; // @[AMOALU.scala 17:51]
+ wire [1:0] io_dmem_req_bits_mask_full_desired_mask_upper_1 = _io_dmem_req_bits_mask_full_desired_mask_upper_T_5 |
+ _io_dmem_req_bits_mask_full_desired_mask_upper_T_7; // @[AMOALU.scala 17:46]
+ wire [1:0] io_dmem_req_bits_mask_full_desired_mask_lower_1 = _io_dmem_req_bits_T_1_address[1] ? 2'h0 :
+ _io_dmem_req_bits_mask_full_desired_mask_T; // @[AMOALU.scala 18:22]
+ wire [3:0] _io_dmem_req_bits_mask_full_desired_mask_T_1 = {io_dmem_req_bits_mask_full_desired_mask_upper_1,
+ io_dmem_req_bits_mask_full_desired_mask_lower_1}; // @[Cat.scala 31:58]
+ wire [3:0] _io_dmem_req_bits_mask_full_desired_mask_upper_T_9 = _io_dmem_req_bits_T_1_address[2] ?
+ _io_dmem_req_bits_mask_full_desired_mask_T_1 : 4'h0; // @[AMOALU.scala 17:22]
+ wire [3:0] _io_dmem_req_bits_mask_full_desired_mask_upper_T_11 = io_dmem_req_bits_mask_full_desired_mask_size >= 2'h3
+ ? 4'hf : 4'h0; // @[AMOALU.scala 17:51]
+ wire [3:0] io_dmem_req_bits_mask_full_desired_mask_upper_2 = _io_dmem_req_bits_mask_full_desired_mask_upper_T_9 |
+ _io_dmem_req_bits_mask_full_desired_mask_upper_T_11; // @[AMOALU.scala 17:46]
+ wire [3:0] io_dmem_req_bits_mask_full_desired_mask_lower_2 = _io_dmem_req_bits_T_1_address[2] ? 4'h0 :
+ _io_dmem_req_bits_mask_full_desired_mask_T_1; // @[AMOALU.scala 18:22]
+ wire [7:0] io_dmem_req_bits_mask_full_desired_mask = {io_dmem_req_bits_mask_full_desired_mask_upper_2,
+ io_dmem_req_bits_mask_full_desired_mask_lower_2}; // @[Cat.scala 31:58]
+ wire [7:0] _io_dmem_req_bits_mask_full_T = ~io_dmem_req_bits_mask_full_desired_mask; // @[ScratchpadSlavePort.scala 79:19]
+ wire [7:0] _io_dmem_req_bits_mask_full_T_1 = _io_dmem_req_bits_T_1_mask | _io_dmem_req_bits_mask_full_T; // @[ScratchpadSlavePort.scala 79:17]
+ wire io_dmem_req_bits_mask_full = &_io_dmem_req_bits_mask_full_T_1; // @[ScratchpadSlavePort.scala 79:34]
+ wire _bundleIn_0_d_bits_T = acq_opcode == 3'h0; // @[package.scala 15:47]
+ wire _bundleIn_0_d_bits_T_1 = acq_opcode == 3'h1; // @[package.scala 15:47]
+ wire _bundleIn_0_d_bits_T_2 = _bundleIn_0_d_bits_T | _bundleIn_0_d_bits_T_1; // @[package.scala 72:59]
+ reg [63:0] bundleIn_0_d_bits_data_r; // @[Reg.scala 16:16]
+ assign auto_in_a_ready = io_dmem_req_ready & ready; // @[ScratchpadSlavePort.scala 103:40]
+ assign auto_in_d_valid = io_dmem_resp_valid | state == 3'h5; // @[ScratchpadSlavePort.scala 110:41]
+ assign auto_in_d_bits_opcode = _bundleIn_0_d_bits_T_2 ? 3'h0 : 3'h1; // @[ScratchpadSlavePort.scala 111:24]
+ assign auto_in_d_bits_size = acq_size; // @[ScratchpadSlavePort.scala 111:24]
+ assign auto_in_d_bits_source = acq_source; // @[ScratchpadSlavePort.scala 111:24]
+ assign auto_in_d_bits_data = _ready_T_1 ? io_dmem_resp_bits_data_raw : bundleIn_0_d_bits_data_r; // @[package.scala 79:42]
+ assign io_dmem_req_valid = auto_in_a_valid & ready_likely | _dmem_req_valid_T_1; // @[ScratchpadSlavePort.scala 100:65]
+ assign io_dmem_req_bits_addr = {{2'd0}, _io_dmem_req_bits_T_1_address}; // @[ScratchpadSlavePort.scala 58:21 87:16]
+ assign io_dmem_req_bits_cmd = _T_1 | _io_dmem_req_bits_T_1_opcode == 3'h1 & io_dmem_req_bits_mask_full ? 5'h1 :
+ _io_dmem_req_bits_req_cmd_T_27; // @[ScratchpadSlavePort.scala 59:15 81:88 82:17]
+ assign io_dmem_req_bits_size = _dmem_req_valid_T_1 ? acq_size : auto_in_a_bits_size; // @[ScratchpadSlavePort.scala 104:41]
+ assign io_dmem_s1_kill = state != 3'h1; // @[ScratchpadSlavePort.scala 107:30]
+ assign io_dmem_s1_data_data = acq_data; // @[ScratchpadSlavePort.scala 105:26]
+ assign io_dmem_s1_data_mask = acq_mask; // @[ScratchpadSlavePort.scala 106:26]
+ always @(posedge clock) begin
+ if (reset) begin // @[ScratchpadSlavePort.scala 45:20]
+ state <= 3'h4; // @[ScratchpadSlavePort.scala 45:20]
+ end else if (dmem_req_valid & io_dmem_req_ready) begin // @[ScratchpadSlavePort.scala 52:48]
+ state <= 3'h1; // @[ScratchpadSlavePort.scala 52:56]
+ end else if (io_dmem_s2_nack) begin // @[ScratchpadSlavePort.scala 51:28]
+ state <= 3'h3; // @[ScratchpadSlavePort.scala 51:36]
+ end else if (_T_3) begin // @[ScratchpadSlavePort.scala 50:27]
+ state <= 3'h0; // @[ScratchpadSlavePort.scala 50:35]
+ end else begin
+ state <= _GEN_2;
+ end
+ if (_T_5) begin // @[ScratchpadSlavePort.scala 55:27]
+ acq_opcode <= auto_in_a_bits_opcode; // @[ScratchpadSlavePort.scala 55:33]
+ end
+ if (_T_5) begin // @[ScratchpadSlavePort.scala 55:27]
+ acq_param <= auto_in_a_bits_param; // @[ScratchpadSlavePort.scala 55:33]
+ end
+ if (_T_5) begin // @[ScratchpadSlavePort.scala 55:27]
+ acq_size <= auto_in_a_bits_size; // @[ScratchpadSlavePort.scala 55:33]
+ end
+ if (_T_5) begin // @[ScratchpadSlavePort.scala 55:27]
+ acq_source <= auto_in_a_bits_source; // @[ScratchpadSlavePort.scala 55:33]
+ end
+ if (_T_5) begin // @[ScratchpadSlavePort.scala 55:27]
+ acq_address <= auto_in_a_bits_address; // @[ScratchpadSlavePort.scala 55:33]
+ end
+ if (_T_5) begin // @[ScratchpadSlavePort.scala 55:27]
+ acq_mask <= auto_in_a_bits_mask; // @[ScratchpadSlavePort.scala 55:33]
+ end
+ if (_T_5) begin // @[ScratchpadSlavePort.scala 55:27]
+ acq_data <= auto_in_a_bits_data; // @[ScratchpadSlavePort.scala 55:33]
+ end
+ if (_ready_T_1) begin // @[Reg.scala 17:18]
+ bundleIn_0_d_bits_data_r <= io_dmem_resp_bits_data_raw; // @[Reg.scala 17:22]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ state = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ acq_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ acq_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ acq_size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ acq_source = _RAND_4[7:0];
+ _RAND_5 = {1{`RANDOM}};
+ acq_address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ acq_mask = _RAND_6[7:0];
+ _RAND_7 = {2{`RANDOM}};
+ acq_data = _RAND_7[63:0];
+ _RAND_8 = {2{`RANDOM}};
+ bundleIn_0_d_bits_data_r = _RAND_8[63:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Repeater_16(
+ input clock,
+ input reset,
+ input io_repeat,
+ output io_full,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [31:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [31:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+`endif // RANDOMIZE_REG_INIT
+ reg full; // @[Repeater.scala 19:21]
+ reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
+ reg [2:0] saved_param; // @[Repeater.scala 20:18]
+ reg [2:0] saved_size; // @[Repeater.scala 20:18]
+ reg [2:0] saved_source; // @[Repeater.scala 20:18]
+ reg [31:0] saved_address; // @[Repeater.scala 20:18]
+ reg [7:0] saved_mask; // @[Repeater.scala 20:18]
+ wire _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
+ wire _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign io_full = full; // @[Repeater.scala 26:11]
+ assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
+ assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
+ assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
+ assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
+ assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
+ assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
+ assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
+ assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
+ always @(posedge clock) begin
+ if (reset) begin // @[Repeater.scala 19:21]
+ full <= 1'h0; // @[Repeater.scala 19:21]
+ end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
+ full <= 1'h0; // @[Repeater.scala 29:45]
+ end else begin
+ full <= _GEN_0;
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
+ end
+ if (_T & io_repeat) begin // @[Repeater.scala 28:38]
+ saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ full = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ saved_opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ saved_param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ saved_size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ saved_source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ saved_address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ saved_mask = _RAND_6[7:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLFragmenter_15(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [7:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [7:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire repeater_clock; // @[Fragmenter.scala 262:30]
+ wire repeater_reset; // @[Fragmenter.scala 262:30]
+ wire repeater_io_repeat; // @[Fragmenter.scala 262:30]
+ wire repeater_io_full; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [31:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
+ wire repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
+ wire [2:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
+ wire [31:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
+ wire [7:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
+ reg [2:0] acknum; // @[Fragmenter.scala 189:29]
+ reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
+ reg dToggle; // @[Fragmenter.scala 191:30]
+ wire [2:0] dFragnum = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 192:41]
+ wire dFirst = acknum == 3'h0; // @[Fragmenter.scala 193:29]
+ wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala 194:30]
+ wire [3:0] dsizeOH = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
+ wire [5:0] _dsizeOH1_T_1 = 6'h7 << auto_out_d_bits_size; // @[package.scala 234:77]
+ wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire _T_5 = ~reset; // @[Fragmenter.scala 202:16]
+ wire ack_decrement = dHasData | dsizeOH[3]; // @[Fragmenter.scala 204:32]
+ wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala 206:47]
+ wire [5:0] _GEN_7 = {{3'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
+ wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
+ wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
+ wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
+ wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
+ wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
+ wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
+ wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
+ wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
+ wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
+ wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
+ wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
+ wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
+ wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
+ wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
+ wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
+ wire doEarlyAck = auto_out_d_bits_source[4]; // @[Fragmenter.scala 219:54]
+ wire _drop_T_1 = doEarlyAck ? dFirst : dLast; // @[Fragmenter.scala 222:37]
+ wire drop = ~dHasData & ~_drop_T_1; // @[Fragmenter.scala 222:30]
+ wire bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ wire _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_9 = {{2'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
+ wire [2:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
+ wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h3 ? 3'h3 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
+ wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
+ wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
+ wire [9:0] _aFragOH1_T_1 = 10'h7 << aFrag; // @[package.scala 234:77]
+ wire [2:0] aFragOH1 = ~_aFragOH1_T_1[2:0]; // @[package.scala 234:46]
+ wire aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] gennum; // @[Fragmenter.scala 291:29]
+ wire aFirst = gennum == 3'h0; // @[Fragmenter.scala 292:29]
+ wire [2:0] _old_gennum1_T_2 = gennum - 3'h1; // @[Fragmenter.scala 293:79]
+ wire [2:0] old_gennum1 = aFirst ? aOrigOH1[5:3] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
+ wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
+ wire [2:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
+ reg aToggle_r; // @[Reg.scala 16:16]
+ wire _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
+ wire aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
+ wire aFull = repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala 298:78]
+ wire bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ wire _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
+ wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
+ wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala 304:65]
+ wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
+ wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
+ wire [5:0] _GEN_10 = {{3'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
+ wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h7; // @[Fragmenter.scala 304:111]
+ wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
+ wire [31:0] _GEN_11 = {{26'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
+ wire [3:0] bundleOut_0_a_bits_source_lo = {aToggle,new_gennum}; // @[Cat.scala 31:58]
+ wire [3:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aFull}; // @[Cat.scala 31:58]
+ wire _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
+ Repeater_16 repeater ( // @[Fragmenter.scala 262:30]
+ .clock(repeater_clock),
+ .reset(repeater_reset),
+ .io_repeat(repeater_io_repeat),
+ .io_full(repeater_io_full),
+ .io_enq_ready(repeater_io_enq_ready),
+ .io_enq_valid(repeater_io_enq_valid),
+ .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
+ .io_enq_bits_param(repeater_io_enq_bits_param),
+ .io_enq_bits_size(repeater_io_enq_bits_size),
+ .io_enq_bits_source(repeater_io_enq_bits_source),
+ .io_enq_bits_address(repeater_io_enq_bits_address),
+ .io_enq_bits_mask(repeater_io_enq_bits_mask),
+ .io_deq_ready(repeater_io_deq_ready),
+ .io_deq_valid(repeater_io_deq_valid),
+ .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
+ .io_deq_bits_param(repeater_io_deq_bits_param),
+ .io_deq_bits_size(repeater_io_deq_bits_size),
+ .io_deq_bits_source(repeater_io_deq_bits_source),
+ .io_deq_bits_address(repeater_io_deq_bits_address),
+ .io_deq_bits_mask(repeater_io_deq_bits_mask)
+ );
+ assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
+ assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
+ assign auto_in_d_bits_source = auto_out_d_bits_source[7:5]; // @[Fragmenter.scala 226:47]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
+ assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
+ assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,bundleOut_0_a_bits_source_lo}; // @[Cat.scala 31:58]
+ assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
+ assign auto_out_a_bits_mask = repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
+ assign repeater_clock = clock;
+ assign repeater_reset = reset;
+ assign repeater_io_repeat = ~aHasData & new_gennum != 3'h0; // @[Fragmenter.scala 302:41]
+ assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ always @(posedge clock) begin
+ if (reset) begin // @[Fragmenter.scala 189:29]
+ acknum <= 3'h0; // @[Fragmenter.scala 189:29]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 209:24]
+ acknum <= dFragnum;
+ end else begin
+ acknum <= _acknum_T_1;
+ end
+ end
+ if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 191:30]
+ dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
+ end else if (_T_7) begin // @[Fragmenter.scala 208:29]
+ if (dFirst) begin // @[Fragmenter.scala 210:25]
+ dToggle <= auto_out_d_bits_source[3]; // @[Fragmenter.scala 212:21]
+ end
+ end
+ if (reset) begin // @[Fragmenter.scala 291:29]
+ gennum <= 3'h0; // @[Fragmenter.scala 291:29]
+ end else if (_T_8) begin // @[Fragmenter.scala 300:29]
+ gennum <= new_gennum; // @[Fragmenter.scala 300:38]
+ end
+ if (aFirst) begin // @[Reg.scala 17:18]
+ aToggle_r <= dToggle; // @[Reg.scala 17:22]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 309:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
+ $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
+ ); // @[Fragmenter.scala 309:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_9 | repeater_io_deq_bits_mask == 8'hff) & _T_5) begin
+ $fatal; // @[Fragmenter.scala 312:16]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 8'hff)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
+ ); // @[Fragmenter.scala 312:16]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ acknum = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ dOrig = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ dToggle = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ gennum = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ aToggle_r = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module HellaCacheArbiter(
+ input clock,
+ output io_requestor_0_req_ready,
+ input io_requestor_0_req_valid,
+ input [33:0] io_requestor_0_req_bits_addr,
+ input [6:0] io_requestor_0_req_bits_tag,
+ input [4:0] io_requestor_0_req_bits_cmd,
+ input [1:0] io_requestor_0_req_bits_size,
+ input io_requestor_0_req_bits_signed,
+ input io_requestor_0_s1_kill,
+ input [63:0] io_requestor_0_s1_data_data,
+ output io_requestor_0_s2_nack,
+ output io_requestor_0_resp_valid,
+ output [6:0] io_requestor_0_resp_bits_tag,
+ output [63:0] io_requestor_0_resp_bits_data,
+ output io_requestor_0_resp_bits_replay,
+ output io_requestor_0_resp_bits_has_data,
+ output [63:0] io_requestor_0_resp_bits_data_word_bypass,
+ output io_requestor_0_replay_next,
+ output io_requestor_0_s2_xcpt_ma_ld,
+ output io_requestor_0_s2_xcpt_ma_st,
+ output io_requestor_0_s2_xcpt_pf_ld,
+ output io_requestor_0_s2_xcpt_pf_st,
+ output io_requestor_0_s2_xcpt_ae_ld,
+ output io_requestor_0_s2_xcpt_ae_st,
+ output io_requestor_0_ordered,
+ output io_requestor_0_perf_grant,
+ output io_requestor_1_req_ready,
+ input io_requestor_1_req_valid,
+ input [33:0] io_requestor_1_req_bits_addr,
+ input [4:0] io_requestor_1_req_bits_cmd,
+ input [1:0] io_requestor_1_req_bits_size,
+ input io_requestor_1_s1_kill,
+ input [63:0] io_requestor_1_s1_data_data,
+ input [7:0] io_requestor_1_s1_data_mask,
+ output io_requestor_1_s2_nack,
+ output io_requestor_1_resp_valid,
+ output [63:0] io_requestor_1_resp_bits_data_raw,
+ input io_mem_req_ready,
+ output io_mem_req_valid,
+ output [33:0] io_mem_req_bits_addr,
+ output [6:0] io_mem_req_bits_tag,
+ output [4:0] io_mem_req_bits_cmd,
+ output [1:0] io_mem_req_bits_size,
+ output io_mem_req_bits_signed,
+ output [1:0] io_mem_req_bits_dprv,
+ output io_mem_req_bits_no_xcpt,
+ output io_mem_s1_kill,
+ output [63:0] io_mem_s1_data_data,
+ output [7:0] io_mem_s1_data_mask,
+ input io_mem_s2_nack,
+ input io_mem_resp_valid,
+ input [6:0] io_mem_resp_bits_tag,
+ input [63:0] io_mem_resp_bits_data,
+ input io_mem_resp_bits_replay,
+ input io_mem_resp_bits_has_data,
+ input [63:0] io_mem_resp_bits_data_word_bypass,
+ input [63:0] io_mem_resp_bits_data_raw,
+ input io_mem_replay_next,
+ input io_mem_s2_xcpt_ma_ld,
+ input io_mem_s2_xcpt_ma_st,
+ input io_mem_s2_xcpt_pf_ld,
+ input io_mem_s2_xcpt_pf_st,
+ input io_mem_s2_xcpt_ae_ld,
+ input io_mem_s2_xcpt_ae_st,
+ input io_mem_ordered,
+ input io_mem_perf_grant
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+ reg s1_id; // @[HellaCacheArbiter.scala 19:20]
+ reg s2_id; // @[HellaCacheArbiter.scala 20:20]
+ wire [7:0] _io_mem_req_bits_tag_T_1 = {io_requestor_0_req_bits_tag,1'h0}; // @[Cat.scala 31:58]
+ wire [7:0] _GEN_1 = io_requestor_0_req_valid ? _io_mem_req_bits_tag_T_1 : 8'h1; // @[HellaCacheArbiter.scala 49:26 33:{29,29}]
+ wire _T_1 = ~s2_id; // @[HellaCacheArbiter.scala 51:21]
+ wire tag_hit = ~io_mem_resp_bits_tag[0]; // @[HellaCacheArbiter.scala 59:57]
+ assign io_requestor_0_req_ready = io_mem_req_ready; // @[HellaCacheArbiter.scala 25:31]
+ assign io_requestor_0_s2_nack = io_mem_s2_nack & _T_1; // @[HellaCacheArbiter.scala 66:49]
+ assign io_requestor_0_resp_valid = io_mem_resp_valid & tag_hit; // @[HellaCacheArbiter.scala 60:39]
+ assign io_requestor_0_resp_bits_tag = {{1'd0}, io_mem_resp_bits_tag[6:1]}; // @[HellaCacheArbiter.scala 72:21]
+ assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala 71:17]
+ assign io_requestor_0_resp_bits_replay = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala 71:17]
+ assign io_requestor_0_resp_bits_has_data = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala 71:17]
+ assign io_requestor_0_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala 71:17]
+ assign io_requestor_0_replay_next = io_mem_replay_next; // @[HellaCacheArbiter.scala 74:35]
+ assign io_requestor_0_s2_xcpt_ma_ld = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala 61:31]
+ assign io_requestor_0_s2_xcpt_ma_st = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala 61:31]
+ assign io_requestor_0_s2_xcpt_pf_ld = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala 61:31]
+ assign io_requestor_0_s2_xcpt_pf_st = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala 61:31]
+ assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala 61:31]
+ assign io_requestor_0_s2_xcpt_ae_st = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala 61:31]
+ assign io_requestor_0_ordered = io_mem_ordered; // @[HellaCacheArbiter.scala 64:31]
+ assign io_requestor_0_perf_grant = io_mem_perf_grant; // @[HellaCacheArbiter.scala 65:28]
+ assign io_requestor_1_req_ready = io_requestor_0_req_ready & ~io_requestor_0_req_valid; // @[HellaCacheArbiter.scala 27:64]
+ assign io_requestor_1_s2_nack = io_mem_s2_nack & s2_id; // @[HellaCacheArbiter.scala 66:49]
+ assign io_requestor_1_resp_valid = io_mem_resp_valid & io_mem_resp_bits_tag[0]; // @[HellaCacheArbiter.scala 60:39]
+ assign io_requestor_1_resp_bits_data_raw = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala 71:17]
+ assign io_mem_req_valid = io_requestor_0_req_valid | io_requestor_1_req_valid; // @[HellaCacheArbiter.scala 24:63]
+ assign io_mem_req_bits_addr = io_requestor_0_req_valid ? io_requestor_0_req_bits_addr : io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala 32:{25,25} 49:26]
+ assign io_mem_req_bits_tag = _GEN_1[6:0];
+ assign io_mem_req_bits_cmd = io_requestor_0_req_valid ? io_requestor_0_req_bits_cmd : io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala 32:{25,25} 49:26]
+ assign io_mem_req_bits_size = io_requestor_0_req_valid ? io_requestor_0_req_bits_size : io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala 32:{25,25} 49:26]
+ assign io_mem_req_bits_signed = io_requestor_0_req_valid & io_requestor_0_req_bits_signed; // @[HellaCacheArbiter.scala 32:{25,25} 49:26]
+ assign io_mem_req_bits_dprv = io_requestor_0_req_valid ? 2'h3 : 2'h0; // @[HellaCacheArbiter.scala 32:{25,25} 49:26]
+ assign io_mem_req_bits_no_xcpt = io_requestor_0_req_valid ? 1'h0 : 1'h1; // @[HellaCacheArbiter.scala 32:{25,25} 49:26]
+ assign io_mem_s1_kill = ~s1_id ? io_requestor_0_s1_kill : io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala 37:{24,24} 50:34]
+ assign io_mem_s1_data_data = ~s1_id ? io_requestor_0_s1_data_data : io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala 38:{24,24} 50:34]
+ assign io_mem_s1_data_mask = ~s1_id ? 8'h0 : io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala 38:{24,24} 50:34]
+ always @(posedge clock) begin
+ if (io_requestor_0_req_valid) begin // @[HellaCacheArbiter.scala 49:26]
+ s1_id <= 1'h0; // @[HellaCacheArbiter.scala 34:15]
+ end else begin
+ s1_id <= 1'h1; // @[HellaCacheArbiter.scala 34:15]
+ end
+ s2_id <= s1_id; // @[HellaCacheArbiter.scala 20:20]
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ s1_id = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ s2_id = _RAND_1[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module PTW(
+ input clock,
+ input reset,
+ output io_requestor_0_status_debug,
+ output io_requestor_0_pmp_0_cfg_l,
+ output [1:0] io_requestor_0_pmp_0_cfg_a,
+ output io_requestor_0_pmp_0_cfg_w,
+ output io_requestor_0_pmp_0_cfg_r,
+ output [29:0] io_requestor_0_pmp_0_addr,
+ output [31:0] io_requestor_0_pmp_0_mask,
+ output io_requestor_0_pmp_1_cfg_l,
+ output [1:0] io_requestor_0_pmp_1_cfg_a,
+ output io_requestor_0_pmp_1_cfg_w,
+ output io_requestor_0_pmp_1_cfg_r,
+ output [29:0] io_requestor_0_pmp_1_addr,
+ output [31:0] io_requestor_0_pmp_1_mask,
+ output io_requestor_0_pmp_2_cfg_l,
+ output [1:0] io_requestor_0_pmp_2_cfg_a,
+ output io_requestor_0_pmp_2_cfg_w,
+ output io_requestor_0_pmp_2_cfg_r,
+ output [29:0] io_requestor_0_pmp_2_addr,
+ output [31:0] io_requestor_0_pmp_2_mask,
+ output io_requestor_0_pmp_3_cfg_l,
+ output [1:0] io_requestor_0_pmp_3_cfg_a,
+ output io_requestor_0_pmp_3_cfg_w,
+ output io_requestor_0_pmp_3_cfg_r,
+ output [29:0] io_requestor_0_pmp_3_addr,
+ output [31:0] io_requestor_0_pmp_3_mask,
+ output io_requestor_0_pmp_4_cfg_l,
+ output [1:0] io_requestor_0_pmp_4_cfg_a,
+ output io_requestor_0_pmp_4_cfg_w,
+ output io_requestor_0_pmp_4_cfg_r,
+ output [29:0] io_requestor_0_pmp_4_addr,
+ output [31:0] io_requestor_0_pmp_4_mask,
+ output io_requestor_0_pmp_5_cfg_l,
+ output [1:0] io_requestor_0_pmp_5_cfg_a,
+ output io_requestor_0_pmp_5_cfg_w,
+ output io_requestor_0_pmp_5_cfg_r,
+ output [29:0] io_requestor_0_pmp_5_addr,
+ output [31:0] io_requestor_0_pmp_5_mask,
+ output io_requestor_0_pmp_6_cfg_l,
+ output [1:0] io_requestor_0_pmp_6_cfg_a,
+ output io_requestor_0_pmp_6_cfg_w,
+ output io_requestor_0_pmp_6_cfg_r,
+ output [29:0] io_requestor_0_pmp_6_addr,
+ output [31:0] io_requestor_0_pmp_6_mask,
+ output io_requestor_0_pmp_7_cfg_l,
+ output [1:0] io_requestor_0_pmp_7_cfg_a,
+ output io_requestor_0_pmp_7_cfg_w,
+ output io_requestor_0_pmp_7_cfg_r,
+ output [29:0] io_requestor_0_pmp_7_addr,
+ output [31:0] io_requestor_0_pmp_7_mask,
+ output io_requestor_1_status_debug,
+ output io_requestor_1_pmp_0_cfg_l,
+ output [1:0] io_requestor_1_pmp_0_cfg_a,
+ output io_requestor_1_pmp_0_cfg_x,
+ output [29:0] io_requestor_1_pmp_0_addr,
+ output [31:0] io_requestor_1_pmp_0_mask,
+ output io_requestor_1_pmp_1_cfg_l,
+ output [1:0] io_requestor_1_pmp_1_cfg_a,
+ output io_requestor_1_pmp_1_cfg_x,
+ output [29:0] io_requestor_1_pmp_1_addr,
+ output [31:0] io_requestor_1_pmp_1_mask,
+ output io_requestor_1_pmp_2_cfg_l,
+ output [1:0] io_requestor_1_pmp_2_cfg_a,
+ output io_requestor_1_pmp_2_cfg_x,
+ output [29:0] io_requestor_1_pmp_2_addr,
+ output [31:0] io_requestor_1_pmp_2_mask,
+ output io_requestor_1_pmp_3_cfg_l,
+ output [1:0] io_requestor_1_pmp_3_cfg_a,
+ output io_requestor_1_pmp_3_cfg_x,
+ output [29:0] io_requestor_1_pmp_3_addr,
+ output [31:0] io_requestor_1_pmp_3_mask,
+ output io_requestor_1_pmp_4_cfg_l,
+ output [1:0] io_requestor_1_pmp_4_cfg_a,
+ output io_requestor_1_pmp_4_cfg_x,
+ output [29:0] io_requestor_1_pmp_4_addr,
+ output [31:0] io_requestor_1_pmp_4_mask,
+ output io_requestor_1_pmp_5_cfg_l,
+ output [1:0] io_requestor_1_pmp_5_cfg_a,
+ output io_requestor_1_pmp_5_cfg_x,
+ output [29:0] io_requestor_1_pmp_5_addr,
+ output [31:0] io_requestor_1_pmp_5_mask,
+ output io_requestor_1_pmp_6_cfg_l,
+ output [1:0] io_requestor_1_pmp_6_cfg_a,
+ output io_requestor_1_pmp_6_cfg_x,
+ output [29:0] io_requestor_1_pmp_6_addr,
+ output [31:0] io_requestor_1_pmp_6_mask,
+ output io_requestor_1_pmp_7_cfg_l,
+ output [1:0] io_requestor_1_pmp_7_cfg_a,
+ output io_requestor_1_pmp_7_cfg_x,
+ output [29:0] io_requestor_1_pmp_7_addr,
+ output [31:0] io_requestor_1_pmp_7_mask,
+ output [63:0] io_requestor_1_customCSRs_csrs_0_value,
+ input io_dpath_status_debug,
+ input io_dpath_pmp_0_cfg_l,
+ input [1:0] io_dpath_pmp_0_cfg_a,
+ input io_dpath_pmp_0_cfg_x,
+ input io_dpath_pmp_0_cfg_w,
+ input io_dpath_pmp_0_cfg_r,
+ input [29:0] io_dpath_pmp_0_addr,
+ input [31:0] io_dpath_pmp_0_mask,
+ input io_dpath_pmp_1_cfg_l,
+ input [1:0] io_dpath_pmp_1_cfg_a,
+ input io_dpath_pmp_1_cfg_x,
+ input io_dpath_pmp_1_cfg_w,
+ input io_dpath_pmp_1_cfg_r,
+ input [29:0] io_dpath_pmp_1_addr,
+ input [31:0] io_dpath_pmp_1_mask,
+ input io_dpath_pmp_2_cfg_l,
+ input [1:0] io_dpath_pmp_2_cfg_a,
+ input io_dpath_pmp_2_cfg_x,
+ input io_dpath_pmp_2_cfg_w,
+ input io_dpath_pmp_2_cfg_r,
+ input [29:0] io_dpath_pmp_2_addr,
+ input [31:0] io_dpath_pmp_2_mask,
+ input io_dpath_pmp_3_cfg_l,
+ input [1:0] io_dpath_pmp_3_cfg_a,
+ input io_dpath_pmp_3_cfg_x,
+ input io_dpath_pmp_3_cfg_w,
+ input io_dpath_pmp_3_cfg_r,
+ input [29:0] io_dpath_pmp_3_addr,
+ input [31:0] io_dpath_pmp_3_mask,
+ input io_dpath_pmp_4_cfg_l,
+ input [1:0] io_dpath_pmp_4_cfg_a,
+ input io_dpath_pmp_4_cfg_x,
+ input io_dpath_pmp_4_cfg_w,
+ input io_dpath_pmp_4_cfg_r,
+ input [29:0] io_dpath_pmp_4_addr,
+ input [31:0] io_dpath_pmp_4_mask,
+ input io_dpath_pmp_5_cfg_l,
+ input [1:0] io_dpath_pmp_5_cfg_a,
+ input io_dpath_pmp_5_cfg_x,
+ input io_dpath_pmp_5_cfg_w,
+ input io_dpath_pmp_5_cfg_r,
+ input [29:0] io_dpath_pmp_5_addr,
+ input [31:0] io_dpath_pmp_5_mask,
+ input io_dpath_pmp_6_cfg_l,
+ input [1:0] io_dpath_pmp_6_cfg_a,
+ input io_dpath_pmp_6_cfg_x,
+ input io_dpath_pmp_6_cfg_w,
+ input io_dpath_pmp_6_cfg_r,
+ input [29:0] io_dpath_pmp_6_addr,
+ input [31:0] io_dpath_pmp_6_mask,
+ input io_dpath_pmp_7_cfg_l,
+ input [1:0] io_dpath_pmp_7_cfg_a,
+ input io_dpath_pmp_7_cfg_x,
+ input io_dpath_pmp_7_cfg_w,
+ input io_dpath_pmp_7_cfg_r,
+ input [29:0] io_dpath_pmp_7_addr,
+ input [31:0] io_dpath_pmp_7_mask,
+ output io_dpath_perf_l2hit,
+ output io_dpath_perf_pte_miss,
+ output io_dpath_perf_pte_hit,
+ input [63:0] io_dpath_customCSRs_csrs_0_value
+);
+ assign io_requestor_0_status_debug = io_dpath_status_debug; // @[PTW.scala 402:28]
+ assign io_requestor_0_pmp_0_cfg_l = io_dpath_pmp_0_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_0_cfg_a = io_dpath_pmp_0_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_0_cfg_w = io_dpath_pmp_0_cfg_w; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_0_cfg_r = io_dpath_pmp_0_cfg_r; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_0_addr = io_dpath_pmp_0_addr; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_0_mask = io_dpath_pmp_0_mask; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_1_cfg_l = io_dpath_pmp_1_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_1_cfg_a = io_dpath_pmp_1_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_1_cfg_w = io_dpath_pmp_1_cfg_w; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_1_cfg_r = io_dpath_pmp_1_cfg_r; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_1_addr = io_dpath_pmp_1_addr; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_1_mask = io_dpath_pmp_1_mask; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_2_cfg_l = io_dpath_pmp_2_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_2_cfg_a = io_dpath_pmp_2_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_2_cfg_w = io_dpath_pmp_2_cfg_w; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_2_cfg_r = io_dpath_pmp_2_cfg_r; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_2_addr = io_dpath_pmp_2_addr; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_2_mask = io_dpath_pmp_2_mask; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_3_cfg_l = io_dpath_pmp_3_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_3_cfg_a = io_dpath_pmp_3_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_3_cfg_w = io_dpath_pmp_3_cfg_w; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_3_cfg_r = io_dpath_pmp_3_cfg_r; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_3_addr = io_dpath_pmp_3_addr; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_3_mask = io_dpath_pmp_3_mask; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_4_cfg_l = io_dpath_pmp_4_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_4_cfg_a = io_dpath_pmp_4_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_4_cfg_w = io_dpath_pmp_4_cfg_w; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_4_cfg_r = io_dpath_pmp_4_cfg_r; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_4_addr = io_dpath_pmp_4_addr; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_4_mask = io_dpath_pmp_4_mask; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_5_cfg_l = io_dpath_pmp_5_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_5_cfg_a = io_dpath_pmp_5_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_5_cfg_w = io_dpath_pmp_5_cfg_w; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_5_cfg_r = io_dpath_pmp_5_cfg_r; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_5_addr = io_dpath_pmp_5_addr; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_5_mask = io_dpath_pmp_5_mask; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_6_cfg_l = io_dpath_pmp_6_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_6_cfg_a = io_dpath_pmp_6_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_6_cfg_w = io_dpath_pmp_6_cfg_w; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_6_cfg_r = io_dpath_pmp_6_cfg_r; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_6_addr = io_dpath_pmp_6_addr; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_6_mask = io_dpath_pmp_6_mask; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_7_cfg_l = io_dpath_pmp_7_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_7_cfg_a = io_dpath_pmp_7_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_7_cfg_w = io_dpath_pmp_7_cfg_w; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_7_cfg_r = io_dpath_pmp_7_cfg_r; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_7_addr = io_dpath_pmp_7_addr; // @[PTW.scala 405:25]
+ assign io_requestor_0_pmp_7_mask = io_dpath_pmp_7_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_status_debug = io_dpath_status_debug; // @[PTW.scala 402:28]
+ assign io_requestor_1_pmp_0_cfg_l = io_dpath_pmp_0_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_0_cfg_a = io_dpath_pmp_0_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_0_cfg_x = io_dpath_pmp_0_cfg_x; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_0_addr = io_dpath_pmp_0_addr; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_0_mask = io_dpath_pmp_0_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_1_cfg_l = io_dpath_pmp_1_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_1_cfg_a = io_dpath_pmp_1_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_1_cfg_x = io_dpath_pmp_1_cfg_x; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_1_addr = io_dpath_pmp_1_addr; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_1_mask = io_dpath_pmp_1_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_2_cfg_l = io_dpath_pmp_2_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_2_cfg_a = io_dpath_pmp_2_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_2_cfg_x = io_dpath_pmp_2_cfg_x; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_2_addr = io_dpath_pmp_2_addr; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_2_mask = io_dpath_pmp_2_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_3_cfg_l = io_dpath_pmp_3_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_3_cfg_a = io_dpath_pmp_3_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_3_cfg_x = io_dpath_pmp_3_cfg_x; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_3_addr = io_dpath_pmp_3_addr; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_3_mask = io_dpath_pmp_3_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_4_cfg_l = io_dpath_pmp_4_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_4_cfg_a = io_dpath_pmp_4_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_4_cfg_x = io_dpath_pmp_4_cfg_x; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_4_addr = io_dpath_pmp_4_addr; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_4_mask = io_dpath_pmp_4_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_5_cfg_l = io_dpath_pmp_5_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_5_cfg_a = io_dpath_pmp_5_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_5_cfg_x = io_dpath_pmp_5_cfg_x; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_5_addr = io_dpath_pmp_5_addr; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_5_mask = io_dpath_pmp_5_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_6_cfg_l = io_dpath_pmp_6_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_6_cfg_a = io_dpath_pmp_6_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_6_cfg_x = io_dpath_pmp_6_cfg_x; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_6_addr = io_dpath_pmp_6_addr; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_6_mask = io_dpath_pmp_6_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_7_cfg_l = io_dpath_pmp_7_cfg_l; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_7_cfg_a = io_dpath_pmp_7_cfg_a; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_7_cfg_x = io_dpath_pmp_7_cfg_x; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_7_addr = io_dpath_pmp_7_addr; // @[PTW.scala 405:25]
+ assign io_requestor_1_pmp_7_mask = io_dpath_pmp_7_mask; // @[PTW.scala 405:25]
+ assign io_requestor_1_customCSRs_csrs_0_value = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala 401:32]
+ assign io_dpath_perf_l2hit = 1'h0; // @[PTW.scala 264:23]
+ assign io_dpath_perf_pte_miss = 1'h0; // @[PTW.scala 413:18 256:26]
+ assign io_dpath_perf_pte_hit = 1'h0; // @[PTW.scala 257:57]
+ always @(posedge clock) begin
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(io_dpath_perf_l2hit & (io_dpath_perf_pte_miss | io_dpath_perf_pte_hit))) & ~reset) begin
+ $fatal; // @[PTW.scala 258:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~(io_dpath_perf_l2hit & (io_dpath_perf_pte_miss | io_dpath_perf_pte_hit)))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:258 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n"
+ ); // @[PTW.scala 258:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+endmodule
+module RVCExpander(
+ input [31:0] io_in,
+ output [31:0] io_out_bits,
+ output [4:0] io_out_rd,
+ output [4:0] io_out_rs1,
+ output [4:0] io_out_rs2,
+ output io_rvc
+);
+ wire [6:0] io_out_s_opc = |io_in[12:5] ? 7'h13 : 7'h1f; // @[RVC.scala 53:20]
+ wire [4:0] _io_out_s_T_6 = {2'h1,io_in[4:2]}; // @[Cat.scala 31:58]
+ wire [29:0] _io_out_s_T_7 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],io_out_s_opc}; // @[Cat.scala 31:58]
+ wire [7:0] _io_out_s_T_15 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 31:58]
+ wire [4:0] _io_out_s_T_17 = {2'h1,io_in[9:7]}; // @[Cat.scala 31:58]
+ wire [27:0] _io_out_s_T_20 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 31:58]
+ wire [6:0] _io_out_s_T_31 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 31:58]
+ wire [26:0] _io_out_s_T_36 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 31:58]
+ wire [27:0] _io_out_s_T_51 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 31:58]
+ wire [26:0] _io_out_s_T_73 = {_io_out_s_T_31[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_io_out_s_T_31[4:0],7'h3f}; // @[Cat.scala 31:58]
+ wire [27:0] _io_out_s_T_93 = {_io_out_s_T_15[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_io_out_s_T_15[4:0],7'h27}; // @[Cat.scala 31:58]
+ wire [26:0] _io_out_s_T_115 = {_io_out_s_T_31[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_io_out_s_T_31[4:0],7'h23}; // @[Cat.scala 31:58]
+ wire [27:0] _io_out_s_T_135 = {_io_out_s_T_15[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_io_out_s_T_15[4:0],7'h23}; // @[Cat.scala 31:58]
+ wire [6:0] _io_out_s_T_145 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 74:12]
+ wire [11:0] _io_out_s_T_147 = {_io_out_s_T_145,io_in[6:2]}; // @[Cat.scala 31:58]
+ wire [31:0] io_out_s_8_bits = {_io_out_s_T_145,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 31:58]
+ wire _io_out_s_opc_T_3 = |io_in[11:7]; // @[RVC.scala 77:24]
+ wire [6:0] io_out_s_opc_1 = |io_in[11:7] ? 7'h1b : 7'h1f; // @[RVC.scala 77:20]
+ wire [31:0] io_out_s_9_bits = {_io_out_s_T_145,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],io_out_s_opc_1}; // @[Cat.scala 31:58]
+ wire [31:0] io_out_s_10_bits = {_io_out_s_T_145,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 31:58]
+ wire _io_out_s_opc_T_9 = |_io_out_s_T_147; // @[RVC.scala 90:29]
+ wire [6:0] io_out_s_opc_2 = |_io_out_s_T_147 ? 7'h37 : 7'h3f; // @[RVC.scala 90:20]
+ wire [14:0] _io_out_s_me_T_2 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 74:12]
+ wire [31:0] _io_out_s_me_T_4 = {_io_out_s_me_T_2,io_in[6:2],12'h0}; // @[Cat.scala 31:58]
+ wire [31:0] io_out_s_me_bits = {_io_out_s_me_T_4[31:12],io_in[11:7],io_out_s_opc_2}; // @[Cat.scala 31:58]
+ wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_9 ? 7'h13 : 7'h1f; // @[RVC.scala 86:20]
+ wire [2:0] _io_out_s_T_187 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 74:12]
+ wire [31:0] io_out_s_res_bits = {_io_out_s_T_187,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:
+ 7],io_out_s_opc_3}; // @[Cat.scala 31:58]
+ wire [31:0] io_out_s_11_bits = io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala 92:10]
+ wire [4:0] io_out_s_11_rd = io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 92:10]
+ wire [4:0] io_out_s_11_rs2 = io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? _io_out_s_T_6 : _io_out_s_T_6; // @[RVC.scala 92:10]
+ wire [25:0] _io_out_s_T_208 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 31:58]
+ wire [30:0] _GEN_0 = {{5'd0}, _io_out_s_T_208}; // @[RVC.scala 99:23]
+ wire [30:0] _io_out_s_T_217 = _GEN_0 | 31'h40000000; // @[RVC.scala 99:23]
+ wire [31:0] _io_out_s_T_227 = {_io_out_s_T_145,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 31:58]
+ wire [2:0] _io_out_s_funct_T_2 = {io_in[12],io_in[6:5]}; // @[Cat.scala 31:58]
+ wire [2:0] _io_out_s_funct_T_4 = _io_out_s_funct_T_2 == 3'h1 ? 3'h4 : 3'h0; // @[package.scala 32:76]
+ wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_2 == 3'h2 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala 32:76]
+ wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_2 == 3'h3 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala 32:76]
+ wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_2 == 3'h4 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala 32:76]
+ wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_2 == 3'h5 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala 32:76]
+ wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_2 == 3'h6 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala 32:76]
+ wire [2:0] io_out_s_funct = _io_out_s_funct_T_2 == 3'h7 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala 32:76]
+ wire [30:0] io_out_s_sub = io_in[6:5] == 2'h0 ? 31'h40000000 : 31'h0; // @[RVC.scala 103:22]
+ wire [6:0] io_out_s_opc_4 = io_in[12] ? 7'h3b : 7'h33; // @[RVC.scala 104:22]
+ wire [24:0] _io_out_s_T_234 = {2'h1,io_in[4:2],2'h1,io_in[9:7],io_out_s_funct,2'h1,io_in[9:7],io_out_s_opc_4}; // @[Cat.scala 31:58]
+ wire [30:0] _GEN_1 = {{6'd0}, _io_out_s_T_234}; // @[RVC.scala 105:43]
+ wire [30:0] _io_out_s_T_235 = _GEN_1 | io_out_s_sub; // @[RVC.scala 105:43]
+ wire [30:0] _io_out_s_T_238 = io_in[11:10] == 2'h1 ? _io_out_s_T_217 : {{5'd0}, _io_out_s_T_208}; // @[package.scala 32:76]
+ wire [31:0] _io_out_s_T_240 = io_in[11:10] == 2'h2 ? _io_out_s_T_227 : {{1'd0}, _io_out_s_T_238}; // @[package.scala 32:76]
+ wire [31:0] io_out_s_12_bits = io_in[11:10] == 2'h3 ? {{1'd0}, _io_out_s_T_235} : _io_out_s_T_240; // @[package.scala 32:76]
+ wire [9:0] _io_out_s_T_252 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 74:12]
+ wire [20:0] _io_out_s_T_260 = {_io_out_s_T_252,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0
+ }; // @[Cat.scala 31:58]
+ wire [31:0] io_out_s_13_bits = {_io_out_s_T_260[20],_io_out_s_T_260[10:1],_io_out_s_T_260[11],_io_out_s_T_260[19:12],5'h0
+ ,7'h6f}; // @[Cat.scala 31:58]
+ wire [4:0] _io_out_s_T_306 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 74:12]
+ wire [12:0] _io_out_s_T_311 = {_io_out_s_T_306,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 31:58]
+ wire [31:0] io_out_s_14_bits = {_io_out_s_T_311[12],_io_out_s_T_311[10:5],5'h0,2'h1,io_in[9:7],3'h0,_io_out_s_T_311[4:
+ 1],_io_out_s_T_311[11],7'h63}; // @[Cat.scala 31:58]
+ wire [31:0] io_out_s_15_bits = {_io_out_s_T_311[12],_io_out_s_T_311[10:5],5'h0,2'h1,io_in[9:7],3'h1,_io_out_s_T_311[4:
+ 1],_io_out_s_T_311[11],7'h63}; // @[Cat.scala 31:58]
+ wire [6:0] io_out_s_load_opc = _io_out_s_opc_T_3 ? 7'h3 : 7'h1f; // @[RVC.scala 113:23]
+ wire [25:0] _io_out_s_T_395 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 31:58]
+ wire [28:0] _io_out_s_T_405 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 31:58]
+ wire [27:0] _io_out_s_T_414 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],io_out_s_load_opc}; // @[Cat.scala 31:58]
+ wire [28:0] _io_out_s_T_423 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],io_out_s_load_opc}; // @[Cat.scala 31:58]
+ wire [24:0] _io_out_s_mv_T_2 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 31:58]
+ wire [24:0] _io_out_s_add_T_3 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 31:58]
+ wire [24:0] io_out_s_jr = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 31:58]
+ wire [24:0] io_out_s_reserved = {io_out_s_jr[24:7],7'h1f}; // @[Cat.scala 31:58]
+ wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_opc_T_3 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala 134:33]
+ wire _io_out_s_jr_mv_T_1 = |io_in[6:2]; // @[RVC.scala 135:27]
+ wire [31:0] io_out_s_mv_bits = {{7'd0}, _io_out_s_mv_T_2}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] io_out_s_jr_reserved_bits = {{7'd0}, _io_out_s_jr_reserved_T_2}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] io_out_s_jr_mv_bits = |io_in[6:2] ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala 135:22]
+ wire [4:0] io_out_s_jr_mv_rd = |io_in[6:2] ? io_in[11:7] : 5'h0; // @[RVC.scala 135:22]
+ wire [4:0] io_out_s_jr_mv_rs1 = |io_in[6:2] ? 5'h0 : io_in[11:7]; // @[RVC.scala 135:22]
+ wire [4:0] io_out_s_jr_mv_rs2 = |io_in[6:2] ? io_in[6:2] : io_in[6:2]; // @[RVC.scala 135:22]
+ wire [24:0] io_out_s_jalr = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 31:58]
+ wire [24:0] _io_out_s_ebreak_T_1 = {io_out_s_jr[24:7],7'h73}; // @[Cat.scala 31:58]
+ wire [24:0] io_out_s_ebreak = _io_out_s_ebreak_T_1 | 25'h100000; // @[RVC.scala 137:46]
+ wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_opc_T_3 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala 138:33]
+ wire [31:0] io_out_s_add_bits = {{7'd0}, _io_out_s_add_T_3}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] io_out_s_jalr_ebreak_bits = {{7'd0}, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jr_mv_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala 139:25]
+ wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jr_mv_T_1 ? io_in[11:7] : 5'h1; // @[RVC.scala 139:25]
+ wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jr_mv_T_1 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 139:25]
+ wire [31:0] io_out_s_20_bits = io_in[12] ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala 140:10]
+ wire [4:0] io_out_s_20_rd = io_in[12] ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala 140:10]
+ wire [4:0] io_out_s_20_rs1 = io_in[12] ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala 140:10]
+ wire [4:0] io_out_s_20_rs2 = io_in[12] ? io_out_s_jr_mv_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala 140:10]
+ wire [8:0] _io_out_s_T_430 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 31:58]
+ wire [28:0] _io_out_s_T_437 = {_io_out_s_T_430[8:5],io_in[6:2],5'h2,3'h3,_io_out_s_T_430[4:0],7'h27}; // @[Cat.scala 31:58]
+ wire [7:0] _io_out_s_T_443 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 31:58]
+ wire [27:0] _io_out_s_T_450 = {_io_out_s_T_443[7:5],io_in[6:2],5'h2,3'h2,_io_out_s_T_443[4:0],7'h23}; // @[Cat.scala 31:58]
+ wire [28:0] _io_out_s_T_463 = {_io_out_s_T_430[8:5],io_in[6:2],5'h2,3'h3,_io_out_s_T_430[4:0],7'h23}; // @[Cat.scala 31:58]
+ wire [4:0] io_out_s_24_rs1 = io_in[19:15]; // @[RVC.scala 20:57]
+ wire [4:0] io_out_s_24_rs2 = io_in[24:20]; // @[RVC.scala 20:79]
+ wire [4:0] _io_out_T_2 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 31:58]
+ wire [31:0] io_out_s_1_bits = {{4'd0}, _io_out_s_T_20}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] io_out_s_0_bits = {{2'd0}, _io_out_s_T_7}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_4_bits = _io_out_T_2 == 5'h1 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_4_rd = _io_out_T_2 == 5'h1 ? _io_out_s_T_6 : _io_out_s_T_6; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_4_rs1 = _io_out_T_2 == 5'h1 ? _io_out_s_T_17 : 5'h2; // @[package.scala 32:76]
+ wire [31:0] io_out_s_2_bits = {{5'd0}, _io_out_s_T_36}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_6_bits = _io_out_T_2 == 5'h2 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_6_rd = _io_out_T_2 == 5'h2 ? _io_out_s_T_6 : _io_out_T_4_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_6_rs1 = _io_out_T_2 == 5'h2 ? _io_out_s_T_17 : _io_out_T_4_rs1; // @[package.scala 32:76]
+ wire [31:0] io_out_s_3_bits = {{4'd0}, _io_out_s_T_51}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_8_bits = _io_out_T_2 == 5'h3 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_8_rd = _io_out_T_2 == 5'h3 ? _io_out_s_T_6 : _io_out_T_6_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_8_rs1 = _io_out_T_2 == 5'h3 ? _io_out_s_T_17 : _io_out_T_6_rs1; // @[package.scala 32:76]
+ wire [31:0] io_out_s_4_bits = {{5'd0}, _io_out_s_T_73}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_10_bits = _io_out_T_2 == 5'h4 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_10_rd = _io_out_T_2 == 5'h4 ? _io_out_s_T_6 : _io_out_T_8_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_10_rs1 = _io_out_T_2 == 5'h4 ? _io_out_s_T_17 : _io_out_T_8_rs1; // @[package.scala 32:76]
+ wire [31:0] io_out_s_5_bits = {{4'd0}, _io_out_s_T_93}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_12_bits = _io_out_T_2 == 5'h5 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_12_rd = _io_out_T_2 == 5'h5 ? _io_out_s_T_6 : _io_out_T_10_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_12_rs1 = _io_out_T_2 == 5'h5 ? _io_out_s_T_17 : _io_out_T_10_rs1; // @[package.scala 32:76]
+ wire [31:0] io_out_s_6_bits = {{5'd0}, _io_out_s_T_115}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_14_bits = _io_out_T_2 == 5'h6 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_14_rd = _io_out_T_2 == 5'h6 ? _io_out_s_T_6 : _io_out_T_12_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_14_rs1 = _io_out_T_2 == 5'h6 ? _io_out_s_T_17 : _io_out_T_12_rs1; // @[package.scala 32:76]
+ wire [31:0] io_out_s_7_bits = {{4'd0}, _io_out_s_T_135}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_16_bits = _io_out_T_2 == 5'h7 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_16_rd = _io_out_T_2 == 5'h7 ? _io_out_s_T_6 : _io_out_T_14_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_16_rs1 = _io_out_T_2 == 5'h7 ? _io_out_s_T_17 : _io_out_T_14_rs1; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_18_bits = _io_out_T_2 == 5'h8 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_18_rd = _io_out_T_2 == 5'h8 ? io_in[11:7] : _io_out_T_16_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_18_rs1 = _io_out_T_2 == 5'h8 ? io_in[11:7] : _io_out_T_16_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_18_rs2 = _io_out_T_2 == 5'h8 ? _io_out_s_T_6 : _io_out_T_16_rd; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_20_bits = _io_out_T_2 == 5'h9 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_20_rd = _io_out_T_2 == 5'h9 ? io_in[11:7] : _io_out_T_18_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_20_rs1 = _io_out_T_2 == 5'h9 ? io_in[11:7] : _io_out_T_18_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_20_rs2 = _io_out_T_2 == 5'h9 ? _io_out_s_T_6 : _io_out_T_18_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_22_bits = _io_out_T_2 == 5'ha ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_22_rd = _io_out_T_2 == 5'ha ? io_in[11:7] : _io_out_T_20_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_22_rs1 = _io_out_T_2 == 5'ha ? 5'h0 : _io_out_T_20_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_22_rs2 = _io_out_T_2 == 5'ha ? _io_out_s_T_6 : _io_out_T_20_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_24_bits = _io_out_T_2 == 5'hb ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_24_rd = _io_out_T_2 == 5'hb ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_24_rs1 = _io_out_T_2 == 5'hb ? io_out_s_11_rd : _io_out_T_22_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_24_rs2 = _io_out_T_2 == 5'hb ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_26_bits = _io_out_T_2 == 5'hc ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_26_rd = _io_out_T_2 == 5'hc ? _io_out_s_T_17 : _io_out_T_24_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_26_rs1 = _io_out_T_2 == 5'hc ? _io_out_s_T_17 : _io_out_T_24_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_26_rs2 = _io_out_T_2 == 5'hc ? _io_out_s_T_6 : _io_out_T_24_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_28_bits = _io_out_T_2 == 5'hd ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_28_rd = _io_out_T_2 == 5'hd ? 5'h0 : _io_out_T_26_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_28_rs1 = _io_out_T_2 == 5'hd ? _io_out_s_T_17 : _io_out_T_26_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_28_rs2 = _io_out_T_2 == 5'hd ? _io_out_s_T_6 : _io_out_T_26_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_30_bits = _io_out_T_2 == 5'he ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_30_rd = _io_out_T_2 == 5'he ? _io_out_s_T_17 : _io_out_T_28_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_30_rs1 = _io_out_T_2 == 5'he ? _io_out_s_T_17 : _io_out_T_28_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_30_rs2 = _io_out_T_2 == 5'he ? 5'h0 : _io_out_T_28_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_32_bits = _io_out_T_2 == 5'hf ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_32_rd = _io_out_T_2 == 5'hf ? 5'h0 : _io_out_T_30_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_32_rs1 = _io_out_T_2 == 5'hf ? _io_out_s_T_17 : _io_out_T_30_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_32_rs2 = _io_out_T_2 == 5'hf ? 5'h0 : _io_out_T_30_rs2; // @[package.scala 32:76]
+ wire [31:0] io_out_s_16_bits = {{6'd0}, _io_out_s_T_395}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_34_bits = _io_out_T_2 == 5'h10 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_34_rd = _io_out_T_2 == 5'h10 ? io_in[11:7] : _io_out_T_32_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_34_rs1 = _io_out_T_2 == 5'h10 ? io_in[11:7] : _io_out_T_32_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_34_rs2 = _io_out_T_2 == 5'h10 ? io_in[6:2] : _io_out_T_32_rs2; // @[package.scala 32:76]
+ wire [31:0] io_out_s_17_bits = {{3'd0}, _io_out_s_T_405}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_36_bits = _io_out_T_2 == 5'h11 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_36_rd = _io_out_T_2 == 5'h11 ? io_in[11:7] : _io_out_T_34_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_36_rs1 = _io_out_T_2 == 5'h11 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_36_rs2 = _io_out_T_2 == 5'h11 ? io_in[6:2] : _io_out_T_34_rs2; // @[package.scala 32:76]
+ wire [31:0] io_out_s_18_bits = {{4'd0}, _io_out_s_T_414}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_38_bits = _io_out_T_2 == 5'h12 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_38_rd = _io_out_T_2 == 5'h12 ? io_in[11:7] : _io_out_T_36_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_38_rs1 = _io_out_T_2 == 5'h12 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_38_rs2 = _io_out_T_2 == 5'h12 ? io_in[6:2] : _io_out_T_36_rs2; // @[package.scala 32:76]
+ wire [31:0] io_out_s_19_bits = {{3'd0}, _io_out_s_T_423}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_40_bits = _io_out_T_2 == 5'h13 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_40_rd = _io_out_T_2 == 5'h13 ? io_in[11:7] : _io_out_T_38_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_40_rs1 = _io_out_T_2 == 5'h13 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_40_rs2 = _io_out_T_2 == 5'h13 ? io_in[6:2] : _io_out_T_38_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_42_bits = _io_out_T_2 == 5'h14 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_42_rd = _io_out_T_2 == 5'h14 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_42_rs1 = _io_out_T_2 == 5'h14 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_42_rs2 = _io_out_T_2 == 5'h14 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala 32:76]
+ wire [31:0] io_out_s_21_bits = {{3'd0}, _io_out_s_T_437}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_44_bits = _io_out_T_2 == 5'h15 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_44_rd = _io_out_T_2 == 5'h15 ? io_in[11:7] : _io_out_T_42_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_44_rs1 = _io_out_T_2 == 5'h15 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_44_rs2 = _io_out_T_2 == 5'h15 ? io_in[6:2] : _io_out_T_42_rs2; // @[package.scala 32:76]
+ wire [31:0] io_out_s_22_bits = {{4'd0}, _io_out_s_T_450}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_46_bits = _io_out_T_2 == 5'h16 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_46_rd = _io_out_T_2 == 5'h16 ? io_in[11:7] : _io_out_T_44_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_46_rs1 = _io_out_T_2 == 5'h16 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_46_rs2 = _io_out_T_2 == 5'h16 ? io_in[6:2] : _io_out_T_44_rs2; // @[package.scala 32:76]
+ wire [31:0] io_out_s_23_bits = {{3'd0}, _io_out_s_T_463}; // @[RVC.scala 21:19 22:14]
+ wire [31:0] _io_out_T_48_bits = _io_out_T_2 == 5'h17 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_48_rd = _io_out_T_2 == 5'h17 ? io_in[11:7] : _io_out_T_46_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_48_rs1 = _io_out_T_2 == 5'h17 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_48_rs2 = _io_out_T_2 == 5'h17 ? io_in[6:2] : _io_out_T_46_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_50_bits = _io_out_T_2 == 5'h18 ? io_in : _io_out_T_48_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_50_rd = _io_out_T_2 == 5'h18 ? io_in[11:7] : _io_out_T_48_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_50_rs1 = _io_out_T_2 == 5'h18 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_50_rs2 = _io_out_T_2 == 5'h18 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_52_bits = _io_out_T_2 == 5'h19 ? io_in : _io_out_T_50_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_52_rd = _io_out_T_2 == 5'h19 ? io_in[11:7] : _io_out_T_50_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_52_rs1 = _io_out_T_2 == 5'h19 ? io_out_s_24_rs1 : _io_out_T_50_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_52_rs2 = _io_out_T_2 == 5'h19 ? io_out_s_24_rs2 : _io_out_T_50_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_54_bits = _io_out_T_2 == 5'h1a ? io_in : _io_out_T_52_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_54_rd = _io_out_T_2 == 5'h1a ? io_in[11:7] : _io_out_T_52_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_54_rs1 = _io_out_T_2 == 5'h1a ? io_out_s_24_rs1 : _io_out_T_52_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_54_rs2 = _io_out_T_2 == 5'h1a ? io_out_s_24_rs2 : _io_out_T_52_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_56_bits = _io_out_T_2 == 5'h1b ? io_in : _io_out_T_54_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_56_rd = _io_out_T_2 == 5'h1b ? io_in[11:7] : _io_out_T_54_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_56_rs1 = _io_out_T_2 == 5'h1b ? io_out_s_24_rs1 : _io_out_T_54_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_56_rs2 = _io_out_T_2 == 5'h1b ? io_out_s_24_rs2 : _io_out_T_54_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_58_bits = _io_out_T_2 == 5'h1c ? io_in : _io_out_T_56_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_58_rd = _io_out_T_2 == 5'h1c ? io_in[11:7] : _io_out_T_56_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_58_rs1 = _io_out_T_2 == 5'h1c ? io_out_s_24_rs1 : _io_out_T_56_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_58_rs2 = _io_out_T_2 == 5'h1c ? io_out_s_24_rs2 : _io_out_T_56_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_60_bits = _io_out_T_2 == 5'h1d ? io_in : _io_out_T_58_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_60_rd = _io_out_T_2 == 5'h1d ? io_in[11:7] : _io_out_T_58_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_60_rs1 = _io_out_T_2 == 5'h1d ? io_out_s_24_rs1 : _io_out_T_58_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_60_rs2 = _io_out_T_2 == 5'h1d ? io_out_s_24_rs2 : _io_out_T_58_rs2; // @[package.scala 32:76]
+ wire [31:0] _io_out_T_62_bits = _io_out_T_2 == 5'h1e ? io_in : _io_out_T_60_bits; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_62_rd = _io_out_T_2 == 5'h1e ? io_in[11:7] : _io_out_T_60_rd; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_62_rs1 = _io_out_T_2 == 5'h1e ? io_out_s_24_rs1 : _io_out_T_60_rs1; // @[package.scala 32:76]
+ wire [4:0] _io_out_T_62_rs2 = _io_out_T_2 == 5'h1e ? io_out_s_24_rs2 : _io_out_T_60_rs2; // @[package.scala 32:76]
+ assign io_out_bits = _io_out_T_2 == 5'h1f ? io_in : _io_out_T_62_bits; // @[package.scala 32:76]
+ assign io_out_rd = _io_out_T_2 == 5'h1f ? io_in[11:7] : _io_out_T_62_rd; // @[package.scala 32:76]
+ assign io_out_rs1 = _io_out_T_2 == 5'h1f ? io_out_s_24_rs1 : _io_out_T_62_rs1; // @[package.scala 32:76]
+ assign io_out_rs2 = _io_out_T_2 == 5'h1f ? io_out_s_24_rs2 : _io_out_T_62_rs2; // @[package.scala 32:76]
+ assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala 163:26]
+endmodule
+module IBuf(
+ input clock,
+ input reset,
+ output io_imem_ready,
+ input io_imem_valid,
+ input [33:0] io_imem_bits_pc,
+ input [31:0] io_imem_bits_data,
+ input io_imem_bits_xcpt_ae_inst,
+ input io_imem_bits_replay,
+ input io_kill,
+ output [33:0] io_pc,
+ input io_inst_0_ready,
+ output io_inst_0_valid,
+ output io_inst_0_bits_xcpt0_ae_inst,
+ output io_inst_0_bits_xcpt1_pf_inst,
+ output io_inst_0_bits_xcpt1_gf_inst,
+ output io_inst_0_bits_xcpt1_ae_inst,
+ output io_inst_0_bits_replay,
+ output io_inst_0_bits_rvc,
+ output [31:0] io_inst_0_bits_inst_bits,
+ output [4:0] io_inst_0_bits_inst_rd,
+ output [4:0] io_inst_0_bits_inst_rs1,
+ output [4:0] io_inst_0_bits_inst_rs2,
+ output [31:0] io_inst_0_bits_raw
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [63:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] exp_io_in; // @[IBuf.scala 86:21]
+ wire [31:0] exp_io_out_bits; // @[IBuf.scala 86:21]
+ wire [4:0] exp_io_out_rd; // @[IBuf.scala 86:21]
+ wire [4:0] exp_io_out_rs1; // @[IBuf.scala 86:21]
+ wire [4:0] exp_io_out_rs2; // @[IBuf.scala 86:21]
+ wire exp_io_rvc; // @[IBuf.scala 86:21]
+ reg nBufValid; // @[IBuf.scala 34:47]
+ reg [33:0] buf__pc; // @[IBuf.scala 35:16]
+ reg [31:0] buf__data; // @[IBuf.scala 35:16]
+ reg buf__xcpt_ae_inst; // @[IBuf.scala 35:16]
+ reg buf__replay; // @[IBuf.scala 35:16]
+ wire pcWordBits = io_imem_bits_pc[1]; // @[package.scala 154:13]
+ wire [1:0] _GEN_58 = {{1'd0}, pcWordBits}; // @[IBuf.scala 41:88]
+ wire [1:0] nIC = 2'h2 - _GEN_58; // @[IBuf.scala 41:88]
+ wire [1:0] _nValid_T = io_imem_valid ? nIC : 2'h0; // @[IBuf.scala 43:19]
+ wire [1:0] _GEN_59 = {{1'd0}, nBufValid}; // @[IBuf.scala 43:49]
+ wire [1:0] nValid = _nValid_T + _GEN_59; // @[IBuf.scala 43:49]
+ wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala 57:35]
+ wire [3:0] _valid_T_2 = _valid_T - 4'h1; // @[IBuf.scala 74:33]
+ wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala 74:37]
+ wire [1:0] _full_insn_T_2 = {{1'd0}, valid[1]}; // @[IBuf.scala 93:42]
+ wire [1:0] _bufMask_T = 2'h1 << nBufValid; // @[OneHot.scala 57:35]
+ wire [1:0] bufMask = _bufMask_T - 2'h1; // @[IBuf.scala 75:37]
+ wire [1:0] buf_replay = buf__replay ? bufMask : 2'h0; // @[IBuf.scala 77:23]
+ wire full_insn = exp_io_rvc | _full_insn_T_2[0] | buf_replay[0]; // @[IBuf.scala 93:48]
+ wire [1:0] _nReady_T_4 = exp_io_rvc ? 2'h1 : 2'h2; // @[IBuf.scala 102:71]
+ wire [1:0] nReady = full_insn ? _nReady_T_4 : 2'h0; // @[IBuf.scala 102:{56,65}]
+ wire [1:0] nICReady = nReady - _GEN_59; // @[IBuf.scala 42:25]
+ wire _io_imem_ready_T = nReady >= _GEN_59; // @[IBuf.scala 44:47]
+ wire [1:0] _io_imem_ready_T_4 = nIC - nICReady; // @[IBuf.scala 44:92]
+ wire _io_imem_ready_T_5 = 2'h1 >= _io_imem_ready_T_4; // @[IBuf.scala 44:85]
+ wire _nBufValid_T_2 = _io_imem_ready_T | ~nBufValid; // @[package.scala 209:38]
+ wire [1:0] _nBufValid_T_4 = _GEN_59 - nReady; // @[IBuf.scala 48:65]
+ wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[IBuf.scala 48:23]
+ wire [1:0] shamt = _GEN_58 + nICReady; // @[IBuf.scala 55:32]
+ wire [63:0] buf_data_data = {io_imem_bits_data[31:16],io_imem_bits_data[31:16],io_imem_bits_data}; // @[Cat.scala 31:58]
+ wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala 128:19]
+ wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala 128:10]
+ wire [33:0] _buf_pc_T_1 = io_imem_bits_pc & 34'h3fffffffc; // @[IBuf.scala 59:35]
+ wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala 59:80]
+ wire [33:0] _GEN_67 = {{31'd0}, _buf_pc_T_2}; // @[IBuf.scala 59:68]
+ wire [33:0] _buf_pc_T_4 = io_imem_bits_pc + _GEN_67; // @[IBuf.scala 59:68]
+ wire [33:0] _buf_pc_T_5 = _buf_pc_T_4 & 34'h3; // @[IBuf.scala 59:109]
+ wire [33:0] _buf_pc_T_6 = _buf_pc_T_1 | _buf_pc_T_5; // @[IBuf.scala 59:49]
+ wire [1:0] _GEN_0 = io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5 ? _io_imem_ready_T_4 :
+ _nBufValid_T_5; // @[IBuf.scala 48:17 54:92 56:19]
+ wire [1:0] _GEN_24 = io_inst_0_ready ? _GEN_0 : {{1'd0}, nBufValid}; // @[IBuf.scala 47:29 34:47]
+ wire [1:0] _GEN_48 = io_kill ? 2'h0 : _GEN_24; // @[IBuf.scala 63:20 64:17]
+ wire [1:0] _icShiftAmt_T_1 = 2'h2 + _GEN_59; // @[IBuf.scala 68:32]
+ wire [1:0] icShiftAmt = _icShiftAmt_T_1 - _GEN_58; // @[IBuf.scala 68:44]
+ wire [63:0] _icData_T_2 = {io_imem_bits_data,io_imem_bits_data[15:0],io_imem_bits_data[15:0]}; // @[Cat.scala 31:58]
+ wire [127:0] icData_data = {_icData_T_2[63:48],_icData_T_2[63:48],_icData_T_2[63:48],_icData_T_2[63:48],
+ io_imem_bits_data,io_imem_bits_data[15:0],io_imem_bits_data[15:0]}; // @[Cat.scala 31:58]
+ wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala 121:19]
+ wire [190:0] _GEN_1 = {{63'd0}, icData_data}; // @[IBuf.scala 121:10]
+ wire [190:0] _icData_T_4 = _GEN_1 << _icData_T_3; // @[IBuf.scala 121:10]
+ wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala 154:13]
+ wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala 71:65]
+ wire [62:0] _icMask_T_2 = 63'hffffffff << _icMask_T_1; // @[IBuf.scala 71:51]
+ wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala 71:92]
+ wire [31:0] _inst_T = icData & icMask; // @[IBuf.scala 72:21]
+ wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala 72:43]
+ wire [31:0] _inst_T_2 = buf__data & _inst_T_1; // @[IBuf.scala 72:41]
+ wire xcpt_1_ae_inst = bufMask[1] ? buf__xcpt_ae_inst : io_imem_bits_xcpt_ae_inst; // @[IBuf.scala 76:53]
+ wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala 78:65]
+ wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala 78:63]
+ wire [1:0] _ic_replay_T_2 = io_imem_bits_replay ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala 78:35]
+ wire [1:0] ic_replay = buf_replay | _ic_replay_T_2; // @[IBuf.scala 78:30]
+ wire [1:0] _replay_T_5 = {{1'd0}, ic_replay[1]}; // @[IBuf.scala 92:61]
+ wire [2:0] _io_inst_0_bits_xcpt1_T_4 = {2'h0,xcpt_1_ae_inst}; // @[IBuf.scala 96:63]
+ wire [2:0] _io_inst_0_bits_xcpt1_T_5 = exp_io_rvc ? 3'h0 : _io_inst_0_bits_xcpt1_T_4; // @[IBuf.scala 96:35]
+ RVCExpander exp ( // @[IBuf.scala 86:21]
+ .io_in(exp_io_in),
+ .io_out_bits(exp_io_out_bits),
+ .io_out_rd(exp_io_out_rd),
+ .io_out_rs1(exp_io_out_rs1),
+ .io_out_rs2(exp_io_out_rs2),
+ .io_rvc(exp_io_rvc)
+ );
+ assign io_imem_ready = io_inst_0_ready & nReady >= _GEN_59 & (nICReady >= nIC | 2'h1 >= _io_imem_ready_T_4); // @[IBuf.scala 44:60]
+ assign io_pc = nBufValid > 1'h0 ? buf__pc : io_imem_bits_pc; // @[IBuf.scala 82:15]
+ assign io_inst_0_valid = valid[0] & full_insn; // @[IBuf.scala 94:36]
+ assign io_inst_0_bits_xcpt0_ae_inst = bufMask[0] ? buf__xcpt_ae_inst : io_imem_bits_xcpt_ae_inst; // @[IBuf.scala 76:53]
+ assign io_inst_0_bits_xcpt1_pf_inst = _io_inst_0_bits_xcpt1_T_5[2]; // @[IBuf.scala 96:79]
+ assign io_inst_0_bits_xcpt1_gf_inst = _io_inst_0_bits_xcpt1_T_5[1]; // @[IBuf.scala 96:79]
+ assign io_inst_0_bits_xcpt1_ae_inst = _io_inst_0_bits_xcpt1_T_5[0]; // @[IBuf.scala 96:79]
+ assign io_inst_0_bits_replay = ic_replay[0] | ~exp_io_rvc & _replay_T_5[0]; // @[IBuf.scala 92:33]
+ assign io_inst_0_bits_rvc = exp_io_rvc; // @[IBuf.scala 98:27]
+ assign io_inst_0_bits_inst_bits = exp_io_out_bits; // @[IBuf.scala 88:26]
+ assign io_inst_0_bits_inst_rd = exp_io_out_rd; // @[IBuf.scala 88:26]
+ assign io_inst_0_bits_inst_rs1 = exp_io_out_rs1; // @[IBuf.scala 88:26]
+ assign io_inst_0_bits_inst_rs2 = exp_io_out_rs2; // @[IBuf.scala 88:26]
+ assign io_inst_0_bits_raw = _inst_T | _inst_T_2; // @[IBuf.scala 72:30]
+ assign exp_io_in = _inst_T | _inst_T_2; // @[IBuf.scala 72:30]
+ always @(posedge clock) begin
+ if (reset) begin // @[IBuf.scala 34:47]
+ nBufValid <= 1'h0; // @[IBuf.scala 34:47]
+ end else begin
+ nBufValid <= _GEN_48[0];
+ end
+ if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
+ if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
+ buf__pc <= _buf_pc_T_6; // @[IBuf.scala 59:16]
+ end
+ end
+ if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
+ if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
+ buf__data <= {{16'd0}, _buf_data_T_1[15:0]}; // @[IBuf.scala 58:18]
+ end
+ end
+ if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
+ if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
+ buf__xcpt_ae_inst <= io_imem_bits_xcpt_ae_inst; // @[IBuf.scala 57:13]
+ end
+ end
+ if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
+ if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
+ buf__replay <= io_imem_bits_replay; // @[IBuf.scala 57:13]
+ end
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ nBufValid = _RAND_0[0:0];
+ _RAND_1 = {2{`RANDOM}};
+ buf__pc = _RAND_1[33:0];
+ _RAND_2 = {1{`RANDOM}};
+ buf__data = _RAND_2[31:0];
+ _RAND_3 = {1{`RANDOM}};
+ buf__xcpt_ae_inst = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ buf__replay = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module CSRFile(
+ input clock,
+ input reset,
+ input io_ungated_clock,
+ input io_interrupts_debug,
+ input io_interrupts_mtip,
+ input io_interrupts_msip,
+ input io_interrupts_meip,
+ input io_hartid,
+ input [11:0] io_rw_addr,
+ input [2:0] io_rw_cmd,
+ output [63:0] io_rw_rdata,
+ input [63:0] io_rw_wdata,
+ input [31:0] io_decode_0_inst,
+ output io_decode_0_fp_illegal,
+ output io_decode_0_fp_csr,
+ output io_decode_0_read_illegal,
+ output io_decode_0_write_illegal,
+ output io_decode_0_write_flush,
+ output io_decode_0_system_illegal,
+ output io_csr_stall,
+ output io_eret,
+ output io_singleStep,
+ output io_status_debug,
+ output io_status_cease,
+ output io_status_wfi,
+ output [31:0] io_status_isa,
+ output [1:0] io_status_dprv,
+ output io_status_dv,
+ output [1:0] io_status_prv,
+ output io_status_v,
+ output io_status_sd,
+ output [22:0] io_status_zero2,
+ output io_status_mpv,
+ output io_status_gva,
+ output io_status_mbe,
+ output io_status_sbe,
+ output [1:0] io_status_sxl,
+ output [1:0] io_status_uxl,
+ output io_status_sd_rv32,
+ output [7:0] io_status_zero1,
+ output io_status_tsr,
+ output io_status_tw,
+ output io_status_tvm,
+ output io_status_mxr,
+ output io_status_sum,
+ output io_status_mprv,
+ output [1:0] io_status_xs,
+ output [1:0] io_status_fs,
+ output [1:0] io_status_mpp,
+ output [1:0] io_status_vs,
+ output io_status_spp,
+ output io_status_mpie,
+ output io_status_ube,
+ output io_status_spie,
+ output io_status_upie,
+ output io_status_mie,
+ output io_status_hie,
+ output io_status_sie,
+ output io_status_uie,
+ output [33:0] io_evec,
+ input io_exception,
+ input io_retire,
+ input [63:0] io_cause,
+ input [33:0] io_pc,
+ input [33:0] io_tval,
+ input io_gva,
+ output [63:0] io_time,
+ output io_interrupt,
+ output [63:0] io_interrupt_cause,
+ output io_bp_0_control_action,
+ output [1:0] io_bp_0_control_tmatch,
+ output io_bp_0_control_x,
+ output io_bp_0_control_w,
+ output io_bp_0_control_r,
+ output [32:0] io_bp_0_address,
+ output io_pmp_0_cfg_l,
+ output [1:0] io_pmp_0_cfg_a,
+ output io_pmp_0_cfg_x,
+ output io_pmp_0_cfg_w,
+ output io_pmp_0_cfg_r,
+ output [29:0] io_pmp_0_addr,
+ output [31:0] io_pmp_0_mask,
+ output io_pmp_1_cfg_l,
+ output [1:0] io_pmp_1_cfg_a,
+ output io_pmp_1_cfg_x,
+ output io_pmp_1_cfg_w,
+ output io_pmp_1_cfg_r,
+ output [29:0] io_pmp_1_addr,
+ output [31:0] io_pmp_1_mask,
+ output io_pmp_2_cfg_l,
+ output [1:0] io_pmp_2_cfg_a,
+ output io_pmp_2_cfg_x,
+ output io_pmp_2_cfg_w,
+ output io_pmp_2_cfg_r,
+ output [29:0] io_pmp_2_addr,
+ output [31:0] io_pmp_2_mask,
+ output io_pmp_3_cfg_l,
+ output [1:0] io_pmp_3_cfg_a,
+ output io_pmp_3_cfg_x,
+ output io_pmp_3_cfg_w,
+ output io_pmp_3_cfg_r,
+ output [29:0] io_pmp_3_addr,
+ output [31:0] io_pmp_3_mask,
+ output io_pmp_4_cfg_l,
+ output [1:0] io_pmp_4_cfg_a,
+ output io_pmp_4_cfg_x,
+ output io_pmp_4_cfg_w,
+ output io_pmp_4_cfg_r,
+ output [29:0] io_pmp_4_addr,
+ output [31:0] io_pmp_4_mask,
+ output io_pmp_5_cfg_l,
+ output [1:0] io_pmp_5_cfg_a,
+ output io_pmp_5_cfg_x,
+ output io_pmp_5_cfg_w,
+ output io_pmp_5_cfg_r,
+ output [29:0] io_pmp_5_addr,
+ output [31:0] io_pmp_5_mask,
+ output io_pmp_6_cfg_l,
+ output [1:0] io_pmp_6_cfg_a,
+ output io_pmp_6_cfg_x,
+ output io_pmp_6_cfg_w,
+ output io_pmp_6_cfg_r,
+ output [29:0] io_pmp_6_addr,
+ output [31:0] io_pmp_6_mask,
+ output io_pmp_7_cfg_l,
+ output [1:0] io_pmp_7_cfg_a,
+ output io_pmp_7_cfg_x,
+ output io_pmp_7_cfg_w,
+ output io_pmp_7_cfg_r,
+ output [29:0] io_pmp_7_addr,
+ output [31:0] io_pmp_7_mask,
+ output io_inhibit_cycle,
+ input [31:0] io_inst_0,
+ output io_trace_0_valid,
+ output [33:0] io_trace_0_iaddr,
+ output [31:0] io_trace_0_insn,
+ output io_trace_0_exception,
+ output [63:0] io_customCSRs_0_value
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [63:0] _RAND_8;
+ reg [63:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [63:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [31:0] _RAND_30;
+ reg [31:0] _RAND_31;
+ reg [31:0] _RAND_32;
+ reg [31:0] _RAND_33;
+ reg [31:0] _RAND_34;
+ reg [31:0] _RAND_35;
+ reg [31:0] _RAND_36;
+ reg [31:0] _RAND_37;
+ reg [31:0] _RAND_38;
+ reg [31:0] _RAND_39;
+ reg [31:0] _RAND_40;
+ reg [31:0] _RAND_41;
+ reg [31:0] _RAND_42;
+ reg [31:0] _RAND_43;
+ reg [31:0] _RAND_44;
+ reg [31:0] _RAND_45;
+ reg [31:0] _RAND_46;
+ reg [31:0] _RAND_47;
+ reg [31:0] _RAND_48;
+ reg [31:0] _RAND_49;
+ reg [31:0] _RAND_50;
+ reg [31:0] _RAND_51;
+ reg [31:0] _RAND_52;
+ reg [31:0] _RAND_53;
+ reg [31:0] _RAND_54;
+ reg [31:0] _RAND_55;
+ reg [31:0] _RAND_56;
+ reg [31:0] _RAND_57;
+ reg [31:0] _RAND_58;
+ reg [31:0] _RAND_59;
+ reg [31:0] _RAND_60;
+ reg [31:0] _RAND_61;
+ reg [31:0] _RAND_62;
+ reg [31:0] _RAND_63;
+ reg [31:0] _RAND_64;
+ reg [31:0] _RAND_65;
+ reg [63:0] _RAND_66;
+ reg [63:0] _RAND_67;
+ reg [63:0] _RAND_68;
+ reg [63:0] _RAND_69;
+ reg [63:0] _RAND_70;
+ reg [31:0] _RAND_71;
+ reg [31:0] _RAND_72;
+ reg [31:0] _RAND_73;
+ reg [31:0] _RAND_74;
+ reg [63:0] _RAND_75;
+ reg [31:0] _RAND_76;
+ reg [63:0] _RAND_77;
+ reg [63:0] _RAND_78;
+ reg [63:0] _RAND_79;
+ reg [31:0] _RAND_80;
+`endif // RANDOMIZE_REG_INIT
+ reg reg_mstatus_gva; // @[CSR.scala 369:24]
+ reg reg_mstatus_spp; // @[CSR.scala 369:24]
+ reg reg_mstatus_mpie; // @[CSR.scala 369:24]
+ reg reg_mstatus_mie; // @[CSR.scala 369:24]
+ reg reg_dcsr_ebreakm; // @[CSR.scala 377:21]
+ reg [2:0] reg_dcsr_cause; // @[CSR.scala 377:21]
+ reg reg_dcsr_step; // @[CSR.scala 377:21]
+ reg reg_debug; // @[CSR.scala 449:22]
+ reg [33:0] reg_dpc; // @[CSR.scala 450:20]
+ reg [63:0] reg_dscratch; // @[CSR.scala 451:25]
+ reg reg_singleStepped; // @[CSR.scala 453:30]
+ reg reg_bp_0_control_dmode; // @[CSR.scala 459:19]
+ reg reg_bp_0_control_action; // @[CSR.scala 459:19]
+ reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala 459:19]
+ reg reg_bp_0_control_x; // @[CSR.scala 459:19]
+ reg reg_bp_0_control_w; // @[CSR.scala 459:19]
+ reg reg_bp_0_control_r; // @[CSR.scala 459:19]
+ reg [32:0] reg_bp_0_address; // @[CSR.scala 459:19]
+ reg reg_pmp_0_cfg_l; // @[CSR.scala 460:20]
+ reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala 460:20]
+ reg reg_pmp_0_cfg_x; // @[CSR.scala 460:20]
+ reg reg_pmp_0_cfg_w; // @[CSR.scala 460:20]
+ reg reg_pmp_0_cfg_r; // @[CSR.scala 460:20]
+ reg [29:0] reg_pmp_0_addr; // @[CSR.scala 460:20]
+ reg reg_pmp_1_cfg_l; // @[CSR.scala 460:20]
+ reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala 460:20]
+ reg reg_pmp_1_cfg_x; // @[CSR.scala 460:20]
+ reg reg_pmp_1_cfg_w; // @[CSR.scala 460:20]
+ reg reg_pmp_1_cfg_r; // @[CSR.scala 460:20]
+ reg [29:0] reg_pmp_1_addr; // @[CSR.scala 460:20]
+ reg reg_pmp_2_cfg_l; // @[CSR.scala 460:20]
+ reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala 460:20]
+ reg reg_pmp_2_cfg_x; // @[CSR.scala 460:20]
+ reg reg_pmp_2_cfg_w; // @[CSR.scala 460:20]
+ reg reg_pmp_2_cfg_r; // @[CSR.scala 460:20]
+ reg [29:0] reg_pmp_2_addr; // @[CSR.scala 460:20]
+ reg reg_pmp_3_cfg_l; // @[CSR.scala 460:20]
+ reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala 460:20]
+ reg reg_pmp_3_cfg_x; // @[CSR.scala 460:20]
+ reg reg_pmp_3_cfg_w; // @[CSR.scala 460:20]
+ reg reg_pmp_3_cfg_r; // @[CSR.scala 460:20]
+ reg [29:0] reg_pmp_3_addr; // @[CSR.scala 460:20]
+ reg reg_pmp_4_cfg_l; // @[CSR.scala 460:20]
+ reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala 460:20]
+ reg reg_pmp_4_cfg_x; // @[CSR.scala 460:20]
+ reg reg_pmp_4_cfg_w; // @[CSR.scala 460:20]
+ reg reg_pmp_4_cfg_r; // @[CSR.scala 460:20]
+ reg [29:0] reg_pmp_4_addr; // @[CSR.scala 460:20]
+ reg reg_pmp_5_cfg_l; // @[CSR.scala 460:20]
+ reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala 460:20]
+ reg reg_pmp_5_cfg_x; // @[CSR.scala 460:20]
+ reg reg_pmp_5_cfg_w; // @[CSR.scala 460:20]
+ reg reg_pmp_5_cfg_r; // @[CSR.scala 460:20]
+ reg [29:0] reg_pmp_5_addr; // @[CSR.scala 460:20]
+ reg reg_pmp_6_cfg_l; // @[CSR.scala 460:20]
+ reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala 460:20]
+ reg reg_pmp_6_cfg_x; // @[CSR.scala 460:20]
+ reg reg_pmp_6_cfg_w; // @[CSR.scala 460:20]
+ reg reg_pmp_6_cfg_r; // @[CSR.scala 460:20]
+ reg [29:0] reg_pmp_6_addr; // @[CSR.scala 460:20]
+ reg reg_pmp_7_cfg_l; // @[CSR.scala 460:20]
+ reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala 460:20]
+ reg reg_pmp_7_cfg_x; // @[CSR.scala 460:20]
+ reg reg_pmp_7_cfg_w; // @[CSR.scala 460:20]
+ reg reg_pmp_7_cfg_r; // @[CSR.scala 460:20]
+ reg [29:0] reg_pmp_7_addr; // @[CSR.scala 460:20]
+ reg [63:0] reg_mie; // @[CSR.scala 462:20]
+ reg [33:0] reg_mepc; // @[CSR.scala 472:21]
+ reg [63:0] reg_mcause; // @[CSR.scala 473:27]
+ reg [33:0] reg_mtval; // @[CSR.scala 474:22]
+ reg [63:0] reg_mscratch; // @[CSR.scala 476:25]
+ reg [31:0] reg_mtvec; // @[CSR.scala 479:27]
+ reg reg_wfi; // @[CSR.scala 538:50]
+ reg [2:0] reg_mcountinhibit; // @[CSR.scala 547:34]
+ wire x79 = reg_mcountinhibit[2]; // @[CSR.scala 549:75]
+ reg [5:0] small_; // @[Counters.scala 45:37]
+ wire [5:0] _GEN_36 = {{5'd0}, io_retire}; // @[Counters.scala 46:33]
+ wire [6:0] nextSmall = small_ + _GEN_36; // @[Counters.scala 46:33]
+ wire _T_18 = ~x79; // @[Counters.scala 47:9]
+ wire [6:0] _GEN_0 = ~x79 ? nextSmall : {{1'd0}, small_}; // @[Counters.scala 47:{19,27} 45:37]
+ reg [57:0] large_; // @[Counters.scala 50:27]
+ wire [57:0] _large_r_T_1 = large_ + 58'h1; // @[Counters.scala 51:55]
+ wire [57:0] _GEN_1 = nextSmall[6] & _T_18 ? _large_r_T_1 : large_; // @[Counters.scala 50:27 51:{46,50}]
+ wire [63:0] value = {large_,small_}; // @[Cat.scala 31:58]
+ wire x86 = ~io_csr_stall; // @[CSR.scala 551:56]
+ reg [5:0] small_1; // @[Counters.scala 45:37]
+ wire [5:0] _GEN_37 = {{5'd0}, x86}; // @[Counters.scala 46:33]
+ wire [6:0] nextSmall_1 = small_1 + _GEN_37; // @[Counters.scala 46:33]
+ wire _T_19 = ~reg_mcountinhibit[0]; // @[Counters.scala 47:9]
+ wire [6:0] _GEN_2 = ~reg_mcountinhibit[0] ? nextSmall_1 : {{1'd0}, small_1}; // @[Counters.scala 47:{19,27} 45:37]
+ reg [57:0] large_1; // @[Counters.scala 50:27]
+ wire [57:0] _large_r_T_3 = large_1 + 58'h1; // @[Counters.scala 51:55]
+ wire [57:0] _GEN_3 = nextSmall_1[6] & _T_19 ? _large_r_T_3 : large_1; // @[Counters.scala 50:27 51:{46,50}]
+ wire [63:0] value_1 = {large_1,small_1}; // @[Cat.scala 31:58]
+ wire [15:0] _read_mip_T = {4'h0,io_interrupts_meip,1'h0,2'h0,io_interrupts_mtip,1'h0,2'h0,io_interrupts_msip,1'h0,2'h0
+ }; // @[CSR.scala 567:22]
+ wire [15:0] read_mip = _read_mip_T & 16'h888; // @[CSR.scala 567:29]
+ wire [63:0] _GEN_42 = {{48'd0}, read_mip}; // @[CSR.scala 571:56]
+ wire [63:0] pending_interrupts = _GEN_42 & reg_mie; // @[CSR.scala 571:56]
+ wire [14:0] d_interrupts = {io_interrupts_debug, 14'h0}; // @[CSR.scala 572:42]
+ wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala 577:83]
+ wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_3; // @[CSR.scala 577:81]
+ wire [63:0] m_interrupts = reg_mstatus_mie ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala 577:25]
+ wire _any_T_78 = d_interrupts[14] | d_interrupts[13] | d_interrupts[12] | d_interrupts[11] | d_interrupts[3] |
+ d_interrupts[7] | d_interrupts[9] | d_interrupts[1] | d_interrupts[5] | d_interrupts[10] | d_interrupts[2] |
+ d_interrupts[6] | d_interrupts[8] | d_interrupts[0] | d_interrupts[4] | m_interrupts[15]; // @[CSR.scala 1534:90]
+ wire anyInterrupt = _any_T_78 | m_interrupts[14] | m_interrupts[13] | m_interrupts[12] | m_interrupts[11] |
+ m_interrupts[3] | m_interrupts[7] | m_interrupts[9] | m_interrupts[1] | m_interrupts[5] | m_interrupts[10] |
+ m_interrupts[2] | m_interrupts[6] | m_interrupts[8] | m_interrupts[0] | m_interrupts[4]; // @[CSR.scala 1534:90]
+ wire [3:0] _which_T_95 = m_interrupts[0] ? 4'h0 : 4'h4; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_96 = m_interrupts[8] ? 4'h8 : _which_T_95; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_97 = m_interrupts[6] ? 4'h6 : _which_T_96; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_98 = m_interrupts[2] ? 4'h2 : _which_T_97; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_99 = m_interrupts[10] ? 4'ha : _which_T_98; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_100 = m_interrupts[5] ? 4'h5 : _which_T_99; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_101 = m_interrupts[1] ? 4'h1 : _which_T_100; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_102 = m_interrupts[9] ? 4'h9 : _which_T_101; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_103 = m_interrupts[7] ? 4'h7 : _which_T_102; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_104 = m_interrupts[3] ? 4'h3 : _which_T_103; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_105 = m_interrupts[11] ? 4'hb : _which_T_104; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_106 = m_interrupts[12] ? 4'hc : _which_T_105; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_107 = m_interrupts[13] ? 4'hd : _which_T_106; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_108 = m_interrupts[14] ? 4'he : _which_T_107; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_109 = m_interrupts[15] ? 4'hf : _which_T_108; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_111 = d_interrupts[4] ? 4'h4 : _which_T_109; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_112 = d_interrupts[0] ? 4'h0 : _which_T_111; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_113 = d_interrupts[8] ? 4'h8 : _which_T_112; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_114 = d_interrupts[6] ? 4'h6 : _which_T_113; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_115 = d_interrupts[2] ? 4'h2 : _which_T_114; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_116 = d_interrupts[10] ? 4'ha : _which_T_115; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_117 = d_interrupts[5] ? 4'h5 : _which_T_116; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_118 = d_interrupts[1] ? 4'h1 : _which_T_117; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_119 = d_interrupts[9] ? 4'h9 : _which_T_118; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_120 = d_interrupts[7] ? 4'h7 : _which_T_119; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_121 = d_interrupts[3] ? 4'h3 : _which_T_120; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_122 = d_interrupts[11] ? 4'hb : _which_T_121; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_123 = d_interrupts[12] ? 4'hc : _which_T_122; // @[Mux.scala 47:70]
+ wire [3:0] _which_T_124 = d_interrupts[13] ? 4'hd : _which_T_123; // @[Mux.scala 47:70]
+ wire [3:0] whichInterrupt = d_interrupts[14] ? 4'he : _which_T_124; // @[Mux.scala 47:70]
+ wire [63:0] _GEN_43 = {{60'd0}, whichInterrupt}; // @[CSR.scala 582:67]
+ wire _io_interrupt_T = ~io_singleStep; // @[CSR.scala 583:36]
+ wire [30:0] pmp_mask_base = {reg_pmp_0_addr,reg_pmp_0_cfg_a[0]}; // @[Cat.scala 31:58]
+ wire [30:0] _pmp_mask_T_1 = pmp_mask_base + 31'h1; // @[PMP.scala 59:23]
+ wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala 59:16]
+ wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala 59:14]
+ wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3,2'h3}; // @[Cat.scala 31:58]
+ wire [30:0] pmp_mask_base_1 = {reg_pmp_1_addr,reg_pmp_1_cfg_a[0]}; // @[Cat.scala 31:58]
+ wire [30:0] _pmp_mask_T_6 = pmp_mask_base_1 + 31'h1; // @[PMP.scala 59:23]
+ wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala 59:16]
+ wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala 59:14]
+ wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8,2'h3}; // @[Cat.scala 31:58]
+ wire [30:0] pmp_mask_base_2 = {reg_pmp_2_addr,reg_pmp_2_cfg_a[0]}; // @[Cat.scala 31:58]
+ wire [30:0] _pmp_mask_T_11 = pmp_mask_base_2 + 31'h1; // @[PMP.scala 59:23]
+ wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala 59:16]
+ wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala 59:14]
+ wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13,2'h3}; // @[Cat.scala 31:58]
+ wire [30:0] pmp_mask_base_3 = {reg_pmp_3_addr,reg_pmp_3_cfg_a[0]}; // @[Cat.scala 31:58]
+ wire [30:0] _pmp_mask_T_16 = pmp_mask_base_3 + 31'h1; // @[PMP.scala 59:23]
+ wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala 59:16]
+ wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala 59:14]
+ wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18,2'h3}; // @[Cat.scala 31:58]
+ wire [30:0] pmp_mask_base_4 = {reg_pmp_4_addr,reg_pmp_4_cfg_a[0]}; // @[Cat.scala 31:58]
+ wire [30:0] _pmp_mask_T_21 = pmp_mask_base_4 + 31'h1; // @[PMP.scala 59:23]
+ wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala 59:16]
+ wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala 59:14]
+ wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23,2'h3}; // @[Cat.scala 31:58]
+ wire [30:0] pmp_mask_base_5 = {reg_pmp_5_addr,reg_pmp_5_cfg_a[0]}; // @[Cat.scala 31:58]
+ wire [30:0] _pmp_mask_T_26 = pmp_mask_base_5 + 31'h1; // @[PMP.scala 59:23]
+ wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala 59:16]
+ wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala 59:14]
+ wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28,2'h3}; // @[Cat.scala 31:58]
+ wire [30:0] pmp_mask_base_6 = {reg_pmp_6_addr,reg_pmp_6_cfg_a[0]}; // @[Cat.scala 31:58]
+ wire [30:0] _pmp_mask_T_31 = pmp_mask_base_6 + 31'h1; // @[PMP.scala 59:23]
+ wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala 59:16]
+ wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala 59:14]
+ wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33,2'h3}; // @[Cat.scala 31:58]
+ wire [30:0] pmp_mask_base_7 = {reg_pmp_7_addr,reg_pmp_7_cfg_a[0]}; // @[Cat.scala 31:58]
+ wire [30:0] _pmp_mask_T_36 = pmp_mask_base_7 + 31'h1; // @[PMP.scala 59:23]
+ wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala 59:16]
+ wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala 59:14]
+ wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38,2'h3}; // @[Cat.scala 31:58]
+ reg [63:0] reg_misa; // @[CSR.scala 605:21]
+ wire [8:0] read_mstatus_lo_lo = {io_status_spp,io_status_mpie,io_status_ube,io_status_spie,io_status_upie,
+ io_status_mie,io_status_hie,io_status_sie,io_status_uie}; // @[CSR.scala 606:38]
+ wire [21:0] read_mstatus_lo = {io_status_tw,io_status_tvm,io_status_mxr,io_status_sum,io_status_mprv,io_status_xs,
+ io_status_fs,io_status_mpp,io_status_vs,read_mstatus_lo_lo}; // @[CSR.scala 606:38]
+ wire [64:0] read_mstatus_hi_hi = {io_status_debug,io_status_cease,io_status_wfi,io_status_isa,io_status_dprv,
+ io_status_dv,io_status_prv,io_status_v,io_status_sd,io_status_zero2}; // @[CSR.scala 606:38]
+ wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi,io_status_mpv,io_status_gva,io_status_mbe,io_status_sbe,
+ io_status_sxl,io_status_uxl,io_status_sd_rv32,io_status_zero1,io_status_tsr}; // @[CSR.scala 606:38]
+ wire [104:0] _read_mstatus_T = {read_mstatus_hi,read_mstatus_lo}; // @[CSR.scala 606:38]
+ wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[CSR.scala 606:40]
+ wire [7:0] _read_mtvec_T_1 = reg_mtvec[0] ? 8'hfe : 8'h2; // @[CSR.scala 1563:39]
+ wire [31:0] _read_mtvec_T_3 = {{24'd0}, _read_mtvec_T_1}; // @[package.scala 165:41]
+ wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala 165:37]
+ wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala 165:35]
+ wire [63:0] read_mtvec = {32'h0,_read_mtvec_T_5}; // @[Cat.scala 31:58]
+ wire [6:0] lo_4 = {4'h8,reg_bp_0_control_x,reg_bp_0_control_w,reg_bp_0_control_r}; // @[CSR.scala 612:48]
+ wire [63:0] _T_20 = {4'h2,reg_bp_0_control_dmode,46'h40000000000,reg_bp_0_control_action,1'h0,2'h0,
+ reg_bp_0_control_tmatch,lo_4}; // @[CSR.scala 612:48]
+ wire [30:0] _T_23 = reg_bp_0_address[32] ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] _T_24 = {_T_23,reg_bp_0_address}; // @[Cat.scala 31:58]
+ wire [33:0] _T_26 = ~reg_mepc; // @[CSR.scala 1562:28]
+ wire [1:0] _T_28 = reg_misa[2] ? 2'h1 : 2'h3; // @[CSR.scala 1562:36]
+ wire [33:0] _GEN_582 = {{32'd0}, _T_28}; // @[CSR.scala 1562:31]
+ wire [33:0] _T_29 = _T_26 | _GEN_582; // @[CSR.scala 1562:31]
+ wire [33:0] _T_30 = ~_T_29; // @[CSR.scala 1562:26]
+ wire [29:0] _T_33 = _T_30[33] ? 30'h3fffffff : 30'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] _T_34 = {_T_33,_T_30}; // @[Cat.scala 31:58]
+ wire [29:0] _T_37 = reg_mtval[33] ? 30'h3fffffff : 30'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] _T_38 = {_T_37,reg_mtval}; // @[Cat.scala 31:58]
+ wire [31:0] _T_39 = {4'h4,12'h0,reg_dcsr_ebreakm,4'h0,2'h0,reg_dcsr_cause,1'h0,2'h0,reg_dcsr_step,2'h3}; // @[CSR.scala 627:27]
+ wire [33:0] _T_40 = ~reg_dpc; // @[CSR.scala 1562:28]
+ wire [33:0] _T_43 = _T_40 | _GEN_582; // @[CSR.scala 1562:31]
+ wire [33:0] _T_44 = ~_T_43; // @[CSR.scala 1562:26]
+ wire [29:0] _T_47 = _T_44[33] ? 30'h3fffffff : 30'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] _T_48 = {_T_47,_T_44}; // @[Cat.scala 31:58]
+ wire [7:0] _T_49 = {reg_pmp_0_cfg_l,2'h0,reg_pmp_0_cfg_a,reg_pmp_0_cfg_x,reg_pmp_0_cfg_w,reg_pmp_0_cfg_r}; // @[package.scala 36:38]
+ wire [7:0] _T_51 = {reg_pmp_2_cfg_l,2'h0,reg_pmp_2_cfg_a,reg_pmp_2_cfg_x,reg_pmp_2_cfg_w,reg_pmp_2_cfg_r}; // @[package.scala 36:38]
+ wire [7:0] _T_53 = {reg_pmp_4_cfg_l,2'h0,reg_pmp_4_cfg_a,reg_pmp_4_cfg_x,reg_pmp_4_cfg_w,reg_pmp_4_cfg_r}; // @[package.scala 36:38]
+ wire [7:0] _T_55 = {reg_pmp_6_cfg_l,2'h0,reg_pmp_6_cfg_a,reg_pmp_6_cfg_x,reg_pmp_6_cfg_w,reg_pmp_6_cfg_r}; // @[package.scala 36:38]
+ wire [15:0] lo_lo_6 = {reg_pmp_1_cfg_l,2'h0,reg_pmp_1_cfg_a,reg_pmp_1_cfg_x,reg_pmp_1_cfg_w,reg_pmp_1_cfg_r,_T_49}; // @[Cat.scala 31:58]
+ wire [31:0] lo_15 = {reg_pmp_3_cfg_l,2'h0,reg_pmp_3_cfg_a,reg_pmp_3_cfg_x,reg_pmp_3_cfg_w,reg_pmp_3_cfg_r,_T_51,
+ lo_lo_6}; // @[Cat.scala 31:58]
+ wire [15:0] hi_lo_6 = {reg_pmp_5_cfg_l,2'h0,reg_pmp_5_cfg_a,reg_pmp_5_cfg_x,reg_pmp_5_cfg_w,reg_pmp_5_cfg_r,_T_53}; // @[Cat.scala 31:58]
+ wire [63:0] _T_57 = {reg_pmp_7_cfg_l,2'h0,reg_pmp_7_cfg_a,reg_pmp_7_cfg_x,reg_pmp_7_cfg_w,reg_pmp_7_cfg_r,_T_55,
+ hi_lo_6,lo_15}; // @[Cat.scala 31:58]
+ reg [63:0] reg_custom_0; // @[CSR.scala 750:43]
+ wire [12:0] addr = {io_status_v,io_rw_addr}; // @[Cat.scala 31:58]
+ wire [12:0] _decoded_T = addr & 13'h413; // @[Decode.scala 14:65]
+ wire [12:0] _decoded_T_2 = addr & 13'h453; // @[Decode.scala 14:65]
+ wire decoded_1 = _decoded_T_2 == 13'h401; // @[Decode.scala 14:121]
+ wire decoded_2 = _decoded_T == 13'h402; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_8 = addr & 13'h865; // @[Decode.scala 14:65]
+ wire decoded_4 = _decoded_T_8 == 13'h1; // @[Decode.scala 14:121]
+ wire decoded_5 = _decoded_T_8 == 13'h0; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_12 = addr & 13'h825; // @[Decode.scala 14:65]
+ wire decoded_6 = _decoded_T_12 == 13'h5; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_14 = addr & 13'h44; // @[Decode.scala 14:65]
+ wire decoded_7 = _decoded_T_14 == 13'h44; // @[Decode.scala 14:121]
+ wire decoded_8 = _decoded_T_8 == 13'h4; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_18 = addr & 13'h47; // @[Decode.scala 14:65]
+ wire decoded_9 = _decoded_T_18 == 13'h40; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_20 = addr & 13'h443; // @[Decode.scala 14:65]
+ wire decoded_10 = _decoded_T_20 == 13'h41; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_22 = addr & 13'h823; // @[Decode.scala 14:65]
+ wire decoded_11 = _decoded_T_22 == 13'h3; // @[Decode.scala 14:121]
+ wire decoded_12 = _decoded_T_22 == 13'h2; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_26 = addr & 13'h483; // @[Decode.scala 14:65]
+ wire decoded_13 = _decoded_T_26 == 13'h400; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_28 = addr & 13'hc13; // @[Decode.scala 14:65]
+ wire decoded_14 = _decoded_T_28 == 13'h410; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_30 = addr & 13'hc11; // @[Decode.scala 14:65]
+ wire decoded_15 = _decoded_T_30 == 13'h411; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_32 = addr & 13'hc12; // @[Decode.scala 14:65]
+ wire decoded_16 = _decoded_T_32 == 13'h412; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_34 = addr & 13'hbe; // @[Decode.scala 14:65]
+ wire decoded_17 = _decoded_T_34 == 13'h20; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_36 = addr & 13'h81e; // @[Decode.scala 14:65]
+ wire decoded_18 = _decoded_T_36 == 13'h800; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_38 = addr & 13'hdf; // @[Decode.scala 14:65]
+ wire decoded_19 = _decoded_T_38 == 13'h2; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_156 = addr & 13'h492; // @[Decode.scala 14:65]
+ wire decoded_78 = _decoded_T_156 == 13'h80; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_160 = addr & 13'h49f; // @[Decode.scala 14:65]
+ wire decoded_80 = _decoded_T_160 == 13'h90; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_162 = addr & 13'h48f; // @[Decode.scala 14:65]
+ wire decoded_81 = _decoded_T_162 == 13'h81; // @[Decode.scala 14:121]
+ wire decoded_82 = _decoded_T_160 == 13'h92; // @[Decode.scala 14:121]
+ wire decoded_83 = _decoded_T_162 == 13'h83; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_168 = addr & 13'h8f; // @[Decode.scala 14:65]
+ wire decoded_84 = _decoded_T_168 == 13'h84; // @[Decode.scala 14:121]
+ wire decoded_85 = _decoded_T_168 == 13'h85; // @[Decode.scala 14:121]
+ wire decoded_86 = _decoded_T_168 == 13'h86; // @[Decode.scala 14:121]
+ wire decoded_87 = _decoded_T_168 == 13'h87; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_192 = addr & 13'hc20; // @[Decode.scala 14:65]
+ wire decoded_96 = _decoded_T_192 == 13'h400; // @[Decode.scala 14:121]
+ wire [12:0] _decoded_T_194 = addr & 13'h485; // @[Decode.scala 14:65]
+ wire decoded_97 = _decoded_T_194 == 13'h400; // @[Decode.scala 14:121]
+ wire decoded_99 = _decoded_T_26 == 13'h403; // @[Decode.scala 14:121]
+ wire [63:0] _wdata_T_1 = io_rw_cmd[1] ? io_rw_rdata : 64'h0; // @[CSR.scala 1540:9]
+ wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata; // @[CSR.scala 1540:34]
+ wire [63:0] _wdata_T_5 = &io_rw_cmd[1:0] ? io_rw_wdata : 64'h0; // @[CSR.scala 1540:49]
+ wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala 1540:45]
+ wire [63:0] wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala 1540:43]
+ wire system_insn = io_rw_cmd == 3'h4; // @[CSR.scala 813:31]
+ wire [31:0] _T_167 = {io_rw_addr, 20'h0}; // @[CSR.scala 829:28]
+ wire [31:0] _T_168 = _T_167 & 32'h20100000; // @[Decode.scala 14:65]
+ wire _T_169 = _T_168 == 32'h0; // @[Decode.scala 14:121]
+ wire [31:0] _T_171 = _T_167 & 32'h10100000; // @[Decode.scala 14:65]
+ wire _T_172 = _T_171 == 32'h100000; // @[Decode.scala 14:121]
+ wire [31:0] _T_174 = _T_167 & 32'h20400000; // @[Decode.scala 14:65]
+ wire _T_175 = _T_174 == 32'h20000000; // @[Decode.scala 14:121]
+ wire [31:0] _T_177 = _T_167 & 32'h20200000; // @[Decode.scala 14:65]
+ wire _T_178 = _T_177 == 32'h20000000; // @[Decode.scala 14:121]
+ wire [31:0] _T_180 = _T_167 & 32'h30000000; // @[Decode.scala 14:65]
+ wire _T_181 = _T_180 == 32'h10000000; // @[Decode.scala 14:121]
+ wire insn_call = system_insn & _T_169; // @[CSR.scala 829:95]
+ wire insn_break = system_insn & _T_172; // @[CSR.scala 829:95]
+ wire insn_ret = system_insn & _T_175; // @[CSR.scala 829:95]
+ wire insn_cease = system_insn & _T_178; // @[CSR.scala 829:95]
+ wire insn_wfi = system_insn & _T_181; // @[CSR.scala 829:95]
+ wire [11:0] addr_1 = io_decode_0_inst[31:20]; // @[CSR.scala 832:27]
+ wire [31:0] _T_198 = io_decode_0_inst & 32'h20400000; // @[Decode.scala 14:65]
+ wire is_ret = _T_198 == 32'h20000000; // @[Decode.scala 14:121]
+ wire _csr_exists_T_15 = addr_1 == 12'h7b1; // @[CSR.scala 834:93]
+ wire _csr_exists_T_114 = addr_1 == 12'h7a0 | addr_1 == 12'h7a1 | addr_1 == 12'h7a2 | addr_1 == 12'h7a3 | addr_1 == 12'h301
+ | addr_1 == 12'h300 | addr_1 == 12'h305 | addr_1 == 12'h344 | addr_1 == 12'h304 | addr_1 == 12'h340 | addr_1 == 12'h341
+ | addr_1 == 12'h343 | addr_1 == 12'h342 | addr_1 == 12'hf14 | addr_1 == 12'h7b0 | _csr_exists_T_15; // @[CSR.scala 834:109]
+ wire _csr_exists_T_129 = _csr_exists_T_114 | addr_1 == 12'h7b2 | addr_1 == 12'h320 | addr_1 == 12'hb00 | addr_1 == 12'hb02
+ | addr_1 == 12'h323 | addr_1 == 12'hb03 | addr_1 == 12'h324 | addr_1 == 12'hb04 | addr_1 == 12'h325 | addr_1 == 12'hb05
+ | addr_1 == 12'h326 | addr_1 == 12'hb06 | addr_1 == 12'h327 | addr_1 == 12'hb07 | addr_1 == 12'h328; // @[CSR.scala 834:109]
+ wire _csr_exists_T_144 = _csr_exists_T_129 | addr_1 == 12'hb08 | addr_1 == 12'h329 | addr_1 == 12'hb09 | addr_1 == 12'h32a
+ | addr_1 == 12'hb0a | addr_1 == 12'h32b | addr_1 == 12'hb0b | addr_1 == 12'h32c | addr_1 == 12'hb0c | addr_1 == 12'h32d
+ | addr_1 == 12'hb0d | addr_1 == 12'h32e | addr_1 == 12'hb0e | addr_1 == 12'h32f | addr_1 == 12'hb0f; // @[CSR.scala 834:109]
+ wire _csr_exists_T_159 = _csr_exists_T_144 | addr_1 == 12'h330 | addr_1 == 12'hb10 | addr_1 == 12'h331 | addr_1 == 12'hb11
+ | addr_1 == 12'h332 | addr_1 == 12'hb12 | addr_1 == 12'h333 | addr_1 == 12'hb13 | addr_1 == 12'h334 | addr_1 == 12'hb14
+ | addr_1 == 12'h335 | addr_1 == 12'hb15 | addr_1 == 12'h336 | addr_1 == 12'hb16 | addr_1 == 12'h337; // @[CSR.scala 834:109]
+ wire _csr_exists_T_174 = _csr_exists_T_159 | addr_1 == 12'hb17 | addr_1 == 12'h338 | addr_1 == 12'hb18 | addr_1 == 12'h339
+ | addr_1 == 12'hb19 | addr_1 == 12'h33a | addr_1 == 12'hb1a | addr_1 == 12'h33b | addr_1 == 12'hb1b | addr_1 == 12'h33c
+ | addr_1 == 12'hb1c | addr_1 == 12'h33d | addr_1 == 12'hb1d | addr_1 == 12'h33e | addr_1 == 12'hb1e; // @[CSR.scala 834:109]
+ wire _csr_exists_T_189 = _csr_exists_T_174 | addr_1 == 12'h33f | addr_1 == 12'hb1f | addr_1 == 12'h3a0 | addr_1 == 12'h3a2
+ | addr_1 == 12'h3b0 | addr_1 == 12'h3b1 | addr_1 == 12'h3b2 | addr_1 == 12'h3b3 | addr_1 == 12'h3b4 | addr_1 == 12'h3b5
+ | addr_1 == 12'h3b6 | addr_1 == 12'h3b7 | addr_1 == 12'h3b8 | addr_1 == 12'h3b9 | addr_1 == 12'h3ba; // @[CSR.scala 834:109]
+ wire csr_exists = _csr_exists_T_189 | addr_1 == 12'h3bb | addr_1 == 12'h3bc | addr_1 == 12'h3bd | addr_1 == 12'h3be
+ | addr_1 == 12'h3bf | addr_1 == 12'h7c1 | addr_1 == 12'hf12 | addr_1 == 12'hf11 | addr_1 == 12'hf13; // @[CSR.scala 834:109]
+ wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala 858:7]
+ wire [11:0] _io_decode_0_read_illegal_T_12 = addr_1 & 12'hc10; // @[Decode.scala 14:65]
+ wire _io_decode_0_read_illegal_T_13 = _io_decode_0_read_illegal_T_12 == 12'h410; // @[Decode.scala 14:121]
+ wire _io_decode_0_read_illegal_T_16 = ~reg_debug; // @[CSR.scala 861:45]
+ wire _io_decode_0_read_illegal_T_17 = _io_decode_0_read_illegal_T_13 & ~reg_debug; // @[CSR.scala 861:42]
+ wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_1 | _io_decode_0_read_illegal_T_17; // @[CSR.scala 860:36]
+ wire _io_decode_0_read_illegal_T_21 = io_decode_0_fp_csr & io_decode_0_fp_illegal; // @[CSR.scala 863:21]
+ wire [11:0] io_decode_0_write_flush_addr_m = addr_1 | 12'h300; // @[CSR.scala 866:25]
+ wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause; // @[CSR.scala 894:14]
+ wire [63:0] cause = insn_call ? 64'hb : _cause_T_5; // @[CSR.scala 893:8]
+ wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala 895:25]
+ wire _causeIsDebugInt_T_1 = cause_lsbs == 8'he; // @[CSR.scala 896:53]
+ wire causeIsDebugInt = cause[63] & cause_lsbs == 8'he; // @[CSR.scala 896:39]
+ wire _causeIsDebugTrigger_T_1 = ~cause[63]; // @[CSR.scala 897:29]
+ wire causeIsDebugTrigger = ~cause[63] & _causeIsDebugInt_T_1; // @[CSR.scala 897:44]
+ wire [3:0] _causeIsDebugBreak_T_3 = {reg_dcsr_ebreakm,1'h0,2'h0}; // @[Cat.scala 31:58]
+ wire [3:0] _causeIsDebugBreak_T_4 = {{3'd0}, _causeIsDebugBreak_T_3[3]}; // @[CSR.scala 898:134]
+ wire causeIsDebugBreak = _causeIsDebugTrigger_T_1 & insn_break & _causeIsDebugBreak_T_4[0]; // @[CSR.scala 898:56]
+ wire trapToDebug = reg_singleStepped | causeIsDebugInt | causeIsDebugTrigger | causeIsDebugBreak | reg_debug; // @[CSR.scala 899:123]
+ wire [11:0] _debugTVec_T = insn_break ? 12'h800 : 12'h808; // @[CSR.scala 902:37]
+ wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala 902:22]
+ wire [7:0] notDebugTVec_interruptOffset = {cause[5:0], 2'h0}; // @[CSR.scala 912:59]
+ wire [63:0] notDebugTVec_interruptVec = {read_mtvec[63:8],notDebugTVec_interruptOffset}; // @[Cat.scala 31:58]
+ wire notDebugTVec_doVector = read_mtvec[0] & cause[63] & cause_lsbs[7:6] == 2'h0; // @[CSR.scala 914:55]
+ wire [63:0] _notDebugTVec_T_1 = {read_mtvec[63:2], 2'h0}; // @[CSR.scala 915:56]
+ wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala 915:8]
+ wire [63:0] tvec = trapToDebug ? {{52'd0}, debugTVec} : notDebugTVec; // @[CSR.scala 928:17]
+ wire _io_eret_T = insn_call | insn_break; // @[CSR.scala 933:24]
+ wire exception = _io_eret_T | io_exception; // @[CSR.scala 953:43]
+ wire [1:0] _T_209 = insn_ret + insn_call; // @[Bitwise.scala 48:55]
+ wire [1:0] _T_211 = insn_break + io_exception; // @[Bitwise.scala 48:55]
+ wire [2:0] _T_213 = _T_209 + _T_211; // @[Bitwise.scala 48:55]
+ wire _T_217 = ~reset; // @[CSR.scala 954:9]
+ wire _GEN_48 = insn_wfi & _io_interrupt_T & _io_decode_0_read_illegal_T_16 | reg_wfi; // @[CSR.scala 538:50 956:{51,61}]
+ wire _GEN_50 = io_retire | exception | reg_singleStepped; // @[CSR.scala 453:30 960:{36,56}]
+ wire [33:0] _epc_T = ~io_pc; // @[CSR.scala 1561:28]
+ wire [33:0] _epc_T_1 = _epc_T | 34'h1; // @[CSR.scala 1561:31]
+ wire [33:0] epc = ~_epc_T_1; // @[CSR.scala 1561:26]
+ wire [1:0] _reg_dcsr_cause_T = causeIsDebugTrigger ? 2'h2 : 2'h1; // @[CSR.scala 973:86]
+ wire [1:0] _reg_dcsr_cause_T_1 = causeIsDebugInt ? 2'h3 : _reg_dcsr_cause_T; // @[CSR.scala 973:56]
+ wire [2:0] _reg_dcsr_cause_T_2 = reg_singleStepped ? 3'h4 : {{1'd0}, _reg_dcsr_cause_T_1}; // @[CSR.scala 973:30]
+ wire _GEN_53 = _io_decode_0_read_illegal_T_16 | reg_debug; // @[CSR.scala 969:25 971:19 449:22]
+ wire [33:0] _GEN_54 = _io_decode_0_read_illegal_T_16 ? epc : reg_dpc; // @[CSR.scala 969:25 972:17 450:20]
+ wire [1:0] _GEN_75 = {{1'd0}, reg_mstatus_spp}; // @[CSR.scala 1007:23 369:24 997:35]
+ wire _GEN_147 = trapToDebug ? _GEN_53 : reg_debug; // @[CSR.scala 449:22 968:24]
+ wire [33:0] _GEN_148 = trapToDebug ? _GEN_54 : reg_dpc; // @[CSR.scala 450:20 968:24]
+ wire [1:0] _GEN_172 = trapToDebug ? {{1'd0}, reg_mstatus_spp} : _GEN_75; // @[CSR.scala 369:24 968:24]
+ wire [33:0] _GEN_176 = trapToDebug ? reg_mepc : epc; // @[CSR.scala 472:21 968:24]
+ wire [63:0] _GEN_177 = trapToDebug ? reg_mcause : cause; // @[CSR.scala 968:24 473:27]
+ wire [33:0] _GEN_178 = trapToDebug ? reg_mtval : io_tval; // @[CSR.scala 474:22 968:24]
+ wire _GEN_180 = trapToDebug ? reg_mstatus_mpie : reg_mstatus_mie; // @[CSR.scala 369:24 968:24]
+ wire _GEN_182 = trapToDebug & reg_mstatus_mie; // @[CSR.scala 369:24 968:24]
+ wire _GEN_184 = exception ? _GEN_147 : reg_debug; // @[CSR.scala 967:20 449:22]
+ wire [33:0] _GEN_185 = exception ? _GEN_148 : reg_dpc; // @[CSR.scala 450:20 967:20]
+ wire [1:0] _GEN_209 = exception ? _GEN_172 : {{1'd0}, reg_mstatus_spp}; // @[CSR.scala 967:20 369:24]
+ wire [33:0] _GEN_213 = exception ? _GEN_176 : reg_mepc; // @[CSR.scala 967:20 472:21]
+ wire [63:0] _GEN_214 = exception ? _GEN_177 : reg_mcause; // @[CSR.scala 967:20 473:27]
+ wire [33:0] _GEN_215 = exception ? _GEN_178 : reg_mtval; // @[CSR.scala 967:20 474:22]
+ wire _GEN_217 = exception ? _GEN_180 : reg_mstatus_mpie; // @[CSR.scala 967:20 369:24]
+ wire _GEN_219 = exception ? _GEN_182 : reg_mstatus_mie; // @[CSR.scala 967:20 369:24]
+ wire [33:0] _GEN_241 = io_rw_addr[10] & io_rw_addr[7] ? _T_44 : _T_30; // @[CSR.scala 1064:70 1068:15]
+ wire _GEN_243 = io_rw_addr[10] & io_rw_addr[7] ? _GEN_219 : reg_mstatus_mpie; // @[CSR.scala 1064:70]
+ wire _GEN_244 = io_rw_addr[10] & io_rw_addr[7] ? _GEN_217 : 1'h1; // @[CSR.scala 1064:70]
+ wire [63:0] _GEN_268 = insn_ret ? {{30'd0}, _GEN_241} : tvec; // @[CSR.scala 1045:19 929:11]
+ wire _GEN_275 = insn_ret ? _GEN_243 : _GEN_219; // @[CSR.scala 1045:19]
+ wire _GEN_276 = insn_ret ? _GEN_244 : _GEN_217; // @[CSR.scala 1045:19]
+ reg io_status_cease_r; // @[Reg.scala 28:20]
+ wire _GEN_281 = insn_cease | io_status_cease_r; // @[Reg.scala 29:18 28:20 29:22]
+ wire [63:0] _io_rw_rdata_T_1 = decoded_1 ? _T_20 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_2 = decoded_2 ? _T_24 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_4 = decoded_4 ? reg_misa : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_5 = decoded_5 ? read_mstatus : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_6 = decoded_6 ? read_mtvec : 64'h0; // @[Mux.scala 27:73]
+ wire [15:0] _io_rw_rdata_T_7 = decoded_7 ? read_mip : 16'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_8 = decoded_8 ? reg_mie : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_9 = decoded_9 ? reg_mscratch : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_10 = decoded_10 ? _T_34 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_11 = decoded_11 ? _T_38 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_12 = decoded_12 ? reg_mcause : 64'h0; // @[Mux.scala 27:73]
+ wire _io_rw_rdata_T_13 = decoded_13 & io_hartid; // @[Mux.scala 27:73]
+ wire [31:0] _io_rw_rdata_T_14 = decoded_14 ? _T_39 : 32'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_15 = decoded_15 ? _T_48 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_16 = decoded_16 ? reg_dscratch : 64'h0; // @[Mux.scala 27:73]
+ wire [2:0] _io_rw_rdata_T_17 = decoded_17 ? reg_mcountinhibit : 3'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_18 = decoded_18 ? value_1 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_19 = decoded_19 ? value : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_78 = decoded_78 ? _T_57 : 64'h0; // @[Mux.scala 27:73]
+ wire [29:0] _io_rw_rdata_T_80 = decoded_80 ? reg_pmp_0_addr : 30'h0; // @[Mux.scala 27:73]
+ wire [29:0] _io_rw_rdata_T_81 = decoded_81 ? reg_pmp_1_addr : 30'h0; // @[Mux.scala 27:73]
+ wire [29:0] _io_rw_rdata_T_82 = decoded_82 ? reg_pmp_2_addr : 30'h0; // @[Mux.scala 27:73]
+ wire [29:0] _io_rw_rdata_T_83 = decoded_83 ? reg_pmp_3_addr : 30'h0; // @[Mux.scala 27:73]
+ wire [29:0] _io_rw_rdata_T_84 = decoded_84 ? reg_pmp_4_addr : 30'h0; // @[Mux.scala 27:73]
+ wire [29:0] _io_rw_rdata_T_85 = decoded_85 ? reg_pmp_5_addr : 30'h0; // @[Mux.scala 27:73]
+ wire [29:0] _io_rw_rdata_T_86 = decoded_86 ? reg_pmp_6_addr : 30'h0; // @[Mux.scala 27:73]
+ wire [29:0] _io_rw_rdata_T_87 = decoded_87 ? reg_pmp_7_addr : 30'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_96 = decoded_96 ? reg_custom_0 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_97 = decoded_97 ? 64'h1 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_99 = decoded_99 ? 64'h20181004 : 64'h0; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_101 = _io_rw_rdata_T_1 | _io_rw_rdata_T_2; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_103 = _io_rw_rdata_T_101 | _io_rw_rdata_T_4; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_104 = _io_rw_rdata_T_103 | _io_rw_rdata_T_5; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_105 = _io_rw_rdata_T_104 | _io_rw_rdata_T_6; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_588 = {{48'd0}, _io_rw_rdata_T_7}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_106 = _io_rw_rdata_T_105 | _GEN_588; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_107 = _io_rw_rdata_T_106 | _io_rw_rdata_T_8; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_108 = _io_rw_rdata_T_107 | _io_rw_rdata_T_9; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_109 = _io_rw_rdata_T_108 | _io_rw_rdata_T_10; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_110 = _io_rw_rdata_T_109 | _io_rw_rdata_T_11; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_111 = _io_rw_rdata_T_110 | _io_rw_rdata_T_12; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_589 = {{63'd0}, _io_rw_rdata_T_13}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_112 = _io_rw_rdata_T_111 | _GEN_589; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_590 = {{32'd0}, _io_rw_rdata_T_14}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_113 = _io_rw_rdata_T_112 | _GEN_590; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_114 = _io_rw_rdata_T_113 | _io_rw_rdata_T_15; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_115 = _io_rw_rdata_T_114 | _io_rw_rdata_T_16; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_591 = {{61'd0}, _io_rw_rdata_T_17}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_116 = _io_rw_rdata_T_115 | _GEN_591; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_117 = _io_rw_rdata_T_116 | _io_rw_rdata_T_18; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_118 = _io_rw_rdata_T_117 | _io_rw_rdata_T_19; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_177 = _io_rw_rdata_T_118 | _io_rw_rdata_T_78; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_592 = {{34'd0}, _io_rw_rdata_T_80}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_179 = _io_rw_rdata_T_177 | _GEN_592; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_593 = {{34'd0}, _io_rw_rdata_T_81}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_180 = _io_rw_rdata_T_179 | _GEN_593; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_594 = {{34'd0}, _io_rw_rdata_T_82}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_181 = _io_rw_rdata_T_180 | _GEN_594; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_595 = {{34'd0}, _io_rw_rdata_T_83}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_182 = _io_rw_rdata_T_181 | _GEN_595; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_596 = {{34'd0}, _io_rw_rdata_T_84}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_183 = _io_rw_rdata_T_182 | _GEN_596; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_597 = {{34'd0}, _io_rw_rdata_T_85}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_184 = _io_rw_rdata_T_183 | _GEN_597; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_598 = {{34'd0}, _io_rw_rdata_T_86}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_185 = _io_rw_rdata_T_184 | _GEN_598; // @[Mux.scala 27:73]
+ wire [63:0] _GEN_599 = {{34'd0}, _io_rw_rdata_T_87}; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_186 = _io_rw_rdata_T_185 | _GEN_599; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_195 = _io_rw_rdata_T_186 | _io_rw_rdata_T_96; // @[Mux.scala 27:73]
+ wire [63:0] _io_rw_rdata_T_196 = _io_rw_rdata_T_195 | _io_rw_rdata_T_97; // @[Mux.scala 27:73]
+ wire _T_361 = io_rw_cmd == 3'h5; // @[package.scala 15:47]
+ wire _T_362 = io_rw_cmd == 3'h6; // @[package.scala 15:47]
+ wire _T_363 = io_rw_cmd == 3'h7; // @[package.scala 15:47]
+ wire csr_wen = _T_362 | _T_363 | _T_361; // @[package.scala 72:59]
+ wire [104:0] _new_mstatus_WIRE = {{41'd0}, wdata};
+ wire new_mstatus_mie = _new_mstatus_WIRE[3]; // @[CSR.scala 1153:47]
+ wire new_mstatus_mpie = _new_mstatus_WIRE[7]; // @[CSR.scala 1153:47]
+ wire f = wdata[5]; // @[CSR.scala 1183:20]
+ wire [63:0] _reg_misa_T = ~wdata; // @[CSR.scala 1187:25]
+ wire _reg_misa_T_1 = ~f; // @[CSR.scala 1187:35]
+ wire [3:0] _reg_misa_T_2 = {_reg_misa_T_1, 3'h0}; // @[CSR.scala 1187:38]
+ wire [63:0] _GEN_600 = {{60'd0}, _reg_misa_T_2}; // @[CSR.scala 1187:32]
+ wire [63:0] _reg_misa_T_3 = _reg_misa_T | _GEN_600; // @[CSR.scala 1187:32]
+ wire [63:0] _reg_misa_T_4 = ~_reg_misa_T_3; // @[CSR.scala 1187:23]
+ wire [63:0] _reg_misa_T_5 = _reg_misa_T_4 & 64'h1005; // @[CSR.scala 1187:55]
+ wire [63:0] _reg_misa_T_7 = reg_misa & 64'hffffffffffffeffa; // @[CSR.scala 1187:73]
+ wire [63:0] _reg_misa_T_8 = _reg_misa_T_5 | _reg_misa_T_7; // @[CSR.scala 1187:62]
+ wire [63:0] _reg_mie_T = wdata & 64'h888; // @[CSR.scala 1205:59]
+ wire [63:0] _reg_mepc_T_1 = _reg_misa_T | 64'h1; // @[CSR.scala 1561:31]
+ wire [63:0] _reg_mepc_T_2 = ~_reg_mepc_T_1; // @[CSR.scala 1561:26]
+ wire [63:0] _GEN_290 = decoded_10 ? _reg_mepc_T_2 : {{30'd0}, _GEN_213}; // @[CSR.scala 1206:{40,51}]
+ wire [63:0] _GEN_292 = decoded_6 ? wdata : {{32'd0}, reg_mtvec}; // @[CSR.scala 1209:{40,52} 479:27]
+ wire [63:0] _reg_mcause_T = wdata & 64'h800000000000000f; // @[CSR.scala 1210:62]
+ wire [63:0] _GEN_294 = decoded_11 ? wdata : {{30'd0}, _GEN_215}; // @[CSR.scala 1211:{40,52}]
+ wire [63:0] _reg_mcountinhibit_T_1 = wdata & 64'hfffffffffffffffd; // @[CSR.scala 1230:76]
+ wire [63:0] _GEN_295 = decoded_17 ? _reg_mcountinhibit_T_1 : {{61'd0}, reg_mcountinhibit}; // @[CSR.scala 1230:{47,67} 547:34]
+ wire [63:0] _GEN_296 = decoded_18 ? wdata : {{57'd0}, _GEN_2}; // @[CSR.scala 1558:31 Counters.scala 65:11]
+ wire [63:0] _GEN_298 = decoded_19 ? wdata : {{57'd0}, _GEN_0}; // @[CSR.scala 1558:31 Counters.scala 65:11]
+ wire new_dcsr_step = wdata[2]; // @[CSR.scala 1246:43]
+ wire new_dcsr_ebreakm = wdata[15]; // @[CSR.scala 1246:43]
+ wire [63:0] _GEN_302 = decoded_15 ? _reg_mepc_T_2 : {{30'd0}, _GEN_185}; // @[CSR.scala 1254:{42,52}]
+ wire [63:0] _GEN_305 = decoded_2 ? wdata : {{31'd0}, reg_bp_0_address}; // @[CSR.scala 1377:{44,57} 459:19]
+ wire [63:0] _newBPC_T_2 = io_rw_cmd[1] ? _T_20 : 64'h0; // @[CSR.scala 1540:9]
+ wire [63:0] _newBPC_T_3 = _newBPC_T_2 | io_rw_wdata; // @[CSR.scala 1540:34]
+ wire [63:0] _newBPC_T_8 = _newBPC_T_3 & _wdata_T_6; // @[CSR.scala 1540:43]
+ wire newBPC_action = _newBPC_T_8[12]; // @[CSR.scala 1395:96]
+ wire newBPC_dmode = _newBPC_T_8[59]; // @[CSR.scala 1395:96]
+ wire dMode = newBPC_dmode & reg_debug; // @[CSR.scala 1396:38]
+ wire _GEN_306 = dMode & newBPC_action; // @[CSR.scala 1398:{120,51,71}]
+ wire [63:0] _GEN_322 = ~reg_bp_0_control_dmode | reg_debug ? _GEN_305 : {{31'd0}, reg_bp_0_address}; // @[CSR.scala 1376:70 459:19]
+ wire newCfg_r = wdata[0]; // @[CSR.scala 1409:46]
+ wire newCfg_w = wdata[1]; // @[CSR.scala 1409:46]
+ wire newCfg_x = wdata[2]; // @[CSR.scala 1409:46]
+ wire [1:0] newCfg_a = wdata[4:3]; // @[CSR.scala 1409:46]
+ wire newCfg_l = wdata[7]; // @[CSR.scala 1409:46]
+ wire _T_1583 = ~reg_pmp_1_cfg_a[1] & reg_pmp_1_cfg_a[0]; // @[PMP.scala 48:20]
+ wire _T_1585 = reg_pmp_0_cfg_l | reg_pmp_1_cfg_l & _T_1583; // @[PMP.scala 50:44]
+ wire [63:0] _GEN_377 = decoded_80 & ~_T_1585 ? wdata : {{34'd0}, reg_pmp_0_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
+ wire newCfg_1_r = wdata[8]; // @[CSR.scala 1409:46]
+ wire newCfg_1_w = wdata[9]; // @[CSR.scala 1409:46]
+ wire newCfg_1_x = wdata[10]; // @[CSR.scala 1409:46]
+ wire [1:0] newCfg_1_a = wdata[12:11]; // @[CSR.scala 1409:46]
+ wire newCfg_1_l = wdata[15]; // @[CSR.scala 1409:46]
+ wire _T_1593 = ~reg_pmp_2_cfg_a[1] & reg_pmp_2_cfg_a[0]; // @[PMP.scala 48:20]
+ wire _T_1595 = reg_pmp_1_cfg_l | reg_pmp_2_cfg_l & _T_1593; // @[PMP.scala 50:44]
+ wire [63:0] _GEN_384 = decoded_81 & ~_T_1595 ? wdata : {{34'd0}, reg_pmp_1_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
+ wire newCfg_2_r = wdata[16]; // @[CSR.scala 1409:46]
+ wire newCfg_2_w = wdata[17]; // @[CSR.scala 1409:46]
+ wire newCfg_2_x = wdata[18]; // @[CSR.scala 1409:46]
+ wire [1:0] newCfg_2_a = wdata[20:19]; // @[CSR.scala 1409:46]
+ wire newCfg_2_l = wdata[23]; // @[CSR.scala 1409:46]
+ wire _T_1603 = ~reg_pmp_3_cfg_a[1] & reg_pmp_3_cfg_a[0]; // @[PMP.scala 48:20]
+ wire _T_1605 = reg_pmp_2_cfg_l | reg_pmp_3_cfg_l & _T_1603; // @[PMP.scala 50:44]
+ wire [63:0] _GEN_391 = decoded_82 & ~_T_1605 ? wdata : {{34'd0}, reg_pmp_2_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
+ wire newCfg_3_r = wdata[24]; // @[CSR.scala 1409:46]
+ wire newCfg_3_w = wdata[25]; // @[CSR.scala 1409:46]
+ wire newCfg_3_x = wdata[26]; // @[CSR.scala 1409:46]
+ wire [1:0] newCfg_3_a = wdata[28:27]; // @[CSR.scala 1409:46]
+ wire newCfg_3_l = wdata[31]; // @[CSR.scala 1409:46]
+ wire _T_1613 = ~reg_pmp_4_cfg_a[1] & reg_pmp_4_cfg_a[0]; // @[PMP.scala 48:20]
+ wire _T_1615 = reg_pmp_3_cfg_l | reg_pmp_4_cfg_l & _T_1613; // @[PMP.scala 50:44]
+ wire [63:0] _GEN_398 = decoded_83 & ~_T_1615 ? wdata : {{34'd0}, reg_pmp_3_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
+ wire newCfg_4_r = wdata[32]; // @[CSR.scala 1409:46]
+ wire newCfg_4_w = wdata[33]; // @[CSR.scala 1409:46]
+ wire newCfg_4_x = wdata[34]; // @[CSR.scala 1409:46]
+ wire [1:0] newCfg_4_a = wdata[36:35]; // @[CSR.scala 1409:46]
+ wire newCfg_4_l = wdata[39]; // @[CSR.scala 1409:46]
+ wire _T_1623 = ~reg_pmp_5_cfg_a[1] & reg_pmp_5_cfg_a[0]; // @[PMP.scala 48:20]
+ wire _T_1625 = reg_pmp_4_cfg_l | reg_pmp_5_cfg_l & _T_1623; // @[PMP.scala 50:44]
+ wire [63:0] _GEN_405 = decoded_84 & ~_T_1625 ? wdata : {{34'd0}, reg_pmp_4_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
+ wire newCfg_5_r = wdata[40]; // @[CSR.scala 1409:46]
+ wire newCfg_5_w = wdata[41]; // @[CSR.scala 1409:46]
+ wire newCfg_5_x = wdata[42]; // @[CSR.scala 1409:46]
+ wire [1:0] newCfg_5_a = wdata[44:43]; // @[CSR.scala 1409:46]
+ wire newCfg_5_l = wdata[47]; // @[CSR.scala 1409:46]
+ wire _T_1633 = ~reg_pmp_6_cfg_a[1] & reg_pmp_6_cfg_a[0]; // @[PMP.scala 48:20]
+ wire _T_1635 = reg_pmp_5_cfg_l | reg_pmp_6_cfg_l & _T_1633; // @[PMP.scala 50:44]
+ wire [63:0] _GEN_412 = decoded_85 & ~_T_1635 ? wdata : {{34'd0}, reg_pmp_5_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
+ wire newCfg_6_r = wdata[48]; // @[CSR.scala 1409:46]
+ wire newCfg_6_w = wdata[49]; // @[CSR.scala 1409:46]
+ wire newCfg_6_x = wdata[50]; // @[CSR.scala 1409:46]
+ wire [1:0] newCfg_6_a = wdata[52:51]; // @[CSR.scala 1409:46]
+ wire newCfg_6_l = wdata[55]; // @[CSR.scala 1409:46]
+ wire _T_1643 = ~reg_pmp_7_cfg_a[1] & reg_pmp_7_cfg_a[0]; // @[PMP.scala 48:20]
+ wire _T_1645 = reg_pmp_6_cfg_l | reg_pmp_7_cfg_l & _T_1643; // @[PMP.scala 50:44]
+ wire [63:0] _GEN_419 = decoded_86 & ~_T_1645 ? wdata : {{34'd0}, reg_pmp_6_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
+ wire newCfg_7_r = wdata[56]; // @[CSR.scala 1409:46]
+ wire newCfg_7_w = wdata[57]; // @[CSR.scala 1409:46]
+ wire newCfg_7_x = wdata[58]; // @[CSR.scala 1409:46]
+ wire [1:0] newCfg_7_a = wdata[60:59]; // @[CSR.scala 1409:46]
+ wire newCfg_7_l = wdata[63]; // @[CSR.scala 1409:46]
+ wire _T_1655 = reg_pmp_7_cfg_l | reg_pmp_7_cfg_l & _T_1643; // @[PMP.scala 50:44]
+ wire [63:0] _GEN_426 = decoded_87 & ~_T_1655 ? wdata : {{34'd0}, reg_pmp_7_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
+ wire [63:0] _reg_custom_0_T = wdata & 64'h8; // @[CSR.scala 1424:23]
+ wire [63:0] _reg_custom_0_T_2 = reg_custom_0 & 64'hfffffffffffffff7; // @[CSR.scala 1424:38]
+ wire [63:0] _reg_custom_0_T_3 = _reg_custom_0_T | _reg_custom_0_T_2; // @[CSR.scala 1424:31]
+ wire [63:0] _GEN_440 = csr_wen ? _GEN_290 : {{30'd0}, _GEN_213}; // @[CSR.scala 1148:18]
+ wire [63:0] _GEN_442 = csr_wen ? _GEN_292 : {{32'd0}, reg_mtvec}; // @[CSR.scala 1148:18 479:27]
+ wire [63:0] _GEN_444 = csr_wen ? _GEN_294 : {{30'd0}, _GEN_215}; // @[CSR.scala 1148:18]
+ wire [63:0] _GEN_445 = csr_wen ? _GEN_295 : {{61'd0}, reg_mcountinhibit}; // @[CSR.scala 1148:18 547:34]
+ wire [63:0] _GEN_446 = csr_wen ? _GEN_296 : {{57'd0}, _GEN_2}; // @[CSR.scala 1148:18]
+ wire [63:0] _GEN_448 = csr_wen ? _GEN_298 : {{57'd0}, _GEN_0}; // @[CSR.scala 1148:18]
+ wire [63:0] _GEN_452 = csr_wen ? _GEN_302 : {{30'd0}, _GEN_185}; // @[CSR.scala 1148:18]
+ wire [63:0] _GEN_455 = csr_wen ? _GEN_322 : {{31'd0}, reg_bp_0_address}; // @[CSR.scala 1148:18 459:19]
+ wire [63:0] _GEN_493 = csr_wen ? _GEN_377 : {{34'd0}, reg_pmp_0_addr}; // @[CSR.scala 1148:18 460:20]
+ wire [63:0] _GEN_500 = csr_wen ? _GEN_384 : {{34'd0}, reg_pmp_1_addr}; // @[CSR.scala 1148:18 460:20]
+ wire [63:0] _GEN_507 = csr_wen ? _GEN_391 : {{34'd0}, reg_pmp_2_addr}; // @[CSR.scala 1148:18 460:20]
+ wire [63:0] _GEN_514 = csr_wen ? _GEN_398 : {{34'd0}, reg_pmp_3_addr}; // @[CSR.scala 1148:18 460:20]
+ wire [63:0] _GEN_521 = csr_wen ? _GEN_405 : {{34'd0}, reg_pmp_4_addr}; // @[CSR.scala 1148:18 460:20]
+ wire [63:0] _GEN_528 = csr_wen ? _GEN_412 : {{34'd0}, reg_pmp_5_addr}; // @[CSR.scala 1148:18 460:20]
+ wire [63:0] _GEN_535 = csr_wen ? _GEN_419 : {{34'd0}, reg_pmp_6_addr}; // @[CSR.scala 1148:18 460:20]
+ wire [63:0] _GEN_542 = csr_wen ? _GEN_426 : {{34'd0}, reg_pmp_7_addr}; // @[CSR.scala 1148:18 460:20]
+ assign io_rw_rdata = _io_rw_rdata_T_196 | _io_rw_rdata_T_99; // @[Mux.scala 27:73]
+ assign io_decode_0_fp_illegal = io_status_fs == 2'h0 | ~reg_misa[5]; // @[CSR.scala 850:87]
+ assign io_decode_0_fp_csr = 1'h0; // @[CSR.scala 852:19]
+ assign io_decode_0_read_illegal = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_21; // @[CSR.scala 862:68]
+ assign io_decode_0_write_illegal = &addr_1[11:10]; // @[CSR.scala 864:41]
+ assign io_decode_0_write_flush = ~(io_decode_0_write_flush_addr_m >= 12'h340 & io_decode_0_write_flush_addr_m <= 12'h343
+ ); // @[CSR.scala 867:7]
+ assign io_decode_0_system_illegal = is_ret & addr_1[10] & addr_1[7] & _io_decode_0_read_illegal_T_16; // @[CSR.scala 872:37]
+ assign io_csr_stall = reg_wfi | io_status_cease; // @[CSR.scala 1091:27]
+ assign io_eret = insn_call | insn_break | insn_ret; // @[CSR.scala 933:38]
+ assign io_singleStep = reg_dcsr_step & _io_decode_0_read_illegal_T_16; // @[CSR.scala 934:34]
+ assign io_status_debug = reg_debug; // @[CSR.scala 937:19]
+ assign io_status_cease = io_status_cease_r; // @[CSR.scala 1092:19]
+ assign io_status_wfi = reg_wfi; // @[CSR.scala 1093:17]
+ assign io_status_isa = reg_misa[31:0]; // @[CSR.scala 938:17]
+ assign io_status_dprv = 2'h3; // @[CSR.scala 941:24]
+ assign io_status_dv = 1'h0; // @[CSR.scala 942:33]
+ assign io_status_prv = 2'h3; // @[CSR.scala 935:13]
+ assign io_status_v = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_sd = &io_status_fs | &io_status_xs | &io_status_vs; // @[CSR.scala 936:58]
+ assign io_status_zero2 = 23'h0; // @[CSR.scala 935:13]
+ assign io_status_mpv = 1'h0; // @[CSR.scala 944:17]
+ assign io_status_gva = reg_mstatus_gva; // @[CSR.scala 945:17]
+ assign io_status_mbe = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_sbe = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_sxl = 2'h0; // @[CSR.scala 940:17]
+ assign io_status_uxl = 2'h0; // @[CSR.scala 939:17]
+ assign io_status_sd_rv32 = 1'h0; // @[CSR.scala 943:35]
+ assign io_status_zero1 = 8'h0; // @[CSR.scala 935:13]
+ assign io_status_tsr = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_tw = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_tvm = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_mxr = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_sum = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_mprv = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_xs = 2'h0; // @[CSR.scala 935:13]
+ assign io_status_fs = 2'h0; // @[CSR.scala 935:13]
+ assign io_status_mpp = 2'h3; // @[CSR.scala 935:13]
+ assign io_status_vs = 2'h0; // @[CSR.scala 935:13]
+ assign io_status_spp = reg_mstatus_spp; // @[CSR.scala 935:13]
+ assign io_status_mpie = reg_mstatus_mpie; // @[CSR.scala 935:13]
+ assign io_status_ube = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_spie = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_upie = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_mie = reg_mstatus_mie; // @[CSR.scala 935:13]
+ assign io_status_hie = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_sie = 1'h0; // @[CSR.scala 935:13]
+ assign io_status_uie = 1'h0; // @[CSR.scala 935:13]
+ assign io_evec = _GEN_268[33:0];
+ assign io_time = {large_1,small_1}; // @[Cat.scala 31:58]
+ assign io_interrupt = (anyInterrupt & ~io_singleStep | reg_singleStepped) & ~(reg_debug | io_status_cease); // @[CSR.scala 583:73]
+ assign io_interrupt_cause = 64'h8000000000000000 + _GEN_43; // @[CSR.scala 582:67]
+ assign io_bp_0_control_action = reg_bp_0_control_action; // @[CSR.scala 585:9]
+ assign io_bp_0_control_tmatch = reg_bp_0_control_tmatch; // @[CSR.scala 585:9]
+ assign io_bp_0_control_x = reg_bp_0_control_x; // @[CSR.scala 585:9]
+ assign io_bp_0_control_w = reg_bp_0_control_w; // @[CSR.scala 585:9]
+ assign io_bp_0_control_r = reg_bp_0_control_r; // @[CSR.scala 585:9]
+ assign io_bp_0_address = reg_bp_0_address; // @[CSR.scala 585:9]
+ assign io_pmp_0_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_0_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_0_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_0_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_0_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_0_addr = reg_pmp_0_addr; // @[PMP.scala 25:19 27:14]
+ assign io_pmp_0_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala 25:19 28:14]
+ assign io_pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala 25:19 27:14]
+ assign io_pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala 25:19 28:14]
+ assign io_pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala 25:19 27:14]
+ assign io_pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala 25:19 28:14]
+ assign io_pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala 25:19 27:14]
+ assign io_pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala 25:19 28:14]
+ assign io_pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala 25:19 27:14]
+ assign io_pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala 25:19 28:14]
+ assign io_pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala 25:19 27:14]
+ assign io_pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala 25:19 28:14]
+ assign io_pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala 25:19 27:14]
+ assign io_pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala 25:19 28:14]
+ assign io_pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala 25:19 26:13]
+ assign io_pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala 25:19 27:14]
+ assign io_pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala 25:19 28:14]
+ assign io_inhibit_cycle = reg_mcountinhibit[0]; // @[CSR.scala 548:40]
+ assign io_trace_0_valid = io_retire > 1'h0 | io_trace_0_exception; // @[CSR.scala 1519:30]
+ assign io_trace_0_iaddr = io_pc; // @[CSR.scala 1521:13]
+ assign io_trace_0_insn = io_inst_0; // @[CSR.scala 1520:12]
+ assign io_trace_0_exception = _io_eret_T | io_exception; // @[CSR.scala 953:43]
+ assign io_customCSRs_0_value = reg_custom_0; // @[CSR.scala 1098:14]
+ always @(posedge clock) begin
+ if (reset) begin // @[CSR.scala 369:24]
+ reg_mstatus_gva <= 1'h0; // @[CSR.scala 369:24]
+ end else if (exception) begin // @[CSR.scala 967:20]
+ if (!(trapToDebug)) begin // @[CSR.scala 968:24]
+ reg_mstatus_gva <= io_gva;
+ end
+ end
+ if (reset) begin // @[CSR.scala 369:24]
+ reg_mstatus_spp <= 1'h0; // @[CSR.scala 369:24]
+ end else begin
+ reg_mstatus_spp <= _GEN_209[0];
+ end
+ if (reset) begin // @[CSR.scala 369:24]
+ reg_mstatus_mpie <= 1'h0; // @[CSR.scala 369:24]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_5) begin // @[CSR.scala 1152:39]
+ reg_mstatus_mpie <= new_mstatus_mpie; // @[CSR.scala 1155:24]
+ end else begin
+ reg_mstatus_mpie <= _GEN_276;
+ end
+ end else begin
+ reg_mstatus_mpie <= _GEN_276;
+ end
+ if (reset) begin // @[CSR.scala 369:24]
+ reg_mstatus_mie <= 1'h0; // @[CSR.scala 369:24]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_5) begin // @[CSR.scala 1152:39]
+ reg_mstatus_mie <= new_mstatus_mie; // @[CSR.scala 1154:23]
+ end else begin
+ reg_mstatus_mie <= _GEN_275;
+ end
+ end else begin
+ reg_mstatus_mie <= _GEN_275;
+ end
+ if (reset) begin // @[CSR.scala 377:21]
+ reg_dcsr_ebreakm <= 1'h0; // @[CSR.scala 377:21]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_14) begin // @[CSR.scala 1245:38]
+ reg_dcsr_ebreakm <= new_dcsr_ebreakm; // @[CSR.scala 1248:26]
+ end
+ end
+ if (reset) begin // @[CSR.scala 377:21]
+ reg_dcsr_cause <= 3'h0; // @[CSR.scala 377:21]
+ end else if (exception) begin // @[CSR.scala 967:20]
+ if (trapToDebug) begin // @[CSR.scala 968:24]
+ if (_io_decode_0_read_illegal_T_16) begin // @[CSR.scala 969:25]
+ reg_dcsr_cause <= _reg_dcsr_cause_T_2; // @[CSR.scala 973:24]
+ end
+ end
+ end
+ if (reset) begin // @[CSR.scala 377:21]
+ reg_dcsr_step <= 1'h0; // @[CSR.scala 377:21]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_14) begin // @[CSR.scala 1245:38]
+ reg_dcsr_step <= new_dcsr_step; // @[CSR.scala 1247:23]
+ end
+ end
+ if (reset) begin // @[CSR.scala 449:22]
+ reg_debug <= 1'h0; // @[CSR.scala 449:22]
+ end else if (insn_ret) begin // @[CSR.scala 1045:19]
+ if (io_rw_addr[10] & io_rw_addr[7]) begin // @[CSR.scala 1064:70]
+ reg_debug <= 1'h0; // @[CSR.scala 1067:17]
+ end else begin
+ reg_debug <= _GEN_184;
+ end
+ end else begin
+ reg_debug <= _GEN_184;
+ end
+ reg_dpc <= _GEN_452[33:0];
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_16) begin // @[CSR.scala 1255:42]
+ reg_dscratch <= wdata; // @[CSR.scala 1255:57]
+ end
+ end
+ if (_io_interrupt_T) begin // @[CSR.scala 961:25]
+ reg_singleStepped <= 1'h0; // @[CSR.scala 961:45]
+ end else begin
+ reg_singleStepped <= _GEN_50;
+ end
+ if (reset) begin // @[CSR.scala 1497:18]
+ reg_bp_0_control_dmode <= 1'h0; // @[CSR.scala 1499:17]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (~reg_bp_0_control_dmode | reg_debug) begin // @[CSR.scala 1376:70]
+ if (decoded_1) begin // @[CSR.scala 1388:44]
+ reg_bp_0_control_dmode <= dMode; // @[CSR.scala 1397:30]
+ end
+ end
+ end
+ if (reset) begin // @[CSR.scala 1497:18]
+ reg_bp_0_control_action <= 1'h0; // @[CSR.scala 1498:18]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (~reg_bp_0_control_dmode | reg_debug) begin // @[CSR.scala 1376:70]
+ if (decoded_1) begin // @[CSR.scala 1388:44]
+ reg_bp_0_control_action <= _GEN_306;
+ end
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (~reg_bp_0_control_dmode | reg_debug) begin // @[CSR.scala 1376:70]
+ if (decoded_1) begin // @[CSR.scala 1388:44]
+ reg_bp_0_control_tmatch <= wdata[8:7]; // @[CSR.scala 1389:24]
+ end
+ end
+ end
+ if (reset) begin // @[CSR.scala 1497:18]
+ reg_bp_0_control_x <= 1'h0; // @[CSR.scala 1503:13]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (~reg_bp_0_control_dmode | reg_debug) begin // @[CSR.scala 1376:70]
+ if (decoded_1) begin // @[CSR.scala 1388:44]
+ reg_bp_0_control_x <= wdata[2]; // @[CSR.scala 1389:24]
+ end
+ end
+ end
+ if (reset) begin // @[CSR.scala 1497:18]
+ reg_bp_0_control_w <= 1'h0; // @[CSR.scala 1502:13]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (~reg_bp_0_control_dmode | reg_debug) begin // @[CSR.scala 1376:70]
+ if (decoded_1) begin // @[CSR.scala 1388:44]
+ reg_bp_0_control_w <= wdata[1]; // @[CSR.scala 1389:24]
+ end
+ end
+ end
+ if (reset) begin // @[CSR.scala 1497:18]
+ reg_bp_0_control_r <= 1'h0; // @[CSR.scala 1501:13]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (~reg_bp_0_control_dmode | reg_debug) begin // @[CSR.scala 1376:70]
+ if (decoded_1) begin // @[CSR.scala 1388:44]
+ reg_bp_0_control_r <= wdata[0]; // @[CSR.scala 1389:24]
+ end
+ end
+ end
+ reg_bp_0_address <= _GEN_455[32:0];
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_0_cfg_l <= 1'h0; // @[PMP.scala 39:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_0_cfg_l <= newCfg_l; // @[CSR.scala 1410:17]
+ end
+ end
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_0_cfg_a <= 2'h0; // @[PMP.scala 38:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_0_cfg_a <= newCfg_a; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_0_cfg_x <= newCfg_x; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_0_cfg_w <= newCfg_w & newCfg_r; // @[CSR.scala 1412:19]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_0_cfg_r <= newCfg_r; // @[CSR.scala 1410:17]
+ end
+ end
+ reg_pmp_0_addr <= _GEN_493[29:0];
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_1_cfg_l <= 1'h0; // @[PMP.scala 39:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_1_cfg_l <= newCfg_1_l; // @[CSR.scala 1410:17]
+ end
+ end
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_1_cfg_a <= 2'h0; // @[PMP.scala 38:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_1_cfg_a <= newCfg_1_a; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_1_cfg_x <= newCfg_1_x; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_1_cfg_w <= newCfg_1_w & newCfg_1_r; // @[CSR.scala 1412:19]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_1_cfg_r <= newCfg_1_r; // @[CSR.scala 1410:17]
+ end
+ end
+ reg_pmp_1_addr <= _GEN_500[29:0];
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_2_cfg_l <= 1'h0; // @[PMP.scala 39:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_2_cfg_l <= newCfg_2_l; // @[CSR.scala 1410:17]
+ end
+ end
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_2_cfg_a <= 2'h0; // @[PMP.scala 38:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_2_cfg_a <= newCfg_2_a; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_2_cfg_x <= newCfg_2_x; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_2_cfg_w <= newCfg_2_w & newCfg_2_r; // @[CSR.scala 1412:19]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_2_cfg_r <= newCfg_2_r; // @[CSR.scala 1410:17]
+ end
+ end
+ reg_pmp_2_addr <= _GEN_507[29:0];
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_3_cfg_l <= 1'h0; // @[PMP.scala 39:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_3_cfg_l <= newCfg_3_l; // @[CSR.scala 1410:17]
+ end
+ end
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_3_cfg_a <= 2'h0; // @[PMP.scala 38:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_3_cfg_a <= newCfg_3_a; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_3_cfg_x <= newCfg_3_x; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_3_cfg_w <= newCfg_3_w & newCfg_3_r; // @[CSR.scala 1412:19]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_3_cfg_r <= newCfg_3_r; // @[CSR.scala 1410:17]
+ end
+ end
+ reg_pmp_3_addr <= _GEN_514[29:0];
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_4_cfg_l <= 1'h0; // @[PMP.scala 39:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_4_cfg_l <= newCfg_4_l; // @[CSR.scala 1410:17]
+ end
+ end
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_4_cfg_a <= 2'h0; // @[PMP.scala 38:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_4_cfg_a <= newCfg_4_a; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_4_cfg_x <= newCfg_4_x; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_4_cfg_w <= newCfg_4_w & newCfg_4_r; // @[CSR.scala 1412:19]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_4_cfg_r <= newCfg_4_r; // @[CSR.scala 1410:17]
+ end
+ end
+ reg_pmp_4_addr <= _GEN_521[29:0];
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_5_cfg_l <= 1'h0; // @[PMP.scala 39:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_5_cfg_l <= newCfg_5_l; // @[CSR.scala 1410:17]
+ end
+ end
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_5_cfg_a <= 2'h0; // @[PMP.scala 38:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_5_cfg_a <= newCfg_5_a; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_5_cfg_x <= newCfg_5_x; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_5_cfg_w <= newCfg_5_w & newCfg_5_r; // @[CSR.scala 1412:19]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_5_cfg_r <= newCfg_5_r; // @[CSR.scala 1410:17]
+ end
+ end
+ reg_pmp_5_addr <= _GEN_528[29:0];
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_6_cfg_l <= 1'h0; // @[PMP.scala 39:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_6_cfg_l <= newCfg_6_l; // @[CSR.scala 1410:17]
+ end
+ end
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_6_cfg_a <= 2'h0; // @[PMP.scala 38:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_6_cfg_a <= newCfg_6_a; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_6_cfg_x <= newCfg_6_x; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_6_cfg_w <= newCfg_6_w & newCfg_6_r; // @[CSR.scala 1412:19]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_6_cfg_r <= newCfg_6_r; // @[CSR.scala 1410:17]
+ end
+ end
+ reg_pmp_6_addr <= _GEN_535[29:0];
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_7_cfg_l <= 1'h0; // @[PMP.scala 39:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_7_cfg_l <= newCfg_7_l; // @[CSR.scala 1410:17]
+ end
+ end
+ if (reset) begin // @[CSR.scala 1514:18]
+ reg_pmp_7_cfg_a <= 2'h0; // @[PMP.scala 38:11]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_7_cfg_a <= newCfg_7_a; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_7_cfg_x <= newCfg_7_x; // @[CSR.scala 1410:17]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_7_cfg_w <= newCfg_7_w & newCfg_7_r; // @[CSR.scala 1412:19]
+ end
+ end
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_78 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
+ reg_pmp_7_cfg_r <= newCfg_7_r; // @[CSR.scala 1410:17]
+ end
+ end
+ reg_pmp_7_addr <= _GEN_542[29:0];
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_8) begin // @[CSR.scala 1205:40]
+ reg_mie <= _reg_mie_T; // @[CSR.scala 1205:50]
+ end
+ end
+ reg_mepc <= _GEN_440[33:0];
+ if (reset) begin // @[CSR.scala 473:27]
+ reg_mcause <= 64'h0; // @[CSR.scala 473:27]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_12) begin // @[CSR.scala 1210:40]
+ reg_mcause <= _reg_mcause_T; // @[CSR.scala 1210:53]
+ end else begin
+ reg_mcause <= _GEN_214;
+ end
+ end else begin
+ reg_mcause <= _GEN_214;
+ end
+ reg_mtval <= _GEN_444[33:0];
+ if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_9) begin // @[CSR.scala 1207:40]
+ reg_mscratch <= wdata; // @[CSR.scala 1207:55]
+ end
+ end
+ if (reset) begin // @[CSR.scala 479:27]
+ reg_mtvec <= 32'h0; // @[CSR.scala 479:27]
+ end else begin
+ reg_mtvec <= _GEN_442[31:0];
+ end
+ if (reset) begin // @[CSR.scala 547:34]
+ reg_mcountinhibit <= 3'h0; // @[CSR.scala 547:34]
+ end else begin
+ reg_mcountinhibit <= _GEN_445[2:0];
+ end
+ if (reset) begin // @[Counters.scala 45:37]
+ small_ <= 6'h0; // @[Counters.scala 45:37]
+ end else begin
+ small_ <= _GEN_448[5:0];
+ end
+ if (reset) begin // @[Counters.scala 50:27]
+ large_ <= 58'h0; // @[Counters.scala 50:27]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_19) begin // @[CSR.scala 1558:31]
+ large_ <= wdata[63:6]; // @[Counters.scala 66:23]
+ end else begin
+ large_ <= _GEN_1;
+ end
+ end else begin
+ large_ <= _GEN_1;
+ end
+ if (reset) begin // @[CSR.scala 605:21]
+ reg_misa <= 64'h8000000000801105; // @[CSR.scala 605:21]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_4) begin // @[CSR.scala 1181:36]
+ if (~io_pc[1] | wdata[2]) begin // @[CSR.scala 1185:64]
+ reg_misa <= _reg_misa_T_8; // @[CSR.scala 1187:20]
+ end
+ end
+ end
+ if (reset) begin // @[CSR.scala 750:43]
+ reg_custom_0 <= 64'h8; // @[CSR.scala 750:43]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_96) begin // @[CSR.scala 1423:35]
+ reg_custom_0 <= _reg_custom_0_T_3; // @[CSR.scala 1424:13]
+ end
+ end
+ if (reset) begin // @[Reg.scala 28:20]
+ io_status_cease_r <= 1'h0; // @[Reg.scala 28:20]
+ end else begin
+ io_status_cease_r <= _GEN_281;
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_213 <= 3'h1) & ~reset) begin
+ $fatal; // @[CSR.scala 954:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(_T_213 <= 3'h1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:954 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, \"these conditions must be mutually exclusive\")\n"
+ ); // @[CSR.scala 954:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~reg_singleStepped | ~io_retire) & _T_217) begin
+ $fatal; // @[CSR.scala 963:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_217 & ~(~reg_singleStepped | ~io_retire)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at CSR.scala:963 assert(!reg_singleStepped || io.retire === UInt(0))\n"); // @[CSR.scala 963:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+ always @(posedge io_ungated_clock) begin
+ if (reset) begin // @[CSR.scala 538:50]
+ reg_wfi <= 1'h0; // @[CSR.scala 538:50]
+ end else if (|pending_interrupts | io_interrupts_debug | exception) begin // @[CSR.scala 957:69]
+ reg_wfi <= 1'h0; // @[CSR.scala 957:79]
+ end else begin
+ reg_wfi <= _GEN_48;
+ end
+ if (reset) begin // @[Counters.scala 45:37]
+ small_1 <= 6'h0; // @[Counters.scala 45:37]
+ end else begin
+ small_1 <= _GEN_446[5:0];
+ end
+ if (reset) begin // @[Counters.scala 50:27]
+ large_1 <= 58'h0; // @[Counters.scala 50:27]
+ end else if (csr_wen) begin // @[CSR.scala 1148:18]
+ if (decoded_18) begin // @[CSR.scala 1558:31]
+ large_1 <= wdata[63:6]; // @[Counters.scala 66:23]
+ end else begin
+ large_1 <= _GEN_3;
+ end
+ end else begin
+ large_1 <= _GEN_3;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ reg_mstatus_gva = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ reg_mstatus_spp = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ reg_mstatus_mpie = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ reg_mstatus_mie = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ reg_dcsr_ebreakm = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ reg_dcsr_cause = _RAND_5[2:0];
+ _RAND_6 = {1{`RANDOM}};
+ reg_dcsr_step = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ reg_debug = _RAND_7[0:0];
+ _RAND_8 = {2{`RANDOM}};
+ reg_dpc = _RAND_8[33:0];
+ _RAND_9 = {2{`RANDOM}};
+ reg_dscratch = _RAND_9[63:0];
+ _RAND_10 = {1{`RANDOM}};
+ reg_singleStepped = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ reg_bp_0_control_dmode = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ reg_bp_0_control_action = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ reg_bp_0_control_tmatch = _RAND_13[1:0];
+ _RAND_14 = {1{`RANDOM}};
+ reg_bp_0_control_x = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ reg_bp_0_control_w = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ reg_bp_0_control_r = _RAND_16[0:0];
+ _RAND_17 = {2{`RANDOM}};
+ reg_bp_0_address = _RAND_17[32:0];
+ _RAND_18 = {1{`RANDOM}};
+ reg_pmp_0_cfg_l = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ reg_pmp_0_cfg_a = _RAND_19[1:0];
+ _RAND_20 = {1{`RANDOM}};
+ reg_pmp_0_cfg_x = _RAND_20[0:0];
+ _RAND_21 = {1{`RANDOM}};
+ reg_pmp_0_cfg_w = _RAND_21[0:0];
+ _RAND_22 = {1{`RANDOM}};
+ reg_pmp_0_cfg_r = _RAND_22[0:0];
+ _RAND_23 = {1{`RANDOM}};
+ reg_pmp_0_addr = _RAND_23[29:0];
+ _RAND_24 = {1{`RANDOM}};
+ reg_pmp_1_cfg_l = _RAND_24[0:0];
+ _RAND_25 = {1{`RANDOM}};
+ reg_pmp_1_cfg_a = _RAND_25[1:0];
+ _RAND_26 = {1{`RANDOM}};
+ reg_pmp_1_cfg_x = _RAND_26[0:0];
+ _RAND_27 = {1{`RANDOM}};
+ reg_pmp_1_cfg_w = _RAND_27[0:0];
+ _RAND_28 = {1{`RANDOM}};
+ reg_pmp_1_cfg_r = _RAND_28[0:0];
+ _RAND_29 = {1{`RANDOM}};
+ reg_pmp_1_addr = _RAND_29[29:0];
+ _RAND_30 = {1{`RANDOM}};
+ reg_pmp_2_cfg_l = _RAND_30[0:0];
+ _RAND_31 = {1{`RANDOM}};
+ reg_pmp_2_cfg_a = _RAND_31[1:0];
+ _RAND_32 = {1{`RANDOM}};
+ reg_pmp_2_cfg_x = _RAND_32[0:0];
+ _RAND_33 = {1{`RANDOM}};
+ reg_pmp_2_cfg_w = _RAND_33[0:0];
+ _RAND_34 = {1{`RANDOM}};
+ reg_pmp_2_cfg_r = _RAND_34[0:0];
+ _RAND_35 = {1{`RANDOM}};
+ reg_pmp_2_addr = _RAND_35[29:0];
+ _RAND_36 = {1{`RANDOM}};
+ reg_pmp_3_cfg_l = _RAND_36[0:0];
+ _RAND_37 = {1{`RANDOM}};
+ reg_pmp_3_cfg_a = _RAND_37[1:0];
+ _RAND_38 = {1{`RANDOM}};
+ reg_pmp_3_cfg_x = _RAND_38[0:0];
+ _RAND_39 = {1{`RANDOM}};
+ reg_pmp_3_cfg_w = _RAND_39[0:0];
+ _RAND_40 = {1{`RANDOM}};
+ reg_pmp_3_cfg_r = _RAND_40[0:0];
+ _RAND_41 = {1{`RANDOM}};
+ reg_pmp_3_addr = _RAND_41[29:0];
+ _RAND_42 = {1{`RANDOM}};
+ reg_pmp_4_cfg_l = _RAND_42[0:0];
+ _RAND_43 = {1{`RANDOM}};
+ reg_pmp_4_cfg_a = _RAND_43[1:0];
+ _RAND_44 = {1{`RANDOM}};
+ reg_pmp_4_cfg_x = _RAND_44[0:0];
+ _RAND_45 = {1{`RANDOM}};
+ reg_pmp_4_cfg_w = _RAND_45[0:0];
+ _RAND_46 = {1{`RANDOM}};
+ reg_pmp_4_cfg_r = _RAND_46[0:0];
+ _RAND_47 = {1{`RANDOM}};
+ reg_pmp_4_addr = _RAND_47[29:0];
+ _RAND_48 = {1{`RANDOM}};
+ reg_pmp_5_cfg_l = _RAND_48[0:0];
+ _RAND_49 = {1{`RANDOM}};
+ reg_pmp_5_cfg_a = _RAND_49[1:0];
+ _RAND_50 = {1{`RANDOM}};
+ reg_pmp_5_cfg_x = _RAND_50[0:0];
+ _RAND_51 = {1{`RANDOM}};
+ reg_pmp_5_cfg_w = _RAND_51[0:0];
+ _RAND_52 = {1{`RANDOM}};
+ reg_pmp_5_cfg_r = _RAND_52[0:0];
+ _RAND_53 = {1{`RANDOM}};
+ reg_pmp_5_addr = _RAND_53[29:0];
+ _RAND_54 = {1{`RANDOM}};
+ reg_pmp_6_cfg_l = _RAND_54[0:0];
+ _RAND_55 = {1{`RANDOM}};
+ reg_pmp_6_cfg_a = _RAND_55[1:0];
+ _RAND_56 = {1{`RANDOM}};
+ reg_pmp_6_cfg_x = _RAND_56[0:0];
+ _RAND_57 = {1{`RANDOM}};
+ reg_pmp_6_cfg_w = _RAND_57[0:0];
+ _RAND_58 = {1{`RANDOM}};
+ reg_pmp_6_cfg_r = _RAND_58[0:0];
+ _RAND_59 = {1{`RANDOM}};
+ reg_pmp_6_addr = _RAND_59[29:0];
+ _RAND_60 = {1{`RANDOM}};
+ reg_pmp_7_cfg_l = _RAND_60[0:0];
+ _RAND_61 = {1{`RANDOM}};
+ reg_pmp_7_cfg_a = _RAND_61[1:0];
+ _RAND_62 = {1{`RANDOM}};
+ reg_pmp_7_cfg_x = _RAND_62[0:0];
+ _RAND_63 = {1{`RANDOM}};
+ reg_pmp_7_cfg_w = _RAND_63[0:0];
+ _RAND_64 = {1{`RANDOM}};
+ reg_pmp_7_cfg_r = _RAND_64[0:0];
+ _RAND_65 = {1{`RANDOM}};
+ reg_pmp_7_addr = _RAND_65[29:0];
+ _RAND_66 = {2{`RANDOM}};
+ reg_mie = _RAND_66[63:0];
+ _RAND_67 = {2{`RANDOM}};
+ reg_mepc = _RAND_67[33:0];
+ _RAND_68 = {2{`RANDOM}};
+ reg_mcause = _RAND_68[63:0];
+ _RAND_69 = {2{`RANDOM}};
+ reg_mtval = _RAND_69[33:0];
+ _RAND_70 = {2{`RANDOM}};
+ reg_mscratch = _RAND_70[63:0];
+ _RAND_71 = {1{`RANDOM}};
+ reg_mtvec = _RAND_71[31:0];
+ _RAND_72 = {1{`RANDOM}};
+ reg_wfi = _RAND_72[0:0];
+ _RAND_73 = {1{`RANDOM}};
+ reg_mcountinhibit = _RAND_73[2:0];
+ _RAND_74 = {1{`RANDOM}};
+ small_ = _RAND_74[5:0];
+ _RAND_75 = {2{`RANDOM}};
+ large_ = _RAND_75[57:0];
+ _RAND_76 = {1{`RANDOM}};
+ small_1 = _RAND_76[5:0];
+ _RAND_77 = {2{`RANDOM}};
+ large_1 = _RAND_77[57:0];
+ _RAND_78 = {2{`RANDOM}};
+ reg_misa = _RAND_78[63:0];
+ _RAND_79 = {2{`RANDOM}};
+ reg_custom_0 = _RAND_79[63:0];
+ _RAND_80 = {1{`RANDOM}};
+ io_status_cease_r = _RAND_80[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module BreakpointUnit(
+ input io_status_debug,
+ input io_bp_0_control_action,
+ input [1:0] io_bp_0_control_tmatch,
+ input io_bp_0_control_x,
+ input io_bp_0_control_w,
+ input io_bp_0_control_r,
+ input [32:0] io_bp_0_address,
+ input [32:0] io_pc,
+ input [32:0] io_ea,
+ output io_xcpt_if,
+ output io_xcpt_ld,
+ output io_xcpt_st,
+ output io_debug_if,
+ output io_debug_ld,
+ output io_debug_st
+);
+ wire en = ~io_status_debug; // @[Breakpoint.scala 31:35]
+ wire _r_T_4 = io_ea >= io_bp_0_address ^ io_bp_0_control_tmatch[0]; // @[Breakpoint.scala 66:20]
+ wire [32:0] _r_T_5 = ~io_ea; // @[Breakpoint.scala 63:6]
+ wire _r_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0]; // @[Breakpoint.scala 60:73]
+ wire _r_T_10 = io_bp_0_control_tmatch[0] & io_bp_0_address[0] & io_bp_0_address[1]; // @[Breakpoint.scala 60:73]
+ wire _r_T_12 = io_bp_0_control_tmatch[0] & io_bp_0_address[0] & io_bp_0_address[1] & io_bp_0_address[2]; // @[Breakpoint.scala 60:73]
+ wire [3:0] _r_T_13 = {_r_T_12,_r_T_10,_r_T_8,io_bp_0_control_tmatch[0]}; // @[Cat.scala 31:58]
+ wire [32:0] _GEN_11 = {{29'd0}, _r_T_13}; // @[Breakpoint.scala 63:9]
+ wire [32:0] _r_T_14 = _r_T_5 | _GEN_11; // @[Breakpoint.scala 63:9]
+ wire [32:0] _r_T_15 = ~io_bp_0_address; // @[Breakpoint.scala 63:24]
+ wire [32:0] _r_T_24 = _r_T_15 | _GEN_11; // @[Breakpoint.scala 63:33]
+ wire _r_T_25 = _r_T_14 == _r_T_24; // @[Breakpoint.scala 63:19]
+ wire _r_T_26 = io_bp_0_control_tmatch[1] ? _r_T_4 : _r_T_25; // @[Breakpoint.scala 69:8]
+ wire r = en & io_bp_0_control_r & _r_T_26; // @[Breakpoint.scala 107:32]
+ wire w = en & io_bp_0_control_w & _r_T_26; // @[Breakpoint.scala 108:32]
+ wire _x_T_4 = io_pc >= io_bp_0_address ^ io_bp_0_control_tmatch[0]; // @[Breakpoint.scala 66:20]
+ wire [32:0] _x_T_5 = ~io_pc; // @[Breakpoint.scala 63:6]
+ wire [32:0] _x_T_14 = _x_T_5 | _GEN_11; // @[Breakpoint.scala 63:9]
+ wire _x_T_25 = _x_T_14 == _r_T_24; // @[Breakpoint.scala 63:19]
+ wire _x_T_26 = io_bp_0_control_tmatch[1] ? _x_T_4 : _x_T_25; // @[Breakpoint.scala 69:8]
+ wire x = en & io_bp_0_control_x & _x_T_26; // @[Breakpoint.scala 109:32]
+ wire _io_xcpt_ld_T = ~io_bp_0_control_action; // @[Breakpoint.scala 119:51]
+ assign io_xcpt_if = x & _io_xcpt_ld_T; // @[Breakpoint.scala 121:{27,40} 97:14]
+ assign io_xcpt_ld = r & ~io_bp_0_control_action; // @[Breakpoint.scala 119:{27,40} 98:14]
+ assign io_xcpt_st = w & _io_xcpt_ld_T; // @[Breakpoint.scala 120:{27,40} 99:14]
+ assign io_debug_if = x & io_bp_0_control_action; // @[Breakpoint.scala 100:15 121:{27,73}]
+ assign io_debug_ld = r & io_bp_0_control_action; // @[Breakpoint.scala 101:15 119:{27,73}]
+ assign io_debug_st = w & io_bp_0_control_action; // @[Breakpoint.scala 102:15 120:{27,73}]
+endmodule
+module ALU(
+ input io_dw,
+ input [3:0] io_fn,
+ input [63:0] io_in2,
+ input [63:0] io_in1,
+ output [63:0] io_out,
+ output [63:0] io_adder_out,
+ output io_cmp_out
+);
+ wire [63:0] _in2_inv_T_1 = ~io_in2; // @[ALU.scala 61:35]
+ wire [63:0] in2_inv = io_fn[3] ? _in2_inv_T_1 : io_in2; // @[ALU.scala 61:20]
+ wire [63:0] in1_xor_in2 = io_in1 ^ in2_inv; // @[ALU.scala 62:28]
+ wire [63:0] _io_adder_out_T_1 = io_in1 + in2_inv; // @[ALU.scala 63:26]
+ wire [63:0] _GEN_1 = {{63'd0}, io_fn[3]}; // @[ALU.scala 63:36]
+ wire _slt_T_7 = io_fn[1] ? io_in2[63] : io_in1[63]; // @[ALU.scala 68:8]
+ wire slt = io_in1[63] == io_in2[63] ? io_adder_out[63] : _slt_T_7; // @[ALU.scala 67:8]
+ wire _io_cmp_out_T_2 = ~io_fn[3]; // @[ALU.scala 44:26]
+ wire _io_cmp_out_T_4 = _io_cmp_out_T_2 ? in1_xor_in2 == 64'h0 : slt; // @[ALU.scala 69:41]
+ wire _T_2 = io_fn[3] & io_in1[31]; // @[ALU.scala 76:46]
+ wire [31:0] _T_4 = _T_2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 74:12]
+ wire [31:0] _T_7 = io_dw ? io_in1[63:32] : _T_4; // @[ALU.scala 77:24]
+ wire _T_10 = io_in2[5] & io_dw; // @[ALU.scala 78:33]
+ wire [5:0] shamt = {_T_10,io_in2[4:0]}; // @[Cat.scala 31:58]
+ wire [63:0] shin_r = {_T_7,io_in1[31:0]}; // @[Cat.scala 31:58]
+ wire _shin_T_2 = io_fn == 4'h5 | io_fn == 4'hb; // @[ALU.scala 81:35]
+ wire [63:0] _GEN_2 = {{32'd0}, shin_r[63:32]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_6 = _GEN_2 & 64'hffffffff; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_8 = {shin_r[31:0], 32'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shin_T_10 = _shin_T_8 & 64'hffffffff00000000; // @[Bitwise.scala 105:80]
+ wire [63:0] _shin_T_11 = _shin_T_6 | _shin_T_10; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_3 = {{16'd0}, _shin_T_11[63:16]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_16 = _GEN_3 & 64'hffff0000ffff; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_18 = {_shin_T_11[47:0], 16'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shin_T_20 = _shin_T_18 & 64'hffff0000ffff0000; // @[Bitwise.scala 105:80]
+ wire [63:0] _shin_T_21 = _shin_T_16 | _shin_T_20; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_4 = {{8'd0}, _shin_T_21[63:8]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_26 = _GEN_4 & 64'hff00ff00ff00ff; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_28 = {_shin_T_21[55:0], 8'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shin_T_30 = _shin_T_28 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 105:80]
+ wire [63:0] _shin_T_31 = _shin_T_26 | _shin_T_30; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_5 = {{4'd0}, _shin_T_31[63:4]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_36 = _GEN_5 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_38 = {_shin_T_31[59:0], 4'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shin_T_40 = _shin_T_38 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 105:80]
+ wire [63:0] _shin_T_41 = _shin_T_36 | _shin_T_40; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_6 = {{2'd0}, _shin_T_41[63:2]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_46 = _GEN_6 & 64'h3333333333333333; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_48 = {_shin_T_41[61:0], 2'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shin_T_50 = _shin_T_48 & 64'hcccccccccccccccc; // @[Bitwise.scala 105:80]
+ wire [63:0] _shin_T_51 = _shin_T_46 | _shin_T_50; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_7 = {{1'd0}, _shin_T_51[63:1]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_56 = _GEN_7 & 64'h5555555555555555; // @[Bitwise.scala 105:31]
+ wire [63:0] _shin_T_58 = {_shin_T_51[62:0], 1'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shin_T_60 = _shin_T_58 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 105:80]
+ wire [63:0] _shin_T_61 = _shin_T_56 | _shin_T_60; // @[Bitwise.scala 105:39]
+ wire [63:0] shin = io_fn == 4'h5 | io_fn == 4'hb ? shin_r : _shin_T_61; // @[ALU.scala 81:17]
+ wire _shout_r_T_2 = io_fn[3] & shin[63]; // @[ALU.scala 82:35]
+ wire [64:0] _shout_r_T_4 = {_shout_r_T_2,shin}; // @[ALU.scala 82:57]
+ wire [64:0] _shout_r_T_5 = $signed(_shout_r_T_4) >>> shamt; // @[ALU.scala 82:64]
+ wire [63:0] shout_r = _shout_r_T_5[63:0]; // @[ALU.scala 82:73]
+ wire [63:0] _GEN_8 = {{32'd0}, shout_r[63:32]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_3 = _GEN_8 & 64'hffffffff; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_5 = {shout_r[31:0], 32'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shout_l_T_7 = _shout_l_T_5 & 64'hffffffff00000000; // @[Bitwise.scala 105:80]
+ wire [63:0] _shout_l_T_8 = _shout_l_T_3 | _shout_l_T_7; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_9 = {{16'd0}, _shout_l_T_8[63:16]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_13 = _GEN_9 & 64'hffff0000ffff; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_15 = {_shout_l_T_8[47:0], 16'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shout_l_T_17 = _shout_l_T_15 & 64'hffff0000ffff0000; // @[Bitwise.scala 105:80]
+ wire [63:0] _shout_l_T_18 = _shout_l_T_13 | _shout_l_T_17; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_10 = {{8'd0}, _shout_l_T_18[63:8]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_23 = _GEN_10 & 64'hff00ff00ff00ff; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_25 = {_shout_l_T_18[55:0], 8'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shout_l_T_27 = _shout_l_T_25 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 105:80]
+ wire [63:0] _shout_l_T_28 = _shout_l_T_23 | _shout_l_T_27; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_11 = {{4'd0}, _shout_l_T_28[63:4]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_33 = _GEN_11 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_35 = {_shout_l_T_28[59:0], 4'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shout_l_T_37 = _shout_l_T_35 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 105:80]
+ wire [63:0] _shout_l_T_38 = _shout_l_T_33 | _shout_l_T_37; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_12 = {{2'd0}, _shout_l_T_38[63:2]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_43 = _GEN_12 & 64'h3333333333333333; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_45 = {_shout_l_T_38[61:0], 2'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shout_l_T_47 = _shout_l_T_45 & 64'hcccccccccccccccc; // @[Bitwise.scala 105:80]
+ wire [63:0] _shout_l_T_48 = _shout_l_T_43 | _shout_l_T_47; // @[Bitwise.scala 105:39]
+ wire [63:0] _GEN_13 = {{1'd0}, _shout_l_T_48[63:1]}; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_53 = _GEN_13 & 64'h5555555555555555; // @[Bitwise.scala 105:31]
+ wire [63:0] _shout_l_T_55 = {_shout_l_T_48[62:0], 1'h0}; // @[Bitwise.scala 105:70]
+ wire [63:0] _shout_l_T_57 = _shout_l_T_55 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 105:80]
+ wire [63:0] shout_l = _shout_l_T_53 | _shout_l_T_57; // @[Bitwise.scala 105:39]
+ wire [63:0] _shout_T_3 = _shin_T_2 ? shout_r : 64'h0; // @[ALU.scala 84:18]
+ wire [63:0] _shout_T_5 = io_fn == 4'h1 ? shout_l : 64'h0; // @[ALU.scala 85:18]
+ wire [63:0] shout = _shout_T_3 | _shout_T_5; // @[ALU.scala 84:74]
+ wire _logic_T_1 = io_fn == 4'h6; // @[ALU.scala 88:45]
+ wire [63:0] _logic_T_3 = io_fn == 4'h4 | io_fn == 4'h6 ? in1_xor_in2 : 64'h0; // @[ALU.scala 88:18]
+ wire [63:0] _logic_T_7 = io_in1 & io_in2; // @[ALU.scala 89:63]
+ wire [63:0] _logic_T_8 = _logic_T_1 | io_fn == 4'h7 ? _logic_T_7 : 64'h0; // @[ALU.scala 89:18]
+ wire [63:0] logic_ = _logic_T_3 | _logic_T_8; // @[ALU.scala 88:78]
+ wire _shift_logic_T = io_fn >= 4'hc; // @[ALU.scala 41:30]
+ wire _shift_logic_T_1 = _shift_logic_T & slt; // @[ALU.scala 90:35]
+ wire [63:0] _GEN_14 = {{63'd0}, _shift_logic_T_1}; // @[ALU.scala 90:43]
+ wire [63:0] _shift_logic_T_2 = _GEN_14 | logic_; // @[ALU.scala 90:43]
+ wire [63:0] shift_logic = _shift_logic_T_2 | shout; // @[ALU.scala 90:51]
+ wire [63:0] out = io_fn == 4'h0 | io_fn == 4'ha ? io_adder_out : shift_logic; // @[ALU.scala 91:16]
+ wire [31:0] _io_out_T_2 = out[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] _io_out_T_4 = {_io_out_T_2,out[31:0]}; // @[Cat.scala 31:58]
+ assign io_out = ~io_dw ? _io_out_T_4 : out; // @[ALU.scala 93:10 96:{28,37}]
+ assign io_adder_out = _io_adder_out_T_1 + _GEN_1; // @[ALU.scala 63:36]
+ assign io_cmp_out = io_fn[0] ^ _io_cmp_out_T_4; // @[ALU.scala 69:36]
+endmodule
+module MulDiv(
+ input clock,
+ input reset,
+ output io_req_ready,
+ input io_req_valid,
+ input [3:0] io_req_bits_fn,
+ input io_req_bits_dw,
+ input [63:0] io_req_bits_in1,
+ input [63:0] io_req_bits_in2,
+ input [4:0] io_req_bits_tag,
+ input io_kill,
+ input io_resp_ready,
+ output io_resp_valid,
+ output [63:0] io_resp_bits_data,
+ output [4:0] io_resp_bits_tag
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [95:0] _RAND_7;
+ reg [159:0] _RAND_8;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] state; // @[Multiplier.scala 50:22]
+ reg req_dw; // @[Multiplier.scala 52:16]
+ reg [4:0] req_tag; // @[Multiplier.scala 52:16]
+ reg [6:0] count; // @[Multiplier.scala 53:18]
+ reg neg_out; // @[Multiplier.scala 56:20]
+ reg isHi; // @[Multiplier.scala 57:17]
+ reg resHi; // @[Multiplier.scala 58:18]
+ reg [64:0] divisor; // @[Multiplier.scala 59:20]
+ reg [129:0] remainder; // @[Multiplier.scala 60:22]
+ wire [3:0] _T = io_req_bits_fn & 4'h4; // @[Decode.scala 14:65]
+ wire cmdMul = _T == 4'h0; // @[Decode.scala 14:121]
+ wire [3:0] _T_3 = io_req_bits_fn & 4'h5; // @[Decode.scala 14:65]
+ wire _T_4 = _T_3 == 4'h1; // @[Decode.scala 14:121]
+ wire [3:0] _T_5 = io_req_bits_fn & 4'h2; // @[Decode.scala 14:65]
+ wire _T_6 = _T_5 == 4'h2; // @[Decode.scala 14:121]
+ wire cmdHi = _T_4 | _T_6; // @[Decode.scala 15:30]
+ wire [3:0] _T_9 = io_req_bits_fn & 4'h6; // @[Decode.scala 14:65]
+ wire _T_10 = _T_9 == 4'h0; // @[Decode.scala 14:121]
+ wire [3:0] _T_11 = io_req_bits_fn & 4'h1; // @[Decode.scala 14:65]
+ wire _T_12 = _T_11 == 4'h0; // @[Decode.scala 14:121]
+ wire lhsSigned = _T_10 | _T_12; // @[Decode.scala 15:30]
+ wire _T_16 = _T_3 == 4'h4; // @[Decode.scala 14:121]
+ wire rhsSigned = _T_10 | _T_16; // @[Decode.scala 15:30]
+ wire _T_19 = ~io_req_bits_dw; // @[Multiplier.scala 77:60]
+ wire _sign_T_2 = _T_19 ? io_req_bits_in1[31] : io_req_bits_in1[63]; // @[Multiplier.scala 80:29]
+ wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala 80:23]
+ wire [31:0] _hi_T_1 = lhs_sign ? 32'hffffffff : 32'h0; // @[Bitwise.scala 74:12]
+ wire [31:0] hi = _T_19 ? _hi_T_1 : io_req_bits_in1[63:32]; // @[Multiplier.scala 81:17]
+ wire [63:0] lhs_in = {hi,io_req_bits_in1[31:0]}; // @[Cat.scala 31:58]
+ wire _sign_T_5 = _T_19 ? io_req_bits_in2[31] : io_req_bits_in2[63]; // @[Multiplier.scala 80:29]
+ wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala 80:23]
+ wire [31:0] _hi_T_4 = rhs_sign ? 32'hffffffff : 32'h0; // @[Bitwise.scala 74:12]
+ wire [31:0] hi_1 = _T_19 ? _hi_T_4 : io_req_bits_in2[63:32]; // @[Multiplier.scala 81:17]
+ wire [64:0] subtractor = remainder[128:64] - divisor; // @[Multiplier.scala 87:37]
+ wire [63:0] result = resHi ? remainder[128:65] : remainder[63:0]; // @[Multiplier.scala 88:19]
+ wire [63:0] negated_remainder = 64'h0 - result; // @[Multiplier.scala 89:27]
+ wire [129:0] _GEN_0 = remainder[63] ? {{66'd0}, negated_remainder} : remainder; // @[Multiplier.scala 92:27 93:17 60:22]
+ wire [129:0] _GEN_2 = state == 3'h1 ? _GEN_0 : remainder; // @[Multiplier.scala 60:22 91:57]
+ wire [2:0] _GEN_4 = state == 3'h1 ? 3'h3 : state; // @[Multiplier.scala 91:57 98:11 50:22]
+ wire [2:0] _GEN_6 = state == 3'h5 ? 3'h7 : _GEN_4; // @[Multiplier.scala 100:57 102:11]
+ wire _GEN_7 = state == 3'h5 ? 1'h0 : resHi; // @[Multiplier.scala 100:57 103:11 58:18]
+ wire [128:0] mulReg = {remainder[129:65],remainder[63:0]}; // @[Cat.scala 31:58]
+ wire mplierSign = remainder[64]; // @[Multiplier.scala 107:31]
+ wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala 108:24]
+ wire [64:0] accum = mulReg[128:64]; // @[Multiplier.scala 109:37]
+ wire [1:0] _prod_T_2 = {mplierSign,mplier[0]}; // @[Multiplier.scala 111:60]
+ wire [66:0] _prod_T_3 = $signed(_prod_T_2) * $signed(divisor); // @[Multiplier.scala 111:67]
+ wire [66:0] _GEN_35 = {{2{accum[64]}},accum}; // @[Multiplier.scala 111:76]
+ wire [66:0] nextMulReg_hi = $signed(_prod_T_3) + $signed(_GEN_35); // @[Cat.scala 31:58]
+ wire [129:0] nextMulReg = {nextMulReg_hi,mplier[63:1]}; // @[Cat.scala 31:58]
+ wire nextMplierSign = count == 7'h3e & neg_out; // @[Multiplier.scala 113:57]
+ wire _eOut_T_4 = ~isHi; // @[Multiplier.scala 117:7]
+ wire [128:0] nextMulReg1 = {nextMulReg[128:64],nextMulReg[63:0]}; // @[Cat.scala 31:58]
+ wire [129:0] _remainder_T_2 = {nextMulReg1[128:64],nextMplierSign,nextMulReg1[63:0]}; // @[Cat.scala 31:58]
+ wire [6:0] _count_T_1 = count + 7'h1; // @[Multiplier.scala 122:20]
+ wire [2:0] _GEN_8 = count == 7'h3f ? 3'h6 : _GEN_6; // @[Multiplier.scala 123:51 124:13]
+ wire _GEN_9 = count == 7'h3f ? isHi : _GEN_7; // @[Multiplier.scala 123:51 125:13]
+ wire [2:0] _GEN_12 = state == 3'h2 ? _GEN_8 : _GEN_6; // @[Multiplier.scala 105:50]
+ wire _GEN_13 = state == 3'h2 ? _GEN_9 : _GEN_7; // @[Multiplier.scala 105:50]
+ wire unrolls_less = subtractor[64]; // @[Multiplier.scala 132:28]
+ wire [63:0] _unrolls_T_2 = unrolls_less ? remainder[127:64] : subtractor[63:0]; // @[Multiplier.scala 133:14]
+ wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala 133:67]
+ wire [128:0] unrolls_0 = {_unrolls_T_2,remainder[63:0],_unrolls_T_4}; // @[Cat.scala 31:58]
+ wire [2:0] _state_T = neg_out ? 3'h5 : 3'h7; // @[Multiplier.scala 138:19]
+ wire [2:0] _GEN_14 = count == 7'h40 ? _state_T : _GEN_12; // @[Multiplier.scala 137:38 138:13]
+ wire divby0 = count == 7'h0 & _unrolls_T_4; // @[Multiplier.scala 145:30]
+ wire _T_36 = io_resp_ready & io_resp_valid; // @[Decoupled.scala 50:35]
+ wire _T_38 = io_req_ready & io_req_valid; // @[Decoupled.scala 50:35]
+ wire [5:0] _count_T_7 = cmdMul & _T_19 ? 6'h20 : 6'h0; // @[Multiplier.scala 167:38]
+ wire [64:0] _divisor_T = {rhs_sign,hi_1,io_req_bits_in2[31:0]}; // @[Cat.scala 31:58]
+ wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala 174:23]
+ wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala 174:52]
+ wire _loOut_T = ~req_dw; // @[Multiplier.scala 77:60]
+ wire [31:0] loOut = _loOut_T & outMul ? result[63:32] : result[31:0]; // @[Multiplier.scala 175:18]
+ wire [31:0] _hiOut_T_4 = loOut[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 74:12]
+ wire [31:0] hiOut = _loOut_T ? _hiOut_T_4 : result[63:32]; // @[Multiplier.scala 176:18]
+ assign io_req_ready = state == 3'h0; // @[Multiplier.scala 181:25]
+ assign io_resp_valid = state == 3'h6 | state == 3'h7; // @[Multiplier.scala 180:42]
+ assign io_resp_bits_data = {hiOut,loOut}; // @[Cat.scala 31:58]
+ assign io_resp_bits_tag = req_tag; // @[Multiplier.scala 177:20]
+ always @(posedge clock) begin
+ if (reset) begin // @[Multiplier.scala 50:22]
+ state <= 3'h0; // @[Multiplier.scala 50:22]
+ end else if (_T_38) begin // @[Multiplier.scala 163:24]
+ if (cmdMul) begin // @[Multiplier.scala 164:17]
+ state <= 3'h2;
+ end else if (lhs_sign | rhs_sign) begin // @[Multiplier.scala 164:36]
+ state <= 3'h1;
+ end else begin
+ state <= 3'h3;
+ end
+ end else if (_T_36 | io_kill) begin // @[Multiplier.scala 160:36]
+ state <= 3'h0; // @[Multiplier.scala 161:11]
+ end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
+ state <= _GEN_14;
+ end else begin
+ state <= _GEN_12;
+ end
+ if (_T_38) begin // @[Multiplier.scala 163:24]
+ req_dw <= io_req_bits_dw; // @[Multiplier.scala 171:9]
+ end
+ if (_T_38) begin // @[Multiplier.scala 163:24]
+ req_tag <= io_req_bits_tag; // @[Multiplier.scala 171:9]
+ end
+ if (_T_38) begin // @[Multiplier.scala 163:24]
+ count <= {{1'd0}, _count_T_7}; // @[Multiplier.scala 167:11]
+ end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
+ count <= _count_T_1; // @[Multiplier.scala 143:11]
+ end else if (state == 3'h2) begin // @[Multiplier.scala 105:50]
+ count <= _count_T_1; // @[Multiplier.scala 122:11]
+ end
+ if (_T_38) begin // @[Multiplier.scala 163:24]
+ if (cmdHi) begin // @[Multiplier.scala 168:19]
+ neg_out <= lhs_sign;
+ end else begin
+ neg_out <= lhs_sign != rhs_sign;
+ end
+ end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
+ if (divby0 & _eOut_T_4) begin // @[Multiplier.scala 158:28]
+ neg_out <= 1'h0; // @[Multiplier.scala 158:38]
+ end
+ end
+ if (_T_38) begin // @[Multiplier.scala 163:24]
+ isHi <= cmdHi; // @[Multiplier.scala 165:10]
+ end
+ if (_T_38) begin // @[Multiplier.scala 163:24]
+ resHi <= 1'h0; // @[Multiplier.scala 166:11]
+ end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
+ if (count == 7'h40) begin // @[Multiplier.scala 137:38]
+ resHi <= isHi; // @[Multiplier.scala 139:13]
+ end else begin
+ resHi <= _GEN_13;
+ end
+ end else begin
+ resHi <= _GEN_13;
+ end
+ if (_T_38) begin // @[Multiplier.scala 163:24]
+ divisor <= _divisor_T; // @[Multiplier.scala 169:13]
+ end else if (state == 3'h1) begin // @[Multiplier.scala 91:57]
+ if (divisor[63]) begin // @[Multiplier.scala 95:25]
+ divisor <= subtractor; // @[Multiplier.scala 96:15]
+ end
+ end
+ if (_T_38) begin // @[Multiplier.scala 163:24]
+ remainder <= {{66'd0}, lhs_in}; // @[Multiplier.scala 170:15]
+ end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
+ remainder <= {{1'd0}, unrolls_0}; // @[Multiplier.scala 136:15]
+ end else if (state == 3'h2) begin // @[Multiplier.scala 105:50]
+ remainder <= _remainder_T_2; // @[Multiplier.scala 120:15]
+ end else if (state == 3'h5) begin // @[Multiplier.scala 100:57]
+ remainder <= {{66'd0}, negated_remainder}; // @[Multiplier.scala 101:15]
+ end else begin
+ remainder <= _GEN_2;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ state = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ req_dw = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ req_tag = _RAND_2[4:0];
+ _RAND_3 = {1{`RANDOM}};
+ count = _RAND_3[6:0];
+ _RAND_4 = {1{`RANDOM}};
+ neg_out = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ isHi = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ resHi = _RAND_6[0:0];
+ _RAND_7 = {3{`RANDOM}};
+ divisor = _RAND_7[64:0];
+ _RAND_8 = {5{`RANDOM}};
+ remainder = _RAND_8[129:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module PlusArgTimeout(
+ input clock,
+ input reset,
+ input [31:0] io_count
+);
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 62:19]
+ wire _T = plusarg_reader_out > 32'h0; // @[PlusArg.scala 63:13]
+ plusarg_reader #(.FORMAT("max_core_cycles=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 62:19]
+ .out(plusarg_reader_out)
+ );
+ always @(posedge clock) begin
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(io_count < plusarg_reader_out) & (_T & ~reset)) begin
+ $fatal; // @[PlusArg.scala 64:12]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T & ~reset & ~(io_count < plusarg_reader_out)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n"
+ ); // @[PlusArg.scala 64:12]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+endmodule
+module Rocket(
+ input clock,
+ input reset,
+ input io_hartid,
+ input io_interrupts_debug,
+ input io_interrupts_mtip,
+ input io_interrupts_msip,
+ input io_interrupts_meip,
+ output io_imem_might_request,
+ output io_imem_req_valid,
+ output [33:0] io_imem_req_bits_pc,
+ output io_imem_req_bits_speculative,
+ output io_imem_resp_ready,
+ input io_imem_resp_valid,
+ input [33:0] io_imem_resp_bits_pc,
+ input [31:0] io_imem_resp_bits_data,
+ input io_imem_resp_bits_xcpt_ae_inst,
+ input io_imem_resp_bits_replay,
+ output io_imem_btb_update_valid,
+ output io_imem_bht_update_valid,
+ output io_imem_flush_icache,
+ input io_dmem_req_ready,
+ output io_dmem_req_valid,
+ output [33:0] io_dmem_req_bits_addr,
+ output [6:0] io_dmem_req_bits_tag,
+ output [4:0] io_dmem_req_bits_cmd,
+ output [1:0] io_dmem_req_bits_size,
+ output io_dmem_req_bits_signed,
+ output io_dmem_req_bits_dv,
+ output io_dmem_s1_kill,
+ output [63:0] io_dmem_s1_data_data,
+ input io_dmem_s2_nack,
+ input io_dmem_resp_valid,
+ input [6:0] io_dmem_resp_bits_tag,
+ input [63:0] io_dmem_resp_bits_data,
+ input io_dmem_resp_bits_replay,
+ input io_dmem_resp_bits_has_data,
+ input [63:0] io_dmem_resp_bits_data_word_bypass,
+ input io_dmem_replay_next,
+ input io_dmem_s2_xcpt_ma_ld,
+ input io_dmem_s2_xcpt_ma_st,
+ input io_dmem_s2_xcpt_pf_ld,
+ input io_dmem_s2_xcpt_pf_st,
+ input io_dmem_s2_xcpt_ae_ld,
+ input io_dmem_s2_xcpt_ae_st,
+ input io_dmem_ordered,
+ input io_dmem_perf_grant,
+ output io_ptw_status_debug,
+ output io_ptw_pmp_0_cfg_l,
+ output [1:0] io_ptw_pmp_0_cfg_a,
+ output io_ptw_pmp_0_cfg_x,
+ output io_ptw_pmp_0_cfg_w,
+ output io_ptw_pmp_0_cfg_r,
+ output [29:0] io_ptw_pmp_0_addr,
+ output [31:0] io_ptw_pmp_0_mask,
+ output io_ptw_pmp_1_cfg_l,
+ output [1:0] io_ptw_pmp_1_cfg_a,
+ output io_ptw_pmp_1_cfg_x,
+ output io_ptw_pmp_1_cfg_w,
+ output io_ptw_pmp_1_cfg_r,
+ output [29:0] io_ptw_pmp_1_addr,
+ output [31:0] io_ptw_pmp_1_mask,
+ output io_ptw_pmp_2_cfg_l,
+ output [1:0] io_ptw_pmp_2_cfg_a,
+ output io_ptw_pmp_2_cfg_x,
+ output io_ptw_pmp_2_cfg_w,
+ output io_ptw_pmp_2_cfg_r,
+ output [29:0] io_ptw_pmp_2_addr,
+ output [31:0] io_ptw_pmp_2_mask,
+ output io_ptw_pmp_3_cfg_l,
+ output [1:0] io_ptw_pmp_3_cfg_a,
+ output io_ptw_pmp_3_cfg_x,
+ output io_ptw_pmp_3_cfg_w,
+ output io_ptw_pmp_3_cfg_r,
+ output [29:0] io_ptw_pmp_3_addr,
+ output [31:0] io_ptw_pmp_3_mask,
+ output io_ptw_pmp_4_cfg_l,
+ output [1:0] io_ptw_pmp_4_cfg_a,
+ output io_ptw_pmp_4_cfg_x,
+ output io_ptw_pmp_4_cfg_w,
+ output io_ptw_pmp_4_cfg_r,
+ output [29:0] io_ptw_pmp_4_addr,
+ output [31:0] io_ptw_pmp_4_mask,
+ output io_ptw_pmp_5_cfg_l,
+ output [1:0] io_ptw_pmp_5_cfg_a,
+ output io_ptw_pmp_5_cfg_x,
+ output io_ptw_pmp_5_cfg_w,
+ output io_ptw_pmp_5_cfg_r,
+ output [29:0] io_ptw_pmp_5_addr,
+ output [31:0] io_ptw_pmp_5_mask,
+ output io_ptw_pmp_6_cfg_l,
+ output [1:0] io_ptw_pmp_6_cfg_a,
+ output io_ptw_pmp_6_cfg_x,
+ output io_ptw_pmp_6_cfg_w,
+ output io_ptw_pmp_6_cfg_r,
+ output [29:0] io_ptw_pmp_6_addr,
+ output [31:0] io_ptw_pmp_6_mask,
+ output io_ptw_pmp_7_cfg_l,
+ output [1:0] io_ptw_pmp_7_cfg_a,
+ output io_ptw_pmp_7_cfg_x,
+ output io_ptw_pmp_7_cfg_w,
+ output io_ptw_pmp_7_cfg_r,
+ output [29:0] io_ptw_pmp_7_addr,
+ output [31:0] io_ptw_pmp_7_mask,
+ output [63:0] io_ptw_customCSRs_csrs_0_value,
+ output io_wfi
+);
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+ reg [63:0] _RAND_1;
+ reg [63:0] _RAND_2;
+`endif // RANDOMIZE_GARBAGE_ASSIGN
+`ifdef RANDOMIZE_MEM_INIT
+ reg [63:0] _RAND_0;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [31:0] _RAND_30;
+ reg [31:0] _RAND_31;
+ reg [31:0] _RAND_32;
+ reg [31:0] _RAND_33;
+ reg [31:0] _RAND_34;
+ reg [31:0] _RAND_35;
+ reg [31:0] _RAND_36;
+ reg [31:0] _RAND_37;
+ reg [31:0] _RAND_38;
+ reg [31:0] _RAND_39;
+ reg [31:0] _RAND_40;
+ reg [31:0] _RAND_41;
+ reg [31:0] _RAND_42;
+ reg [31:0] _RAND_43;
+ reg [63:0] _RAND_44;
+ reg [31:0] _RAND_45;
+ reg [63:0] _RAND_46;
+ reg [31:0] _RAND_47;
+ reg [31:0] _RAND_48;
+ reg [31:0] _RAND_49;
+ reg [31:0] _RAND_50;
+ reg [31:0] _RAND_51;
+ reg [31:0] _RAND_52;
+ reg [31:0] _RAND_53;
+ reg [31:0] _RAND_54;
+ reg [31:0] _RAND_55;
+ reg [63:0] _RAND_56;
+ reg [31:0] _RAND_57;
+ reg [31:0] _RAND_58;
+ reg [31:0] _RAND_59;
+ reg [63:0] _RAND_60;
+ reg [31:0] _RAND_61;
+ reg [31:0] _RAND_62;
+ reg [31:0] _RAND_63;
+ reg [63:0] _RAND_64;
+ reg [63:0] _RAND_65;
+ reg [31:0] _RAND_66;
+ reg [31:0] _RAND_67;
+ reg [31:0] _RAND_68;
+ reg [31:0] _RAND_69;
+ reg [31:0] _RAND_70;
+ reg [63:0] _RAND_71;
+ reg [63:0] _RAND_72;
+ reg [31:0] _RAND_73;
+ reg [31:0] _RAND_74;
+ reg [31:0] _RAND_75;
+ reg [63:0] _RAND_76;
+ reg [31:0] _RAND_77;
+ reg [31:0] _RAND_78;
+ reg [31:0] _RAND_79;
+ reg [31:0] _RAND_80;
+ reg [31:0] _RAND_81;
+ reg [63:0] _RAND_82;
+ reg [63:0] _RAND_83;
+ reg [31:0] _RAND_84;
+ reg [31:0] _RAND_85;
+ reg [31:0] _RAND_86;
+ reg [63:0] _RAND_87;
+ reg [63:0] _RAND_88;
+ reg [63:0] _RAND_89;
+ reg [63:0] _RAND_90;
+`endif // RANDOMIZE_REG_INIT
+ wire ibuf_clock; // @[RocketCore.scala 263:20]
+ wire ibuf_reset; // @[RocketCore.scala 263:20]
+ wire ibuf_io_imem_ready; // @[RocketCore.scala 263:20]
+ wire ibuf_io_imem_valid; // @[RocketCore.scala 263:20]
+ wire [33:0] ibuf_io_imem_bits_pc; // @[RocketCore.scala 263:20]
+ wire [31:0] ibuf_io_imem_bits_data; // @[RocketCore.scala 263:20]
+ wire ibuf_io_imem_bits_xcpt_ae_inst; // @[RocketCore.scala 263:20]
+ wire ibuf_io_imem_bits_replay; // @[RocketCore.scala 263:20]
+ wire ibuf_io_kill; // @[RocketCore.scala 263:20]
+ wire [33:0] ibuf_io_pc; // @[RocketCore.scala 263:20]
+ wire ibuf_io_inst_0_ready; // @[RocketCore.scala 263:20]
+ wire ibuf_io_inst_0_valid; // @[RocketCore.scala 263:20]
+ wire ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala 263:20]
+ wire ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala 263:20]
+ wire ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala 263:20]
+ wire ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala 263:20]
+ wire ibuf_io_inst_0_bits_replay; // @[RocketCore.scala 263:20]
+ wire ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala 263:20]
+ wire [31:0] ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala 263:20]
+ wire [4:0] ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala 263:20]
+ wire [4:0] ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 263:20]
+ wire [4:0] ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 263:20]
+ wire [31:0] ibuf_io_inst_0_bits_raw; // @[RocketCore.scala 263:20]
+ reg [63:0] rf [0:30]; // @[RocketCore.scala 1061:15]
+ wire rf_id_rs_MPORT_en; // @[RocketCore.scala 1061:15]
+ wire [4:0] rf_id_rs_MPORT_addr; // @[RocketCore.scala 1061:15]
+ wire [63:0] rf_id_rs_MPORT_data; // @[RocketCore.scala 1061:15]
+ wire rf_id_rs_MPORT_1_en; // @[RocketCore.scala 1061:15]
+ wire [4:0] rf_id_rs_MPORT_1_addr; // @[RocketCore.scala 1061:15]
+ wire [63:0] rf_id_rs_MPORT_1_data; // @[RocketCore.scala 1061:15]
+ wire [63:0] rf_MPORT_data; // @[RocketCore.scala 1061:15]
+ wire [4:0] rf_MPORT_addr; // @[RocketCore.scala 1061:15]
+ wire rf_MPORT_mask; // @[RocketCore.scala 1061:15]
+ wire rf_MPORT_en; // @[RocketCore.scala 1061:15]
+ wire csr_clock; // @[RocketCore.scala 291:19]
+ wire csr_reset; // @[RocketCore.scala 291:19]
+ wire csr_io_ungated_clock; // @[RocketCore.scala 291:19]
+ wire csr_io_interrupts_debug; // @[RocketCore.scala 291:19]
+ wire csr_io_interrupts_mtip; // @[RocketCore.scala 291:19]
+ wire csr_io_interrupts_msip; // @[RocketCore.scala 291:19]
+ wire csr_io_interrupts_meip; // @[RocketCore.scala 291:19]
+ wire csr_io_hartid; // @[RocketCore.scala 291:19]
+ wire [11:0] csr_io_rw_addr; // @[RocketCore.scala 291:19]
+ wire [2:0] csr_io_rw_cmd; // @[RocketCore.scala 291:19]
+ wire [63:0] csr_io_rw_rdata; // @[RocketCore.scala 291:19]
+ wire [63:0] csr_io_rw_wdata; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_decode_0_inst; // @[RocketCore.scala 291:19]
+ wire csr_io_decode_0_fp_illegal; // @[RocketCore.scala 291:19]
+ wire csr_io_decode_0_fp_csr; // @[RocketCore.scala 291:19]
+ wire csr_io_decode_0_read_illegal; // @[RocketCore.scala 291:19]
+ wire csr_io_decode_0_write_illegal; // @[RocketCore.scala 291:19]
+ wire csr_io_decode_0_write_flush; // @[RocketCore.scala 291:19]
+ wire csr_io_decode_0_system_illegal; // @[RocketCore.scala 291:19]
+ wire csr_io_csr_stall; // @[RocketCore.scala 291:19]
+ wire csr_io_eret; // @[RocketCore.scala 291:19]
+ wire csr_io_singleStep; // @[RocketCore.scala 291:19]
+ wire csr_io_status_debug; // @[RocketCore.scala 291:19]
+ wire csr_io_status_cease; // @[RocketCore.scala 291:19]
+ wire csr_io_status_wfi; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_status_isa; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_status_dprv; // @[RocketCore.scala 291:19]
+ wire csr_io_status_dv; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_status_prv; // @[RocketCore.scala 291:19]
+ wire csr_io_status_v; // @[RocketCore.scala 291:19]
+ wire csr_io_status_sd; // @[RocketCore.scala 291:19]
+ wire [22:0] csr_io_status_zero2; // @[RocketCore.scala 291:19]
+ wire csr_io_status_mpv; // @[RocketCore.scala 291:19]
+ wire csr_io_status_gva; // @[RocketCore.scala 291:19]
+ wire csr_io_status_mbe; // @[RocketCore.scala 291:19]
+ wire csr_io_status_sbe; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_status_sxl; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_status_uxl; // @[RocketCore.scala 291:19]
+ wire csr_io_status_sd_rv32; // @[RocketCore.scala 291:19]
+ wire [7:0] csr_io_status_zero1; // @[RocketCore.scala 291:19]
+ wire csr_io_status_tsr; // @[RocketCore.scala 291:19]
+ wire csr_io_status_tw; // @[RocketCore.scala 291:19]
+ wire csr_io_status_tvm; // @[RocketCore.scala 291:19]
+ wire csr_io_status_mxr; // @[RocketCore.scala 291:19]
+ wire csr_io_status_sum; // @[RocketCore.scala 291:19]
+ wire csr_io_status_mprv; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_status_xs; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_status_fs; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_status_mpp; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_status_vs; // @[RocketCore.scala 291:19]
+ wire csr_io_status_spp; // @[RocketCore.scala 291:19]
+ wire csr_io_status_mpie; // @[RocketCore.scala 291:19]
+ wire csr_io_status_ube; // @[RocketCore.scala 291:19]
+ wire csr_io_status_spie; // @[RocketCore.scala 291:19]
+ wire csr_io_status_upie; // @[RocketCore.scala 291:19]
+ wire csr_io_status_mie; // @[RocketCore.scala 291:19]
+ wire csr_io_status_hie; // @[RocketCore.scala 291:19]
+ wire csr_io_status_sie; // @[RocketCore.scala 291:19]
+ wire csr_io_status_uie; // @[RocketCore.scala 291:19]
+ wire [33:0] csr_io_evec; // @[RocketCore.scala 291:19]
+ wire csr_io_exception; // @[RocketCore.scala 291:19]
+ wire csr_io_retire; // @[RocketCore.scala 291:19]
+ wire [63:0] csr_io_cause; // @[RocketCore.scala 291:19]
+ wire [33:0] csr_io_pc; // @[RocketCore.scala 291:19]
+ wire [33:0] csr_io_tval; // @[RocketCore.scala 291:19]
+ wire csr_io_gva; // @[RocketCore.scala 291:19]
+ wire [63:0] csr_io_time; // @[RocketCore.scala 291:19]
+ wire csr_io_interrupt; // @[RocketCore.scala 291:19]
+ wire [63:0] csr_io_interrupt_cause; // @[RocketCore.scala 291:19]
+ wire csr_io_bp_0_control_action; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_bp_0_control_tmatch; // @[RocketCore.scala 291:19]
+ wire csr_io_bp_0_control_x; // @[RocketCore.scala 291:19]
+ wire csr_io_bp_0_control_w; // @[RocketCore.scala 291:19]
+ wire csr_io_bp_0_control_r; // @[RocketCore.scala 291:19]
+ wire [32:0] csr_io_bp_0_address; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_0_cfg_l; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_pmp_0_cfg_a; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_0_cfg_x; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_0_cfg_w; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_0_cfg_r; // @[RocketCore.scala 291:19]
+ wire [29:0] csr_io_pmp_0_addr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_pmp_0_mask; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_1_cfg_l; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_pmp_1_cfg_a; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_1_cfg_x; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_1_cfg_w; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_1_cfg_r; // @[RocketCore.scala 291:19]
+ wire [29:0] csr_io_pmp_1_addr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_pmp_1_mask; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_2_cfg_l; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_pmp_2_cfg_a; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_2_cfg_x; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_2_cfg_w; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_2_cfg_r; // @[RocketCore.scala 291:19]
+ wire [29:0] csr_io_pmp_2_addr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_pmp_2_mask; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_3_cfg_l; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_pmp_3_cfg_a; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_3_cfg_x; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_3_cfg_w; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_3_cfg_r; // @[RocketCore.scala 291:19]
+ wire [29:0] csr_io_pmp_3_addr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_pmp_3_mask; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_4_cfg_l; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_pmp_4_cfg_a; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_4_cfg_x; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_4_cfg_w; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_4_cfg_r; // @[RocketCore.scala 291:19]
+ wire [29:0] csr_io_pmp_4_addr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_pmp_4_mask; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_5_cfg_l; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_pmp_5_cfg_a; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_5_cfg_x; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_5_cfg_w; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_5_cfg_r; // @[RocketCore.scala 291:19]
+ wire [29:0] csr_io_pmp_5_addr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_pmp_5_mask; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_6_cfg_l; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_pmp_6_cfg_a; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_6_cfg_x; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_6_cfg_w; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_6_cfg_r; // @[RocketCore.scala 291:19]
+ wire [29:0] csr_io_pmp_6_addr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_pmp_6_mask; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_7_cfg_l; // @[RocketCore.scala 291:19]
+ wire [1:0] csr_io_pmp_7_cfg_a; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_7_cfg_x; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_7_cfg_w; // @[RocketCore.scala 291:19]
+ wire csr_io_pmp_7_cfg_r; // @[RocketCore.scala 291:19]
+ wire [29:0] csr_io_pmp_7_addr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_pmp_7_mask; // @[RocketCore.scala 291:19]
+ wire csr_io_inhibit_cycle; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_inst_0; // @[RocketCore.scala 291:19]
+ wire csr_io_trace_0_valid; // @[RocketCore.scala 291:19]
+ wire [33:0] csr_io_trace_0_iaddr; // @[RocketCore.scala 291:19]
+ wire [31:0] csr_io_trace_0_insn; // @[RocketCore.scala 291:19]
+ wire csr_io_trace_0_exception; // @[RocketCore.scala 291:19]
+ wire [63:0] csr_io_customCSRs_0_value; // @[RocketCore.scala 291:19]
+ wire bpu_io_status_debug; // @[RocketCore.scala 334:19]
+ wire bpu_io_bp_0_control_action; // @[RocketCore.scala 334:19]
+ wire [1:0] bpu_io_bp_0_control_tmatch; // @[RocketCore.scala 334:19]
+ wire bpu_io_bp_0_control_x; // @[RocketCore.scala 334:19]
+ wire bpu_io_bp_0_control_w; // @[RocketCore.scala 334:19]
+ wire bpu_io_bp_0_control_r; // @[RocketCore.scala 334:19]
+ wire [32:0] bpu_io_bp_0_address; // @[RocketCore.scala 334:19]
+ wire [32:0] bpu_io_pc; // @[RocketCore.scala 334:19]
+ wire [32:0] bpu_io_ea; // @[RocketCore.scala 334:19]
+ wire bpu_io_xcpt_if; // @[RocketCore.scala 334:19]
+ wire bpu_io_xcpt_ld; // @[RocketCore.scala 334:19]
+ wire bpu_io_xcpt_st; // @[RocketCore.scala 334:19]
+ wire bpu_io_debug_if; // @[RocketCore.scala 334:19]
+ wire bpu_io_debug_ld; // @[RocketCore.scala 334:19]
+ wire bpu_io_debug_st; // @[RocketCore.scala 334:19]
+ wire alu_io_dw; // @[RocketCore.scala 399:19]
+ wire [3:0] alu_io_fn; // @[RocketCore.scala 399:19]
+ wire [63:0] alu_io_in2; // @[RocketCore.scala 399:19]
+ wire [63:0] alu_io_in1; // @[RocketCore.scala 399:19]
+ wire [63:0] alu_io_out; // @[RocketCore.scala 399:19]
+ wire [63:0] alu_io_adder_out; // @[RocketCore.scala 399:19]
+ wire alu_io_cmp_out; // @[RocketCore.scala 399:19]
+ wire div_clock; // @[RocketCore.scala 423:19]
+ wire div_reset; // @[RocketCore.scala 423:19]
+ wire div_io_req_ready; // @[RocketCore.scala 423:19]
+ wire div_io_req_valid; // @[RocketCore.scala 423:19]
+ wire [3:0] div_io_req_bits_fn; // @[RocketCore.scala 423:19]
+ wire div_io_req_bits_dw; // @[RocketCore.scala 423:19]
+ wire [63:0] div_io_req_bits_in1; // @[RocketCore.scala 423:19]
+ wire [63:0] div_io_req_bits_in2; // @[RocketCore.scala 423:19]
+ wire [4:0] div_io_req_bits_tag; // @[RocketCore.scala 423:19]
+ wire div_io_kill; // @[RocketCore.scala 423:19]
+ wire div_io_resp_ready; // @[RocketCore.scala 423:19]
+ wire div_io_resp_valid; // @[RocketCore.scala 423:19]
+ wire [63:0] div_io_resp_bits_data; // @[RocketCore.scala 423:19]
+ wire [4:0] div_io_resp_bits_tag; // @[RocketCore.scala 423:19]
+ wire PlusArgTimeout_clock; // @[PlusArg.scala 89:11]
+ wire PlusArgTimeout_reset; // @[PlusArg.scala 89:11]
+ wire [31:0] PlusArgTimeout_io_count; // @[PlusArg.scala 89:11]
+ reg id_reg_pause; // @[RocketCore.scala 116:25]
+ reg imem_might_request_reg; // @[RocketCore.scala 117:35]
+ reg ex_ctrl_branch; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_jal; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_jalr; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_rxs2; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_rxs1; // @[RocketCore.scala 194:20]
+ reg [1:0] ex_ctrl_sel_alu2; // @[RocketCore.scala 194:20]
+ reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala 194:20]
+ reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_alu_dw; // @[RocketCore.scala 194:20]
+ reg [3:0] ex_ctrl_alu_fn; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_mem; // @[RocketCore.scala 194:20]
+ reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_div; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_wxd; // @[RocketCore.scala 194:20]
+ reg [2:0] ex_ctrl_csr; // @[RocketCore.scala 194:20]
+ reg ex_ctrl_fence_i; // @[RocketCore.scala 194:20]
+ reg mem_ctrl_branch; // @[RocketCore.scala 195:21]
+ reg mem_ctrl_jal; // @[RocketCore.scala 195:21]
+ reg mem_ctrl_jalr; // @[RocketCore.scala 195:21]
+ reg mem_ctrl_rxs2; // @[RocketCore.scala 195:21]
+ reg mem_ctrl_rxs1; // @[RocketCore.scala 195:21]
+ reg mem_ctrl_mem; // @[RocketCore.scala 195:21]
+ reg mem_ctrl_div; // @[RocketCore.scala 195:21]
+ reg mem_ctrl_wxd; // @[RocketCore.scala 195:21]
+ reg [2:0] mem_ctrl_csr; // @[RocketCore.scala 195:21]
+ reg mem_ctrl_fence_i; // @[RocketCore.scala 195:21]
+ reg wb_ctrl_rxs2; // @[RocketCore.scala 196:20]
+ reg wb_ctrl_rxs1; // @[RocketCore.scala 196:20]
+ reg wb_ctrl_mem; // @[RocketCore.scala 196:20]
+ reg wb_ctrl_div; // @[RocketCore.scala 196:20]
+ reg wb_ctrl_wxd; // @[RocketCore.scala 196:20]
+ reg [2:0] wb_ctrl_csr; // @[RocketCore.scala 196:20]
+ reg wb_ctrl_fence_i; // @[RocketCore.scala 196:20]
+ reg ex_reg_xcpt_interrupt; // @[RocketCore.scala 198:35]
+ reg ex_reg_valid; // @[RocketCore.scala 199:35]
+ reg ex_reg_rvc; // @[RocketCore.scala 200:35]
+ reg ex_reg_xcpt; // @[RocketCore.scala 202:35]
+ reg ex_reg_flush_pipe; // @[RocketCore.scala 203:35]
+ reg ex_reg_load_use; // @[RocketCore.scala 204:35]
+ reg [63:0] ex_reg_cause; // @[RocketCore.scala 205:35]
+ reg ex_reg_replay; // @[RocketCore.scala 206:26]
+ reg [33:0] ex_reg_pc; // @[RocketCore.scala 207:22]
+ reg [1:0] ex_reg_mem_size; // @[RocketCore.scala 208:28]
+ reg [31:0] ex_reg_inst; // @[RocketCore.scala 210:24]
+ reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala 211:28]
+ reg mem_reg_xcpt_interrupt; // @[RocketCore.scala 216:36]
+ reg mem_reg_valid; // @[RocketCore.scala 217:36]
+ reg mem_reg_rvc; // @[RocketCore.scala 218:36]
+ reg mem_reg_xcpt; // @[RocketCore.scala 220:36]
+ reg mem_reg_replay; // @[RocketCore.scala 221:36]
+ reg mem_reg_flush_pipe; // @[RocketCore.scala 222:36]
+ reg [63:0] mem_reg_cause; // @[RocketCore.scala 223:36]
+ reg mem_reg_slow_bypass; // @[RocketCore.scala 224:36]
+ reg mem_reg_load; // @[RocketCore.scala 225:36]
+ reg mem_reg_store; // @[RocketCore.scala 226:36]
+ reg [33:0] mem_reg_pc; // @[RocketCore.scala 228:23]
+ reg [31:0] mem_reg_inst; // @[RocketCore.scala 229:25]
+ reg mem_reg_hls_or_dv; // @[RocketCore.scala 231:30]
+ reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala 232:29]
+ reg [63:0] mem_reg_wdata; // @[RocketCore.scala 235:26]
+ reg [63:0] mem_reg_rs2; // @[RocketCore.scala 236:24]
+ reg mem_br_taken; // @[RocketCore.scala 237:25]
+ reg wb_reg_valid; // @[RocketCore.scala 241:35]
+ reg wb_reg_xcpt; // @[RocketCore.scala 242:35]
+ reg wb_reg_replay; // @[RocketCore.scala 243:35]
+ reg wb_reg_flush_pipe; // @[RocketCore.scala 244:35]
+ reg [63:0] wb_reg_cause; // @[RocketCore.scala 245:35]
+ reg [33:0] wb_reg_pc; // @[RocketCore.scala 247:22]
+ reg wb_reg_hls_or_dv; // @[RocketCore.scala 249:29]
+ reg [31:0] wb_reg_inst; // @[RocketCore.scala 252:24]
+ reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala 253:28]
+ reg [63:0] wb_reg_wdata; // @[RocketCore.scala 254:25]
+ wire replay_wb_common = io_dmem_s2_nack | wb_reg_replay; // @[RocketCore.scala 664:42]
+ wire _T_90 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala 637:19]
+ wire _T_91 = wb_reg_valid & wb_ctrl_mem & io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala 637:34]
+ wire _T_93 = _T_90 & io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala 638:34]
+ wire _T_99 = _T_90 & io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala 641:34]
+ wire _T_101 = _T_90 & io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala 642:34]
+ wire _T_103 = _T_90 & io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala 643:34]
+ wire _T_105 = _T_90 & io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala 644:34]
+ wire wb_xcpt = wb_reg_xcpt | _T_91 | _T_93 | _T_99 | _T_101 | _T_103 | _T_105; // @[RocketCore.scala 1021:26]
+ wire take_pc_wb = replay_wb_common | wb_xcpt | csr_io_eret | wb_reg_flush_pipe; // @[RocketCore.scala 667:53]
+ wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala 541:35]
+ wire _mem_cfi_taken_T = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala 538:40]
+ wire mem_cfi_taken = mem_ctrl_branch & mem_br_taken | mem_ctrl_jalr | mem_ctrl_jal; // @[RocketCore.scala 538:74]
+ wire take_pc_mem = mem_reg_valid & ~mem_reg_xcpt & mem_cfi_taken; // @[RocketCore.scala 541:49]
+ wire take_pc_mem_wb = take_pc_wb | take_pc_mem; // @[RocketCore.scala 259:35]
+ wire [31:0] _id_ctrl_decoder_bit_T = ibuf_io_inst_0_bits_inst_bits & 32'hfe00707f; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_bit_T_1 = _id_ctrl_decoder_bit_T == 32'h2000033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_3 = _id_ctrl_decoder_bit_T == 32'h2001033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_5 = _id_ctrl_decoder_bit_T == 32'h2003033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_7 = _id_ctrl_decoder_bit_T == 32'h2002033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_9 = _id_ctrl_decoder_bit_T == 32'h2004033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_11 = _id_ctrl_decoder_bit_T == 32'h2005033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_13 = _id_ctrl_decoder_bit_T == 32'h2006033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_15 = _id_ctrl_decoder_bit_T == 32'h2007033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_17 = _id_ctrl_decoder_bit_T == 32'h200003b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_19 = _id_ctrl_decoder_bit_T == 32'h200403b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_21 = _id_ctrl_decoder_bit_T == 32'h200503b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_23 = _id_ctrl_decoder_bit_T == 32'h200603b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_25 = _id_ctrl_decoder_bit_T == 32'h200703b; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_bit_T_26 = ibuf_io_inst_0_bits_inst_bits & 32'hf800707f; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_bit_T_27 = _id_ctrl_decoder_bit_T_26 == 32'h202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_29 = _id_ctrl_decoder_bit_T_26 == 32'h2000202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_31 = _id_ctrl_decoder_bit_T_26 == 32'h800202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_33 = _id_ctrl_decoder_bit_T_26 == 32'h6000202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_35 = _id_ctrl_decoder_bit_T_26 == 32'h4000202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_37 = _id_ctrl_decoder_bit_T_26 == 32'h8000202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_39 = _id_ctrl_decoder_bit_T_26 == 32'hc000202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_41 = _id_ctrl_decoder_bit_T_26 == 32'ha000202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_43 = _id_ctrl_decoder_bit_T_26 == 32'he000202f; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_bit_T_44 = ibuf_io_inst_0_bits_inst_bits & 32'hf9f0707f; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_bit_T_45 = _id_ctrl_decoder_bit_T_44 == 32'h1000202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_47 = _id_ctrl_decoder_bit_T_26 == 32'h1800202f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_49 = _id_ctrl_decoder_bit_T_26 == 32'h302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_51 = _id_ctrl_decoder_bit_T_26 == 32'h800302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_53 = _id_ctrl_decoder_bit_T_26 == 32'h2000302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_55 = _id_ctrl_decoder_bit_T_26 == 32'h6000302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_57 = _id_ctrl_decoder_bit_T_26 == 32'h4000302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_59 = _id_ctrl_decoder_bit_T_26 == 32'h8000302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_61 = _id_ctrl_decoder_bit_T_26 == 32'hc000302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_63 = _id_ctrl_decoder_bit_T_26 == 32'ha000302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_65 = _id_ctrl_decoder_bit_T_26 == 32'he000302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_67 = _id_ctrl_decoder_bit_T_44 == 32'h1000302f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_69 = _id_ctrl_decoder_bit_T_26 == 32'h1800302f; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_bit_T_70 = ibuf_io_inst_0_bits_inst_bits & 32'h707f; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_bit_T_71 = _id_ctrl_decoder_bit_T_70 == 32'h3003; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_73 = _id_ctrl_decoder_bit_T_70 == 32'h6003; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_75 = _id_ctrl_decoder_bit_T_70 == 32'h3023; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_bit_T_76 = ibuf_io_inst_0_bits_inst_bits & 32'hfc00707f; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_bit_T_77 = _id_ctrl_decoder_bit_T_76 == 32'h1013; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_79 = _id_ctrl_decoder_bit_T_76 == 32'h5013; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_81 = _id_ctrl_decoder_bit_T_76 == 32'h40005013; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_83 = _id_ctrl_decoder_bit_T_70 == 32'h1b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_85 = _id_ctrl_decoder_bit_T == 32'h101b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_87 = _id_ctrl_decoder_bit_T == 32'h501b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_89 = _id_ctrl_decoder_bit_T == 32'h4000501b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_91 = _id_ctrl_decoder_bit_T == 32'h3b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_93 = _id_ctrl_decoder_bit_T == 32'h4000003b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_95 = _id_ctrl_decoder_bit_T == 32'h103b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_97 = _id_ctrl_decoder_bit_T == 32'h503b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_99 = _id_ctrl_decoder_bit_T == 32'h4000503b; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_100 = ibuf_io_inst_0_bits_inst_bits == 32'h7b200073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_102 = _id_ctrl_decoder_bit_T_70 == 32'h100f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_104 = _id_ctrl_decoder_bit_T_70 == 32'h1063; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_106 = _id_ctrl_decoder_bit_T_70 == 32'h63; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_108 = _id_ctrl_decoder_bit_T_70 == 32'h4063; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_110 = _id_ctrl_decoder_bit_T_70 == 32'h6063; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_112 = _id_ctrl_decoder_bit_T_70 == 32'h5063; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_114 = _id_ctrl_decoder_bit_T_70 == 32'h7063; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_bit_T_115 = ibuf_io_inst_0_bits_inst_bits & 32'h7f; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_bit_T_116 = _id_ctrl_decoder_bit_T_115 == 32'h6f; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_118 = _id_ctrl_decoder_bit_T_70 == 32'h67; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_120 = _id_ctrl_decoder_bit_T_115 == 32'h17; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_122 = _id_ctrl_decoder_bit_T_70 == 32'h3; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_124 = _id_ctrl_decoder_bit_T_70 == 32'h1003; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_126 = _id_ctrl_decoder_bit_T_70 == 32'h2003; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_128 = _id_ctrl_decoder_bit_T_70 == 32'h4003; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_130 = _id_ctrl_decoder_bit_T_70 == 32'h5003; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_132 = _id_ctrl_decoder_bit_T_70 == 32'h23; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_134 = _id_ctrl_decoder_bit_T_70 == 32'h1023; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_136 = _id_ctrl_decoder_bit_T_70 == 32'h2023; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_138 = _id_ctrl_decoder_bit_T_115 == 32'h37; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_140 = _id_ctrl_decoder_bit_T_70 == 32'h13; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_142 = _id_ctrl_decoder_bit_T_70 == 32'h2013; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_144 = _id_ctrl_decoder_bit_T_70 == 32'h3013; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_146 = _id_ctrl_decoder_bit_T_70 == 32'h7013; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_148 = _id_ctrl_decoder_bit_T_70 == 32'h6013; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_150 = _id_ctrl_decoder_bit_T_70 == 32'h4013; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_152 = _id_ctrl_decoder_bit_T == 32'h33; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_154 = _id_ctrl_decoder_bit_T == 32'h40000033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_156 = _id_ctrl_decoder_bit_T == 32'h2033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_158 = _id_ctrl_decoder_bit_T == 32'h3033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_160 = _id_ctrl_decoder_bit_T == 32'h7033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_162 = _id_ctrl_decoder_bit_T == 32'h6033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_164 = _id_ctrl_decoder_bit_T == 32'h4033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_166 = _id_ctrl_decoder_bit_T == 32'h1033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_168 = _id_ctrl_decoder_bit_T == 32'h5033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_170 = _id_ctrl_decoder_bit_T == 32'h40005033; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_172 = _id_ctrl_decoder_bit_T_70 == 32'hf; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_173 = ibuf_io_inst_0_bits_inst_bits == 32'h73; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_174 = ibuf_io_inst_0_bits_inst_bits == 32'h100073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_175 = ibuf_io_inst_0_bits_inst_bits == 32'h30200073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_176 = ibuf_io_inst_0_bits_inst_bits == 32'h10500073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_177 = ibuf_io_inst_0_bits_inst_bits == 32'h30500073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_179 = _id_ctrl_decoder_bit_T_70 == 32'h1073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_181 = _id_ctrl_decoder_bit_T_70 == 32'h2073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_183 = _id_ctrl_decoder_bit_T_70 == 32'h3073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_185 = _id_ctrl_decoder_bit_T_70 == 32'h5073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_187 = _id_ctrl_decoder_bit_T_70 == 32'h6073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_189 = _id_ctrl_decoder_bit_T_70 == 32'h7073; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_bit_T_220 = _id_ctrl_decoder_bit_T_1 | _id_ctrl_decoder_bit_T_3 | _id_ctrl_decoder_bit_T_5 |
+ _id_ctrl_decoder_bit_T_7 | _id_ctrl_decoder_bit_T_9 | _id_ctrl_decoder_bit_T_11 | _id_ctrl_decoder_bit_T_13 |
+ _id_ctrl_decoder_bit_T_15 | _id_ctrl_decoder_bit_T_17 | _id_ctrl_decoder_bit_T_19 | _id_ctrl_decoder_bit_T_21 |
+ _id_ctrl_decoder_bit_T_23 | _id_ctrl_decoder_bit_T_25 | _id_ctrl_decoder_bit_T_27 | _id_ctrl_decoder_bit_T_29 |
+ _id_ctrl_decoder_bit_T_31 | _id_ctrl_decoder_bit_T_33 | _id_ctrl_decoder_bit_T_35 | _id_ctrl_decoder_bit_T_37 |
+ _id_ctrl_decoder_bit_T_39 | _id_ctrl_decoder_bit_T_41 | _id_ctrl_decoder_bit_T_43 | _id_ctrl_decoder_bit_T_45 |
+ _id_ctrl_decoder_bit_T_47 | _id_ctrl_decoder_bit_T_49 | _id_ctrl_decoder_bit_T_51 | _id_ctrl_decoder_bit_T_53 |
+ _id_ctrl_decoder_bit_T_55 | _id_ctrl_decoder_bit_T_57 | _id_ctrl_decoder_bit_T_59 | _id_ctrl_decoder_bit_T_61; // @[Decode.scala 15:30]
+ wire _id_ctrl_decoder_bit_T_250 = _id_ctrl_decoder_bit_T_220 | _id_ctrl_decoder_bit_T_63 | _id_ctrl_decoder_bit_T_65
+ | _id_ctrl_decoder_bit_T_67 | _id_ctrl_decoder_bit_T_69 | _id_ctrl_decoder_bit_T_71 | _id_ctrl_decoder_bit_T_73 |
+ _id_ctrl_decoder_bit_T_75 | _id_ctrl_decoder_bit_T_77 | _id_ctrl_decoder_bit_T_79 | _id_ctrl_decoder_bit_T_81 |
+ _id_ctrl_decoder_bit_T_83 | _id_ctrl_decoder_bit_T_85 | _id_ctrl_decoder_bit_T_87 | _id_ctrl_decoder_bit_T_89 |
+ _id_ctrl_decoder_bit_T_91 | _id_ctrl_decoder_bit_T_93 | _id_ctrl_decoder_bit_T_95 | _id_ctrl_decoder_bit_T_97 |
+ _id_ctrl_decoder_bit_T_99 | _id_ctrl_decoder_bit_T_100 | _id_ctrl_decoder_bit_T_102 | _id_ctrl_decoder_bit_T_104 |
+ _id_ctrl_decoder_bit_T_106 | _id_ctrl_decoder_bit_T_108 | _id_ctrl_decoder_bit_T_110 | _id_ctrl_decoder_bit_T_112 |
+ _id_ctrl_decoder_bit_T_114 | _id_ctrl_decoder_bit_T_116 | _id_ctrl_decoder_bit_T_118 | _id_ctrl_decoder_bit_T_120; // @[Decode.scala 15:30]
+ wire _id_ctrl_decoder_bit_T_280 = _id_ctrl_decoder_bit_T_250 | _id_ctrl_decoder_bit_T_122 |
+ _id_ctrl_decoder_bit_T_124 | _id_ctrl_decoder_bit_T_126 | _id_ctrl_decoder_bit_T_128 | _id_ctrl_decoder_bit_T_130 |
+ _id_ctrl_decoder_bit_T_132 | _id_ctrl_decoder_bit_T_134 | _id_ctrl_decoder_bit_T_136 | _id_ctrl_decoder_bit_T_138 |
+ _id_ctrl_decoder_bit_T_140 | _id_ctrl_decoder_bit_T_142 | _id_ctrl_decoder_bit_T_144 | _id_ctrl_decoder_bit_T_146 |
+ _id_ctrl_decoder_bit_T_148 | _id_ctrl_decoder_bit_T_150 | _id_ctrl_decoder_bit_T_152 | _id_ctrl_decoder_bit_T_154 |
+ _id_ctrl_decoder_bit_T_156 | _id_ctrl_decoder_bit_T_158 | _id_ctrl_decoder_bit_T_160 | _id_ctrl_decoder_bit_T_162 |
+ _id_ctrl_decoder_bit_T_164 | _id_ctrl_decoder_bit_T_166 | _id_ctrl_decoder_bit_T_168 | _id_ctrl_decoder_bit_T_170 |
+ _id_ctrl_decoder_bit_T_172 | _id_ctrl_decoder_bit_T_173 | _id_ctrl_decoder_bit_T_174 | _id_ctrl_decoder_bit_T_175 |
+ _id_ctrl_decoder_bit_T_176; // @[Decode.scala 15:30]
+ wire id_ctrl_decoder_0 = _id_ctrl_decoder_bit_T_280 | _id_ctrl_decoder_bit_T_177 | _id_ctrl_decoder_bit_T_179 |
+ _id_ctrl_decoder_bit_T_181 | _id_ctrl_decoder_bit_T_183 | _id_ctrl_decoder_bit_T_185 | _id_ctrl_decoder_bit_T_187 |
+ _id_ctrl_decoder_bit_T_189; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T = ibuf_io_inst_0_bits_inst_bits & 32'h54; // @[Decode.scala 14:65]
+ wire id_ctrl_decoder_3 = _id_ctrl_decoder_T == 32'h40; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_2 = ibuf_io_inst_0_bits_inst_bits & 32'h48; // @[Decode.scala 14:65]
+ wire id_ctrl_decoder_4 = _id_ctrl_decoder_T_2 == 32'h48; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_4 = ibuf_io_inst_0_bits_inst_bits & 32'h1c; // @[Decode.scala 14:65]
+ wire id_ctrl_decoder_5 = _id_ctrl_decoder_T_4 == 32'h4; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_6 = ibuf_io_inst_0_bits_inst_bits & 32'h70; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_7 = _id_ctrl_decoder_T_6 == 32'h20; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_8 = ibuf_io_inst_0_bits_inst_bits & 32'h64; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_9 = _id_ctrl_decoder_T_8 == 32'h20; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_10 = ibuf_io_inst_0_bits_inst_bits & 32'h34; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_11 = _id_ctrl_decoder_T_10 == 32'h20; // @[Decode.scala 14:121]
+ wire id_ctrl_decoder_6 = _id_ctrl_decoder_T_7 | _id_ctrl_decoder_T_9 | _id_ctrl_decoder_T_11; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_14 = ibuf_io_inst_0_bits_inst_bits & 32'h4004; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_15 = _id_ctrl_decoder_T_14 == 32'h0; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_16 = ibuf_io_inst_0_bits_inst_bits & 32'h44; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_17 = _id_ctrl_decoder_T_16 == 32'h0; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_18 = ibuf_io_inst_0_bits_inst_bits & 32'h18; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_19 = _id_ctrl_decoder_T_18 == 32'h0; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_20 = ibuf_io_inst_0_bits_inst_bits & 32'h2050; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_21 = _id_ctrl_decoder_T_20 == 32'h2000; // @[Decode.scala 14:121]
+ wire id_ctrl_decoder_7 = _id_ctrl_decoder_T_15 | _id_ctrl_decoder_T_17 | _id_ctrl_decoder_T_19 |
+ _id_ctrl_decoder_T_21; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_25 = ibuf_io_inst_0_bits_inst_bits & 32'h58; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_26 = _id_ctrl_decoder_T_25 == 32'h0; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_27 = ibuf_io_inst_0_bits_inst_bits & 32'h20; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_28 = _id_ctrl_decoder_T_27 == 32'h0; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_29 = ibuf_io_inst_0_bits_inst_bits & 32'hc; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_30 = _id_ctrl_decoder_T_29 == 32'h4; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_31 = ibuf_io_inst_0_bits_inst_bits & 32'h4050; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_32 = _id_ctrl_decoder_T_31 == 32'h4050; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_37 = _id_ctrl_decoder_T_26 | _id_ctrl_decoder_T_28 | _id_ctrl_decoder_T_30 |
+ id_ctrl_decoder_4 | _id_ctrl_decoder_T_32; // @[Decode.scala 15:30]
+ wire _id_ctrl_decoder_T_39 = _id_ctrl_decoder_T_2 == 32'h0; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_40 = ibuf_io_inst_0_bits_inst_bits & 32'h4008; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_41 = _id_ctrl_decoder_T_40 == 32'h4000; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_45 = _id_ctrl_decoder_T_39 | _id_ctrl_decoder_T_17 | _id_ctrl_decoder_T_19 |
+ _id_ctrl_decoder_T_41; // @[Decode.scala 15:30]
+ wire [1:0] id_ctrl_decoder_9 = {_id_ctrl_decoder_T_45,_id_ctrl_decoder_T_37}; // @[Cat.scala 31:58]
+ wire [31:0] _id_ctrl_decoder_T_46 = ibuf_io_inst_0_bits_inst_bits & 32'h50; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_47 = _id_ctrl_decoder_T_46 == 32'h0; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_51 = _id_ctrl_decoder_T_15 | _id_ctrl_decoder_T_47 | _id_ctrl_decoder_T_17 |
+ _id_ctrl_decoder_T_19; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_52 = ibuf_io_inst_0_bits_inst_bits & 32'h24; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_53 = _id_ctrl_decoder_T_52 == 32'h4; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_55 = _id_ctrl_decoder_T_53 | id_ctrl_decoder_4; // @[Decode.scala 15:30]
+ wire [1:0] id_ctrl_decoder_10 = {_id_ctrl_decoder_T_55,_id_ctrl_decoder_T_51}; // @[Cat.scala 31:58]
+ wire _id_ctrl_decoder_T_57 = _id_ctrl_decoder_T_18 == 32'h8; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_59 = _id_ctrl_decoder_T_16 == 32'h40; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_61 = _id_ctrl_decoder_T_57 | _id_ctrl_decoder_T_59; // @[Decode.scala 15:30]
+ wire _id_ctrl_decoder_T_63 = _id_ctrl_decoder_T_16 == 32'h4; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_65 = _id_ctrl_decoder_T_63 | _id_ctrl_decoder_T_57; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_66 = ibuf_io_inst_0_bits_inst_bits & 32'h14; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_67 = _id_ctrl_decoder_T_66 == 32'h10; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_68 = ibuf_io_inst_0_bits_inst_bits & 32'h30; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_69 = _id_ctrl_decoder_T_68 == 32'h0; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_72 = id_ctrl_decoder_5 | _id_ctrl_decoder_T_67 | _id_ctrl_decoder_T_69; // @[Decode.scala 15:30]
+ wire [2:0] id_ctrl_decoder_11 = {_id_ctrl_decoder_T_72,_id_ctrl_decoder_T_65,_id_ctrl_decoder_T_61}; // @[Cat.scala 31:58]
+ wire [31:0] _id_ctrl_decoder_T_73 = ibuf_io_inst_0_bits_inst_bits & 32'h10; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_74 = _id_ctrl_decoder_T_73 == 32'h0; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_75 = ibuf_io_inst_0_bits_inst_bits & 32'h8; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_76 = _id_ctrl_decoder_T_75 == 32'h0; // @[Decode.scala 14:121]
+ wire id_ctrl_decoder_12 = _id_ctrl_decoder_T_74 | _id_ctrl_decoder_T_76; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_78 = ibuf_io_inst_0_bits_inst_bits & 32'h3054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_79 = _id_ctrl_decoder_T_78 == 32'h1010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_80 = ibuf_io_inst_0_bits_inst_bits & 32'h1058; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_81 = _id_ctrl_decoder_T_80 == 32'h1040; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_82 = ibuf_io_inst_0_bits_inst_bits & 32'h7044; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_83 = _id_ctrl_decoder_T_82 == 32'h7000; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_84 = ibuf_io_inst_0_bits_inst_bits & 32'h2001074; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_85 = _id_ctrl_decoder_T_84 == 32'h2001030; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_89 = _id_ctrl_decoder_T_79 | _id_ctrl_decoder_T_81 | _id_ctrl_decoder_T_83 |
+ _id_ctrl_decoder_T_85; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_90 = ibuf_io_inst_0_bits_inst_bits & 32'h4054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_91 = _id_ctrl_decoder_T_90 == 32'h40; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_92 = ibuf_io_inst_0_bits_inst_bits & 32'h2058; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_93 = _id_ctrl_decoder_T_92 == 32'h2040; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_95 = _id_ctrl_decoder_T_78 == 32'h3010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_96 = ibuf_io_inst_0_bits_inst_bits & 32'h6054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_97 = _id_ctrl_decoder_T_96 == 32'h6010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_98 = ibuf_io_inst_0_bits_inst_bits & 32'h2002074; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_99 = _id_ctrl_decoder_T_98 == 32'h2002030; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_100 = ibuf_io_inst_0_bits_inst_bits & 32'h40003034; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_101 = _id_ctrl_decoder_T_100 == 32'h40000030; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_102 = ibuf_io_inst_0_bits_inst_bits & 32'h40001054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_103 = _id_ctrl_decoder_T_102 == 32'h40001010; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_110 = _id_ctrl_decoder_T_91 | _id_ctrl_decoder_T_93 | _id_ctrl_decoder_T_95 |
+ _id_ctrl_decoder_T_97 | _id_ctrl_decoder_T_99 | _id_ctrl_decoder_T_101 | _id_ctrl_decoder_T_103; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_111 = ibuf_io_inst_0_bits_inst_bits & 32'h2002054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_112 = _id_ctrl_decoder_T_111 == 32'h2010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_113 = ibuf_io_inst_0_bits_inst_bits & 32'h2034; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_114 = _id_ctrl_decoder_T_113 == 32'h2010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_115 = ibuf_io_inst_0_bits_inst_bits & 32'h40004054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_116 = _id_ctrl_decoder_T_115 == 32'h4010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_117 = ibuf_io_inst_0_bits_inst_bits & 32'h5054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_118 = _id_ctrl_decoder_T_117 == 32'h4010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_119 = ibuf_io_inst_0_bits_inst_bits & 32'h4058; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_120 = _id_ctrl_decoder_T_119 == 32'h4040; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_125 = _id_ctrl_decoder_T_112 | _id_ctrl_decoder_T_114 | _id_ctrl_decoder_T_116 |
+ _id_ctrl_decoder_T_118 | _id_ctrl_decoder_T_120; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_126 = ibuf_io_inst_0_bits_inst_bits & 32'h2006054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_127 = _id_ctrl_decoder_T_126 == 32'h2010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_128 = ibuf_io_inst_0_bits_inst_bits & 32'h6034; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_129 = _id_ctrl_decoder_T_128 == 32'h2010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_130 = ibuf_io_inst_0_bits_inst_bits & 32'h40003054; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_131 = _id_ctrl_decoder_T_130 == 32'h40001010; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_136 = _id_ctrl_decoder_T_127 | _id_ctrl_decoder_T_129 | _id_ctrl_decoder_T_120 |
+ _id_ctrl_decoder_T_101 | _id_ctrl_decoder_T_131; // @[Decode.scala 15:30]
+ wire [3:0] id_ctrl_decoder_13 = {_id_ctrl_decoder_T_136,_id_ctrl_decoder_T_125,_id_ctrl_decoder_T_110,
+ _id_ctrl_decoder_T_89}; // @[Cat.scala 31:58]
+ wire _id_ctrl_decoder_bit_T_317 = _id_ctrl_decoder_bit_T_27 | _id_ctrl_decoder_bit_T_29 | _id_ctrl_decoder_bit_T_31
+ | _id_ctrl_decoder_bit_T_33 | _id_ctrl_decoder_bit_T_35 | _id_ctrl_decoder_bit_T_37 | _id_ctrl_decoder_bit_T_39 |
+ _id_ctrl_decoder_bit_T_41 | _id_ctrl_decoder_bit_T_43 | _id_ctrl_decoder_bit_T_45 | _id_ctrl_decoder_bit_T_47 |
+ _id_ctrl_decoder_bit_T_49 | _id_ctrl_decoder_bit_T_51 | _id_ctrl_decoder_bit_T_53 | _id_ctrl_decoder_bit_T_55 |
+ _id_ctrl_decoder_bit_T_57 | _id_ctrl_decoder_bit_T_59 | _id_ctrl_decoder_bit_T_61 | _id_ctrl_decoder_bit_T_63 |
+ _id_ctrl_decoder_bit_T_65 | _id_ctrl_decoder_bit_T_67 | _id_ctrl_decoder_bit_T_69 | _id_ctrl_decoder_bit_T_71 |
+ _id_ctrl_decoder_bit_T_73 | _id_ctrl_decoder_bit_T_75 | _id_ctrl_decoder_bit_T_122 | _id_ctrl_decoder_bit_T_124 |
+ _id_ctrl_decoder_bit_T_126 | _id_ctrl_decoder_bit_T_128 | _id_ctrl_decoder_bit_T_130 | _id_ctrl_decoder_bit_T_132; // @[Decode.scala 15:30]
+ wire id_ctrl_decoder_14 = _id_ctrl_decoder_bit_T_317 | _id_ctrl_decoder_bit_T_134 | _id_ctrl_decoder_bit_T_136; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_137 = ibuf_io_inst_0_bits_inst_bits & 32'h28; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_138 = _id_ctrl_decoder_T_137 == 32'h20; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_139 = ibuf_io_inst_0_bits_inst_bits & 32'h18000020; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_140 = _id_ctrl_decoder_T_139 == 32'h18000020; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_141 = ibuf_io_inst_0_bits_inst_bits & 32'h20000020; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_142 = _id_ctrl_decoder_T_141 == 32'h20000020; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_145 = _id_ctrl_decoder_T_138 | _id_ctrl_decoder_T_140 | _id_ctrl_decoder_T_142; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_146 = ibuf_io_inst_0_bits_inst_bits & 32'h10000008; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_147 = _id_ctrl_decoder_T_146 == 32'h10000008; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_148 = ibuf_io_inst_0_bits_inst_bits & 32'h40000008; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_149 = _id_ctrl_decoder_T_148 == 32'h40000008; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_151 = _id_ctrl_decoder_T_147 | _id_ctrl_decoder_T_149; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_152 = ibuf_io_inst_0_bits_inst_bits & 32'h8000008; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_153 = _id_ctrl_decoder_T_152 == 32'h8000008; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_154 = ibuf_io_inst_0_bits_inst_bits & 32'h80000008; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_155 = _id_ctrl_decoder_T_154 == 32'h80000008; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_158 = _id_ctrl_decoder_T_153 | _id_ctrl_decoder_T_147 | _id_ctrl_decoder_T_155; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_159 = ibuf_io_inst_0_bits_inst_bits & 32'h18000008; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_160 = _id_ctrl_decoder_T_159 == 32'h8; // @[Decode.scala 14:121]
+ wire [4:0] id_ctrl_decoder_15 = {1'h0,_id_ctrl_decoder_T_160,_id_ctrl_decoder_T_158,_id_ctrl_decoder_T_151,
+ _id_ctrl_decoder_T_145}; // @[Cat.scala 31:58]
+ wire [31:0] _id_ctrl_decoder_T_162 = ibuf_io_inst_0_bits_inst_bits & 32'h2000074; // @[Decode.scala 14:65]
+ wire id_ctrl_decoder_21 = _id_ctrl_decoder_T_162 == 32'h2000030; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_165 = _id_ctrl_decoder_T_46 == 32'h10; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_166 = ibuf_io_inst_0_bits_inst_bits & 32'h1010; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_167 = _id_ctrl_decoder_T_166 == 32'h1010; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_168 = ibuf_io_inst_0_bits_inst_bits & 32'h2008; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_169 = _id_ctrl_decoder_T_168 == 32'h2008; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_170 = ibuf_io_inst_0_bits_inst_bits & 32'h2010; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_171 = _id_ctrl_decoder_T_170 == 32'h2010; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_173 = _id_ctrl_decoder_T_137 == 32'h0; // @[Decode.scala 14:121]
+ wire id_ctrl_decoder_22 = _id_ctrl_decoder_T_30 | _id_ctrl_decoder_T_165 | id_ctrl_decoder_4 | _id_ctrl_decoder_T_167
+ | _id_ctrl_decoder_T_169 | _id_ctrl_decoder_T_171 | _id_ctrl_decoder_T_173; // @[Decode.scala 15:30]
+ wire [31:0] _id_ctrl_decoder_T_180 = ibuf_io_inst_0_bits_inst_bits & 32'h1050; // @[Decode.scala 14:65]
+ wire _id_ctrl_decoder_T_181 = _id_ctrl_decoder_T_180 == 32'h1050; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_184 = _id_ctrl_decoder_T_20 == 32'h2050; // @[Decode.scala 14:121]
+ wire _id_ctrl_decoder_T_187 = _id_ctrl_decoder_T_46 == 32'h50; // @[Decode.scala 14:121]
+ wire [2:0] id_ctrl_decoder_23 = {_id_ctrl_decoder_T_187,_id_ctrl_decoder_T_184,_id_ctrl_decoder_T_181}; // @[Cat.scala 31:58]
+ wire [31:0] _id_ctrl_decoder_T_189 = ibuf_io_inst_0_bits_inst_bits & 32'h3058; // @[Decode.scala 14:65]
+ wire id_ctrl_decoder_24 = _id_ctrl_decoder_T_189 == 32'h1008; // @[Decode.scala 14:121]
+ wire id_ctrl_decoder_25 = _id_ctrl_decoder_T_92 == 32'h8; // @[Decode.scala 14:121]
+ wire [31:0] _id_ctrl_decoder_T_193 = ibuf_io_inst_0_bits_inst_bits & 32'h6048; // @[Decode.scala 14:65]
+ wire id_ctrl_decoder_26 = _id_ctrl_decoder_T_193 == 32'h2008; // @[Decode.scala 14:121]
+ wire [4:0] id_raddr2 = ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 276:72]
+ wire [4:0] id_raddr1 = ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 276:72]
+ wire [4:0] id_waddr = ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala 276:72]
+ reg id_reg_fence; // @[RocketCore.scala 283:25]
+ wire [63:0] _id_rs_T_4 = rf_id_rs_MPORT_data; // @[RocketCore.scala 1068:25]
+ wire [63:0] _id_rs_T_9 = rf_id_rs_MPORT_1_data; // @[RocketCore.scala 1068:25]
+ wire _id_csr_en_T = id_ctrl_decoder_23 == 3'h6; // @[package.scala 15:47]
+ wire _id_csr_en_T_1 = id_ctrl_decoder_23 == 3'h7; // @[package.scala 15:47]
+ wire _id_csr_en_T_2 = id_ctrl_decoder_23 == 3'h5; // @[package.scala 15:47]
+ wire _id_csr_en_T_3 = _id_csr_en_T | _id_csr_en_T_1; // @[package.scala 72:59]
+ wire id_csr_en = _id_csr_en_T | _id_csr_en_T_1 | _id_csr_en_T_2; // @[package.scala 72:59]
+ wire id_system_insn = id_ctrl_decoder_23 == 3'h4; // @[RocketCore.scala 293:36]
+ wire id_csr_ren = _id_csr_en_T_3 & ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala 294:54]
+ wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala 296:54]
+ wire id_csr_flush = id_system_insn | id_csr_en & ~id_csr_ren & csr_io_decode_0_write_flush; // @[RocketCore.scala 296:37]
+ wire _id_illegal_insn_T_4 = id_ctrl_decoder_21 & ~csr_io_status_isa[12]; // @[RocketCore.scala 305:34]
+ wire _id_illegal_insn_T_5 = ~id_ctrl_decoder_0 | _id_illegal_insn_T_4; // @[RocketCore.scala 304:40]
+ wire _id_illegal_insn_T_8 = id_ctrl_decoder_26 & ~csr_io_status_isa[0]; // @[RocketCore.scala 306:17]
+ wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 | _id_illegal_insn_T_8; // @[RocketCore.scala 305:65]
+ wire _id_illegal_insn_T_18 = ~csr_io_status_isa[2]; // @[RocketCore.scala 309:33]
+ wire _id_illegal_insn_T_19 = ibuf_io_inst_0_bits_rvc & ~csr_io_status_isa[2]; // @[RocketCore.scala 309:30]
+ wire _id_illegal_insn_T_20 = _id_illegal_insn_T_9 | _id_illegal_insn_T_19; // @[RocketCore.scala 308:47]
+ wire _id_illegal_insn_T_42 = id_csr_en & (csr_io_decode_0_read_illegal | _id_csr_flush_T &
+ csr_io_decode_0_write_illegal); // @[RocketCore.scala 315:15]
+ wire _id_illegal_insn_T_43 = _id_illegal_insn_T_20 | _id_illegal_insn_T_42; // @[RocketCore.scala 314:81]
+ wire _id_illegal_insn_T_46 = ~ibuf_io_inst_0_bits_rvc & (id_system_insn & csr_io_decode_0_system_illegal); // @[RocketCore.scala 316:31]
+ wire id_illegal_insn = _id_illegal_insn_T_43 | _id_illegal_insn_T_46; // @[RocketCore.scala 315:99]
+ wire id_amo_aq = ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala 321:29]
+ wire id_amo_rl = ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala 322:29]
+ wire [3:0] id_fence_succ = ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala 324:33]
+ wire id_fence_next = id_ctrl_decoder_25 | id_ctrl_decoder_26 & id_amo_aq; // @[RocketCore.scala 325:37]
+ wire id_mem_busy = ~io_dmem_ordered | io_dmem_req_valid; // @[RocketCore.scala 326:38]
+ wire _GEN_0 = ~id_mem_busy ? 1'h0 : id_reg_fence; // @[RocketCore.scala 327:23 283:25 327:38]
+ wire id_do_fence_x9 = id_mem_busy & (id_ctrl_decoder_26 & id_amo_rl | id_ctrl_decoder_24 | id_reg_fence &
+ id_ctrl_decoder_14); // @[RocketCore.scala 332:17]
+ wire id_xcpt = csr_io_interrupt | bpu_io_debug_if | bpu_io_xcpt_if | ibuf_io_inst_0_bits_xcpt0_ae_inst |
+ ibuf_io_inst_0_bits_xcpt1_pf_inst | ibuf_io_inst_0_bits_xcpt1_gf_inst | ibuf_io_inst_0_bits_xcpt1_ae_inst |
+ id_illegal_insn; // @[RocketCore.scala 1021:26]
+ wire [4:0] _T_11 = ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : 5'h2; // @[Mux.scala 47:70]
+ wire [4:0] _T_12 = ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _T_11; // @[Mux.scala 47:70]
+ wire [4:0] _T_13 = ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hc : _T_12; // @[Mux.scala 47:70]
+ wire [4:0] _T_14 = ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _T_13; // @[Mux.scala 47:70]
+ wire [4:0] _T_17 = bpu_io_xcpt_if ? 5'h3 : _T_14; // @[Mux.scala 47:70]
+ wire [4:0] _T_18 = bpu_io_debug_if ? 5'he : _T_17; // @[Mux.scala 47:70]
+ wire [4:0] ex_waddr = ex_reg_inst[11:7]; // @[RocketCore.scala 373:29]
+ wire [4:0] mem_waddr = mem_reg_inst[11:7]; // @[RocketCore.scala 374:31]
+ wire [4:0] wb_waddr = wb_reg_inst[11:7]; // @[RocketCore.scala 375:29]
+ wire _T_27 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala 378:19]
+ wire _T_28 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala 379:20]
+ wire _T_30 = mem_reg_valid & mem_ctrl_wxd & ~mem_ctrl_mem; // @[RocketCore.scala 379:36]
+ wire id_bypass_src_0_0 = 5'h0 == id_raddr1; // @[RocketCore.scala 381:82]
+ wire id_bypass_src_0_1 = _T_27 & ex_waddr == id_raddr1; // @[RocketCore.scala 381:74]
+ wire id_bypass_src_0_2 = _T_30 & mem_waddr == id_raddr1; // @[RocketCore.scala 381:74]
+ wire id_bypass_src_0_3 = _T_28 & mem_waddr == id_raddr1; // @[RocketCore.scala 381:74]
+ wire id_bypass_src_1_0 = 5'h0 == id_raddr2; // @[RocketCore.scala 381:82]
+ wire id_bypass_src_1_1 = _T_27 & ex_waddr == id_raddr2; // @[RocketCore.scala 381:74]
+ wire id_bypass_src_1_2 = _T_30 & mem_waddr == id_raddr2; // @[RocketCore.scala 381:74]
+ wire id_bypass_src_1_3 = _T_28 & mem_waddr == id_raddr2; // @[RocketCore.scala 381:74]
+ reg ex_reg_rs_bypass_0; // @[RocketCore.scala 385:29]
+ reg ex_reg_rs_bypass_1; // @[RocketCore.scala 385:29]
+ reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala 386:26]
+ reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala 386:26]
+ reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala 387:26]
+ reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala 387:26]
+ wire [63:0] _ex_rs_T_1 = ex_reg_rs_lsb_0 == 2'h1 ? mem_reg_wdata : 64'h0; // @[package.scala 32:76]
+ wire [63:0] _ex_rs_T_3 = ex_reg_rs_lsb_0 == 2'h2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala 32:76]
+ wire [63:0] _ex_rs_T_5 = ex_reg_rs_lsb_0 == 2'h3 ? io_dmem_resp_bits_data_word_bypass : _ex_rs_T_3; // @[package.scala 32:76]
+ wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0,ex_reg_rs_lsb_0}; // @[Cat.scala 31:58]
+ wire [63:0] _ex_rs_T_8 = ex_reg_rs_lsb_1 == 2'h1 ? mem_reg_wdata : 64'h0; // @[package.scala 32:76]
+ wire [63:0] _ex_rs_T_10 = ex_reg_rs_lsb_1 == 2'h2 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala 32:76]
+ wire [63:0] _ex_rs_T_12 = ex_reg_rs_lsb_1 == 2'h3 ? io_dmem_resp_bits_data_word_bypass : _ex_rs_T_10; // @[package.scala 32:76]
+ wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1,ex_reg_rs_lsb_1}; // @[Cat.scala 31:58]
+ wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[RocketCore.scala 389:14]
+ wire _ex_imm_sign_T = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala 1083:24]
+ wire _ex_imm_sign_T_2 = ex_reg_inst[31]; // @[RocketCore.scala 1083:53]
+ wire ex_imm_sign = ex_ctrl_sel_imm == 3'h5 ? $signed(1'sh0) : $signed(_ex_imm_sign_T_2); // @[RocketCore.scala 1083:19]
+ wire _ex_imm_b30_20_T = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala 1084:26]
+ wire [10:0] _ex_imm_b30_20_T_2 = ex_reg_inst[30:20]; // @[RocketCore.scala 1084:49]
+ wire [7:0] _ex_imm_b19_12_T_4 = ex_reg_inst[19:12]; // @[RocketCore.scala 1085:73]
+ wire _ex_imm_b11_T_2 = _ex_imm_b30_20_T | _ex_imm_sign_T; // @[RocketCore.scala 1086:33]
+ wire _ex_imm_b11_T_5 = ex_reg_inst[20]; // @[RocketCore.scala 1087:44]
+ wire _ex_imm_b11_T_6 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala 1088:23]
+ wire _ex_imm_b11_T_8 = ex_reg_inst[7]; // @[RocketCore.scala 1088:43]
+ wire _ex_imm_b11_T_9 = ex_ctrl_sel_imm == 3'h1 ? $signed(_ex_imm_b11_T_8) : $signed(ex_imm_sign); // @[RocketCore.scala 1088:18]
+ wire _ex_imm_b11_T_10 = ex_ctrl_sel_imm == 3'h3 ? $signed(_ex_imm_b11_T_5) : $signed(_ex_imm_b11_T_9); // @[RocketCore.scala 1087:18]
+ wire [5:0] ex_imm_b10_5 = _ex_imm_b11_T_2 ? 6'h0 : ex_reg_inst[30:25]; // @[RocketCore.scala 1089:20]
+ wire _ex_imm_b4_1_T_1 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala 1091:24]
+ wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_sign_T ? ex_reg_inst[19:16] : ex_reg_inst[24:21]; // @[RocketCore.scala 1092:19]
+ wire [3:0] _ex_imm_b4_1_T_9 = ex_ctrl_sel_imm == 3'h0 | _ex_imm_b11_T_6 ? ex_reg_inst[11:8] : _ex_imm_b4_1_T_8; // @[RocketCore.scala 1091:19]
+ wire [3:0] ex_imm_b4_1 = _ex_imm_b30_20_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala 1090:19]
+ wire _ex_imm_b0_T_6 = _ex_imm_sign_T & ex_reg_inst[15]; // @[RocketCore.scala 1095:17]
+ wire _ex_imm_b0_T_7 = ex_ctrl_sel_imm == 3'h4 ? ex_reg_inst[20] : _ex_imm_b0_T_6; // @[RocketCore.scala 1094:17]
+ wire ex_imm_b0 = _ex_imm_b4_1_T_1 ? ex_reg_inst[7] : _ex_imm_b0_T_7; // @[RocketCore.scala 1093:17]
+ wire ex_imm_hi_lo_lo = _ex_imm_b30_20_T | _ex_imm_sign_T ? $signed(1'sh0) : $signed(_ex_imm_b11_T_10); // @[Cat.scala 31:58]
+ wire [7:0] ex_imm_hi_lo_hi = ex_ctrl_sel_imm != 3'h2 & ex_ctrl_sel_imm != 3'h3 ? $signed({8{ex_imm_sign}}) : $signed(
+ _ex_imm_b19_12_T_4); // @[Cat.scala 31:58]
+ wire [10:0] ex_imm_hi_hi_lo = ex_ctrl_sel_imm == 3'h2 ? $signed(_ex_imm_b30_20_T_2) : $signed({11{ex_imm_sign}}); // @[Cat.scala 31:58]
+ wire ex_imm_hi_hi_hi = ex_ctrl_sel_imm == 3'h5 ? $signed(1'sh0) : $signed(_ex_imm_sign_T_2); // @[Cat.scala 31:58]
+ wire [31:0] ex_imm = {ex_imm_hi_hi_hi,ex_imm_hi_hi_lo,ex_imm_hi_lo_hi,ex_imm_hi_lo_lo,ex_imm_b10_5,ex_imm_b4_1,
+ ex_imm_b0}; // @[RocketCore.scala 1097:53]
+ wire [63:0] _ex_op1_T = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[RocketCore.scala 392:24]
+ wire [33:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala 393:24]
+ wire [63:0] _ex_op1_T_3 = 2'h1 == ex_ctrl_sel_alu1 ? $signed(_ex_op1_T) : $signed(64'sh0); // @[Mux.scala 81:58]
+ wire [63:0] _ex_op2_T = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[RocketCore.scala 395:24]
+ wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? $signed(4'sh2) : $signed(4'sh4); // @[RocketCore.scala 397:19]
+ wire [63:0] _ex_op2_T_3 = 2'h2 == ex_ctrl_sel_alu2 ? $signed(_ex_op2_T) : $signed(64'sh0); // @[Mux.scala 81:58]
+ wire [63:0] _ex_op2_T_5 = 2'h3 == ex_ctrl_sel_alu2 ? $signed({{32{ex_imm[31]}},ex_imm}) : $signed(_ex_op2_T_3); // @[Mux.scala 81:58]
+ wire _T_134 = id_raddr1 != 5'h0; // @[RocketCore.scala 757:55]
+ wire _T_135 = id_ctrl_decoder_7 & id_raddr1 != 5'h0; // @[RocketCore.scala 757:42]
+ wire _data_hazard_ex_T = id_raddr1 == ex_waddr; // @[RocketCore.scala 777:70]
+ wire _T_136 = id_raddr2 != 5'h0; // @[RocketCore.scala 758:55]
+ wire _T_137 = id_ctrl_decoder_6 & id_raddr2 != 5'h0; // @[RocketCore.scala 758:42]
+ wire _data_hazard_ex_T_2 = id_raddr2 == ex_waddr; // @[RocketCore.scala 777:70]
+ wire _T_139 = id_ctrl_decoder_22 & id_waddr != 5'h0; // @[RocketCore.scala 759:42]
+ wire _data_hazard_ex_T_4 = id_waddr == ex_waddr; // @[RocketCore.scala 777:70]
+ wire _data_hazard_ex_T_7 = _T_135 & _data_hazard_ex_T | _T_137 & _data_hazard_ex_T_2 | _T_139 & _data_hazard_ex_T_4; // @[RocketCore.scala 1030:50]
+ wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala 777:36]
+ wire ex_cannot_bypass = ex_ctrl_csr != 3'h0 | ex_ctrl_jalr | ex_ctrl_mem | ex_ctrl_div; // @[RocketCore.scala 776:94]
+ wire id_ex_hazard = ex_reg_valid & (data_hazard_ex & ex_cannot_bypass); // @[RocketCore.scala 779:35]
+ wire _data_hazard_mem_T = id_raddr1 == mem_waddr; // @[RocketCore.scala 786:72]
+ wire _data_hazard_mem_T_2 = id_raddr2 == mem_waddr; // @[RocketCore.scala 786:72]
+ wire _data_hazard_mem_T_4 = id_waddr == mem_waddr; // @[RocketCore.scala 786:72]
+ wire _data_hazard_mem_T_7 = _T_135 & _data_hazard_mem_T | _T_137 & _data_hazard_mem_T_2 | _T_139 &
+ _data_hazard_mem_T_4; // @[RocketCore.scala 1030:50]
+ wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala 786:38]
+ wire mem_cannot_bypass = mem_ctrl_csr != 3'h0 | mem_ctrl_mem & mem_reg_slow_bypass | mem_ctrl_div; // @[RocketCore.scala 785:100]
+ wire id_mem_hazard = mem_reg_valid & (data_hazard_mem & mem_cannot_bypass); // @[RocketCore.scala 788:37]
+ wire _data_hazard_wb_T = id_raddr1 == wb_waddr; // @[RocketCore.scala 792:70]
+ wire _data_hazard_wb_T_2 = id_raddr2 == wb_waddr; // @[RocketCore.scala 792:70]
+ wire _data_hazard_wb_T_4 = id_waddr == wb_waddr; // @[RocketCore.scala 792:70]
+ wire _data_hazard_wb_T_7 = _T_135 & _data_hazard_wb_T | _T_137 & _data_hazard_wb_T_2 | _T_139 & _data_hazard_wb_T_4; // @[RocketCore.scala 1030:50]
+ wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala 792:36]
+ wire wb_dcache_miss = wb_ctrl_mem & ~io_dmem_resp_valid; // @[RocketCore.scala 509:36]
+ wire wb_set_sboard = wb_ctrl_div | wb_dcache_miss; // @[RocketCore.scala 663:35]
+ wire id_wb_hazard = wb_reg_valid & (data_hazard_wb & wb_set_sboard); // @[RocketCore.scala 794:35]
+ reg [31:0] _r; // @[RocketCore.scala 1047:25]
+ wire [31:0] r = {_r[31:1], 1'h0}; // @[RocketCore.scala 1048:40]
+ wire [31:0] _id_sboard_hazard_T = r >> id_raddr1; // @[RocketCore.scala 1044:35]
+ wire dmem_resp_valid = io_dmem_resp_valid & io_dmem_resp_bits_has_data; // @[RocketCore.scala 673:44]
+ wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay; // @[RocketCore.scala 674:42]
+ wire dmem_resp_xpu = ~io_dmem_resp_bits_tag[0]; // @[RocketCore.scala 670:23]
+ wire ll_wen_x2 = div_io_resp_ready & div_io_resp_valid; // @[Decoupled.scala 50:35]
+ wire ll_wen = dmem_resp_replay & dmem_resp_xpu | ll_wen_x2; // @[RocketCore.scala 689:44 694:12]
+ wire [4:0] dmem_resp_waddr = io_dmem_resp_bits_tag[5:1]; // @[RocketCore.scala 672:46]
+ wire [4:0] ll_waddr = dmem_resp_replay & dmem_resp_xpu ? dmem_resp_waddr : div_io_resp_bits_tag; // @[RocketCore.scala 689:44 693:14]
+ wire _id_sboard_hazard_T_3 = ll_wen & ll_waddr == id_raddr1; // @[RocketCore.scala 769:58]
+ wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T[0] & ~_id_sboard_hazard_T_3; // @[RocketCore.scala 772:77]
+ wire [31:0] _id_sboard_hazard_T_7 = r >> id_raddr2; // @[RocketCore.scala 1044:35]
+ wire _id_sboard_hazard_T_10 = ll_wen & ll_waddr == id_raddr2; // @[RocketCore.scala 769:58]
+ wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_7[0] & ~_id_sboard_hazard_T_10; // @[RocketCore.scala 772:77]
+ wire [31:0] _id_sboard_hazard_T_14 = r >> id_waddr; // @[RocketCore.scala 1044:35]
+ wire _id_sboard_hazard_T_17 = ll_wen & ll_waddr == id_waddr; // @[RocketCore.scala 769:58]
+ wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_14[0] & ~_id_sboard_hazard_T_17; // @[RocketCore.scala 772:77]
+ wire id_sboard_hazard = _T_135 & _id_sboard_hazard_T_5 | _T_137 & _id_sboard_hazard_T_12 | _T_139 &
+ _id_sboard_hazard_T_19; // @[RocketCore.scala 1030:50]
+ wire _ctrl_stalld_T_5 = csr_io_singleStep & (ex_reg_valid | mem_reg_valid | wb_reg_valid); // @[RocketCore.scala 816:23]
+ wire _ctrl_stalld_T_6 = id_ex_hazard | id_mem_hazard | id_wb_hazard | id_sboard_hazard | _ctrl_stalld_T_5; // @[RocketCore.scala 815:71]
+ reg blocked; // @[RocketCore.scala 807:22]
+ wire _dcache_blocked_T = ~io_dmem_perf_grant; // @[RocketCore.scala 809:16]
+ wire dcache_blocked = blocked & ~io_dmem_perf_grant; // @[RocketCore.scala 809:13]
+ wire _ctrl_stalld_T_13 = id_ctrl_decoder_14 & dcache_blocked; // @[RocketCore.scala 819:17]
+ wire _ctrl_stalld_T_14 = _ctrl_stalld_T_6 | _ctrl_stalld_T_13; // @[RocketCore.scala 818:32]
+ wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala 662:29]
+ wire _ctrl_stalld_T_17 = ~wb_wxd; // @[RocketCore.scala 821:65]
+ wire _ctrl_stalld_T_22 = id_ctrl_decoder_21 & (~(div_io_req_ready | div_io_resp_valid & ~wb_wxd) | div_io_req_valid); // @[RocketCore.scala 821:17]
+ wire _ctrl_stalld_T_23 = _ctrl_stalld_T_14 | _ctrl_stalld_T_22; // @[RocketCore.scala 820:34]
+ wire _ctrl_stalld_T_26 = _ctrl_stalld_T_23 | id_do_fence_x9; // @[RocketCore.scala 822:15]
+ wire _ctrl_stalld_T_27 = _ctrl_stalld_T_26 | csr_io_csr_stall; // @[RocketCore.scala 823:17]
+ wire ctrl_stalld = _ctrl_stalld_T_27 | id_reg_pause; // @[RocketCore.scala 824:22]
+ wire ctrl_killd = ~ibuf_io_inst_0_valid | ibuf_io_inst_0_bits_replay | take_pc_mem_wb | ctrl_stalld |
+ csr_io_interrupt; // @[RocketCore.scala 827:104]
+ wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala 437:19]
+ wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala 438:20]
+ wire _ex_reg_replay_T_1 = ~take_pc_mem_wb & ibuf_io_inst_0_valid; // @[RocketCore.scala 438:29]
+ wire _GEN_1 = id_ctrl_decoder_25 & id_fence_succ == 4'h0 | id_reg_pause; // @[RocketCore.scala 116:25 448:{49,64}]
+ wire _GEN_2 = id_fence_next | _GEN_0; // @[RocketCore.scala 449:{26,41}]
+ wire [2:0] _T_35 = {ibuf_io_inst_0_bits_xcpt1_pf_inst,ibuf_io_inst_0_bits_xcpt1_gf_inst,
+ ibuf_io_inst_0_bits_xcpt1_ae_inst}; // @[RocketCore.scala 455:22]
+ wire _GEN_5 = |_T_35 | ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala 444:16 455:34 458:20]
+ wire [2:0] _T_37 = {2'h0,ibuf_io_inst_0_bits_xcpt0_ae_inst}; // @[RocketCore.scala 460:40]
+ wire _GEN_9 = id_xcpt | id_ctrl_decoder_12; // @[RocketCore.scala 443:13 450:20 452:22]
+ wire _T_40 = id_ctrl_decoder_15 == 5'h14; // @[package.scala 15:47]
+ wire _T_41 = id_ctrl_decoder_15 == 5'h15; // @[package.scala 15:47]
+ wire _T_42 = id_ctrl_decoder_15 == 5'h16; // @[package.scala 15:47]
+ wire _T_43 = id_ctrl_decoder_15 == 5'h5; // @[package.scala 15:47]
+ wire _T_46 = _T_40 | _T_41 | _T_42 | _T_43; // @[package.scala 72:59]
+ wire [1:0] _ex_reg_mem_size_T_6 = {_T_136,_T_134}; // @[Cat.scala 31:58]
+ wire do_bypass = id_bypass_src_0_0 | id_bypass_src_0_1 | id_bypass_src_0_2 | id_bypass_src_0_3; // @[RocketCore.scala 482:48]
+ wire [1:0] _bypass_src_T = id_bypass_src_0_2 ? 2'h2 : 2'h3; // @[Mux.scala 47:70]
+ wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala 47:70]
+ wire wb_valid = wb_reg_valid & ~replay_wb_common & ~wb_xcpt; // @[RocketCore.scala 697:45]
+ wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala 698:25]
+ wire rf_wen = wb_wen | ll_wen; // @[RocketCore.scala 699:23]
+ wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala 700:21]
+ wire _T_129 = rf_waddr != 5'h0; // @[RocketCore.scala 1073:16]
+ wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala 701:38]
+ wire [63:0] ll_wdata = div_io_resp_bits_data;
+ wire [63:0] _rf_wdata_T_4 = wb_ctrl_csr != 3'h0 ? csr_io_rw_rdata : wb_reg_wdata; // @[RocketCore.scala 703:21]
+ wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala 702:21]
+ wire [63:0] rf_wdata = dmem_resp_valid & dmem_resp_xpu ? io_dmem_resp_bits_data : _rf_wdata_T_5; // @[RocketCore.scala 701:21]
+ wire [63:0] _GEN_233 = rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala 1068:19 1076:{31,39}]
+ wire [63:0] _GEN_240 = rf_waddr != 5'h0 ? _GEN_233 : _id_rs_T_4; // @[RocketCore.scala 1068:19 1073:29]
+ wire [63:0] id_rs_0 = rf_wen ? _GEN_240 : _id_rs_T_4; // @[RocketCore.scala 706:17 1068:19]
+ wire do_bypass_1 = id_bypass_src_1_0 | id_bypass_src_1_1 | id_bypass_src_1_2 | id_bypass_src_1_3; // @[RocketCore.scala 482:48]
+ wire [1:0] _bypass_src_T_2 = id_bypass_src_1_2 ? 2'h2 : 2'h3; // @[Mux.scala 47:70]
+ wire [63:0] _GEN_234 = rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala 1068:19 1076:{31,39}]
+ wire [63:0] _GEN_241 = rf_waddr != 5'h0 ? _GEN_234 : _id_rs_T_9; // @[RocketCore.scala 1068:19 1073:29]
+ wire [63:0] id_rs_1 = rf_wen ? _GEN_241 : _id_rs_T_9; // @[RocketCore.scala 706:17 1068:19]
+ wire [31:0] inst = ibuf_io_inst_0_bits_rvc ? {{16'd0}, ibuf_io_inst_0_bits_raw[15:0]} : ibuf_io_inst_0_bits_raw; // @[RocketCore.scala 492:21]
+ wire id_load_use = mem_reg_valid & data_hazard_mem & mem_ctrl_mem; // @[RocketCore.scala 789:51]
+ wire ex_pc_valid = ex_reg_valid | ex_reg_replay | ex_reg_xcpt_interrupt; // @[RocketCore.scala 508:51]
+ wire _replay_ex_structural_T = ~io_dmem_req_ready; // @[RocketCore.scala 510:45]
+ wire _replay_ex_structural_T_3 = ex_ctrl_div & ~div_io_req_ready; // @[RocketCore.scala 511:42]
+ wire replay_ex_structural = ex_ctrl_mem & ~io_dmem_req_ready | _replay_ex_structural_T_3; // @[RocketCore.scala 510:64]
+ wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala 512:43]
+ wire replay_ex = ex_reg_replay | ex_reg_valid & (replay_ex_structural | replay_ex_load_use); // @[RocketCore.scala 513:33]
+ wire ctrl_killx = take_pc_mem_wb | replay_ex | ~ex_reg_valid; // @[RocketCore.scala 514:48]
+ wire _ex_slow_bypass_T = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala 516:40]
+ wire ex_slow_bypass = ex_ctrl_mem_cmd == 5'h7 | ex_reg_mem_size < 2'h2; // @[RocketCore.scala 516:50]
+ wire ex_xcpt = ex_reg_xcpt_interrupt | ex_reg_xcpt; // @[RocketCore.scala 520:28]
+ wire mem_pc_valid = mem_reg_valid | mem_reg_replay | mem_reg_xcpt_interrupt; // @[RocketCore.scala 526:54]
+ wire mem_br_target_sign = mem_reg_inst[31]; // @[RocketCore.scala 1083:53]
+ wire [5:0] mem_br_target_b10_5 = mem_reg_inst[30:25]; // @[RocketCore.scala 1089:66]
+ wire [3:0] mem_br_target_b4_1 = mem_reg_inst[11:8]; // @[RocketCore.scala 1091:57]
+ wire mem_br_target_hi_lo_lo = mem_reg_inst[7]; // @[Cat.scala 31:58]
+ wire [7:0] mem_br_target_hi_lo_hi = {8{mem_br_target_sign}}; // @[Cat.scala 31:58]
+ wire [10:0] mem_br_target_hi_hi_lo = {11{mem_br_target_sign}}; // @[Cat.scala 31:58]
+ wire mem_br_target_hi_hi_hi = mem_reg_inst[31]; // @[Cat.scala 31:58]
+ wire [31:0] _mem_br_target_T_3 = {mem_br_target_hi_hi_hi,mem_br_target_hi_hi_lo,mem_br_target_hi_lo_hi,
+ mem_br_target_hi_lo_lo,mem_br_target_b10_5,mem_br_target_b4_1,1'h0}; // @[RocketCore.scala 1097:53]
+ wire mem_br_target_hi_lo_lo_1 = mem_reg_inst[20]; // @[Cat.scala 31:58]
+ wire [7:0] mem_br_target_hi_lo_hi_1 = mem_reg_inst[19:12]; // @[Cat.scala 31:58]
+ wire [31:0] _mem_br_target_T_5 = {mem_br_target_hi_hi_hi,mem_br_target_hi_hi_lo,mem_br_target_hi_lo_hi_1,
+ mem_br_target_hi_lo_lo_1,mem_br_target_b10_5,mem_reg_inst[24:21],1'h0}; // @[RocketCore.scala 1097:53]
+ wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? $signed(4'sh2) : $signed(4'sh4); // @[RocketCore.scala 530:8]
+ wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? $signed(_mem_br_target_T_5) : $signed({{28{_mem_br_target_T_6[3]}},
+ _mem_br_target_T_6}); // @[RocketCore.scala 529:8]
+ wire [31:0] _mem_br_target_T_8 = _mem_cfi_taken_T ? $signed(_mem_br_target_T_3) : $signed(_mem_br_target_T_7); // @[RocketCore.scala 528:8]
+ wire [33:0] _GEN_253 = {{2{_mem_br_target_T_8[31]}},_mem_br_target_T_8}; // @[RocketCore.scala 527:41]
+ wire [33:0] mem_br_target = $signed(mem_reg_pc) + $signed(_GEN_253); // @[RocketCore.scala 527:41]
+ wire [63:0] _mem_npc_a_T = mem_reg_wdata; // @[RocketCore.scala 1035:16]
+ wire [30:0] a = _mem_npc_a_T[63:33]; // @[RocketCore.scala 1035:23]
+ wire msb = $signed(a) == 31'sh0 | $signed(a) == -31'sh1 ? mem_reg_wdata[33] : ~mem_reg_wdata[32]; // @[RocketCore.scala 1036:18]
+ wire [33:0] _mem_npc_T_3 = {msb,mem_reg_wdata[32:0]}; // @[RocketCore.scala 531:106]
+ wire [33:0] _mem_npc_T_4 = mem_ctrl_jalr ? $signed(_mem_npc_T_3) : $signed(mem_br_target); // @[RocketCore.scala 531:21]
+ wire [33:0] mem_npc = $signed(_mem_npc_T_4) & -34'sh2; // @[RocketCore.scala 531:141]
+ wire _mem_wrong_npc_T_3 = ibuf_io_inst_0_valid | ibuf_io_imem_valid ? mem_npc != ibuf_io_pc : 1'h1; // @[RocketCore.scala 534:8]
+ wire mem_wrong_npc = ex_pc_valid ? mem_npc != ex_reg_pc : _mem_wrong_npc_T_3; // @[RocketCore.scala 533:8]
+ wire mem_npc_misaligned = _id_illegal_insn_T_18 & mem_npc[1]; // @[RocketCore.scala 535:56]
+ wire [63:0] mem_int_wdata = _take_pc_mem_T & (mem_ctrl_jalr ^ mem_npc_misaligned) ? $signed({{30{mem_br_target[33]}},
+ mem_br_target}) : $signed(mem_reg_wdata); // @[RocketCore.scala 536:119]
+ wire mem_cfi = mem_ctrl_branch | mem_ctrl_jalr | mem_ctrl_jal; // @[RocketCore.scala 537:50]
+ wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala 543:20]
+ wire _mem_reg_load_T = ex_ctrl_mem_cmd == 5'h0; // @[package.scala 15:47]
+ wire _mem_reg_load_T_1 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala 15:47]
+ wire _mem_reg_load_T_2 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala 15:47]
+ wire _mem_reg_load_T_6 = _mem_reg_load_T | _mem_reg_load_T_1 | _mem_reg_load_T_2 | _ex_slow_bypass_T; // @[package.scala 72:59]
+ wire _mem_reg_load_T_7 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala 15:47]
+ wire _mem_reg_load_T_8 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala 15:47]
+ wire _mem_reg_load_T_9 = ex_ctrl_mem_cmd == 5'ha; // @[package.scala 15:47]
+ wire _mem_reg_load_T_10 = ex_ctrl_mem_cmd == 5'hb; // @[package.scala 15:47]
+ wire _mem_reg_load_T_13 = _mem_reg_load_T_7 | _mem_reg_load_T_8 | _mem_reg_load_T_9 | _mem_reg_load_T_10; // @[package.scala 72:59]
+ wire _mem_reg_load_T_14 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala 15:47]
+ wire _mem_reg_load_T_15 = ex_ctrl_mem_cmd == 5'hc; // @[package.scala 15:47]
+ wire _mem_reg_load_T_16 = ex_ctrl_mem_cmd == 5'hd; // @[package.scala 15:47]
+ wire _mem_reg_load_T_17 = ex_ctrl_mem_cmd == 5'he; // @[package.scala 15:47]
+ wire _mem_reg_load_T_18 = ex_ctrl_mem_cmd == 5'hf; // @[package.scala 15:47]
+ wire _mem_reg_load_T_22 = _mem_reg_load_T_14 | _mem_reg_load_T_15 | _mem_reg_load_T_16 | _mem_reg_load_T_17 |
+ _mem_reg_load_T_18; // @[package.scala 72:59]
+ wire _mem_reg_load_T_23 = _mem_reg_load_T_13 | _mem_reg_load_T_22; // @[Consts.scala 82:44]
+ wire _mem_reg_load_T_24 = _mem_reg_load_T_6 | _mem_reg_load_T_23; // @[Consts.scala 84:68]
+ wire _mem_reg_store_T_22 = ex_ctrl_mem_cmd == 5'h1 | ex_ctrl_mem_cmd == 5'h11 | _ex_slow_bypass_T |
+ _mem_reg_load_T_23; // @[Consts.scala 85:76]
+ wire [63:0] _mem_reg_wdata_T = alu_io_out; // @[RocketCore.scala 571:25]
+ wire [63:0] _mem_reg_rs2_T_4 = {ex_rs_1[7:0],ex_rs_1[7:0],ex_rs_1[7:0],ex_rs_1[7:0],ex_rs_1[7:0],ex_rs_1[7:0],ex_rs_1[
+ 7:0],ex_rs_1[7:0]}; // @[Cat.scala 31:58]
+ wire [63:0] _mem_reg_rs2_T_8 = {ex_rs_1[15:0],ex_rs_1[15:0],ex_rs_1[15:0],ex_rs_1[15:0]}; // @[Cat.scala 31:58]
+ wire [63:0] _mem_reg_rs2_T_11 = {ex_rs_1[31:0],ex_rs_1[31:0]}; // @[Cat.scala 31:58]
+ wire [63:0] _mem_reg_rs2_T_12 = ex_reg_mem_size == 2'h2 ? _mem_reg_rs2_T_11 : ex_rs_1; // @[AMOALU.scala 26:13]
+ wire [63:0] _mem_reg_rs2_T_13 = ex_reg_mem_size == 2'h1 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala 26:13]
+ wire _GEN_79 = ex_ctrl_jalr & csr_io_status_debug | ex_ctrl_fence_i; // @[RocketCore.scala 553:14 578:48 580:24]
+ wire _GEN_80 = ex_ctrl_jalr & csr_io_status_debug | ex_reg_flush_pipe; // @[RocketCore.scala 561:24 578:48 581:26]
+ wire mem_breakpoint = mem_reg_load & bpu_io_xcpt_ld | mem_reg_store & bpu_io_xcpt_st; // @[RocketCore.scala 585:57]
+ wire mem_debug_breakpoint = mem_reg_load & bpu_io_debug_ld | mem_reg_store & bpu_io_debug_st; // @[RocketCore.scala 586:64]
+ wire mem_ldst_xcpt = mem_debug_breakpoint | mem_breakpoint; // @[RocketCore.scala 1021:26]
+ wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'he : 4'h3; // @[Mux.scala 47:70]
+ wire _T_70 = mem_reg_xcpt_interrupt | mem_reg_xcpt; // @[RocketCore.scala 592:29]
+ wire _T_71 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala 593:20]
+ wire _T_72 = mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala 594:20]
+ wire mem_xcpt = _T_70 | _T_71 | _T_72; // @[RocketCore.scala 1021:26]
+ wire [3:0] _T_74 = _T_71 ? 4'h0 : mem_ldst_cause; // @[Mux.scala 47:70]
+ wire dcache_kill_mem = _T_28 & io_dmem_replay_next; // @[RocketCore.scala 603:55]
+ wire replay_mem = dcache_kill_mem | mem_reg_replay; // @[RocketCore.scala 605:37]
+ wire killm_common = dcache_kill_mem | take_pc_wb | mem_reg_xcpt | ~mem_reg_valid; // @[RocketCore.scala 606:68]
+ reg div_io_kill_REG; // @[RocketCore.scala 607:37]
+ wire ctrl_killm = killm_common | mem_xcpt; // @[RocketCore.scala 608:33]
+ wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala 611:19]
+ wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala 612:34]
+ wire [2:0] _T_113 = _T_103 ? 3'h6 : 3'h4; // @[Mux.scala 47:70]
+ wire [2:0] _T_114 = _T_101 ? 3'h5 : _T_113; // @[Mux.scala 47:70]
+ wire [2:0] _T_115 = _T_99 ? 3'h7 : _T_114; // @[Mux.scala 47:70]
+ wire [4:0] _T_116 = {{2'd0}, _T_115}; // @[Mux.scala 47:70]
+ wire [4:0] _T_118 = _T_93 ? 5'hd : _T_116; // @[Mux.scala 47:70]
+ wire [4:0] _T_119 = _T_91 ? 5'hf : _T_118; // @[Mux.scala 47:70]
+ wire [15:0] _csr_io_inst_0_T_3 = &wb_reg_raw_inst[1:0] ? wb_reg_inst[31:16] : 16'h0; // @[RocketCore.scala 714:50]
+ wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala 723:24]
+ wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala 15:47]
+ wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala 15:47]
+ wire _tval_any_addr_T_2 = wb_reg_cause == 64'hc; // @[package.scala 15:47]
+ wire _tval_any_addr_T_3 = wb_reg_cause == 64'h14; // @[package.scala 15:47]
+ wire _tval_any_addr_T_6 = _tval_any_addr_T | _tval_any_addr_T_1 | _tval_any_addr_T_2 | _tval_any_addr_T_3; // @[package.scala 72:59]
+ wire tval_any_addr = tval_dmem_addr | _tval_any_addr_T_6; // @[RocketCore.scala 724:38]
+ wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala 726:32]
+ wire tval_valid = wb_xcpt & (tval_any_addr | tval_inst); // @[RocketCore.scala 727:28]
+ wire [63:0] _csr_io_tval_a_T = wb_reg_wdata; // @[RocketCore.scala 1035:16]
+ wire [30:0] a_1 = _csr_io_tval_a_T[63:33]; // @[RocketCore.scala 1035:23]
+ wire msb_1 = $signed(a_1) == 31'sh0 | $signed(a_1) == -31'sh1 ? wb_reg_wdata[33] : ~wb_reg_wdata[32]; // @[RocketCore.scala 1036:18]
+ wire [33:0] _csr_io_tval_T_1 = {msb_1,wb_reg_wdata[32:0]}; // @[Cat.scala 31:58]
+ wire htval_valid_imem = wb_reg_xcpt & _tval_any_addr_T_3; // @[RocketCore.scala 731:40]
+ wire _csr_io_htval_T_3 = ~reset; // @[RocketCore.scala 733:11]
+ wire [2:0] _csr_io_rw_cmd_T = wb_reg_valid ? 3'h0 : 3'h4; // @[CSR.scala 167:15]
+ wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala 167:11]
+ wire [31:0] _T_140 = 32'h1 << ll_waddr; // @[RocketCore.scala 1051:62]
+ wire [31:0] _T_141 = ll_wen ? _T_140 : 32'h0; // @[RocketCore.scala 1051:49]
+ wire [31:0] _T_142 = ~_T_141; // @[RocketCore.scala 1043:64]
+ wire [31:0] _T_143 = r & _T_142; // @[RocketCore.scala 1043:62]
+ wire _T_145 = wb_set_sboard & wb_wen; // @[RocketCore.scala 773:28]
+ wire [31:0] _T_146 = 32'h1 << wb_waddr; // @[RocketCore.scala 1051:62]
+ wire [31:0] _T_147 = _T_145 ? _T_146 : 32'h0; // @[RocketCore.scala 1051:49]
+ wire [31:0] _T_148 = _T_143 | _T_147; // @[RocketCore.scala 1042:60]
+ wire _T_149 = ll_wen | _T_145; // @[RocketCore.scala 1054:17]
+ wire [33:0] _io_imem_req_bits_pc_T_1 = replay_wb_common ? wb_reg_pc : mem_npc; // @[RocketCore.scala 833:8]
+ wire [5:0] ex_dcache_tag = {ex_waddr,1'h0}; // @[Cat.scala 31:58]
+ wire [30:0] a_2 = _ex_op1_T[63:33]; // @[RocketCore.scala 1035:23]
+ wire msb_2 = $signed(a_2) == 31'sh0 | $signed(a_2) == -31'sh1 ? alu_io_adder_out[33] : ~alu_io_adder_out[32]; // @[RocketCore.scala 1036:18]
+ wire unpause = csr_io_time[4:0] == 5'h0 | csr_io_inhibit_cycle | take_pc_mem_wb; // @[RocketCore.scala 907:116]
+ wire coreMonitorBundle_valid = csr_io_trace_0_valid & ~csr_io_trace_0_exception; // @[RocketCore.scala 935:52]
+ wire [33:0] _coreMonitorBundle_pc_T = csr_io_trace_0_iaddr; // @[RocketCore.scala 936:48]
+ wire [29:0] _coreMonitorBundle_pc_T_3 = _coreMonitorBundle_pc_T[33] ? 30'h3fffffff : 30'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] coreMonitorBundle_pc = {_coreMonitorBundle_pc_T_3,_coreMonitorBundle_pc_T}; // @[Cat.scala 31:58]
+ wire coreMonitorBundle_wrenx = wb_wen & ~wb_set_sboard; // @[RocketCore.scala 937:37]
+ reg [63:0] coreMonitorBundle_rd0val_x23; // @[RocketCore.scala 942:43]
+ reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala 942:34]
+ reg [63:0] coreMonitorBundle_rd1val_x29; // @[RocketCore.scala 944:43]
+ reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala 944:34]
+ wire [4:0] _T_151 = wb_ctrl_wxd ? wb_waddr : 5'h0; // @[RocketCore.scala 980:13]
+ wire [63:0] _T_152 = coreMonitorBundle_wrenx ? rf_wdata : 64'h0; // @[RocketCore.scala 981:13]
+ wire [4:0] _T_154 = wb_ctrl_rxs1 ? wb_reg_inst[19:15] : 5'h0; // @[RocketCore.scala 983:13]
+ wire [63:0] _T_156 = wb_ctrl_rxs1 ? coreMonitorBundle_rd0val_REG : 64'h0; // @[RocketCore.scala 984:13]
+ wire [4:0] _T_158 = wb_ctrl_rxs2 ? wb_reg_inst[24:20] : 5'h0; // @[RocketCore.scala 985:13]
+ wire [63:0] _T_160 = wb_ctrl_rxs2 ? coreMonitorBundle_rd1val_REG : 64'h0; // @[RocketCore.scala 986:13]
+ wire [31:0] coreMonitorBundle_inst = csr_io_trace_0_insn; // @[RocketCore.scala 929:31 945:26]
+ IBuf ibuf ( // @[RocketCore.scala 263:20]
+ .clock(ibuf_clock),
+ .reset(ibuf_reset),
+ .io_imem_ready(ibuf_io_imem_ready),
+ .io_imem_valid(ibuf_io_imem_valid),
+ .io_imem_bits_pc(ibuf_io_imem_bits_pc),
+ .io_imem_bits_data(ibuf_io_imem_bits_data),
+ .io_imem_bits_xcpt_ae_inst(ibuf_io_imem_bits_xcpt_ae_inst),
+ .io_imem_bits_replay(ibuf_io_imem_bits_replay),
+ .io_kill(ibuf_io_kill),
+ .io_pc(ibuf_io_pc),
+ .io_inst_0_ready(ibuf_io_inst_0_ready),
+ .io_inst_0_valid(ibuf_io_inst_0_valid),
+ .io_inst_0_bits_xcpt0_ae_inst(ibuf_io_inst_0_bits_xcpt0_ae_inst),
+ .io_inst_0_bits_xcpt1_pf_inst(ibuf_io_inst_0_bits_xcpt1_pf_inst),
+ .io_inst_0_bits_xcpt1_gf_inst(ibuf_io_inst_0_bits_xcpt1_gf_inst),
+ .io_inst_0_bits_xcpt1_ae_inst(ibuf_io_inst_0_bits_xcpt1_ae_inst),
+ .io_inst_0_bits_replay(ibuf_io_inst_0_bits_replay),
+ .io_inst_0_bits_rvc(ibuf_io_inst_0_bits_rvc),
+ .io_inst_0_bits_inst_bits(ibuf_io_inst_0_bits_inst_bits),
+ .io_inst_0_bits_inst_rd(ibuf_io_inst_0_bits_inst_rd),
+ .io_inst_0_bits_inst_rs1(ibuf_io_inst_0_bits_inst_rs1),
+ .io_inst_0_bits_inst_rs2(ibuf_io_inst_0_bits_inst_rs2),
+ .io_inst_0_bits_raw(ibuf_io_inst_0_bits_raw)
+ );
+ CSRFile csr ( // @[RocketCore.scala 291:19]
+ .clock(csr_clock),
+ .reset(csr_reset),
+ .io_ungated_clock(csr_io_ungated_clock),
+ .io_interrupts_debug(csr_io_interrupts_debug),
+ .io_interrupts_mtip(csr_io_interrupts_mtip),
+ .io_interrupts_msip(csr_io_interrupts_msip),
+ .io_interrupts_meip(csr_io_interrupts_meip),
+ .io_hartid(csr_io_hartid),
+ .io_rw_addr(csr_io_rw_addr),
+ .io_rw_cmd(csr_io_rw_cmd),
+ .io_rw_rdata(csr_io_rw_rdata),
+ .io_rw_wdata(csr_io_rw_wdata),
+ .io_decode_0_inst(csr_io_decode_0_inst),
+ .io_decode_0_fp_illegal(csr_io_decode_0_fp_illegal),
+ .io_decode_0_fp_csr(csr_io_decode_0_fp_csr),
+ .io_decode_0_read_illegal(csr_io_decode_0_read_illegal),
+ .io_decode_0_write_illegal(csr_io_decode_0_write_illegal),
+ .io_decode_0_write_flush(csr_io_decode_0_write_flush),
+ .io_decode_0_system_illegal(csr_io_decode_0_system_illegal),
+ .io_csr_stall(csr_io_csr_stall),
+ .io_eret(csr_io_eret),
+ .io_singleStep(csr_io_singleStep),
+ .io_status_debug(csr_io_status_debug),
+ .io_status_cease(csr_io_status_cease),
+ .io_status_wfi(csr_io_status_wfi),
+ .io_status_isa(csr_io_status_isa),
+ .io_status_dprv(csr_io_status_dprv),
+ .io_status_dv(csr_io_status_dv),
+ .io_status_prv(csr_io_status_prv),
+ .io_status_v(csr_io_status_v),
+ .io_status_sd(csr_io_status_sd),
+ .io_status_zero2(csr_io_status_zero2),
+ .io_status_mpv(csr_io_status_mpv),
+ .io_status_gva(csr_io_status_gva),
+ .io_status_mbe(csr_io_status_mbe),
+ .io_status_sbe(csr_io_status_sbe),
+ .io_status_sxl(csr_io_status_sxl),
+ .io_status_uxl(csr_io_status_uxl),
+ .io_status_sd_rv32(csr_io_status_sd_rv32),
+ .io_status_zero1(csr_io_status_zero1),
+ .io_status_tsr(csr_io_status_tsr),
+ .io_status_tw(csr_io_status_tw),
+ .io_status_tvm(csr_io_status_tvm),
+ .io_status_mxr(csr_io_status_mxr),
+ .io_status_sum(csr_io_status_sum),
+ .io_status_mprv(csr_io_status_mprv),
+ .io_status_xs(csr_io_status_xs),
+ .io_status_fs(csr_io_status_fs),
+ .io_status_mpp(csr_io_status_mpp),
+ .io_status_vs(csr_io_status_vs),
+ .io_status_spp(csr_io_status_spp),
+ .io_status_mpie(csr_io_status_mpie),
+ .io_status_ube(csr_io_status_ube),
+ .io_status_spie(csr_io_status_spie),
+ .io_status_upie(csr_io_status_upie),
+ .io_status_mie(csr_io_status_mie),
+ .io_status_hie(csr_io_status_hie),
+ .io_status_sie(csr_io_status_sie),
+ .io_status_uie(csr_io_status_uie),
+ .io_evec(csr_io_evec),
+ .io_exception(csr_io_exception),
+ .io_retire(csr_io_retire),
+ .io_cause(csr_io_cause),
+ .io_pc(csr_io_pc),
+ .io_tval(csr_io_tval),
+ .io_gva(csr_io_gva),
+ .io_time(csr_io_time),
+ .io_interrupt(csr_io_interrupt),
+ .io_interrupt_cause(csr_io_interrupt_cause),
+ .io_bp_0_control_action(csr_io_bp_0_control_action),
+ .io_bp_0_control_tmatch(csr_io_bp_0_control_tmatch),
+ .io_bp_0_control_x(csr_io_bp_0_control_x),
+ .io_bp_0_control_w(csr_io_bp_0_control_w),
+ .io_bp_0_control_r(csr_io_bp_0_control_r),
+ .io_bp_0_address(csr_io_bp_0_address),
+ .io_pmp_0_cfg_l(csr_io_pmp_0_cfg_l),
+ .io_pmp_0_cfg_a(csr_io_pmp_0_cfg_a),
+ .io_pmp_0_cfg_x(csr_io_pmp_0_cfg_x),
+ .io_pmp_0_cfg_w(csr_io_pmp_0_cfg_w),
+ .io_pmp_0_cfg_r(csr_io_pmp_0_cfg_r),
+ .io_pmp_0_addr(csr_io_pmp_0_addr),
+ .io_pmp_0_mask(csr_io_pmp_0_mask),
+ .io_pmp_1_cfg_l(csr_io_pmp_1_cfg_l),
+ .io_pmp_1_cfg_a(csr_io_pmp_1_cfg_a),
+ .io_pmp_1_cfg_x(csr_io_pmp_1_cfg_x),
+ .io_pmp_1_cfg_w(csr_io_pmp_1_cfg_w),
+ .io_pmp_1_cfg_r(csr_io_pmp_1_cfg_r),
+ .io_pmp_1_addr(csr_io_pmp_1_addr),
+ .io_pmp_1_mask(csr_io_pmp_1_mask),
+ .io_pmp_2_cfg_l(csr_io_pmp_2_cfg_l),
+ .io_pmp_2_cfg_a(csr_io_pmp_2_cfg_a),
+ .io_pmp_2_cfg_x(csr_io_pmp_2_cfg_x),
+ .io_pmp_2_cfg_w(csr_io_pmp_2_cfg_w),
+ .io_pmp_2_cfg_r(csr_io_pmp_2_cfg_r),
+ .io_pmp_2_addr(csr_io_pmp_2_addr),
+ .io_pmp_2_mask(csr_io_pmp_2_mask),
+ .io_pmp_3_cfg_l(csr_io_pmp_3_cfg_l),
+ .io_pmp_3_cfg_a(csr_io_pmp_3_cfg_a),
+ .io_pmp_3_cfg_x(csr_io_pmp_3_cfg_x),
+ .io_pmp_3_cfg_w(csr_io_pmp_3_cfg_w),
+ .io_pmp_3_cfg_r(csr_io_pmp_3_cfg_r),
+ .io_pmp_3_addr(csr_io_pmp_3_addr),
+ .io_pmp_3_mask(csr_io_pmp_3_mask),
+ .io_pmp_4_cfg_l(csr_io_pmp_4_cfg_l),
+ .io_pmp_4_cfg_a(csr_io_pmp_4_cfg_a),
+ .io_pmp_4_cfg_x(csr_io_pmp_4_cfg_x),
+ .io_pmp_4_cfg_w(csr_io_pmp_4_cfg_w),
+ .io_pmp_4_cfg_r(csr_io_pmp_4_cfg_r),
+ .io_pmp_4_addr(csr_io_pmp_4_addr),
+ .io_pmp_4_mask(csr_io_pmp_4_mask),
+ .io_pmp_5_cfg_l(csr_io_pmp_5_cfg_l),
+ .io_pmp_5_cfg_a(csr_io_pmp_5_cfg_a),
+ .io_pmp_5_cfg_x(csr_io_pmp_5_cfg_x),
+ .io_pmp_5_cfg_w(csr_io_pmp_5_cfg_w),
+ .io_pmp_5_cfg_r(csr_io_pmp_5_cfg_r),
+ .io_pmp_5_addr(csr_io_pmp_5_addr),
+ .io_pmp_5_mask(csr_io_pmp_5_mask),
+ .io_pmp_6_cfg_l(csr_io_pmp_6_cfg_l),
+ .io_pmp_6_cfg_a(csr_io_pmp_6_cfg_a),
+ .io_pmp_6_cfg_x(csr_io_pmp_6_cfg_x),
+ .io_pmp_6_cfg_w(csr_io_pmp_6_cfg_w),
+ .io_pmp_6_cfg_r(csr_io_pmp_6_cfg_r),
+ .io_pmp_6_addr(csr_io_pmp_6_addr),
+ .io_pmp_6_mask(csr_io_pmp_6_mask),
+ .io_pmp_7_cfg_l(csr_io_pmp_7_cfg_l),
+ .io_pmp_7_cfg_a(csr_io_pmp_7_cfg_a),
+ .io_pmp_7_cfg_x(csr_io_pmp_7_cfg_x),
+ .io_pmp_7_cfg_w(csr_io_pmp_7_cfg_w),
+ .io_pmp_7_cfg_r(csr_io_pmp_7_cfg_r),
+ .io_pmp_7_addr(csr_io_pmp_7_addr),
+ .io_pmp_7_mask(csr_io_pmp_7_mask),
+ .io_inhibit_cycle(csr_io_inhibit_cycle),
+ .io_inst_0(csr_io_inst_0),
+ .io_trace_0_valid(csr_io_trace_0_valid),
+ .io_trace_0_iaddr(csr_io_trace_0_iaddr),
+ .io_trace_0_insn(csr_io_trace_0_insn),
+ .io_trace_0_exception(csr_io_trace_0_exception),
+ .io_customCSRs_0_value(csr_io_customCSRs_0_value)
+ );
+ BreakpointUnit bpu ( // @[RocketCore.scala 334:19]
+ .io_status_debug(bpu_io_status_debug),
+ .io_bp_0_control_action(bpu_io_bp_0_control_action),
+ .io_bp_0_control_tmatch(bpu_io_bp_0_control_tmatch),
+ .io_bp_0_control_x(bpu_io_bp_0_control_x),
+ .io_bp_0_control_w(bpu_io_bp_0_control_w),
+ .io_bp_0_control_r(bpu_io_bp_0_control_r),
+ .io_bp_0_address(bpu_io_bp_0_address),
+ .io_pc(bpu_io_pc),
+ .io_ea(bpu_io_ea),
+ .io_xcpt_if(bpu_io_xcpt_if),
+ .io_xcpt_ld(bpu_io_xcpt_ld),
+ .io_xcpt_st(bpu_io_xcpt_st),
+ .io_debug_if(bpu_io_debug_if),
+ .io_debug_ld(bpu_io_debug_ld),
+ .io_debug_st(bpu_io_debug_st)
+ );
+ ALU alu ( // @[RocketCore.scala 399:19]
+ .io_dw(alu_io_dw),
+ .io_fn(alu_io_fn),
+ .io_in2(alu_io_in2),
+ .io_in1(alu_io_in1),
+ .io_out(alu_io_out),
+ .io_adder_out(alu_io_adder_out),
+ .io_cmp_out(alu_io_cmp_out)
+ );
+ MulDiv div ( // @[RocketCore.scala 423:19]
+ .clock(div_clock),
+ .reset(div_reset),
+ .io_req_ready(div_io_req_ready),
+ .io_req_valid(div_io_req_valid),
+ .io_req_bits_fn(div_io_req_bits_fn),
+ .io_req_bits_dw(div_io_req_bits_dw),
+ .io_req_bits_in1(div_io_req_bits_in1),
+ .io_req_bits_in2(div_io_req_bits_in2),
+ .io_req_bits_tag(div_io_req_bits_tag),
+ .io_kill(div_io_kill),
+ .io_resp_ready(div_io_resp_ready),
+ .io_resp_valid(div_io_resp_valid),
+ .io_resp_bits_data(div_io_resp_bits_data),
+ .io_resp_bits_tag(div_io_resp_bits_tag)
+ );
+ PlusArgTimeout PlusArgTimeout ( // @[PlusArg.scala 89:11]
+ .clock(PlusArgTimeout_clock),
+ .reset(PlusArgTimeout_reset),
+ .io_count(PlusArgTimeout_io_count)
+ );
+ assign rf_id_rs_MPORT_en = 1'h1;
+ assign rf_id_rs_MPORT_addr = ~id_raddr1;
+ `ifndef RANDOMIZE_GARBAGE_ASSIGN
+ assign rf_id_rs_MPORT_data = rf[rf_id_rs_MPORT_addr]; // @[RocketCore.scala 1061:15]
+ `else
+ assign rf_id_rs_MPORT_data = rf_id_rs_MPORT_addr >= 5'h1f ? _RAND_1[63:0] : rf[rf_id_rs_MPORT_addr]; // @[RocketCore.scala 1061:15]
+ `endif // RANDOMIZE_GARBAGE_ASSIGN
+ assign rf_id_rs_MPORT_1_en = 1'h1;
+ assign rf_id_rs_MPORT_1_addr = ~id_raddr2;
+ `ifndef RANDOMIZE_GARBAGE_ASSIGN
+ assign rf_id_rs_MPORT_1_data = rf[rf_id_rs_MPORT_1_addr]; // @[RocketCore.scala 1061:15]
+ `else
+ assign rf_id_rs_MPORT_1_data = rf_id_rs_MPORT_1_addr >= 5'h1f ? _RAND_2[63:0] : rf[rf_id_rs_MPORT_1_addr]; // @[RocketCore.scala 1061:15]
+ `endif // RANDOMIZE_GARBAGE_ASSIGN
+ assign rf_MPORT_data = _rf_wdata_T ? io_dmem_resp_bits_data : _rf_wdata_T_5;
+ assign rf_MPORT_addr = ~rf_waddr;
+ assign rf_MPORT_mask = 1'h1;
+ assign rf_MPORT_en = rf_wen & _T_129;
+ assign io_imem_might_request = imem_might_request_reg; // @[RocketCore.scala 836:25]
+ assign io_imem_req_valid = take_pc_wb | take_pc_mem; // @[RocketCore.scala 259:35]
+ assign io_imem_req_bits_pc = wb_xcpt | csr_io_eret ? csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala 832:8]
+ assign io_imem_req_bits_speculative = ~take_pc_wb; // @[RocketCore.scala 830:35]
+ assign io_imem_resp_ready = ibuf_io_imem_ready; // @[RocketCore.scala 267:16]
+ assign io_imem_btb_update_valid = mem_reg_valid & _wb_reg_replay_T & mem_wrong_npc & (~mem_cfi | mem_cfi_taken); // @[RocketCore.scala 851:77]
+ assign io_imem_bht_update_valid = mem_reg_valid & _wb_reg_replay_T; // @[RocketCore.scala 863:45]
+ assign io_imem_flush_icache = wb_reg_valid & wb_ctrl_fence_i & ~io_dmem_s2_nack; // @[RocketCore.scala 835:59]
+ assign io_dmem_req_valid = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala 881:41]
+ assign io_dmem_req_bits_addr = {msb_2,alu_io_adder_out[32:0]}; // @[Cat.scala 31:58]
+ assign io_dmem_req_bits_tag = {{1'd0}, ex_dcache_tag}; // @[RocketCore.scala 884:25]
+ assign io_dmem_req_bits_cmd = ex_ctrl_mem_cmd; // @[RocketCore.scala 885:25]
+ assign io_dmem_req_bits_size = ex_reg_mem_size; // @[RocketCore.scala 886:25]
+ assign io_dmem_req_bits_signed = ~ex_reg_inst[14]; // @[RocketCore.scala 887:30]
+ assign io_dmem_req_bits_dv = 1'h0; // @[RocketCore.scala 892:37]
+ assign io_dmem_s1_kill = killm_common | mem_ldst_xcpt; // @[RocketCore.scala 894:35]
+ assign io_dmem_s1_data_data = mem_reg_rs2; // @[RocketCore.scala 893:24]
+ assign io_ptw_status_debug = csr_io_status_debug; // @[RocketCore.scala 744:17]
+ assign io_ptw_pmp_0_cfg_l = csr_io_pmp_0_cfg_l; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_0_cfg_a = csr_io_pmp_0_cfg_a; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_0_cfg_x = csr_io_pmp_0_cfg_x; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_0_cfg_w = csr_io_pmp_0_cfg_w; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_0_cfg_r = csr_io_pmp_0_cfg_r; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_0_addr = csr_io_pmp_0_addr; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_0_mask = csr_io_pmp_0_mask; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_1_cfg_l = csr_io_pmp_1_cfg_l; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_1_cfg_a = csr_io_pmp_1_cfg_a; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_1_cfg_x = csr_io_pmp_1_cfg_x; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_1_cfg_w = csr_io_pmp_1_cfg_w; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_1_cfg_r = csr_io_pmp_1_cfg_r; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_1_addr = csr_io_pmp_1_addr; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_1_mask = csr_io_pmp_1_mask; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_2_cfg_l = csr_io_pmp_2_cfg_l; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_2_cfg_a = csr_io_pmp_2_cfg_a; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_2_cfg_x = csr_io_pmp_2_cfg_x; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_2_cfg_w = csr_io_pmp_2_cfg_w; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_2_cfg_r = csr_io_pmp_2_cfg_r; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_2_addr = csr_io_pmp_2_addr; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_2_mask = csr_io_pmp_2_mask; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_3_cfg_l = csr_io_pmp_3_cfg_l; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_3_cfg_a = csr_io_pmp_3_cfg_a; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_3_cfg_x = csr_io_pmp_3_cfg_x; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_3_cfg_w = csr_io_pmp_3_cfg_w; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_3_cfg_r = csr_io_pmp_3_cfg_r; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_3_addr = csr_io_pmp_3_addr; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_3_mask = csr_io_pmp_3_mask; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_4_cfg_l = csr_io_pmp_4_cfg_l; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_4_cfg_a = csr_io_pmp_4_cfg_a; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_4_cfg_x = csr_io_pmp_4_cfg_x; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_4_cfg_w = csr_io_pmp_4_cfg_w; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_4_cfg_r = csr_io_pmp_4_cfg_r; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_4_addr = csr_io_pmp_4_addr; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_4_mask = csr_io_pmp_4_mask; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_5_cfg_l = csr_io_pmp_5_cfg_l; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_5_cfg_a = csr_io_pmp_5_cfg_a; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_5_cfg_x = csr_io_pmp_5_cfg_x; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_5_cfg_w = csr_io_pmp_5_cfg_w; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_5_cfg_r = csr_io_pmp_5_cfg_r; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_5_addr = csr_io_pmp_5_addr; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_5_mask = csr_io_pmp_5_mask; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_6_cfg_l = csr_io_pmp_6_cfg_l; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_6_cfg_a = csr_io_pmp_6_cfg_a; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_6_cfg_x = csr_io_pmp_6_cfg_x; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_6_cfg_w = csr_io_pmp_6_cfg_w; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_6_cfg_r = csr_io_pmp_6_cfg_r; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_6_addr = csr_io_pmp_6_addr; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_6_mask = csr_io_pmp_6_mask; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_7_cfg_l = csr_io_pmp_7_cfg_l; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_7_cfg_a = csr_io_pmp_7_cfg_a; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_7_cfg_x = csr_io_pmp_7_cfg_x; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_7_cfg_w = csr_io_pmp_7_cfg_w; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_7_cfg_r = csr_io_pmp_7_cfg_r; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_7_addr = csr_io_pmp_7_addr; // @[RocketCore.scala 747:14]
+ assign io_ptw_pmp_7_mask = csr_io_pmp_7_mask; // @[RocketCore.scala 747:14]
+ assign io_ptw_customCSRs_csrs_0_value = csr_io_customCSRs_0_value; // @[RocketCore.scala 743:79]
+ assign io_wfi = csr_io_status_wfi; // @[RocketCore.scala 910:10]
+ assign ibuf_clock = clock;
+ assign ibuf_reset = reset;
+ assign ibuf_io_imem_valid = io_imem_resp_valid; // @[RocketCore.scala 267:16]
+ assign ibuf_io_imem_bits_pc = io_imem_resp_bits_pc; // @[RocketCore.scala 267:16]
+ assign ibuf_io_imem_bits_data = io_imem_resp_bits_data; // @[RocketCore.scala 267:16]
+ assign ibuf_io_imem_bits_xcpt_ae_inst = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala 267:16]
+ assign ibuf_io_imem_bits_replay = io_imem_resp_bits_replay; // @[RocketCore.scala 267:16]
+ assign ibuf_io_kill = take_pc_wb | take_pc_mem; // @[RocketCore.scala 259:35]
+ assign ibuf_io_inst_0_ready = ~ctrl_stalld; // @[RocketCore.scala 849:28]
+ assign csr_clock = clock;
+ assign csr_reset = reset;
+ assign csr_io_ungated_clock = clock; // @[RocketCore.scala 709:24]
+ assign csr_io_interrupts_debug = io_interrupts_debug; // @[RocketCore.scala 715:21]
+ assign csr_io_interrupts_mtip = io_interrupts_mtip; // @[RocketCore.scala 715:21]
+ assign csr_io_interrupts_msip = io_interrupts_msip; // @[RocketCore.scala 715:21]
+ assign csr_io_interrupts_meip = io_interrupts_meip; // @[RocketCore.scala 715:21]
+ assign csr_io_hartid = io_hartid; // @[RocketCore.scala 716:17]
+ assign csr_io_rw_addr = wb_reg_inst[31:20]; // @[RocketCore.scala 748:32]
+ assign csr_io_rw_cmd = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[CSR.scala 167:9]
+ assign csr_io_rw_wdata = wb_reg_wdata; // @[RocketCore.scala 750:19]
+ assign csr_io_decode_0_inst = ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala 710:25]
+ assign csr_io_exception = wb_reg_xcpt | _T_91 | _T_93 | _T_99 | _T_101 | _T_103 | _T_105; // @[RocketCore.scala 1021:26]
+ assign csr_io_retire = wb_reg_valid & ~replay_wb_common & ~wb_xcpt; // @[RocketCore.scala 697:45]
+ assign csr_io_cause = wb_reg_xcpt ? wb_reg_cause : {{59'd0}, _T_119}; // @[Mux.scala 47:70]
+ assign csr_io_pc = wb_reg_pc; // @[RocketCore.scala 722:13]
+ assign csr_io_tval = tval_valid ? _csr_io_tval_T_1 : 34'h0; // @[RocketCore.scala 729:21]
+ assign csr_io_gva = wb_xcpt & (tval_dmem_addr & wb_reg_hls_or_dv); // @[RocketCore.scala 728:25]
+ assign csr_io_inst_0 = {_csr_io_inst_0_T_3,wb_reg_raw_inst[15:0]}; // @[Cat.scala 31:58]
+ assign bpu_io_status_debug = csr_io_status_debug; // @[RocketCore.scala 335:17]
+ assign bpu_io_bp_0_control_action = csr_io_bp_0_control_action; // @[RocketCore.scala 336:13]
+ assign bpu_io_bp_0_control_tmatch = csr_io_bp_0_control_tmatch; // @[RocketCore.scala 336:13]
+ assign bpu_io_bp_0_control_x = csr_io_bp_0_control_x; // @[RocketCore.scala 336:13]
+ assign bpu_io_bp_0_control_w = csr_io_bp_0_control_w; // @[RocketCore.scala 336:13]
+ assign bpu_io_bp_0_control_r = csr_io_bp_0_control_r; // @[RocketCore.scala 336:13]
+ assign bpu_io_bp_0_address = csr_io_bp_0_address; // @[RocketCore.scala 336:13]
+ assign bpu_io_pc = ibuf_io_pc[32:0]; // @[RocketCore.scala 337:13]
+ assign bpu_io_ea = mem_reg_wdata[32:0]; // @[RocketCore.scala 338:13]
+ assign alu_io_dw = ex_ctrl_alu_dw; // @[RocketCore.scala 400:13]
+ assign alu_io_fn = ex_ctrl_alu_fn; // @[RocketCore.scala 401:13]
+ assign alu_io_in2 = 2'h1 == ex_ctrl_sel_alu2 ? $signed({{60{_ex_op2_T_1[3]}},_ex_op2_T_1}) : $signed(_ex_op2_T_5); // @[RocketCore.scala 402:24]
+ assign alu_io_in1 = 2'h2 == ex_ctrl_sel_alu1 ? $signed({{30{_ex_op1_T_1[33]}},_ex_op1_T_1}) : $signed(_ex_op1_T_3); // @[RocketCore.scala 403:24]
+ assign div_clock = clock;
+ assign div_reset = reset;
+ assign div_io_req_valid = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala 424:36]
+ assign div_io_req_bits_fn = ex_ctrl_alu_fn; // @[RocketCore.scala 426:22]
+ assign div_io_req_bits_dw = ex_ctrl_alu_dw; // @[RocketCore.scala 425:22]
+ assign div_io_req_bits_in1 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[RocketCore.scala 389:14]
+ assign div_io_req_bits_in2 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[RocketCore.scala 389:14]
+ assign div_io_req_bits_tag = ex_reg_inst[11:7]; // @[RocketCore.scala 373:29]
+ assign div_io_kill = killm_common & div_io_kill_REG; // @[RocketCore.scala 607:31]
+ assign div_io_resp_ready = dmem_resp_replay & dmem_resp_xpu ? 1'h0 : _ctrl_stalld_T_17; // @[RocketCore.scala 676:21 689:44 690:23]
+ assign PlusArgTimeout_clock = clock;
+ assign PlusArgTimeout_reset = reset;
+ assign PlusArgTimeout_io_count = csr_io_time[31:0]; // @[PlusArg.scala 89:82]
+ always @(posedge clock) begin
+ if (rf_MPORT_en & rf_MPORT_mask) begin
+ rf[rf_MPORT_addr] <= rf_MPORT_data; // @[RocketCore.scala 1061:15]
+ end
+ if (unpause) begin // @[RocketCore.scala 908:18]
+ id_reg_pause <= 1'h0; // @[RocketCore.scala 908:33]
+ end else if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ id_reg_pause <= _GEN_1;
+ end
+ imem_might_request_reg <= ex_pc_valid | mem_pc_valid | io_ptw_customCSRs_csrs_0_value[1]; // @[RocketCore.scala 837:59]
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_branch <= id_ctrl_decoder_3; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_jal <= id_ctrl_decoder_4; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_jalr <= id_ctrl_decoder_5; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_rxs2 <= id_ctrl_decoder_6; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_rxs1 <= id_ctrl_decoder_7; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_xcpt) begin // @[RocketCore.scala 450:20]
+ if (bpu_io_xcpt_if | |_T_37) begin // @[RocketCore.scala 460:52]
+ ex_ctrl_sel_alu2 <= 2'h0; // @[RocketCore.scala 462:26]
+ end else if (|_T_35) begin // @[RocketCore.scala 455:34]
+ ex_ctrl_sel_alu2 <= 2'h1; // @[RocketCore.scala 457:26]
+ end else begin
+ ex_ctrl_sel_alu2 <= 2'h0; // @[RocketCore.scala 454:24]
+ end
+ end else begin
+ ex_ctrl_sel_alu2 <= id_ctrl_decoder_9; // @[RocketCore.scala 443:13]
+ end
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_xcpt) begin // @[RocketCore.scala 450:20]
+ if (bpu_io_xcpt_if | |_T_37) begin // @[RocketCore.scala 460:52]
+ ex_ctrl_sel_alu1 <= 2'h2; // @[RocketCore.scala 461:26]
+ end else if (|_T_35) begin // @[RocketCore.scala 455:34]
+ ex_ctrl_sel_alu1 <= 2'h2; // @[RocketCore.scala 456:26]
+ end else begin
+ ex_ctrl_sel_alu1 <= 2'h1; // @[RocketCore.scala 453:24]
+ end
+ end else begin
+ ex_ctrl_sel_alu1 <= id_ctrl_decoder_10; // @[RocketCore.scala 443:13]
+ end
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_sel_imm <= id_ctrl_decoder_11; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_alu_dw <= _GEN_9;
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_xcpt) begin // @[RocketCore.scala 450:20]
+ ex_ctrl_alu_fn <= 4'h0; // @[RocketCore.scala 451:22]
+ end else begin
+ ex_ctrl_alu_fn <= id_ctrl_decoder_13; // @[RocketCore.scala 443:13]
+ end
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_mem <= id_ctrl_decoder_14; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_mem_cmd <= id_ctrl_decoder_15;
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_div <= id_ctrl_decoder_21; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_wxd <= id_ctrl_decoder_22; // @[RocketCore.scala 443:13]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_system_insn & id_ctrl_decoder_14) begin // @[RocketCore.scala 295:19]
+ ex_ctrl_csr <= 3'h0;
+ end else if (id_csr_ren) begin // @[RocketCore.scala 295:61]
+ ex_ctrl_csr <= 3'h2;
+ end else begin
+ ex_ctrl_csr <= id_ctrl_decoder_23;
+ end
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_ctrl_fence_i <= id_ctrl_decoder_24; // @[RocketCore.scala 443:13]
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_branch <= ex_ctrl_branch; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_jal <= ex_ctrl_jal; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_jalr <= ex_ctrl_jalr; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_rxs2 <= ex_ctrl_rxs2; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_rxs1 <= ex_ctrl_rxs1; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_mem <= ex_ctrl_mem; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_div <= ex_ctrl_div; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_wxd <= ex_ctrl_wxd; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_csr <= ex_ctrl_csr; // @[RocketCore.scala 553:14]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_ctrl_fence_i <= _GEN_79;
+ end
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_ctrl_rxs2 <= mem_ctrl_rxs2; // @[RocketCore.scala 616:13]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_ctrl_rxs1 <= mem_ctrl_rxs1; // @[RocketCore.scala 616:13]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_ctrl_mem <= mem_ctrl_mem; // @[RocketCore.scala 616:13]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_ctrl_div <= mem_ctrl_div; // @[RocketCore.scala 616:13]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_ctrl_wxd <= mem_ctrl_wxd; // @[RocketCore.scala 616:13]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_ctrl_csr <= mem_ctrl_csr; // @[RocketCore.scala 616:13]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_ctrl_fence_i <= mem_ctrl_fence_i; // @[RocketCore.scala 616:13]
+ end
+ ex_reg_xcpt_interrupt <= _ex_reg_replay_T_1 & csr_io_interrupt; // @[RocketCore.scala 440:62]
+ ex_reg_valid <= ~ctrl_killd; // @[RocketCore.scala 437:19]
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_xcpt) begin // @[RocketCore.scala 450:20]
+ ex_reg_rvc <= _GEN_5;
+ end else begin
+ ex_reg_rvc <= ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala 444:16]
+ end
+ end
+ ex_reg_xcpt <= _ex_reg_valid_T & id_xcpt; // @[RocketCore.scala 439:30]
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_reg_flush_pipe <= id_ctrl_decoder_24 | id_csr_flush; // @[RocketCore.scala 465:23]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_reg_load_use <= id_load_use; // @[RocketCore.scala 466:21]
+ end
+ if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
+ if (csr_io_interrupt) begin // @[Mux.scala 47:70]
+ ex_reg_cause <= csr_io_interrupt_cause;
+ end else begin
+ ex_reg_cause <= {{59'd0}, _T_18};
+ end
+ end
+ ex_reg_replay <= ~take_pc_mem_wb & ibuf_io_inst_0_valid & ibuf_io_inst_0_bits_replay; // @[RocketCore.scala 438:54]
+ if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
+ ex_reg_pc <= ibuf_io_pc; // @[RocketCore.scala 502:15]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (_T_46) begin // @[RocketCore.scala 469:81]
+ ex_reg_mem_size <= _ex_reg_mem_size_T_6; // @[RocketCore.scala 470:23]
+ end else begin
+ ex_reg_mem_size <= ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala 468:21]
+ end
+ end
+ if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
+ ex_reg_inst <= ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala 500:17]
+ end
+ if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
+ ex_reg_raw_inst <= ibuf_io_inst_0_bits_raw; // @[RocketCore.scala 501:21]
+ end
+ mem_reg_xcpt_interrupt <= _ex_reg_replay_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala 546:45]
+ mem_reg_valid <= ~ctrl_killx; // @[RocketCore.scala 543:20]
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_rvc <= ex_reg_rvc; // @[RocketCore.scala 556:17]
+ end
+ end
+ mem_reg_xcpt <= _mem_reg_valid_T & ex_xcpt; // @[RocketCore.scala 545:31]
+ mem_reg_replay <= _ex_reg_replay_T & replay_ex; // @[RocketCore.scala 544:37]
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_flush_pipe <= _GEN_80;
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_cause <= ex_reg_cause; // @[RocketCore.scala 565:19]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_slow_bypass <= ex_slow_bypass; // @[RocketCore.scala 562:25]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_load <= ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala 557:18]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_store <= ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala 558:19]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_pc <= ex_reg_pc; // @[RocketCore.scala 570:16]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_inst <= ex_reg_inst; // @[RocketCore.scala 566:18]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_hls_or_dv <= io_dmem_req_bits_dv; // @[RocketCore.scala 569:23]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_raw_inst <= ex_reg_raw_inst; // @[RocketCore.scala 567:22]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_reg_wdata <= _mem_reg_wdata_T; // @[RocketCore.scala 571:19]
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ if (ex_ctrl_rxs2 & ex_ctrl_mem) begin // @[RocketCore.scala 574:71]
+ if (ex_reg_mem_size == 2'h0) begin // @[AMOALU.scala 26:13]
+ mem_reg_rs2 <= _mem_reg_rs2_T_4;
+ end else begin
+ mem_reg_rs2 <= _mem_reg_rs2_T_13;
+ end
+ end
+ end
+ end
+ if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
+ if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
+ mem_br_taken <= alu_io_cmp_out; // @[RocketCore.scala 572:18]
+ end
+ end
+ wb_reg_valid <= ~ctrl_killm; // @[RocketCore.scala 611:19]
+ wb_reg_xcpt <= mem_xcpt & _wb_reg_replay_T; // @[RocketCore.scala 613:27]
+ wb_reg_replay <= replay_mem & ~take_pc_wb; // @[RocketCore.scala 612:31]
+ wb_reg_flush_pipe <= _wb_reg_valid_T & mem_reg_flush_pipe; // @[RocketCore.scala 614:36]
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ if (_T_70) begin // @[Mux.scala 47:70]
+ wb_reg_cause <= mem_reg_cause;
+ end else begin
+ wb_reg_cause <= {{60'd0}, _T_74};
+ end
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_reg_pc <= mem_reg_pc; // @[RocketCore.scala 630:15]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_reg_hls_or_dv <= mem_reg_hls_or_dv; // @[RocketCore.scala 627:22]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_reg_inst <= mem_reg_inst; // @[RocketCore.scala 624:17]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_reg_raw_inst <= mem_reg_raw_inst; // @[RocketCore.scala 625:21]
+ end
+ if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
+ wb_reg_wdata <= mem_int_wdata; // @[RocketCore.scala 618:18]
+ end
+ if (reset) begin // @[RocketCore.scala 283:25]
+ id_reg_fence <= 1'h0; // @[RocketCore.scala 283:25]
+ end else if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ id_reg_fence <= _GEN_2;
+ end else if (~id_mem_busy) begin // @[RocketCore.scala 327:23]
+ id_reg_fence <= 1'h0; // @[RocketCore.scala 327:38]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_illegal_insn) begin // @[RocketCore.scala 491:47]
+ ex_reg_rs_bypass_0 <= 1'h0; // @[RocketCore.scala 493:27]
+ end else begin
+ ex_reg_rs_bypass_0 <= do_bypass; // @[RocketCore.scala 484:27]
+ end
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ ex_reg_rs_bypass_1 <= do_bypass_1; // @[RocketCore.scala 484:27]
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_illegal_insn) begin // @[RocketCore.scala 491:47]
+ ex_reg_rs_lsb_0 <= inst[1:0]; // @[RocketCore.scala 494:24]
+ end else if (id_ctrl_decoder_7 & ~do_bypass) begin // @[RocketCore.scala 486:38]
+ ex_reg_rs_lsb_0 <= id_rs_0[1:0]; // @[RocketCore.scala 487:26]
+ end else if (id_bypass_src_0_0) begin // @[Mux.scala 47:70]
+ ex_reg_rs_lsb_0 <= 2'h0;
+ end else begin
+ ex_reg_rs_lsb_0 <= _bypass_src_T_1;
+ end
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_ctrl_decoder_6 & ~do_bypass_1) begin // @[RocketCore.scala 486:38]
+ ex_reg_rs_lsb_1 <= id_rs_1[1:0]; // @[RocketCore.scala 487:26]
+ end else if (id_bypass_src_1_0) begin // @[Mux.scala 47:70]
+ ex_reg_rs_lsb_1 <= 2'h0;
+ end else if (id_bypass_src_1_1) begin // @[Mux.scala 47:70]
+ ex_reg_rs_lsb_1 <= 2'h1;
+ end else begin
+ ex_reg_rs_lsb_1 <= _bypass_src_T_2;
+ end
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_illegal_insn) begin // @[RocketCore.scala 491:47]
+ ex_reg_rs_msb_0 <= {{32'd0}, inst[31:2]}; // @[RocketCore.scala 495:24]
+ end else if (id_ctrl_decoder_7 & ~do_bypass) begin // @[RocketCore.scala 486:38]
+ ex_reg_rs_msb_0 <= id_rs_0[63:2]; // @[RocketCore.scala 488:26]
+ end
+ end
+ if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
+ if (id_ctrl_decoder_6 & ~do_bypass_1) begin // @[RocketCore.scala 486:38]
+ ex_reg_rs_msb_1 <= id_rs_1[63:2]; // @[RocketCore.scala 488:26]
+ end
+ end
+ if (reset) begin // @[RocketCore.scala 1047:25]
+ _r <= 32'h0; // @[RocketCore.scala 1047:25]
+ end else if (_T_149) begin // @[RocketCore.scala 1055:18]
+ _r <= _T_148; // @[RocketCore.scala 1055:23]
+ end else if (ll_wen) begin // @[RocketCore.scala 1055:18]
+ _r <= _T_143; // @[RocketCore.scala 1055:23]
+ end
+ blocked <= _replay_ex_structural_T & _dcache_blocked_T & (blocked | io_dmem_req_valid | io_dmem_s2_nack); // @[RocketCore.scala 808:83]
+ div_io_kill_REG <= div_io_req_ready & div_io_req_valid; // @[Decoupled.scala 50:35]
+ if (ex_reg_rs_bypass_0) begin // @[RocketCore.scala 389:14]
+ if (ex_reg_rs_lsb_0 == 2'h3) begin // @[package.scala 32:76]
+ coreMonitorBundle_rd0val_x23 <= io_dmem_resp_bits_data_word_bypass;
+ end else if (ex_reg_rs_lsb_0 == 2'h2) begin // @[package.scala 32:76]
+ coreMonitorBundle_rd0val_x23 <= wb_reg_wdata;
+ end else if (ex_reg_rs_lsb_0 == 2'h1) begin // @[package.scala 32:76]
+ coreMonitorBundle_rd0val_x23 <= mem_reg_wdata;
+ end else begin
+ coreMonitorBundle_rd0val_x23 <= 64'h0;
+ end
+ end else begin
+ coreMonitorBundle_rd0val_x23 <= _ex_rs_T_6;
+ end
+ coreMonitorBundle_rd0val_REG <= coreMonitorBundle_rd0val_x23; // @[RocketCore.scala 942:34]
+ if (ex_reg_rs_bypass_1) begin // @[RocketCore.scala 389:14]
+ if (ex_reg_rs_lsb_1 == 2'h3) begin // @[package.scala 32:76]
+ coreMonitorBundle_rd1val_x29 <= io_dmem_resp_bits_data_word_bypass;
+ end else if (ex_reg_rs_lsb_1 == 2'h2) begin // @[package.scala 32:76]
+ coreMonitorBundle_rd1val_x29 <= wb_reg_wdata;
+ end else if (ex_reg_rs_lsb_1 == 2'h1) begin // @[package.scala 32:76]
+ coreMonitorBundle_rd1val_x29 <= mem_reg_wdata;
+ end else begin
+ coreMonitorBundle_rd1val_x29 <= 64'h0;
+ end
+ end else begin
+ coreMonitorBundle_rd1val_x29 <= _ex_rs_T_13;
+ end
+ coreMonitorBundle_rd1val_REG <= coreMonitorBundle_rd1val_x29; // @[RocketCore.scala 944:34]
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~htval_valid_imem) & ~reset) begin
+ $fatal; // @[RocketCore.scala 733:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~htval_valid_imem)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at RocketCore.scala:733 assert(!htval_valid_imem || io.imem.gpa.valid)\n"); // @[RocketCore.scala 733:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (csr_io_trace_0_valid & _csr_io_htval_T_3) begin
+ $fwrite(32'h80000002,"C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",io_hartid,
+ csr_io_time[31:0],coreMonitorBundle_valid,coreMonitorBundle_pc,_T_151,_T_152,coreMonitorBundle_wrenx,_T_154,
+ _T_156,_T_158,_T_160,coreMonitorBundle_inst,coreMonitorBundle_inst); // @[RocketCore.scala 977:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+ _RAND_1 = {2{`RANDOM}};
+ _RAND_2 = {2{`RANDOM}};
+`endif // RANDOMIZE_GARBAGE_ASSIGN
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 31; initvar = initvar+1)
+ rf[initvar] = _RAND_0[63:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_3 = {1{`RANDOM}};
+ id_reg_pause = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ imem_might_request_reg = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ ex_ctrl_branch = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ ex_ctrl_jal = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ ex_ctrl_jalr = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ ex_ctrl_rxs2 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ ex_ctrl_rxs1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ ex_ctrl_sel_alu2 = _RAND_10[1:0];
+ _RAND_11 = {1{`RANDOM}};
+ ex_ctrl_sel_alu1 = _RAND_11[1:0];
+ _RAND_12 = {1{`RANDOM}};
+ ex_ctrl_sel_imm = _RAND_12[2:0];
+ _RAND_13 = {1{`RANDOM}};
+ ex_ctrl_alu_dw = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ ex_ctrl_alu_fn = _RAND_14[3:0];
+ _RAND_15 = {1{`RANDOM}};
+ ex_ctrl_mem = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ ex_ctrl_mem_cmd = _RAND_16[4:0];
+ _RAND_17 = {1{`RANDOM}};
+ ex_ctrl_div = _RAND_17[0:0];
+ _RAND_18 = {1{`RANDOM}};
+ ex_ctrl_wxd = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ ex_ctrl_csr = _RAND_19[2:0];
+ _RAND_20 = {1{`RANDOM}};
+ ex_ctrl_fence_i = _RAND_20[0:0];
+ _RAND_21 = {1{`RANDOM}};
+ mem_ctrl_branch = _RAND_21[0:0];
+ _RAND_22 = {1{`RANDOM}};
+ mem_ctrl_jal = _RAND_22[0:0];
+ _RAND_23 = {1{`RANDOM}};
+ mem_ctrl_jalr = _RAND_23[0:0];
+ _RAND_24 = {1{`RANDOM}};
+ mem_ctrl_rxs2 = _RAND_24[0:0];
+ _RAND_25 = {1{`RANDOM}};
+ mem_ctrl_rxs1 = _RAND_25[0:0];
+ _RAND_26 = {1{`RANDOM}};
+ mem_ctrl_mem = _RAND_26[0:0];
+ _RAND_27 = {1{`RANDOM}};
+ mem_ctrl_div = _RAND_27[0:0];
+ _RAND_28 = {1{`RANDOM}};
+ mem_ctrl_wxd = _RAND_28[0:0];
+ _RAND_29 = {1{`RANDOM}};
+ mem_ctrl_csr = _RAND_29[2:0];
+ _RAND_30 = {1{`RANDOM}};
+ mem_ctrl_fence_i = _RAND_30[0:0];
+ _RAND_31 = {1{`RANDOM}};
+ wb_ctrl_rxs2 = _RAND_31[0:0];
+ _RAND_32 = {1{`RANDOM}};
+ wb_ctrl_rxs1 = _RAND_32[0:0];
+ _RAND_33 = {1{`RANDOM}};
+ wb_ctrl_mem = _RAND_33[0:0];
+ _RAND_34 = {1{`RANDOM}};
+ wb_ctrl_div = _RAND_34[0:0];
+ _RAND_35 = {1{`RANDOM}};
+ wb_ctrl_wxd = _RAND_35[0:0];
+ _RAND_36 = {1{`RANDOM}};
+ wb_ctrl_csr = _RAND_36[2:0];
+ _RAND_37 = {1{`RANDOM}};
+ wb_ctrl_fence_i = _RAND_37[0:0];
+ _RAND_38 = {1{`RANDOM}};
+ ex_reg_xcpt_interrupt = _RAND_38[0:0];
+ _RAND_39 = {1{`RANDOM}};
+ ex_reg_valid = _RAND_39[0:0];
+ _RAND_40 = {1{`RANDOM}};
+ ex_reg_rvc = _RAND_40[0:0];
+ _RAND_41 = {1{`RANDOM}};
+ ex_reg_xcpt = _RAND_41[0:0];
+ _RAND_42 = {1{`RANDOM}};
+ ex_reg_flush_pipe = _RAND_42[0:0];
+ _RAND_43 = {1{`RANDOM}};
+ ex_reg_load_use = _RAND_43[0:0];
+ _RAND_44 = {2{`RANDOM}};
+ ex_reg_cause = _RAND_44[63:0];
+ _RAND_45 = {1{`RANDOM}};
+ ex_reg_replay = _RAND_45[0:0];
+ _RAND_46 = {2{`RANDOM}};
+ ex_reg_pc = _RAND_46[33:0];
+ _RAND_47 = {1{`RANDOM}};
+ ex_reg_mem_size = _RAND_47[1:0];
+ _RAND_48 = {1{`RANDOM}};
+ ex_reg_inst = _RAND_48[31:0];
+ _RAND_49 = {1{`RANDOM}};
+ ex_reg_raw_inst = _RAND_49[31:0];
+ _RAND_50 = {1{`RANDOM}};
+ mem_reg_xcpt_interrupt = _RAND_50[0:0];
+ _RAND_51 = {1{`RANDOM}};
+ mem_reg_valid = _RAND_51[0:0];
+ _RAND_52 = {1{`RANDOM}};
+ mem_reg_rvc = _RAND_52[0:0];
+ _RAND_53 = {1{`RANDOM}};
+ mem_reg_xcpt = _RAND_53[0:0];
+ _RAND_54 = {1{`RANDOM}};
+ mem_reg_replay = _RAND_54[0:0];
+ _RAND_55 = {1{`RANDOM}};
+ mem_reg_flush_pipe = _RAND_55[0:0];
+ _RAND_56 = {2{`RANDOM}};
+ mem_reg_cause = _RAND_56[63:0];
+ _RAND_57 = {1{`RANDOM}};
+ mem_reg_slow_bypass = _RAND_57[0:0];
+ _RAND_58 = {1{`RANDOM}};
+ mem_reg_load = _RAND_58[0:0];
+ _RAND_59 = {1{`RANDOM}};
+ mem_reg_store = _RAND_59[0:0];
+ _RAND_60 = {2{`RANDOM}};
+ mem_reg_pc = _RAND_60[33:0];
+ _RAND_61 = {1{`RANDOM}};
+ mem_reg_inst = _RAND_61[31:0];
+ _RAND_62 = {1{`RANDOM}};
+ mem_reg_hls_or_dv = _RAND_62[0:0];
+ _RAND_63 = {1{`RANDOM}};
+ mem_reg_raw_inst = _RAND_63[31:0];
+ _RAND_64 = {2{`RANDOM}};
+ mem_reg_wdata = _RAND_64[63:0];
+ _RAND_65 = {2{`RANDOM}};
+ mem_reg_rs2 = _RAND_65[63:0];
+ _RAND_66 = {1{`RANDOM}};
+ mem_br_taken = _RAND_66[0:0];
+ _RAND_67 = {1{`RANDOM}};
+ wb_reg_valid = _RAND_67[0:0];
+ _RAND_68 = {1{`RANDOM}};
+ wb_reg_xcpt = _RAND_68[0:0];
+ _RAND_69 = {1{`RANDOM}};
+ wb_reg_replay = _RAND_69[0:0];
+ _RAND_70 = {1{`RANDOM}};
+ wb_reg_flush_pipe = _RAND_70[0:0];
+ _RAND_71 = {2{`RANDOM}};
+ wb_reg_cause = _RAND_71[63:0];
+ _RAND_72 = {2{`RANDOM}};
+ wb_reg_pc = _RAND_72[33:0];
+ _RAND_73 = {1{`RANDOM}};
+ wb_reg_hls_or_dv = _RAND_73[0:0];
+ _RAND_74 = {1{`RANDOM}};
+ wb_reg_inst = _RAND_74[31:0];
+ _RAND_75 = {1{`RANDOM}};
+ wb_reg_raw_inst = _RAND_75[31:0];
+ _RAND_76 = {2{`RANDOM}};
+ wb_reg_wdata = _RAND_76[63:0];
+ _RAND_77 = {1{`RANDOM}};
+ id_reg_fence = _RAND_77[0:0];
+ _RAND_78 = {1{`RANDOM}};
+ ex_reg_rs_bypass_0 = _RAND_78[0:0];
+ _RAND_79 = {1{`RANDOM}};
+ ex_reg_rs_bypass_1 = _RAND_79[0:0];
+ _RAND_80 = {1{`RANDOM}};
+ ex_reg_rs_lsb_0 = _RAND_80[1:0];
+ _RAND_81 = {1{`RANDOM}};
+ ex_reg_rs_lsb_1 = _RAND_81[1:0];
+ _RAND_82 = {2{`RANDOM}};
+ ex_reg_rs_msb_0 = _RAND_82[61:0];
+ _RAND_83 = {2{`RANDOM}};
+ ex_reg_rs_msb_1 = _RAND_83[61:0];
+ _RAND_84 = {1{`RANDOM}};
+ _r = _RAND_84[31:0];
+ _RAND_85 = {1{`RANDOM}};
+ blocked = _RAND_85[0:0];
+ _RAND_86 = {1{`RANDOM}};
+ div_io_kill_REG = _RAND_86[0:0];
+ _RAND_87 = {2{`RANDOM}};
+ coreMonitorBundle_rd0val_x23 = _RAND_87[63:0];
+ _RAND_88 = {2{`RANDOM}};
+ coreMonitorBundle_rd0val_REG = _RAND_88[63:0];
+ _RAND_89 = {2{`RANDOM}};
+ coreMonitorBundle_rd1val_x29 = _RAND_89[63:0];
+ _RAND_90 = {2{`RANDOM}};
+ coreMonitorBundle_rd1val_REG = _RAND_90[63:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module RocketTile(
+ input clock,
+ input reset,
+ output auto_slave_in_a_ready,
+ input auto_slave_in_a_valid,
+ input [2:0] auto_slave_in_a_bits_opcode,
+ input [2:0] auto_slave_in_a_bits_param,
+ input [2:0] auto_slave_in_a_bits_size,
+ input [2:0] auto_slave_in_a_bits_source,
+ input [31:0] auto_slave_in_a_bits_address,
+ input [7:0] auto_slave_in_a_bits_mask,
+ input [63:0] auto_slave_in_a_bits_data,
+ input auto_slave_in_d_ready,
+ output auto_slave_in_d_valid,
+ output [2:0] auto_slave_in_d_bits_opcode,
+ output [2:0] auto_slave_in_d_bits_size,
+ output [2:0] auto_slave_in_d_bits_source,
+ output [63:0] auto_slave_in_d_bits_data,
+ output auto_wfi_out_0,
+ input auto_int_local_in_2_0,
+ input auto_int_local_in_1_0,
+ input auto_int_local_in_1_1,
+ input auto_int_local_in_0_0,
+ input auto_hartid_in,
+ input auto_tl_other_masters_out_a_ready,
+ output auto_tl_other_masters_out_a_valid,
+ output [2:0] auto_tl_other_masters_out_a_bits_opcode,
+ output [2:0] auto_tl_other_masters_out_a_bits_param,
+ output [3:0] auto_tl_other_masters_out_a_bits_size,
+ output auto_tl_other_masters_out_a_bits_source,
+ output [31:0] auto_tl_other_masters_out_a_bits_address,
+ output [7:0] auto_tl_other_masters_out_a_bits_mask,
+ output [63:0] auto_tl_other_masters_out_a_bits_data,
+ output auto_tl_other_masters_out_d_ready,
+ input auto_tl_other_masters_out_d_valid,
+ input [2:0] auto_tl_other_masters_out_d_bits_opcode,
+ input [1:0] auto_tl_other_masters_out_d_bits_param,
+ input [3:0] auto_tl_other_masters_out_d_bits_size,
+ input auto_tl_other_masters_out_d_bits_source,
+ input auto_tl_other_masters_out_d_bits_sink,
+ input auto_tl_other_masters_out_d_bits_denied,
+ input [63:0] auto_tl_other_masters_out_d_bits_data,
+ input auto_tl_other_masters_out_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ wire tlMasterXbar_clock; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_reset; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_1_a_ready; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_1_a_valid; // @[BaseTile.scala 210:42]
+ wire [31:0] tlMasterXbar_auto_in_1_a_bits_address; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_1_d_valid; // @[BaseTile.scala 210:42]
+ wire [2:0] tlMasterXbar_auto_in_1_d_bits_opcode; // @[BaseTile.scala 210:42]
+ wire [3:0] tlMasterXbar_auto_in_1_d_bits_size; // @[BaseTile.scala 210:42]
+ wire [63:0] tlMasterXbar_auto_in_1_d_bits_data; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_1_d_bits_corrupt; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_0_a_ready; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_0_a_valid; // @[BaseTile.scala 210:42]
+ wire [2:0] tlMasterXbar_auto_in_0_a_bits_opcode; // @[BaseTile.scala 210:42]
+ wire [2:0] tlMasterXbar_auto_in_0_a_bits_param; // @[BaseTile.scala 210:42]
+ wire [3:0] tlMasterXbar_auto_in_0_a_bits_size; // @[BaseTile.scala 210:42]
+ wire [31:0] tlMasterXbar_auto_in_0_a_bits_address; // @[BaseTile.scala 210:42]
+ wire [7:0] tlMasterXbar_auto_in_0_a_bits_mask; // @[BaseTile.scala 210:42]
+ wire [63:0] tlMasterXbar_auto_in_0_a_bits_data; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_0_d_ready; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_0_d_valid; // @[BaseTile.scala 210:42]
+ wire [2:0] tlMasterXbar_auto_in_0_d_bits_opcode; // @[BaseTile.scala 210:42]
+ wire [3:0] tlMasterXbar_auto_in_0_d_bits_size; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_in_0_d_bits_denied; // @[BaseTile.scala 210:42]
+ wire [63:0] tlMasterXbar_auto_in_0_d_bits_data; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_a_ready; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_a_valid; // @[BaseTile.scala 210:42]
+ wire [2:0] tlMasterXbar_auto_out_a_bits_opcode; // @[BaseTile.scala 210:42]
+ wire [2:0] tlMasterXbar_auto_out_a_bits_param; // @[BaseTile.scala 210:42]
+ wire [3:0] tlMasterXbar_auto_out_a_bits_size; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_a_bits_source; // @[BaseTile.scala 210:42]
+ wire [31:0] tlMasterXbar_auto_out_a_bits_address; // @[BaseTile.scala 210:42]
+ wire [7:0] tlMasterXbar_auto_out_a_bits_mask; // @[BaseTile.scala 210:42]
+ wire [63:0] tlMasterXbar_auto_out_a_bits_data; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_d_ready; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_d_valid; // @[BaseTile.scala 210:42]
+ wire [2:0] tlMasterXbar_auto_out_d_bits_opcode; // @[BaseTile.scala 210:42]
+ wire [1:0] tlMasterXbar_auto_out_d_bits_param; // @[BaseTile.scala 210:42]
+ wire [3:0] tlMasterXbar_auto_out_d_bits_size; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_d_bits_source; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_d_bits_sink; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_d_bits_denied; // @[BaseTile.scala 210:42]
+ wire [63:0] tlMasterXbar_auto_out_d_bits_data; // @[BaseTile.scala 210:42]
+ wire tlMasterXbar_auto_out_d_bits_corrupt; // @[BaseTile.scala 210:42]
+ wire tlSlaveXbar_auto_in_a_ready; // @[BaseTile.scala 211:41]
+ wire tlSlaveXbar_auto_in_a_valid; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_in_a_bits_opcode; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_in_a_bits_param; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_in_a_bits_size; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_in_a_bits_source; // @[BaseTile.scala 211:41]
+ wire [31:0] tlSlaveXbar_auto_in_a_bits_address; // @[BaseTile.scala 211:41]
+ wire [7:0] tlSlaveXbar_auto_in_a_bits_mask; // @[BaseTile.scala 211:41]
+ wire [63:0] tlSlaveXbar_auto_in_a_bits_data; // @[BaseTile.scala 211:41]
+ wire tlSlaveXbar_auto_in_d_ready; // @[BaseTile.scala 211:41]
+ wire tlSlaveXbar_auto_in_d_valid; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_in_d_bits_opcode; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_in_d_bits_size; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_in_d_bits_source; // @[BaseTile.scala 211:41]
+ wire [63:0] tlSlaveXbar_auto_in_d_bits_data; // @[BaseTile.scala 211:41]
+ wire tlSlaveXbar_auto_out_a_ready; // @[BaseTile.scala 211:41]
+ wire tlSlaveXbar_auto_out_a_valid; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_out_a_bits_opcode; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_out_a_bits_param; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_out_a_bits_size; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_out_a_bits_source; // @[BaseTile.scala 211:41]
+ wire [31:0] tlSlaveXbar_auto_out_a_bits_address; // @[BaseTile.scala 211:41]
+ wire [7:0] tlSlaveXbar_auto_out_a_bits_mask; // @[BaseTile.scala 211:41]
+ wire [63:0] tlSlaveXbar_auto_out_a_bits_data; // @[BaseTile.scala 211:41]
+ wire tlSlaveXbar_auto_out_d_ready; // @[BaseTile.scala 211:41]
+ wire tlSlaveXbar_auto_out_d_valid; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_out_d_bits_opcode; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_out_d_bits_size; // @[BaseTile.scala 211:41]
+ wire [2:0] tlSlaveXbar_auto_out_d_bits_source; // @[BaseTile.scala 211:41]
+ wire [63:0] tlSlaveXbar_auto_out_d_bits_data; // @[BaseTile.scala 211:41]
+ wire intXbar_auto_int_in_2_0; // @[BaseTile.scala 212:37]
+ wire intXbar_auto_int_in_1_0; // @[BaseTile.scala 212:37]
+ wire intXbar_auto_int_in_1_1; // @[BaseTile.scala 212:37]
+ wire intXbar_auto_int_in_0_0; // @[BaseTile.scala 212:37]
+ wire intXbar_auto_int_out_0; // @[BaseTile.scala 212:37]
+ wire intXbar_auto_int_out_1; // @[BaseTile.scala 212:37]
+ wire intXbar_auto_int_out_2; // @[BaseTile.scala 212:37]
+ wire intXbar_auto_int_out_3; // @[BaseTile.scala 212:37]
+ wire broadcast_auto_in; // @[BundleBridge.scala 196:31]
+ wire broadcast_auto_out_0; // @[BundleBridge.scala 196:31]
+ wire dcache_clock; // @[HellaCache.scala 269:43]
+ wire dcache_reset; // @[HellaCache.scala 269:43]
+ wire dcache_auto_out_a_ready; // @[HellaCache.scala 269:43]
+ wire dcache_auto_out_a_valid; // @[HellaCache.scala 269:43]
+ wire [2:0] dcache_auto_out_a_bits_opcode; // @[HellaCache.scala 269:43]
+ wire [2:0] dcache_auto_out_a_bits_param; // @[HellaCache.scala 269:43]
+ wire [3:0] dcache_auto_out_a_bits_size; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_auto_out_a_bits_address; // @[HellaCache.scala 269:43]
+ wire [7:0] dcache_auto_out_a_bits_mask; // @[HellaCache.scala 269:43]
+ wire [63:0] dcache_auto_out_a_bits_data; // @[HellaCache.scala 269:43]
+ wire dcache_auto_out_d_ready; // @[HellaCache.scala 269:43]
+ wire dcache_auto_out_d_valid; // @[HellaCache.scala 269:43]
+ wire [2:0] dcache_auto_out_d_bits_opcode; // @[HellaCache.scala 269:43]
+ wire [3:0] dcache_auto_out_d_bits_size; // @[HellaCache.scala 269:43]
+ wire dcache_auto_out_d_bits_denied; // @[HellaCache.scala 269:43]
+ wire [63:0] dcache_auto_out_d_bits_data; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_req_ready; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_req_valid; // @[HellaCache.scala 269:43]
+ wire [33:0] dcache_io_cpu_req_bits_addr; // @[HellaCache.scala 269:43]
+ wire [6:0] dcache_io_cpu_req_bits_tag; // @[HellaCache.scala 269:43]
+ wire [4:0] dcache_io_cpu_req_bits_cmd; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_cpu_req_bits_size; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_req_bits_signed; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_cpu_req_bits_dprv; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_req_bits_no_xcpt; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s1_kill; // @[HellaCache.scala 269:43]
+ wire [63:0] dcache_io_cpu_s1_data_data; // @[HellaCache.scala 269:43]
+ wire [7:0] dcache_io_cpu_s1_data_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_nack; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_resp_valid; // @[HellaCache.scala 269:43]
+ wire [33:0] dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala 269:43]
+ wire [6:0] dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala 269:43]
+ wire [4:0] dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_cpu_resp_bits_size; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala 269:43]
+ wire [63:0] dcache_io_cpu_resp_bits_data; // @[HellaCache.scala 269:43]
+ wire [7:0] dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala 269:43]
+ wire [63:0] dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala 269:43]
+ wire [63:0] dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala 269:43]
+ wire [63:0] dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_replay_next; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_xcpt_gf_ld; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_xcpt_gf_st; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_ordered; // @[HellaCache.scala 269:43]
+ wire dcache_io_cpu_perf_grant; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_status_debug; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_0_cfg_l; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_ptw_pmp_0_cfg_a; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_0_cfg_w; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_0_cfg_r; // @[HellaCache.scala 269:43]
+ wire [29:0] dcache_io_ptw_pmp_0_addr; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_io_ptw_pmp_0_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_1_cfg_l; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_ptw_pmp_1_cfg_a; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_1_cfg_w; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_1_cfg_r; // @[HellaCache.scala 269:43]
+ wire [29:0] dcache_io_ptw_pmp_1_addr; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_io_ptw_pmp_1_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_2_cfg_l; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_ptw_pmp_2_cfg_a; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_2_cfg_w; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_2_cfg_r; // @[HellaCache.scala 269:43]
+ wire [29:0] dcache_io_ptw_pmp_2_addr; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_io_ptw_pmp_2_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_3_cfg_l; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_ptw_pmp_3_cfg_a; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_3_cfg_w; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_3_cfg_r; // @[HellaCache.scala 269:43]
+ wire [29:0] dcache_io_ptw_pmp_3_addr; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_io_ptw_pmp_3_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_4_cfg_l; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_ptw_pmp_4_cfg_a; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_4_cfg_w; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_4_cfg_r; // @[HellaCache.scala 269:43]
+ wire [29:0] dcache_io_ptw_pmp_4_addr; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_io_ptw_pmp_4_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_5_cfg_l; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_ptw_pmp_5_cfg_a; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_5_cfg_w; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_5_cfg_r; // @[HellaCache.scala 269:43]
+ wire [29:0] dcache_io_ptw_pmp_5_addr; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_io_ptw_pmp_5_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_6_cfg_l; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_ptw_pmp_6_cfg_a; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_6_cfg_w; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_6_cfg_r; // @[HellaCache.scala 269:43]
+ wire [29:0] dcache_io_ptw_pmp_6_addr; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_io_ptw_pmp_6_mask; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_7_cfg_l; // @[HellaCache.scala 269:43]
+ wire [1:0] dcache_io_ptw_pmp_7_cfg_a; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_7_cfg_w; // @[HellaCache.scala 269:43]
+ wire dcache_io_ptw_pmp_7_cfg_r; // @[HellaCache.scala 269:43]
+ wire [29:0] dcache_io_ptw_pmp_7_addr; // @[HellaCache.scala 269:43]
+ wire [31:0] dcache_io_ptw_pmp_7_mask; // @[HellaCache.scala 269:43]
+ wire frontend_clock; // @[Frontend.scala 371:28]
+ wire frontend_reset; // @[Frontend.scala 371:28]
+ wire frontend_auto_icache_master_out_a_ready; // @[Frontend.scala 371:28]
+ wire frontend_auto_icache_master_out_a_valid; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_auto_icache_master_out_a_bits_address; // @[Frontend.scala 371:28]
+ wire frontend_auto_icache_master_out_d_valid; // @[Frontend.scala 371:28]
+ wire [2:0] frontend_auto_icache_master_out_d_bits_opcode; // @[Frontend.scala 371:28]
+ wire [3:0] frontend_auto_icache_master_out_d_bits_size; // @[Frontend.scala 371:28]
+ wire [63:0] frontend_auto_icache_master_out_d_bits_data; // @[Frontend.scala 371:28]
+ wire frontend_auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_might_request; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_req_valid; // @[Frontend.scala 371:28]
+ wire [33:0] frontend_io_cpu_req_bits_pc; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_req_bits_speculative; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_resp_ready; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_resp_valid; // @[Frontend.scala 371:28]
+ wire [33:0] frontend_io_cpu_resp_bits_pc; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_cpu_resp_bits_data; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_resp_bits_replay; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_btb_update_valid; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_bht_update_valid; // @[Frontend.scala 371:28]
+ wire frontend_io_cpu_flush_icache; // @[Frontend.scala 371:28]
+ wire [33:0] frontend_io_cpu_npc; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_status_debug; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_0_cfg_l; // @[Frontend.scala 371:28]
+ wire [1:0] frontend_io_ptw_pmp_0_cfg_a; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_0_cfg_x; // @[Frontend.scala 371:28]
+ wire [29:0] frontend_io_ptw_pmp_0_addr; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_ptw_pmp_0_mask; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_1_cfg_l; // @[Frontend.scala 371:28]
+ wire [1:0] frontend_io_ptw_pmp_1_cfg_a; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_1_cfg_x; // @[Frontend.scala 371:28]
+ wire [29:0] frontend_io_ptw_pmp_1_addr; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_ptw_pmp_1_mask; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_2_cfg_l; // @[Frontend.scala 371:28]
+ wire [1:0] frontend_io_ptw_pmp_2_cfg_a; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_2_cfg_x; // @[Frontend.scala 371:28]
+ wire [29:0] frontend_io_ptw_pmp_2_addr; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_ptw_pmp_2_mask; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_3_cfg_l; // @[Frontend.scala 371:28]
+ wire [1:0] frontend_io_ptw_pmp_3_cfg_a; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_3_cfg_x; // @[Frontend.scala 371:28]
+ wire [29:0] frontend_io_ptw_pmp_3_addr; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_ptw_pmp_3_mask; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_4_cfg_l; // @[Frontend.scala 371:28]
+ wire [1:0] frontend_io_ptw_pmp_4_cfg_a; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_4_cfg_x; // @[Frontend.scala 371:28]
+ wire [29:0] frontend_io_ptw_pmp_4_addr; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_ptw_pmp_4_mask; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_5_cfg_l; // @[Frontend.scala 371:28]
+ wire [1:0] frontend_io_ptw_pmp_5_cfg_a; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_5_cfg_x; // @[Frontend.scala 371:28]
+ wire [29:0] frontend_io_ptw_pmp_5_addr; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_ptw_pmp_5_mask; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_6_cfg_l; // @[Frontend.scala 371:28]
+ wire [1:0] frontend_io_ptw_pmp_6_cfg_a; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_6_cfg_x; // @[Frontend.scala 371:28]
+ wire [29:0] frontend_io_ptw_pmp_6_addr; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_ptw_pmp_6_mask; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_7_cfg_l; // @[Frontend.scala 371:28]
+ wire [1:0] frontend_io_ptw_pmp_7_cfg_a; // @[Frontend.scala 371:28]
+ wire frontend_io_ptw_pmp_7_cfg_x; // @[Frontend.scala 371:28]
+ wire [29:0] frontend_io_ptw_pmp_7_addr; // @[Frontend.scala 371:28]
+ wire [31:0] frontend_io_ptw_pmp_7_mask; // @[Frontend.scala 371:28]
+ wire [63:0] frontend_io_ptw_customCSRs_csrs_0_value; // @[Frontend.scala 371:28]
+ wire dtim_adapter_clock; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_reset; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_auto_in_a_ready; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_auto_in_a_valid; // @[RocketTile.scala 62:15]
+ wire [2:0] dtim_adapter_auto_in_a_bits_opcode; // @[RocketTile.scala 62:15]
+ wire [2:0] dtim_adapter_auto_in_a_bits_param; // @[RocketTile.scala 62:15]
+ wire [1:0] dtim_adapter_auto_in_a_bits_size; // @[RocketTile.scala 62:15]
+ wire [7:0] dtim_adapter_auto_in_a_bits_source; // @[RocketTile.scala 62:15]
+ wire [31:0] dtim_adapter_auto_in_a_bits_address; // @[RocketTile.scala 62:15]
+ wire [7:0] dtim_adapter_auto_in_a_bits_mask; // @[RocketTile.scala 62:15]
+ wire [63:0] dtim_adapter_auto_in_a_bits_data; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_auto_in_d_ready; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_auto_in_d_valid; // @[RocketTile.scala 62:15]
+ wire [2:0] dtim_adapter_auto_in_d_bits_opcode; // @[RocketTile.scala 62:15]
+ wire [1:0] dtim_adapter_auto_in_d_bits_size; // @[RocketTile.scala 62:15]
+ wire [7:0] dtim_adapter_auto_in_d_bits_source; // @[RocketTile.scala 62:15]
+ wire [63:0] dtim_adapter_auto_in_d_bits_data; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_io_dmem_req_ready; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_io_dmem_req_valid; // @[RocketTile.scala 62:15]
+ wire [33:0] dtim_adapter_io_dmem_req_bits_addr; // @[RocketTile.scala 62:15]
+ wire [4:0] dtim_adapter_io_dmem_req_bits_cmd; // @[RocketTile.scala 62:15]
+ wire [1:0] dtim_adapter_io_dmem_req_bits_size; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_io_dmem_s1_kill; // @[RocketTile.scala 62:15]
+ wire [63:0] dtim_adapter_io_dmem_s1_data_data; // @[RocketTile.scala 62:15]
+ wire [7:0] dtim_adapter_io_dmem_s1_data_mask; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_io_dmem_s2_nack; // @[RocketTile.scala 62:15]
+ wire dtim_adapter_io_dmem_resp_valid; // @[RocketTile.scala 62:15]
+ wire [63:0] dtim_adapter_io_dmem_resp_bits_data_raw; // @[RocketTile.scala 62:15]
+ wire fragmenter_1_clock; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_reset; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_auto_in_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_auto_in_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [31:0] fragmenter_1_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_1_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_1_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_auto_in_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_auto_in_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_1_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_auto_out_a_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_auto_out_a_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_1_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_1_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
+ wire [31:0] fragmenter_1_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_1_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_1_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_auto_out_d_ready; // @[Fragmenter.scala 333:34]
+ wire fragmenter_1_auto_out_d_valid; // @[Fragmenter.scala 333:34]
+ wire [2:0] fragmenter_1_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
+ wire [1:0] fragmenter_1_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
+ wire [7:0] fragmenter_1_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
+ wire [63:0] fragmenter_1_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
+ wire dcacheArb_clock; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_req_valid; // @[HellaCache.scala 280:25]
+ wire [33:0] dcacheArb_io_requestor_0_req_bits_addr; // @[HellaCache.scala 280:25]
+ wire [6:0] dcacheArb_io_requestor_0_req_bits_tag; // @[HellaCache.scala 280:25]
+ wire [4:0] dcacheArb_io_requestor_0_req_bits_cmd; // @[HellaCache.scala 280:25]
+ wire [1:0] dcacheArb_io_requestor_0_req_bits_size; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_req_bits_signed; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_s1_kill; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_requestor_0_s1_data_data; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala 280:25]
+ wire [6:0] dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_1_req_valid; // @[HellaCache.scala 280:25]
+ wire [33:0] dcacheArb_io_requestor_1_req_bits_addr; // @[HellaCache.scala 280:25]
+ wire [4:0] dcacheArb_io_requestor_1_req_bits_cmd; // @[HellaCache.scala 280:25]
+ wire [1:0] dcacheArb_io_requestor_1_req_bits_size; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_1_s1_kill; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_requestor_1_s1_data_data; // @[HellaCache.scala 280:25]
+ wire [7:0] dcacheArb_io_requestor_1_s1_data_mask; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_req_ready; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_req_valid; // @[HellaCache.scala 280:25]
+ wire [33:0] dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala 280:25]
+ wire [6:0] dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala 280:25]
+ wire [4:0] dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala 280:25]
+ wire [1:0] dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala 280:25]
+ wire [1:0] dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_req_bits_no_xcpt; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_s1_kill; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala 280:25]
+ wire [7:0] dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_s2_nack; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_resp_valid; // @[HellaCache.scala 280:25]
+ wire [6:0] dcacheArb_io_mem_resp_bits_tag; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_mem_resp_bits_data; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_resp_bits_replay; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_resp_bits_has_data; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_mem_resp_bits_data_word_bypass; // @[HellaCache.scala 280:25]
+ wire [63:0] dcacheArb_io_mem_resp_bits_data_raw; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_replay_next; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_s2_xcpt_ma_ld; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_s2_xcpt_ma_st; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_s2_xcpt_pf_ld; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_s2_xcpt_pf_st; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_s2_xcpt_ae_ld; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_s2_xcpt_ae_st; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_ordered; // @[HellaCache.scala 280:25]
+ wire dcacheArb_io_mem_perf_grant; // @[HellaCache.scala 280:25]
+ wire ptw_clock; // @[PTW.scala 604:19]
+ wire ptw_reset; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_status_debug; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_status_debug; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala 604:19]
+ wire [63:0] ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_status_debug; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_0_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_dpath_pmp_0_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_0_cfg_x; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_0_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_0_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_dpath_pmp_0_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_dpath_pmp_0_mask; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_1_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_dpath_pmp_1_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_1_cfg_x; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_1_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_1_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_dpath_pmp_1_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_dpath_pmp_1_mask; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_2_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_dpath_pmp_2_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_2_cfg_x; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_2_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_2_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_dpath_pmp_2_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_dpath_pmp_2_mask; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_3_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_dpath_pmp_3_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_3_cfg_x; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_3_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_3_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_dpath_pmp_3_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_dpath_pmp_3_mask; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_4_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_dpath_pmp_4_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_4_cfg_x; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_4_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_4_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_dpath_pmp_4_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_dpath_pmp_4_mask; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_5_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_dpath_pmp_5_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_5_cfg_x; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_5_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_5_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_dpath_pmp_5_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_dpath_pmp_5_mask; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_6_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_dpath_pmp_6_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_6_cfg_x; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_6_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_6_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_dpath_pmp_6_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_dpath_pmp_6_mask; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_7_cfg_l; // @[PTW.scala 604:19]
+ wire [1:0] ptw_io_dpath_pmp_7_cfg_a; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_7_cfg_x; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_7_cfg_w; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_pmp_7_cfg_r; // @[PTW.scala 604:19]
+ wire [29:0] ptw_io_dpath_pmp_7_addr; // @[PTW.scala 604:19]
+ wire [31:0] ptw_io_dpath_pmp_7_mask; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_perf_l2hit; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_perf_pte_miss; // @[PTW.scala 604:19]
+ wire ptw_io_dpath_perf_pte_hit; // @[PTW.scala 604:19]
+ wire [63:0] ptw_io_dpath_customCSRs_csrs_0_value; // @[PTW.scala 604:19]
+ wire core_clock; // @[RocketTile.scala 140:20]
+ wire core_reset; // @[RocketTile.scala 140:20]
+ wire core_io_hartid; // @[RocketTile.scala 140:20]
+ wire core_io_interrupts_debug; // @[RocketTile.scala 140:20]
+ wire core_io_interrupts_mtip; // @[RocketTile.scala 140:20]
+ wire core_io_interrupts_msip; // @[RocketTile.scala 140:20]
+ wire core_io_interrupts_meip; // @[RocketTile.scala 140:20]
+ wire core_io_imem_might_request; // @[RocketTile.scala 140:20]
+ wire core_io_imem_req_valid; // @[RocketTile.scala 140:20]
+ wire [33:0] core_io_imem_req_bits_pc; // @[RocketTile.scala 140:20]
+ wire core_io_imem_req_bits_speculative; // @[RocketTile.scala 140:20]
+ wire core_io_imem_resp_ready; // @[RocketTile.scala 140:20]
+ wire core_io_imem_resp_valid; // @[RocketTile.scala 140:20]
+ wire [33:0] core_io_imem_resp_bits_pc; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_imem_resp_bits_data; // @[RocketTile.scala 140:20]
+ wire core_io_imem_resp_bits_xcpt_ae_inst; // @[RocketTile.scala 140:20]
+ wire core_io_imem_resp_bits_replay; // @[RocketTile.scala 140:20]
+ wire core_io_imem_btb_update_valid; // @[RocketTile.scala 140:20]
+ wire core_io_imem_bht_update_valid; // @[RocketTile.scala 140:20]
+ wire core_io_imem_flush_icache; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_req_ready; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_req_valid; // @[RocketTile.scala 140:20]
+ wire [33:0] core_io_dmem_req_bits_addr; // @[RocketTile.scala 140:20]
+ wire [6:0] core_io_dmem_req_bits_tag; // @[RocketTile.scala 140:20]
+ wire [4:0] core_io_dmem_req_bits_cmd; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_dmem_req_bits_size; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_req_bits_signed; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_req_bits_dv; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_s1_kill; // @[RocketTile.scala 140:20]
+ wire [63:0] core_io_dmem_s1_data_data; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_s2_nack; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_resp_valid; // @[RocketTile.scala 140:20]
+ wire [6:0] core_io_dmem_resp_bits_tag; // @[RocketTile.scala 140:20]
+ wire [63:0] core_io_dmem_resp_bits_data; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_resp_bits_replay; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_resp_bits_has_data; // @[RocketTile.scala 140:20]
+ wire [63:0] core_io_dmem_resp_bits_data_word_bypass; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_replay_next; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_s2_xcpt_ma_ld; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_s2_xcpt_ma_st; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_s2_xcpt_pf_ld; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_s2_xcpt_pf_st; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_s2_xcpt_ae_ld; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_s2_xcpt_ae_st; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_ordered; // @[RocketTile.scala 140:20]
+ wire core_io_dmem_perf_grant; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_status_debug; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala 140:20]
+ wire [29:0] core_io_ptw_pmp_0_addr; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_ptw_pmp_0_mask; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala 140:20]
+ wire [29:0] core_io_ptw_pmp_1_addr; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_ptw_pmp_1_mask; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala 140:20]
+ wire [29:0] core_io_ptw_pmp_2_addr; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_ptw_pmp_2_mask; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala 140:20]
+ wire [29:0] core_io_ptw_pmp_3_addr; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_ptw_pmp_3_mask; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala 140:20]
+ wire [29:0] core_io_ptw_pmp_4_addr; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_ptw_pmp_4_mask; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala 140:20]
+ wire [29:0] core_io_ptw_pmp_5_addr; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_ptw_pmp_5_mask; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala 140:20]
+ wire [29:0] core_io_ptw_pmp_6_addr; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_ptw_pmp_6_mask; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala 140:20]
+ wire [1:0] core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala 140:20]
+ wire core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala 140:20]
+ wire [29:0] core_io_ptw_pmp_7_addr; // @[RocketTile.scala 140:20]
+ wire [31:0] core_io_ptw_pmp_7_mask; // @[RocketTile.scala 140:20]
+ wire [63:0] core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala 140:20]
+ wire core_io_wfi; // @[RocketTile.scala 140:20]
+ reg bundleOut_0_0_REG; // @[Interrupts.scala 126:36]
+ TLXbar_6 tlMasterXbar ( // @[BaseTile.scala 210:42]
+ .clock(tlMasterXbar_clock),
+ .reset(tlMasterXbar_reset),
+ .auto_in_1_a_ready(tlMasterXbar_auto_in_1_a_ready),
+ .auto_in_1_a_valid(tlMasterXbar_auto_in_1_a_valid),
+ .auto_in_1_a_bits_address(tlMasterXbar_auto_in_1_a_bits_address),
+ .auto_in_1_d_valid(tlMasterXbar_auto_in_1_d_valid),
+ .auto_in_1_d_bits_opcode(tlMasterXbar_auto_in_1_d_bits_opcode),
+ .auto_in_1_d_bits_size(tlMasterXbar_auto_in_1_d_bits_size),
+ .auto_in_1_d_bits_data(tlMasterXbar_auto_in_1_d_bits_data),
+ .auto_in_1_d_bits_corrupt(tlMasterXbar_auto_in_1_d_bits_corrupt),
+ .auto_in_0_a_ready(tlMasterXbar_auto_in_0_a_ready),
+ .auto_in_0_a_valid(tlMasterXbar_auto_in_0_a_valid),
+ .auto_in_0_a_bits_opcode(tlMasterXbar_auto_in_0_a_bits_opcode),
+ .auto_in_0_a_bits_param(tlMasterXbar_auto_in_0_a_bits_param),
+ .auto_in_0_a_bits_size(tlMasterXbar_auto_in_0_a_bits_size),
+ .auto_in_0_a_bits_address(tlMasterXbar_auto_in_0_a_bits_address),
+ .auto_in_0_a_bits_mask(tlMasterXbar_auto_in_0_a_bits_mask),
+ .auto_in_0_a_bits_data(tlMasterXbar_auto_in_0_a_bits_data),
+ .auto_in_0_d_ready(tlMasterXbar_auto_in_0_d_ready),
+ .auto_in_0_d_valid(tlMasterXbar_auto_in_0_d_valid),
+ .auto_in_0_d_bits_opcode(tlMasterXbar_auto_in_0_d_bits_opcode),
+ .auto_in_0_d_bits_size(tlMasterXbar_auto_in_0_d_bits_size),
+ .auto_in_0_d_bits_denied(tlMasterXbar_auto_in_0_d_bits_denied),
+ .auto_in_0_d_bits_data(tlMasterXbar_auto_in_0_d_bits_data),
+ .auto_out_a_ready(tlMasterXbar_auto_out_a_ready),
+ .auto_out_a_valid(tlMasterXbar_auto_out_a_valid),
+ .auto_out_a_bits_opcode(tlMasterXbar_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(tlMasterXbar_auto_out_a_bits_param),
+ .auto_out_a_bits_size(tlMasterXbar_auto_out_a_bits_size),
+ .auto_out_a_bits_source(tlMasterXbar_auto_out_a_bits_source),
+ .auto_out_a_bits_address(tlMasterXbar_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(tlMasterXbar_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(tlMasterXbar_auto_out_a_bits_data),
+ .auto_out_d_ready(tlMasterXbar_auto_out_d_ready),
+ .auto_out_d_valid(tlMasterXbar_auto_out_d_valid),
+ .auto_out_d_bits_opcode(tlMasterXbar_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(tlMasterXbar_auto_out_d_bits_param),
+ .auto_out_d_bits_size(tlMasterXbar_auto_out_d_bits_size),
+ .auto_out_d_bits_source(tlMasterXbar_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(tlMasterXbar_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(tlMasterXbar_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(tlMasterXbar_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(tlMasterXbar_auto_out_d_bits_corrupt)
+ );
+ TLXbar_7 tlSlaveXbar ( // @[BaseTile.scala 211:41]
+ .auto_in_a_ready(tlSlaveXbar_auto_in_a_ready),
+ .auto_in_a_valid(tlSlaveXbar_auto_in_a_valid),
+ .auto_in_a_bits_opcode(tlSlaveXbar_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(tlSlaveXbar_auto_in_a_bits_param),
+ .auto_in_a_bits_size(tlSlaveXbar_auto_in_a_bits_size),
+ .auto_in_a_bits_source(tlSlaveXbar_auto_in_a_bits_source),
+ .auto_in_a_bits_address(tlSlaveXbar_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(tlSlaveXbar_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(tlSlaveXbar_auto_in_a_bits_data),
+ .auto_in_d_ready(tlSlaveXbar_auto_in_d_ready),
+ .auto_in_d_valid(tlSlaveXbar_auto_in_d_valid),
+ .auto_in_d_bits_opcode(tlSlaveXbar_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(tlSlaveXbar_auto_in_d_bits_size),
+ .auto_in_d_bits_source(tlSlaveXbar_auto_in_d_bits_source),
+ .auto_in_d_bits_data(tlSlaveXbar_auto_in_d_bits_data),
+ .auto_out_a_ready(tlSlaveXbar_auto_out_a_ready),
+ .auto_out_a_valid(tlSlaveXbar_auto_out_a_valid),
+ .auto_out_a_bits_opcode(tlSlaveXbar_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(tlSlaveXbar_auto_out_a_bits_param),
+ .auto_out_a_bits_size(tlSlaveXbar_auto_out_a_bits_size),
+ .auto_out_a_bits_source(tlSlaveXbar_auto_out_a_bits_source),
+ .auto_out_a_bits_address(tlSlaveXbar_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(tlSlaveXbar_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(tlSlaveXbar_auto_out_a_bits_data),
+ .auto_out_d_ready(tlSlaveXbar_auto_out_d_ready),
+ .auto_out_d_valid(tlSlaveXbar_auto_out_d_valid),
+ .auto_out_d_bits_opcode(tlSlaveXbar_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(tlSlaveXbar_auto_out_d_bits_size),
+ .auto_out_d_bits_source(tlSlaveXbar_auto_out_d_bits_source),
+ .auto_out_d_bits_data(tlSlaveXbar_auto_out_d_bits_data)
+ );
+ IntXbar_1 intXbar ( // @[BaseTile.scala 212:37]
+ .auto_int_in_2_0(intXbar_auto_int_in_2_0),
+ .auto_int_in_1_0(intXbar_auto_int_in_1_0),
+ .auto_int_in_1_1(intXbar_auto_int_in_1_1),
+ .auto_int_in_0_0(intXbar_auto_int_in_0_0),
+ .auto_int_out_0(intXbar_auto_int_out_0),
+ .auto_int_out_1(intXbar_auto_int_out_1),
+ .auto_int_out_2(intXbar_auto_int_out_2),
+ .auto_int_out_3(intXbar_auto_int_out_3)
+ );
+ BundleBridgeNexus_4 broadcast ( // @[BundleBridge.scala 196:31]
+ .auto_in(broadcast_auto_in),
+ .auto_out_0(broadcast_auto_out_0)
+ );
+ DCache dcache ( // @[HellaCache.scala 269:43]
+ .clock(dcache_clock),
+ .reset(dcache_reset),
+ .auto_out_a_ready(dcache_auto_out_a_ready),
+ .auto_out_a_valid(dcache_auto_out_a_valid),
+ .auto_out_a_bits_opcode(dcache_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(dcache_auto_out_a_bits_param),
+ .auto_out_a_bits_size(dcache_auto_out_a_bits_size),
+ .auto_out_a_bits_address(dcache_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(dcache_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(dcache_auto_out_a_bits_data),
+ .auto_out_d_ready(dcache_auto_out_d_ready),
+ .auto_out_d_valid(dcache_auto_out_d_valid),
+ .auto_out_d_bits_opcode(dcache_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(dcache_auto_out_d_bits_size),
+ .auto_out_d_bits_denied(dcache_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(dcache_auto_out_d_bits_data),
+ .io_cpu_req_ready(dcache_io_cpu_req_ready),
+ .io_cpu_req_valid(dcache_io_cpu_req_valid),
+ .io_cpu_req_bits_addr(dcache_io_cpu_req_bits_addr),
+ .io_cpu_req_bits_tag(dcache_io_cpu_req_bits_tag),
+ .io_cpu_req_bits_cmd(dcache_io_cpu_req_bits_cmd),
+ .io_cpu_req_bits_size(dcache_io_cpu_req_bits_size),
+ .io_cpu_req_bits_signed(dcache_io_cpu_req_bits_signed),
+ .io_cpu_req_bits_dprv(dcache_io_cpu_req_bits_dprv),
+ .io_cpu_req_bits_no_xcpt(dcache_io_cpu_req_bits_no_xcpt),
+ .io_cpu_s1_kill(dcache_io_cpu_s1_kill),
+ .io_cpu_s1_data_data(dcache_io_cpu_s1_data_data),
+ .io_cpu_s1_data_mask(dcache_io_cpu_s1_data_mask),
+ .io_cpu_s2_nack(dcache_io_cpu_s2_nack),
+ .io_cpu_resp_valid(dcache_io_cpu_resp_valid),
+ .io_cpu_resp_bits_addr(dcache_io_cpu_resp_bits_addr),
+ .io_cpu_resp_bits_tag(dcache_io_cpu_resp_bits_tag),
+ .io_cpu_resp_bits_cmd(dcache_io_cpu_resp_bits_cmd),
+ .io_cpu_resp_bits_size(dcache_io_cpu_resp_bits_size),
+ .io_cpu_resp_bits_signed(dcache_io_cpu_resp_bits_signed),
+ .io_cpu_resp_bits_dprv(dcache_io_cpu_resp_bits_dprv),
+ .io_cpu_resp_bits_dv(dcache_io_cpu_resp_bits_dv),
+ .io_cpu_resp_bits_data(dcache_io_cpu_resp_bits_data),
+ .io_cpu_resp_bits_mask(dcache_io_cpu_resp_bits_mask),
+ .io_cpu_resp_bits_replay(dcache_io_cpu_resp_bits_replay),
+ .io_cpu_resp_bits_has_data(dcache_io_cpu_resp_bits_has_data),
+ .io_cpu_resp_bits_data_word_bypass(dcache_io_cpu_resp_bits_data_word_bypass),
+ .io_cpu_resp_bits_data_raw(dcache_io_cpu_resp_bits_data_raw),
+ .io_cpu_resp_bits_store_data(dcache_io_cpu_resp_bits_store_data),
+ .io_cpu_replay_next(dcache_io_cpu_replay_next),
+ .io_cpu_s2_xcpt_ma_ld(dcache_io_cpu_s2_xcpt_ma_ld),
+ .io_cpu_s2_xcpt_ma_st(dcache_io_cpu_s2_xcpt_ma_st),
+ .io_cpu_s2_xcpt_pf_ld(dcache_io_cpu_s2_xcpt_pf_ld),
+ .io_cpu_s2_xcpt_pf_st(dcache_io_cpu_s2_xcpt_pf_st),
+ .io_cpu_s2_xcpt_gf_ld(dcache_io_cpu_s2_xcpt_gf_ld),
+ .io_cpu_s2_xcpt_gf_st(dcache_io_cpu_s2_xcpt_gf_st),
+ .io_cpu_s2_xcpt_ae_ld(dcache_io_cpu_s2_xcpt_ae_ld),
+ .io_cpu_s2_xcpt_ae_st(dcache_io_cpu_s2_xcpt_ae_st),
+ .io_cpu_ordered(dcache_io_cpu_ordered),
+ .io_cpu_perf_grant(dcache_io_cpu_perf_grant),
+ .io_ptw_status_debug(dcache_io_ptw_status_debug),
+ .io_ptw_pmp_0_cfg_l(dcache_io_ptw_pmp_0_cfg_l),
+ .io_ptw_pmp_0_cfg_a(dcache_io_ptw_pmp_0_cfg_a),
+ .io_ptw_pmp_0_cfg_w(dcache_io_ptw_pmp_0_cfg_w),
+ .io_ptw_pmp_0_cfg_r(dcache_io_ptw_pmp_0_cfg_r),
+ .io_ptw_pmp_0_addr(dcache_io_ptw_pmp_0_addr),
+ .io_ptw_pmp_0_mask(dcache_io_ptw_pmp_0_mask),
+ .io_ptw_pmp_1_cfg_l(dcache_io_ptw_pmp_1_cfg_l),
+ .io_ptw_pmp_1_cfg_a(dcache_io_ptw_pmp_1_cfg_a),
+ .io_ptw_pmp_1_cfg_w(dcache_io_ptw_pmp_1_cfg_w),
+ .io_ptw_pmp_1_cfg_r(dcache_io_ptw_pmp_1_cfg_r),
+ .io_ptw_pmp_1_addr(dcache_io_ptw_pmp_1_addr),
+ .io_ptw_pmp_1_mask(dcache_io_ptw_pmp_1_mask),
+ .io_ptw_pmp_2_cfg_l(dcache_io_ptw_pmp_2_cfg_l),
+ .io_ptw_pmp_2_cfg_a(dcache_io_ptw_pmp_2_cfg_a),
+ .io_ptw_pmp_2_cfg_w(dcache_io_ptw_pmp_2_cfg_w),
+ .io_ptw_pmp_2_cfg_r(dcache_io_ptw_pmp_2_cfg_r),
+ .io_ptw_pmp_2_addr(dcache_io_ptw_pmp_2_addr),
+ .io_ptw_pmp_2_mask(dcache_io_ptw_pmp_2_mask),
+ .io_ptw_pmp_3_cfg_l(dcache_io_ptw_pmp_3_cfg_l),
+ .io_ptw_pmp_3_cfg_a(dcache_io_ptw_pmp_3_cfg_a),
+ .io_ptw_pmp_3_cfg_w(dcache_io_ptw_pmp_3_cfg_w),
+ .io_ptw_pmp_3_cfg_r(dcache_io_ptw_pmp_3_cfg_r),
+ .io_ptw_pmp_3_addr(dcache_io_ptw_pmp_3_addr),
+ .io_ptw_pmp_3_mask(dcache_io_ptw_pmp_3_mask),
+ .io_ptw_pmp_4_cfg_l(dcache_io_ptw_pmp_4_cfg_l),
+ .io_ptw_pmp_4_cfg_a(dcache_io_ptw_pmp_4_cfg_a),
+ .io_ptw_pmp_4_cfg_w(dcache_io_ptw_pmp_4_cfg_w),
+ .io_ptw_pmp_4_cfg_r(dcache_io_ptw_pmp_4_cfg_r),
+ .io_ptw_pmp_4_addr(dcache_io_ptw_pmp_4_addr),
+ .io_ptw_pmp_4_mask(dcache_io_ptw_pmp_4_mask),
+ .io_ptw_pmp_5_cfg_l(dcache_io_ptw_pmp_5_cfg_l),
+ .io_ptw_pmp_5_cfg_a(dcache_io_ptw_pmp_5_cfg_a),
+ .io_ptw_pmp_5_cfg_w(dcache_io_ptw_pmp_5_cfg_w),
+ .io_ptw_pmp_5_cfg_r(dcache_io_ptw_pmp_5_cfg_r),
+ .io_ptw_pmp_5_addr(dcache_io_ptw_pmp_5_addr),
+ .io_ptw_pmp_5_mask(dcache_io_ptw_pmp_5_mask),
+ .io_ptw_pmp_6_cfg_l(dcache_io_ptw_pmp_6_cfg_l),
+ .io_ptw_pmp_6_cfg_a(dcache_io_ptw_pmp_6_cfg_a),
+ .io_ptw_pmp_6_cfg_w(dcache_io_ptw_pmp_6_cfg_w),
+ .io_ptw_pmp_6_cfg_r(dcache_io_ptw_pmp_6_cfg_r),
+ .io_ptw_pmp_6_addr(dcache_io_ptw_pmp_6_addr),
+ .io_ptw_pmp_6_mask(dcache_io_ptw_pmp_6_mask),
+ .io_ptw_pmp_7_cfg_l(dcache_io_ptw_pmp_7_cfg_l),
+ .io_ptw_pmp_7_cfg_a(dcache_io_ptw_pmp_7_cfg_a),
+ .io_ptw_pmp_7_cfg_w(dcache_io_ptw_pmp_7_cfg_w),
+ .io_ptw_pmp_7_cfg_r(dcache_io_ptw_pmp_7_cfg_r),
+ .io_ptw_pmp_7_addr(dcache_io_ptw_pmp_7_addr),
+ .io_ptw_pmp_7_mask(dcache_io_ptw_pmp_7_mask)
+ );
+ Frontend frontend ( // @[Frontend.scala 371:28]
+ .clock(frontend_clock),
+ .reset(frontend_reset),
+ .auto_icache_master_out_a_ready(frontend_auto_icache_master_out_a_ready),
+ .auto_icache_master_out_a_valid(frontend_auto_icache_master_out_a_valid),
+ .auto_icache_master_out_a_bits_address(frontend_auto_icache_master_out_a_bits_address),
+ .auto_icache_master_out_d_valid(frontend_auto_icache_master_out_d_valid),
+ .auto_icache_master_out_d_bits_opcode(frontend_auto_icache_master_out_d_bits_opcode),
+ .auto_icache_master_out_d_bits_size(frontend_auto_icache_master_out_d_bits_size),
+ .auto_icache_master_out_d_bits_data(frontend_auto_icache_master_out_d_bits_data),
+ .auto_icache_master_out_d_bits_corrupt(frontend_auto_icache_master_out_d_bits_corrupt),
+ .io_cpu_might_request(frontend_io_cpu_might_request),
+ .io_cpu_req_valid(frontend_io_cpu_req_valid),
+ .io_cpu_req_bits_pc(frontend_io_cpu_req_bits_pc),
+ .io_cpu_req_bits_speculative(frontend_io_cpu_req_bits_speculative),
+ .io_cpu_resp_ready(frontend_io_cpu_resp_ready),
+ .io_cpu_resp_valid(frontend_io_cpu_resp_valid),
+ .io_cpu_resp_bits_pc(frontend_io_cpu_resp_bits_pc),
+ .io_cpu_resp_bits_data(frontend_io_cpu_resp_bits_data),
+ .io_cpu_resp_bits_xcpt_ae_inst(frontend_io_cpu_resp_bits_xcpt_ae_inst),
+ .io_cpu_resp_bits_replay(frontend_io_cpu_resp_bits_replay),
+ .io_cpu_btb_update_valid(frontend_io_cpu_btb_update_valid),
+ .io_cpu_bht_update_valid(frontend_io_cpu_bht_update_valid),
+ .io_cpu_flush_icache(frontend_io_cpu_flush_icache),
+ .io_cpu_npc(frontend_io_cpu_npc),
+ .io_ptw_status_debug(frontend_io_ptw_status_debug),
+ .io_ptw_pmp_0_cfg_l(frontend_io_ptw_pmp_0_cfg_l),
+ .io_ptw_pmp_0_cfg_a(frontend_io_ptw_pmp_0_cfg_a),
+ .io_ptw_pmp_0_cfg_x(frontend_io_ptw_pmp_0_cfg_x),
+ .io_ptw_pmp_0_addr(frontend_io_ptw_pmp_0_addr),
+ .io_ptw_pmp_0_mask(frontend_io_ptw_pmp_0_mask),
+ .io_ptw_pmp_1_cfg_l(frontend_io_ptw_pmp_1_cfg_l),
+ .io_ptw_pmp_1_cfg_a(frontend_io_ptw_pmp_1_cfg_a),
+ .io_ptw_pmp_1_cfg_x(frontend_io_ptw_pmp_1_cfg_x),
+ .io_ptw_pmp_1_addr(frontend_io_ptw_pmp_1_addr),
+ .io_ptw_pmp_1_mask(frontend_io_ptw_pmp_1_mask),
+ .io_ptw_pmp_2_cfg_l(frontend_io_ptw_pmp_2_cfg_l),
+ .io_ptw_pmp_2_cfg_a(frontend_io_ptw_pmp_2_cfg_a),
+ .io_ptw_pmp_2_cfg_x(frontend_io_ptw_pmp_2_cfg_x),
+ .io_ptw_pmp_2_addr(frontend_io_ptw_pmp_2_addr),
+ .io_ptw_pmp_2_mask(frontend_io_ptw_pmp_2_mask),
+ .io_ptw_pmp_3_cfg_l(frontend_io_ptw_pmp_3_cfg_l),
+ .io_ptw_pmp_3_cfg_a(frontend_io_ptw_pmp_3_cfg_a),
+ .io_ptw_pmp_3_cfg_x(frontend_io_ptw_pmp_3_cfg_x),
+ .io_ptw_pmp_3_addr(frontend_io_ptw_pmp_3_addr),
+ .io_ptw_pmp_3_mask(frontend_io_ptw_pmp_3_mask),
+ .io_ptw_pmp_4_cfg_l(frontend_io_ptw_pmp_4_cfg_l),
+ .io_ptw_pmp_4_cfg_a(frontend_io_ptw_pmp_4_cfg_a),
+ .io_ptw_pmp_4_cfg_x(frontend_io_ptw_pmp_4_cfg_x),
+ .io_ptw_pmp_4_addr(frontend_io_ptw_pmp_4_addr),
+ .io_ptw_pmp_4_mask(frontend_io_ptw_pmp_4_mask),
+ .io_ptw_pmp_5_cfg_l(frontend_io_ptw_pmp_5_cfg_l),
+ .io_ptw_pmp_5_cfg_a(frontend_io_ptw_pmp_5_cfg_a),
+ .io_ptw_pmp_5_cfg_x(frontend_io_ptw_pmp_5_cfg_x),
+ .io_ptw_pmp_5_addr(frontend_io_ptw_pmp_5_addr),
+ .io_ptw_pmp_5_mask(frontend_io_ptw_pmp_5_mask),
+ .io_ptw_pmp_6_cfg_l(frontend_io_ptw_pmp_6_cfg_l),
+ .io_ptw_pmp_6_cfg_a(frontend_io_ptw_pmp_6_cfg_a),
+ .io_ptw_pmp_6_cfg_x(frontend_io_ptw_pmp_6_cfg_x),
+ .io_ptw_pmp_6_addr(frontend_io_ptw_pmp_6_addr),
+ .io_ptw_pmp_6_mask(frontend_io_ptw_pmp_6_mask),
+ .io_ptw_pmp_7_cfg_l(frontend_io_ptw_pmp_7_cfg_l),
+ .io_ptw_pmp_7_cfg_a(frontend_io_ptw_pmp_7_cfg_a),
+ .io_ptw_pmp_7_cfg_x(frontend_io_ptw_pmp_7_cfg_x),
+ .io_ptw_pmp_7_addr(frontend_io_ptw_pmp_7_addr),
+ .io_ptw_pmp_7_mask(frontend_io_ptw_pmp_7_mask),
+ .io_ptw_customCSRs_csrs_0_value(frontend_io_ptw_customCSRs_csrs_0_value)
+ );
+ ScratchpadSlavePort dtim_adapter ( // @[RocketTile.scala 62:15]
+ .clock(dtim_adapter_clock),
+ .reset(dtim_adapter_reset),
+ .auto_in_a_ready(dtim_adapter_auto_in_a_ready),
+ .auto_in_a_valid(dtim_adapter_auto_in_a_valid),
+ .auto_in_a_bits_opcode(dtim_adapter_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(dtim_adapter_auto_in_a_bits_param),
+ .auto_in_a_bits_size(dtim_adapter_auto_in_a_bits_size),
+ .auto_in_a_bits_source(dtim_adapter_auto_in_a_bits_source),
+ .auto_in_a_bits_address(dtim_adapter_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(dtim_adapter_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(dtim_adapter_auto_in_a_bits_data),
+ .auto_in_d_ready(dtim_adapter_auto_in_d_ready),
+ .auto_in_d_valid(dtim_adapter_auto_in_d_valid),
+ .auto_in_d_bits_opcode(dtim_adapter_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(dtim_adapter_auto_in_d_bits_size),
+ .auto_in_d_bits_source(dtim_adapter_auto_in_d_bits_source),
+ .auto_in_d_bits_data(dtim_adapter_auto_in_d_bits_data),
+ .io_dmem_req_ready(dtim_adapter_io_dmem_req_ready),
+ .io_dmem_req_valid(dtim_adapter_io_dmem_req_valid),
+ .io_dmem_req_bits_addr(dtim_adapter_io_dmem_req_bits_addr),
+ .io_dmem_req_bits_cmd(dtim_adapter_io_dmem_req_bits_cmd),
+ .io_dmem_req_bits_size(dtim_adapter_io_dmem_req_bits_size),
+ .io_dmem_s1_kill(dtim_adapter_io_dmem_s1_kill),
+ .io_dmem_s1_data_data(dtim_adapter_io_dmem_s1_data_data),
+ .io_dmem_s1_data_mask(dtim_adapter_io_dmem_s1_data_mask),
+ .io_dmem_s2_nack(dtim_adapter_io_dmem_s2_nack),
+ .io_dmem_resp_valid(dtim_adapter_io_dmem_resp_valid),
+ .io_dmem_resp_bits_data_raw(dtim_adapter_io_dmem_resp_bits_data_raw)
+ );
+ TLFragmenter_15 fragmenter_1 ( // @[Fragmenter.scala 333:34]
+ .clock(fragmenter_1_clock),
+ .reset(fragmenter_1_reset),
+ .auto_in_a_ready(fragmenter_1_auto_in_a_ready),
+ .auto_in_a_valid(fragmenter_1_auto_in_a_valid),
+ .auto_in_a_bits_opcode(fragmenter_1_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(fragmenter_1_auto_in_a_bits_param),
+ .auto_in_a_bits_size(fragmenter_1_auto_in_a_bits_size),
+ .auto_in_a_bits_source(fragmenter_1_auto_in_a_bits_source),
+ .auto_in_a_bits_address(fragmenter_1_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(fragmenter_1_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(fragmenter_1_auto_in_a_bits_data),
+ .auto_in_d_ready(fragmenter_1_auto_in_d_ready),
+ .auto_in_d_valid(fragmenter_1_auto_in_d_valid),
+ .auto_in_d_bits_opcode(fragmenter_1_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(fragmenter_1_auto_in_d_bits_size),
+ .auto_in_d_bits_source(fragmenter_1_auto_in_d_bits_source),
+ .auto_in_d_bits_data(fragmenter_1_auto_in_d_bits_data),
+ .auto_out_a_ready(fragmenter_1_auto_out_a_ready),
+ .auto_out_a_valid(fragmenter_1_auto_out_a_valid),
+ .auto_out_a_bits_opcode(fragmenter_1_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(fragmenter_1_auto_out_a_bits_param),
+ .auto_out_a_bits_size(fragmenter_1_auto_out_a_bits_size),
+ .auto_out_a_bits_source(fragmenter_1_auto_out_a_bits_source),
+ .auto_out_a_bits_address(fragmenter_1_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(fragmenter_1_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(fragmenter_1_auto_out_a_bits_data),
+ .auto_out_d_ready(fragmenter_1_auto_out_d_ready),
+ .auto_out_d_valid(fragmenter_1_auto_out_d_valid),
+ .auto_out_d_bits_opcode(fragmenter_1_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(fragmenter_1_auto_out_d_bits_size),
+ .auto_out_d_bits_source(fragmenter_1_auto_out_d_bits_source),
+ .auto_out_d_bits_data(fragmenter_1_auto_out_d_bits_data)
+ );
+ HellaCacheArbiter dcacheArb ( // @[HellaCache.scala 280:25]
+ .clock(dcacheArb_clock),
+ .io_requestor_0_req_ready(dcacheArb_io_requestor_0_req_ready),
+ .io_requestor_0_req_valid(dcacheArb_io_requestor_0_req_valid),
+ .io_requestor_0_req_bits_addr(dcacheArb_io_requestor_0_req_bits_addr),
+ .io_requestor_0_req_bits_tag(dcacheArb_io_requestor_0_req_bits_tag),
+ .io_requestor_0_req_bits_cmd(dcacheArb_io_requestor_0_req_bits_cmd),
+ .io_requestor_0_req_bits_size(dcacheArb_io_requestor_0_req_bits_size),
+ .io_requestor_0_req_bits_signed(dcacheArb_io_requestor_0_req_bits_signed),
+ .io_requestor_0_s1_kill(dcacheArb_io_requestor_0_s1_kill),
+ .io_requestor_0_s1_data_data(dcacheArb_io_requestor_0_s1_data_data),
+ .io_requestor_0_s2_nack(dcacheArb_io_requestor_0_s2_nack),
+ .io_requestor_0_resp_valid(dcacheArb_io_requestor_0_resp_valid),
+ .io_requestor_0_resp_bits_tag(dcacheArb_io_requestor_0_resp_bits_tag),
+ .io_requestor_0_resp_bits_data(dcacheArb_io_requestor_0_resp_bits_data),
+ .io_requestor_0_resp_bits_replay(dcacheArb_io_requestor_0_resp_bits_replay),
+ .io_requestor_0_resp_bits_has_data(dcacheArb_io_requestor_0_resp_bits_has_data),
+ .io_requestor_0_resp_bits_data_word_bypass(dcacheArb_io_requestor_0_resp_bits_data_word_bypass),
+ .io_requestor_0_replay_next(dcacheArb_io_requestor_0_replay_next),
+ .io_requestor_0_s2_xcpt_ma_ld(dcacheArb_io_requestor_0_s2_xcpt_ma_ld),
+ .io_requestor_0_s2_xcpt_ma_st(dcacheArb_io_requestor_0_s2_xcpt_ma_st),
+ .io_requestor_0_s2_xcpt_pf_ld(dcacheArb_io_requestor_0_s2_xcpt_pf_ld),
+ .io_requestor_0_s2_xcpt_pf_st(dcacheArb_io_requestor_0_s2_xcpt_pf_st),
+ .io_requestor_0_s2_xcpt_ae_ld(dcacheArb_io_requestor_0_s2_xcpt_ae_ld),
+ .io_requestor_0_s2_xcpt_ae_st(dcacheArb_io_requestor_0_s2_xcpt_ae_st),
+ .io_requestor_0_ordered(dcacheArb_io_requestor_0_ordered),
+ .io_requestor_0_perf_grant(dcacheArb_io_requestor_0_perf_grant),
+ .io_requestor_1_req_ready(dcacheArb_io_requestor_1_req_ready),
+ .io_requestor_1_req_valid(dcacheArb_io_requestor_1_req_valid),
+ .io_requestor_1_req_bits_addr(dcacheArb_io_requestor_1_req_bits_addr),
+ .io_requestor_1_req_bits_cmd(dcacheArb_io_requestor_1_req_bits_cmd),
+ .io_requestor_1_req_bits_size(dcacheArb_io_requestor_1_req_bits_size),
+ .io_requestor_1_s1_kill(dcacheArb_io_requestor_1_s1_kill),
+ .io_requestor_1_s1_data_data(dcacheArb_io_requestor_1_s1_data_data),
+ .io_requestor_1_s1_data_mask(dcacheArb_io_requestor_1_s1_data_mask),
+ .io_requestor_1_s2_nack(dcacheArb_io_requestor_1_s2_nack),
+ .io_requestor_1_resp_valid(dcacheArb_io_requestor_1_resp_valid),
+ .io_requestor_1_resp_bits_data_raw(dcacheArb_io_requestor_1_resp_bits_data_raw),
+ .io_mem_req_ready(dcacheArb_io_mem_req_ready),
+ .io_mem_req_valid(dcacheArb_io_mem_req_valid),
+ .io_mem_req_bits_addr(dcacheArb_io_mem_req_bits_addr),
+ .io_mem_req_bits_tag(dcacheArb_io_mem_req_bits_tag),
+ .io_mem_req_bits_cmd(dcacheArb_io_mem_req_bits_cmd),
+ .io_mem_req_bits_size(dcacheArb_io_mem_req_bits_size),
+ .io_mem_req_bits_signed(dcacheArb_io_mem_req_bits_signed),
+ .io_mem_req_bits_dprv(dcacheArb_io_mem_req_bits_dprv),
+ .io_mem_req_bits_no_xcpt(dcacheArb_io_mem_req_bits_no_xcpt),
+ .io_mem_s1_kill(dcacheArb_io_mem_s1_kill),
+ .io_mem_s1_data_data(dcacheArb_io_mem_s1_data_data),
+ .io_mem_s1_data_mask(dcacheArb_io_mem_s1_data_mask),
+ .io_mem_s2_nack(dcacheArb_io_mem_s2_nack),
+ .io_mem_resp_valid(dcacheArb_io_mem_resp_valid),
+ .io_mem_resp_bits_tag(dcacheArb_io_mem_resp_bits_tag),
+ .io_mem_resp_bits_data(dcacheArb_io_mem_resp_bits_data),
+ .io_mem_resp_bits_replay(dcacheArb_io_mem_resp_bits_replay),
+ .io_mem_resp_bits_has_data(dcacheArb_io_mem_resp_bits_has_data),
+ .io_mem_resp_bits_data_word_bypass(dcacheArb_io_mem_resp_bits_data_word_bypass),
+ .io_mem_resp_bits_data_raw(dcacheArb_io_mem_resp_bits_data_raw),
+ .io_mem_replay_next(dcacheArb_io_mem_replay_next),
+ .io_mem_s2_xcpt_ma_ld(dcacheArb_io_mem_s2_xcpt_ma_ld),
+ .io_mem_s2_xcpt_ma_st(dcacheArb_io_mem_s2_xcpt_ma_st),
+ .io_mem_s2_xcpt_pf_ld(dcacheArb_io_mem_s2_xcpt_pf_ld),
+ .io_mem_s2_xcpt_pf_st(dcacheArb_io_mem_s2_xcpt_pf_st),
+ .io_mem_s2_xcpt_ae_ld(dcacheArb_io_mem_s2_xcpt_ae_ld),
+ .io_mem_s2_xcpt_ae_st(dcacheArb_io_mem_s2_xcpt_ae_st),
+ .io_mem_ordered(dcacheArb_io_mem_ordered),
+ .io_mem_perf_grant(dcacheArb_io_mem_perf_grant)
+ );
+ PTW ptw ( // @[PTW.scala 604:19]
+ .clock(ptw_clock),
+ .reset(ptw_reset),
+ .io_requestor_0_status_debug(ptw_io_requestor_0_status_debug),
+ .io_requestor_0_pmp_0_cfg_l(ptw_io_requestor_0_pmp_0_cfg_l),
+ .io_requestor_0_pmp_0_cfg_a(ptw_io_requestor_0_pmp_0_cfg_a),
+ .io_requestor_0_pmp_0_cfg_w(ptw_io_requestor_0_pmp_0_cfg_w),
+ .io_requestor_0_pmp_0_cfg_r(ptw_io_requestor_0_pmp_0_cfg_r),
+ .io_requestor_0_pmp_0_addr(ptw_io_requestor_0_pmp_0_addr),
+ .io_requestor_0_pmp_0_mask(ptw_io_requestor_0_pmp_0_mask),
+ .io_requestor_0_pmp_1_cfg_l(ptw_io_requestor_0_pmp_1_cfg_l),
+ .io_requestor_0_pmp_1_cfg_a(ptw_io_requestor_0_pmp_1_cfg_a),
+ .io_requestor_0_pmp_1_cfg_w(ptw_io_requestor_0_pmp_1_cfg_w),
+ .io_requestor_0_pmp_1_cfg_r(ptw_io_requestor_0_pmp_1_cfg_r),
+ .io_requestor_0_pmp_1_addr(ptw_io_requestor_0_pmp_1_addr),
+ .io_requestor_0_pmp_1_mask(ptw_io_requestor_0_pmp_1_mask),
+ .io_requestor_0_pmp_2_cfg_l(ptw_io_requestor_0_pmp_2_cfg_l),
+ .io_requestor_0_pmp_2_cfg_a(ptw_io_requestor_0_pmp_2_cfg_a),
+ .io_requestor_0_pmp_2_cfg_w(ptw_io_requestor_0_pmp_2_cfg_w),
+ .io_requestor_0_pmp_2_cfg_r(ptw_io_requestor_0_pmp_2_cfg_r),
+ .io_requestor_0_pmp_2_addr(ptw_io_requestor_0_pmp_2_addr),
+ .io_requestor_0_pmp_2_mask(ptw_io_requestor_0_pmp_2_mask),
+ .io_requestor_0_pmp_3_cfg_l(ptw_io_requestor_0_pmp_3_cfg_l),
+ .io_requestor_0_pmp_3_cfg_a(ptw_io_requestor_0_pmp_3_cfg_a),
+ .io_requestor_0_pmp_3_cfg_w(ptw_io_requestor_0_pmp_3_cfg_w),
+ .io_requestor_0_pmp_3_cfg_r(ptw_io_requestor_0_pmp_3_cfg_r),
+ .io_requestor_0_pmp_3_addr(ptw_io_requestor_0_pmp_3_addr),
+ .io_requestor_0_pmp_3_mask(ptw_io_requestor_0_pmp_3_mask),
+ .io_requestor_0_pmp_4_cfg_l(ptw_io_requestor_0_pmp_4_cfg_l),
+ .io_requestor_0_pmp_4_cfg_a(ptw_io_requestor_0_pmp_4_cfg_a),
+ .io_requestor_0_pmp_4_cfg_w(ptw_io_requestor_0_pmp_4_cfg_w),
+ .io_requestor_0_pmp_4_cfg_r(ptw_io_requestor_0_pmp_4_cfg_r),
+ .io_requestor_0_pmp_4_addr(ptw_io_requestor_0_pmp_4_addr),
+ .io_requestor_0_pmp_4_mask(ptw_io_requestor_0_pmp_4_mask),
+ .io_requestor_0_pmp_5_cfg_l(ptw_io_requestor_0_pmp_5_cfg_l),
+ .io_requestor_0_pmp_5_cfg_a(ptw_io_requestor_0_pmp_5_cfg_a),
+ .io_requestor_0_pmp_5_cfg_w(ptw_io_requestor_0_pmp_5_cfg_w),
+ .io_requestor_0_pmp_5_cfg_r(ptw_io_requestor_0_pmp_5_cfg_r),
+ .io_requestor_0_pmp_5_addr(ptw_io_requestor_0_pmp_5_addr),
+ .io_requestor_0_pmp_5_mask(ptw_io_requestor_0_pmp_5_mask),
+ .io_requestor_0_pmp_6_cfg_l(ptw_io_requestor_0_pmp_6_cfg_l),
+ .io_requestor_0_pmp_6_cfg_a(ptw_io_requestor_0_pmp_6_cfg_a),
+ .io_requestor_0_pmp_6_cfg_w(ptw_io_requestor_0_pmp_6_cfg_w),
+ .io_requestor_0_pmp_6_cfg_r(ptw_io_requestor_0_pmp_6_cfg_r),
+ .io_requestor_0_pmp_6_addr(ptw_io_requestor_0_pmp_6_addr),
+ .io_requestor_0_pmp_6_mask(ptw_io_requestor_0_pmp_6_mask),
+ .io_requestor_0_pmp_7_cfg_l(ptw_io_requestor_0_pmp_7_cfg_l),
+ .io_requestor_0_pmp_7_cfg_a(ptw_io_requestor_0_pmp_7_cfg_a),
+ .io_requestor_0_pmp_7_cfg_w(ptw_io_requestor_0_pmp_7_cfg_w),
+ .io_requestor_0_pmp_7_cfg_r(ptw_io_requestor_0_pmp_7_cfg_r),
+ .io_requestor_0_pmp_7_addr(ptw_io_requestor_0_pmp_7_addr),
+ .io_requestor_0_pmp_7_mask(ptw_io_requestor_0_pmp_7_mask),
+ .io_requestor_1_status_debug(ptw_io_requestor_1_status_debug),
+ .io_requestor_1_pmp_0_cfg_l(ptw_io_requestor_1_pmp_0_cfg_l),
+ .io_requestor_1_pmp_0_cfg_a(ptw_io_requestor_1_pmp_0_cfg_a),
+ .io_requestor_1_pmp_0_cfg_x(ptw_io_requestor_1_pmp_0_cfg_x),
+ .io_requestor_1_pmp_0_addr(ptw_io_requestor_1_pmp_0_addr),
+ .io_requestor_1_pmp_0_mask(ptw_io_requestor_1_pmp_0_mask),
+ .io_requestor_1_pmp_1_cfg_l(ptw_io_requestor_1_pmp_1_cfg_l),
+ .io_requestor_1_pmp_1_cfg_a(ptw_io_requestor_1_pmp_1_cfg_a),
+ .io_requestor_1_pmp_1_cfg_x(ptw_io_requestor_1_pmp_1_cfg_x),
+ .io_requestor_1_pmp_1_addr(ptw_io_requestor_1_pmp_1_addr),
+ .io_requestor_1_pmp_1_mask(ptw_io_requestor_1_pmp_1_mask),
+ .io_requestor_1_pmp_2_cfg_l(ptw_io_requestor_1_pmp_2_cfg_l),
+ .io_requestor_1_pmp_2_cfg_a(ptw_io_requestor_1_pmp_2_cfg_a),
+ .io_requestor_1_pmp_2_cfg_x(ptw_io_requestor_1_pmp_2_cfg_x),
+ .io_requestor_1_pmp_2_addr(ptw_io_requestor_1_pmp_2_addr),
+ .io_requestor_1_pmp_2_mask(ptw_io_requestor_1_pmp_2_mask),
+ .io_requestor_1_pmp_3_cfg_l(ptw_io_requestor_1_pmp_3_cfg_l),
+ .io_requestor_1_pmp_3_cfg_a(ptw_io_requestor_1_pmp_3_cfg_a),
+ .io_requestor_1_pmp_3_cfg_x(ptw_io_requestor_1_pmp_3_cfg_x),
+ .io_requestor_1_pmp_3_addr(ptw_io_requestor_1_pmp_3_addr),
+ .io_requestor_1_pmp_3_mask(ptw_io_requestor_1_pmp_3_mask),
+ .io_requestor_1_pmp_4_cfg_l(ptw_io_requestor_1_pmp_4_cfg_l),
+ .io_requestor_1_pmp_4_cfg_a(ptw_io_requestor_1_pmp_4_cfg_a),
+ .io_requestor_1_pmp_4_cfg_x(ptw_io_requestor_1_pmp_4_cfg_x),
+ .io_requestor_1_pmp_4_addr(ptw_io_requestor_1_pmp_4_addr),
+ .io_requestor_1_pmp_4_mask(ptw_io_requestor_1_pmp_4_mask),
+ .io_requestor_1_pmp_5_cfg_l(ptw_io_requestor_1_pmp_5_cfg_l),
+ .io_requestor_1_pmp_5_cfg_a(ptw_io_requestor_1_pmp_5_cfg_a),
+ .io_requestor_1_pmp_5_cfg_x(ptw_io_requestor_1_pmp_5_cfg_x),
+ .io_requestor_1_pmp_5_addr(ptw_io_requestor_1_pmp_5_addr),
+ .io_requestor_1_pmp_5_mask(ptw_io_requestor_1_pmp_5_mask),
+ .io_requestor_1_pmp_6_cfg_l(ptw_io_requestor_1_pmp_6_cfg_l),
+ .io_requestor_1_pmp_6_cfg_a(ptw_io_requestor_1_pmp_6_cfg_a),
+ .io_requestor_1_pmp_6_cfg_x(ptw_io_requestor_1_pmp_6_cfg_x),
+ .io_requestor_1_pmp_6_addr(ptw_io_requestor_1_pmp_6_addr),
+ .io_requestor_1_pmp_6_mask(ptw_io_requestor_1_pmp_6_mask),
+ .io_requestor_1_pmp_7_cfg_l(ptw_io_requestor_1_pmp_7_cfg_l),
+ .io_requestor_1_pmp_7_cfg_a(ptw_io_requestor_1_pmp_7_cfg_a),
+ .io_requestor_1_pmp_7_cfg_x(ptw_io_requestor_1_pmp_7_cfg_x),
+ .io_requestor_1_pmp_7_addr(ptw_io_requestor_1_pmp_7_addr),
+ .io_requestor_1_pmp_7_mask(ptw_io_requestor_1_pmp_7_mask),
+ .io_requestor_1_customCSRs_csrs_0_value(ptw_io_requestor_1_customCSRs_csrs_0_value),
+ .io_dpath_status_debug(ptw_io_dpath_status_debug),
+ .io_dpath_pmp_0_cfg_l(ptw_io_dpath_pmp_0_cfg_l),
+ .io_dpath_pmp_0_cfg_a(ptw_io_dpath_pmp_0_cfg_a),
+ .io_dpath_pmp_0_cfg_x(ptw_io_dpath_pmp_0_cfg_x),
+ .io_dpath_pmp_0_cfg_w(ptw_io_dpath_pmp_0_cfg_w),
+ .io_dpath_pmp_0_cfg_r(ptw_io_dpath_pmp_0_cfg_r),
+ .io_dpath_pmp_0_addr(ptw_io_dpath_pmp_0_addr),
+ .io_dpath_pmp_0_mask(ptw_io_dpath_pmp_0_mask),
+ .io_dpath_pmp_1_cfg_l(ptw_io_dpath_pmp_1_cfg_l),
+ .io_dpath_pmp_1_cfg_a(ptw_io_dpath_pmp_1_cfg_a),
+ .io_dpath_pmp_1_cfg_x(ptw_io_dpath_pmp_1_cfg_x),
+ .io_dpath_pmp_1_cfg_w(ptw_io_dpath_pmp_1_cfg_w),
+ .io_dpath_pmp_1_cfg_r(ptw_io_dpath_pmp_1_cfg_r),
+ .io_dpath_pmp_1_addr(ptw_io_dpath_pmp_1_addr),
+ .io_dpath_pmp_1_mask(ptw_io_dpath_pmp_1_mask),
+ .io_dpath_pmp_2_cfg_l(ptw_io_dpath_pmp_2_cfg_l),
+ .io_dpath_pmp_2_cfg_a(ptw_io_dpath_pmp_2_cfg_a),
+ .io_dpath_pmp_2_cfg_x(ptw_io_dpath_pmp_2_cfg_x),
+ .io_dpath_pmp_2_cfg_w(ptw_io_dpath_pmp_2_cfg_w),
+ .io_dpath_pmp_2_cfg_r(ptw_io_dpath_pmp_2_cfg_r),
+ .io_dpath_pmp_2_addr(ptw_io_dpath_pmp_2_addr),
+ .io_dpath_pmp_2_mask(ptw_io_dpath_pmp_2_mask),
+ .io_dpath_pmp_3_cfg_l(ptw_io_dpath_pmp_3_cfg_l),
+ .io_dpath_pmp_3_cfg_a(ptw_io_dpath_pmp_3_cfg_a),
+ .io_dpath_pmp_3_cfg_x(ptw_io_dpath_pmp_3_cfg_x),
+ .io_dpath_pmp_3_cfg_w(ptw_io_dpath_pmp_3_cfg_w),
+ .io_dpath_pmp_3_cfg_r(ptw_io_dpath_pmp_3_cfg_r),
+ .io_dpath_pmp_3_addr(ptw_io_dpath_pmp_3_addr),
+ .io_dpath_pmp_3_mask(ptw_io_dpath_pmp_3_mask),
+ .io_dpath_pmp_4_cfg_l(ptw_io_dpath_pmp_4_cfg_l),
+ .io_dpath_pmp_4_cfg_a(ptw_io_dpath_pmp_4_cfg_a),
+ .io_dpath_pmp_4_cfg_x(ptw_io_dpath_pmp_4_cfg_x),
+ .io_dpath_pmp_4_cfg_w(ptw_io_dpath_pmp_4_cfg_w),
+ .io_dpath_pmp_4_cfg_r(ptw_io_dpath_pmp_4_cfg_r),
+ .io_dpath_pmp_4_addr(ptw_io_dpath_pmp_4_addr),
+ .io_dpath_pmp_4_mask(ptw_io_dpath_pmp_4_mask),
+ .io_dpath_pmp_5_cfg_l(ptw_io_dpath_pmp_5_cfg_l),
+ .io_dpath_pmp_5_cfg_a(ptw_io_dpath_pmp_5_cfg_a),
+ .io_dpath_pmp_5_cfg_x(ptw_io_dpath_pmp_5_cfg_x),
+ .io_dpath_pmp_5_cfg_w(ptw_io_dpath_pmp_5_cfg_w),
+ .io_dpath_pmp_5_cfg_r(ptw_io_dpath_pmp_5_cfg_r),
+ .io_dpath_pmp_5_addr(ptw_io_dpath_pmp_5_addr),
+ .io_dpath_pmp_5_mask(ptw_io_dpath_pmp_5_mask),
+ .io_dpath_pmp_6_cfg_l(ptw_io_dpath_pmp_6_cfg_l),
+ .io_dpath_pmp_6_cfg_a(ptw_io_dpath_pmp_6_cfg_a),
+ .io_dpath_pmp_6_cfg_x(ptw_io_dpath_pmp_6_cfg_x),
+ .io_dpath_pmp_6_cfg_w(ptw_io_dpath_pmp_6_cfg_w),
+ .io_dpath_pmp_6_cfg_r(ptw_io_dpath_pmp_6_cfg_r),
+ .io_dpath_pmp_6_addr(ptw_io_dpath_pmp_6_addr),
+ .io_dpath_pmp_6_mask(ptw_io_dpath_pmp_6_mask),
+ .io_dpath_pmp_7_cfg_l(ptw_io_dpath_pmp_7_cfg_l),
+ .io_dpath_pmp_7_cfg_a(ptw_io_dpath_pmp_7_cfg_a),
+ .io_dpath_pmp_7_cfg_x(ptw_io_dpath_pmp_7_cfg_x),
+ .io_dpath_pmp_7_cfg_w(ptw_io_dpath_pmp_7_cfg_w),
+ .io_dpath_pmp_7_cfg_r(ptw_io_dpath_pmp_7_cfg_r),
+ .io_dpath_pmp_7_addr(ptw_io_dpath_pmp_7_addr),
+ .io_dpath_pmp_7_mask(ptw_io_dpath_pmp_7_mask),
+ .io_dpath_perf_l2hit(ptw_io_dpath_perf_l2hit),
+ .io_dpath_perf_pte_miss(ptw_io_dpath_perf_pte_miss),
+ .io_dpath_perf_pte_hit(ptw_io_dpath_perf_pte_hit),
+ .io_dpath_customCSRs_csrs_0_value(ptw_io_dpath_customCSRs_csrs_0_value)
+ );
+ Rocket core ( // @[RocketTile.scala 140:20]
+ .clock(core_clock),
+ .reset(core_reset),
+ .io_hartid(core_io_hartid),
+ .io_interrupts_debug(core_io_interrupts_debug),
+ .io_interrupts_mtip(core_io_interrupts_mtip),
+ .io_interrupts_msip(core_io_interrupts_msip),
+ .io_interrupts_meip(core_io_interrupts_meip),
+ .io_imem_might_request(core_io_imem_might_request),
+ .io_imem_req_valid(core_io_imem_req_valid),
+ .io_imem_req_bits_pc(core_io_imem_req_bits_pc),
+ .io_imem_req_bits_speculative(core_io_imem_req_bits_speculative),
+ .io_imem_resp_ready(core_io_imem_resp_ready),
+ .io_imem_resp_valid(core_io_imem_resp_valid),
+ .io_imem_resp_bits_pc(core_io_imem_resp_bits_pc),
+ .io_imem_resp_bits_data(core_io_imem_resp_bits_data),
+ .io_imem_resp_bits_xcpt_ae_inst(core_io_imem_resp_bits_xcpt_ae_inst),
+ .io_imem_resp_bits_replay(core_io_imem_resp_bits_replay),
+ .io_imem_btb_update_valid(core_io_imem_btb_update_valid),
+ .io_imem_bht_update_valid(core_io_imem_bht_update_valid),
+ .io_imem_flush_icache(core_io_imem_flush_icache),
+ .io_dmem_req_ready(core_io_dmem_req_ready),
+ .io_dmem_req_valid(core_io_dmem_req_valid),
+ .io_dmem_req_bits_addr(core_io_dmem_req_bits_addr),
+ .io_dmem_req_bits_tag(core_io_dmem_req_bits_tag),
+ .io_dmem_req_bits_cmd(core_io_dmem_req_bits_cmd),
+ .io_dmem_req_bits_size(core_io_dmem_req_bits_size),
+ .io_dmem_req_bits_signed(core_io_dmem_req_bits_signed),
+ .io_dmem_req_bits_dv(core_io_dmem_req_bits_dv),
+ .io_dmem_s1_kill(core_io_dmem_s1_kill),
+ .io_dmem_s1_data_data(core_io_dmem_s1_data_data),
+ .io_dmem_s2_nack(core_io_dmem_s2_nack),
+ .io_dmem_resp_valid(core_io_dmem_resp_valid),
+ .io_dmem_resp_bits_tag(core_io_dmem_resp_bits_tag),
+ .io_dmem_resp_bits_data(core_io_dmem_resp_bits_data),
+ .io_dmem_resp_bits_replay(core_io_dmem_resp_bits_replay),
+ .io_dmem_resp_bits_has_data(core_io_dmem_resp_bits_has_data),
+ .io_dmem_resp_bits_data_word_bypass(core_io_dmem_resp_bits_data_word_bypass),
+ .io_dmem_replay_next(core_io_dmem_replay_next),
+ .io_dmem_s2_xcpt_ma_ld(core_io_dmem_s2_xcpt_ma_ld),
+ .io_dmem_s2_xcpt_ma_st(core_io_dmem_s2_xcpt_ma_st),
+ .io_dmem_s2_xcpt_pf_ld(core_io_dmem_s2_xcpt_pf_ld),
+ .io_dmem_s2_xcpt_pf_st(core_io_dmem_s2_xcpt_pf_st),
+ .io_dmem_s2_xcpt_ae_ld(core_io_dmem_s2_xcpt_ae_ld),
+ .io_dmem_s2_xcpt_ae_st(core_io_dmem_s2_xcpt_ae_st),
+ .io_dmem_ordered(core_io_dmem_ordered),
+ .io_dmem_perf_grant(core_io_dmem_perf_grant),
+ .io_ptw_status_debug(core_io_ptw_status_debug),
+ .io_ptw_pmp_0_cfg_l(core_io_ptw_pmp_0_cfg_l),
+ .io_ptw_pmp_0_cfg_a(core_io_ptw_pmp_0_cfg_a),
+ .io_ptw_pmp_0_cfg_x(core_io_ptw_pmp_0_cfg_x),
+ .io_ptw_pmp_0_cfg_w(core_io_ptw_pmp_0_cfg_w),
+ .io_ptw_pmp_0_cfg_r(core_io_ptw_pmp_0_cfg_r),
+ .io_ptw_pmp_0_addr(core_io_ptw_pmp_0_addr),
+ .io_ptw_pmp_0_mask(core_io_ptw_pmp_0_mask),
+ .io_ptw_pmp_1_cfg_l(core_io_ptw_pmp_1_cfg_l),
+ .io_ptw_pmp_1_cfg_a(core_io_ptw_pmp_1_cfg_a),
+ .io_ptw_pmp_1_cfg_x(core_io_ptw_pmp_1_cfg_x),
+ .io_ptw_pmp_1_cfg_w(core_io_ptw_pmp_1_cfg_w),
+ .io_ptw_pmp_1_cfg_r(core_io_ptw_pmp_1_cfg_r),
+ .io_ptw_pmp_1_addr(core_io_ptw_pmp_1_addr),
+ .io_ptw_pmp_1_mask(core_io_ptw_pmp_1_mask),
+ .io_ptw_pmp_2_cfg_l(core_io_ptw_pmp_2_cfg_l),
+ .io_ptw_pmp_2_cfg_a(core_io_ptw_pmp_2_cfg_a),
+ .io_ptw_pmp_2_cfg_x(core_io_ptw_pmp_2_cfg_x),
+ .io_ptw_pmp_2_cfg_w(core_io_ptw_pmp_2_cfg_w),
+ .io_ptw_pmp_2_cfg_r(core_io_ptw_pmp_2_cfg_r),
+ .io_ptw_pmp_2_addr(core_io_ptw_pmp_2_addr),
+ .io_ptw_pmp_2_mask(core_io_ptw_pmp_2_mask),
+ .io_ptw_pmp_3_cfg_l(core_io_ptw_pmp_3_cfg_l),
+ .io_ptw_pmp_3_cfg_a(core_io_ptw_pmp_3_cfg_a),
+ .io_ptw_pmp_3_cfg_x(core_io_ptw_pmp_3_cfg_x),
+ .io_ptw_pmp_3_cfg_w(core_io_ptw_pmp_3_cfg_w),
+ .io_ptw_pmp_3_cfg_r(core_io_ptw_pmp_3_cfg_r),
+ .io_ptw_pmp_3_addr(core_io_ptw_pmp_3_addr),
+ .io_ptw_pmp_3_mask(core_io_ptw_pmp_3_mask),
+ .io_ptw_pmp_4_cfg_l(core_io_ptw_pmp_4_cfg_l),
+ .io_ptw_pmp_4_cfg_a(core_io_ptw_pmp_4_cfg_a),
+ .io_ptw_pmp_4_cfg_x(core_io_ptw_pmp_4_cfg_x),
+ .io_ptw_pmp_4_cfg_w(core_io_ptw_pmp_4_cfg_w),
+ .io_ptw_pmp_4_cfg_r(core_io_ptw_pmp_4_cfg_r),
+ .io_ptw_pmp_4_addr(core_io_ptw_pmp_4_addr),
+ .io_ptw_pmp_4_mask(core_io_ptw_pmp_4_mask),
+ .io_ptw_pmp_5_cfg_l(core_io_ptw_pmp_5_cfg_l),
+ .io_ptw_pmp_5_cfg_a(core_io_ptw_pmp_5_cfg_a),
+ .io_ptw_pmp_5_cfg_x(core_io_ptw_pmp_5_cfg_x),
+ .io_ptw_pmp_5_cfg_w(core_io_ptw_pmp_5_cfg_w),
+ .io_ptw_pmp_5_cfg_r(core_io_ptw_pmp_5_cfg_r),
+ .io_ptw_pmp_5_addr(core_io_ptw_pmp_5_addr),
+ .io_ptw_pmp_5_mask(core_io_ptw_pmp_5_mask),
+ .io_ptw_pmp_6_cfg_l(core_io_ptw_pmp_6_cfg_l),
+ .io_ptw_pmp_6_cfg_a(core_io_ptw_pmp_6_cfg_a),
+ .io_ptw_pmp_6_cfg_x(core_io_ptw_pmp_6_cfg_x),
+ .io_ptw_pmp_6_cfg_w(core_io_ptw_pmp_6_cfg_w),
+ .io_ptw_pmp_6_cfg_r(core_io_ptw_pmp_6_cfg_r),
+ .io_ptw_pmp_6_addr(core_io_ptw_pmp_6_addr),
+ .io_ptw_pmp_6_mask(core_io_ptw_pmp_6_mask),
+ .io_ptw_pmp_7_cfg_l(core_io_ptw_pmp_7_cfg_l),
+ .io_ptw_pmp_7_cfg_a(core_io_ptw_pmp_7_cfg_a),
+ .io_ptw_pmp_7_cfg_x(core_io_ptw_pmp_7_cfg_x),
+ .io_ptw_pmp_7_cfg_w(core_io_ptw_pmp_7_cfg_w),
+ .io_ptw_pmp_7_cfg_r(core_io_ptw_pmp_7_cfg_r),
+ .io_ptw_pmp_7_addr(core_io_ptw_pmp_7_addr),
+ .io_ptw_pmp_7_mask(core_io_ptw_pmp_7_mask),
+ .io_ptw_customCSRs_csrs_0_value(core_io_ptw_customCSRs_csrs_0_value),
+ .io_wfi(core_io_wfi)
+ );
+ assign auto_slave_in_a_ready = tlSlaveXbar_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_slave_in_d_valid = tlSlaveXbar_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_slave_in_d_bits_opcode = tlSlaveXbar_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_slave_in_d_bits_size = tlSlaveXbar_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_slave_in_d_bits_source = tlSlaveXbar_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_slave_in_d_bits_data = tlSlaveXbar_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_wfi_out_0 = bundleOut_0_0_REG; // @[Nodes.scala 1207:84 Interrupts.scala 126:12]
+ assign auto_tl_other_masters_out_a_valid = tlMasterXbar_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_other_masters_out_a_bits_opcode = tlMasterXbar_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_other_masters_out_a_bits_param = tlMasterXbar_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_other_masters_out_a_bits_size = tlMasterXbar_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_other_masters_out_a_bits_source = tlMasterXbar_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_other_masters_out_a_bits_address = tlMasterXbar_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_other_masters_out_a_bits_mask = tlMasterXbar_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_other_masters_out_a_bits_data = tlMasterXbar_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_other_masters_out_d_ready = tlMasterXbar_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign tlMasterXbar_clock = clock;
+ assign tlMasterXbar_reset = reset;
+ assign tlMasterXbar_auto_in_1_a_valid = frontend_auto_icache_master_out_a_valid; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_1_a_bits_address = frontend_auto_icache_master_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_0_a_valid = dcache_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_0_a_bits_opcode = dcache_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_0_a_bits_param = dcache_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_0_a_bits_size = dcache_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_0_a_bits_address = dcache_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_0_a_bits_mask = dcache_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_0_a_bits_data = dcache_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_in_0_d_ready = dcache_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign tlMasterXbar_auto_out_a_ready = auto_tl_other_masters_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_valid = auto_tl_other_masters_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_bits_opcode = auto_tl_other_masters_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_bits_param = auto_tl_other_masters_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_bits_size = auto_tl_other_masters_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_bits_source = auto_tl_other_masters_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_bits_sink = auto_tl_other_masters_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_bits_denied = auto_tl_other_masters_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_bits_data = auto_tl_other_masters_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlMasterXbar_auto_out_d_bits_corrupt = auto_tl_other_masters_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign tlSlaveXbar_auto_in_a_valid = auto_slave_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_in_a_bits_opcode = auto_slave_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_in_a_bits_param = auto_slave_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_in_a_bits_size = auto_slave_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_in_a_bits_source = auto_slave_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_in_a_bits_address = auto_slave_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_in_a_bits_mask = auto_slave_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_in_a_bits_data = auto_slave_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_in_d_ready = auto_slave_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tlSlaveXbar_auto_out_a_ready = fragmenter_1_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign tlSlaveXbar_auto_out_d_valid = fragmenter_1_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign tlSlaveXbar_auto_out_d_bits_opcode = fragmenter_1_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign tlSlaveXbar_auto_out_d_bits_size = fragmenter_1_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign tlSlaveXbar_auto_out_d_bits_source = fragmenter_1_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign tlSlaveXbar_auto_out_d_bits_data = fragmenter_1_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign intXbar_auto_int_in_2_0 = auto_int_local_in_2_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intXbar_auto_int_in_1_0 = auto_int_local_in_1_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intXbar_auto_int_in_1_1 = auto_int_local_in_1_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intXbar_auto_int_in_0_0 = auto_int_local_in_0_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign broadcast_auto_in = auto_hartid_in; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign dcache_clock = clock;
+ assign dcache_reset = reset;
+ assign dcache_auto_out_a_ready = tlMasterXbar_auto_in_0_a_ready; // @[LazyModule.scala 296:16]
+ assign dcache_auto_out_d_valid = tlMasterXbar_auto_in_0_d_valid; // @[LazyModule.scala 296:16]
+ assign dcache_auto_out_d_bits_opcode = tlMasterXbar_auto_in_0_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign dcache_auto_out_d_bits_size = tlMasterXbar_auto_in_0_d_bits_size; // @[LazyModule.scala 296:16]
+ assign dcache_auto_out_d_bits_denied = tlMasterXbar_auto_in_0_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign dcache_auto_out_d_bits_data = tlMasterXbar_auto_in_0_d_bits_data; // @[LazyModule.scala 296:16]
+ assign dcache_io_cpu_req_valid = dcacheArb_io_mem_req_valid; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_req_bits_addr = dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_req_bits_tag = dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_req_bits_cmd = dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_req_bits_size = dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_req_bits_signed = dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_req_bits_dprv = dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_req_bits_no_xcpt = dcacheArb_io_mem_req_bits_no_xcpt; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_s1_kill = dcacheArb_io_mem_s1_kill; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_s1_data_data = dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala 281:30]
+ assign dcache_io_cpu_s1_data_mask = dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala 281:30]
+ assign dcache_io_ptw_status_debug = ptw_io_requestor_0_status_debug; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_0_cfg_l = ptw_io_requestor_0_pmp_0_cfg_l; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_0_cfg_a = ptw_io_requestor_0_pmp_0_cfg_a; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_0_cfg_w = ptw_io_requestor_0_pmp_0_cfg_w; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_0_cfg_r = ptw_io_requestor_0_pmp_0_cfg_r; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_0_addr = ptw_io_requestor_0_pmp_0_addr; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_0_mask = ptw_io_requestor_0_pmp_0_mask; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_1_cfg_l = ptw_io_requestor_0_pmp_1_cfg_l; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_1_cfg_a = ptw_io_requestor_0_pmp_1_cfg_a; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_1_cfg_w = ptw_io_requestor_0_pmp_1_cfg_w; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_1_cfg_r = ptw_io_requestor_0_pmp_1_cfg_r; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_1_addr = ptw_io_requestor_0_pmp_1_addr; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_1_mask = ptw_io_requestor_0_pmp_1_mask; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_2_cfg_l = ptw_io_requestor_0_pmp_2_cfg_l; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_2_cfg_a = ptw_io_requestor_0_pmp_2_cfg_a; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_2_cfg_w = ptw_io_requestor_0_pmp_2_cfg_w; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_2_cfg_r = ptw_io_requestor_0_pmp_2_cfg_r; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_2_addr = ptw_io_requestor_0_pmp_2_addr; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_2_mask = ptw_io_requestor_0_pmp_2_mask; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_3_cfg_l = ptw_io_requestor_0_pmp_3_cfg_l; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_3_cfg_a = ptw_io_requestor_0_pmp_3_cfg_a; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_3_cfg_w = ptw_io_requestor_0_pmp_3_cfg_w; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_3_cfg_r = ptw_io_requestor_0_pmp_3_cfg_r; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_3_addr = ptw_io_requestor_0_pmp_3_addr; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_3_mask = ptw_io_requestor_0_pmp_3_mask; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_4_cfg_l = ptw_io_requestor_0_pmp_4_cfg_l; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_4_cfg_a = ptw_io_requestor_0_pmp_4_cfg_a; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_4_cfg_w = ptw_io_requestor_0_pmp_4_cfg_w; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_4_cfg_r = ptw_io_requestor_0_pmp_4_cfg_r; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_4_addr = ptw_io_requestor_0_pmp_4_addr; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_4_mask = ptw_io_requestor_0_pmp_4_mask; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_5_cfg_l = ptw_io_requestor_0_pmp_5_cfg_l; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_5_cfg_a = ptw_io_requestor_0_pmp_5_cfg_a; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_5_cfg_w = ptw_io_requestor_0_pmp_5_cfg_w; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_5_cfg_r = ptw_io_requestor_0_pmp_5_cfg_r; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_5_addr = ptw_io_requestor_0_pmp_5_addr; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_5_mask = ptw_io_requestor_0_pmp_5_mask; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_6_cfg_l = ptw_io_requestor_0_pmp_6_cfg_l; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_6_cfg_a = ptw_io_requestor_0_pmp_6_cfg_a; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_6_cfg_w = ptw_io_requestor_0_pmp_6_cfg_w; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_6_cfg_r = ptw_io_requestor_0_pmp_6_cfg_r; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_6_addr = ptw_io_requestor_0_pmp_6_addr; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_6_mask = ptw_io_requestor_0_pmp_6_mask; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_7_cfg_l = ptw_io_requestor_0_pmp_7_cfg_l; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_7_cfg_a = ptw_io_requestor_0_pmp_7_cfg_a; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_7_cfg_w = ptw_io_requestor_0_pmp_7_cfg_w; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_7_cfg_r = ptw_io_requestor_0_pmp_7_cfg_r; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_7_addr = ptw_io_requestor_0_pmp_7_addr; // @[RocketTile.scala 198:20]
+ assign dcache_io_ptw_pmp_7_mask = ptw_io_requestor_0_pmp_7_mask; // @[RocketTile.scala 198:20]
+ assign frontend_clock = clock;
+ assign frontend_reset = reset;
+ assign frontend_auto_icache_master_out_a_ready = tlMasterXbar_auto_in_1_a_ready; // @[LazyModule.scala 296:16]
+ assign frontend_auto_icache_master_out_d_valid = tlMasterXbar_auto_in_1_d_valid; // @[LazyModule.scala 296:16]
+ assign frontend_auto_icache_master_out_d_bits_opcode = tlMasterXbar_auto_in_1_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign frontend_auto_icache_master_out_d_bits_size = tlMasterXbar_auto_in_1_d_bits_size; // @[LazyModule.scala 296:16]
+ assign frontend_auto_icache_master_out_d_bits_data = tlMasterXbar_auto_in_1_d_bits_data; // @[LazyModule.scala 296:16]
+ assign frontend_auto_icache_master_out_d_bits_corrupt = tlMasterXbar_auto_in_1_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign frontend_io_cpu_might_request = core_io_imem_might_request; // @[RocketTile.scala 173:32]
+ assign frontend_io_cpu_req_valid = core_io_imem_req_valid; // @[RocketTile.scala 173:32]
+ assign frontend_io_cpu_req_bits_pc = core_io_imem_req_bits_pc; // @[RocketTile.scala 173:32]
+ assign frontend_io_cpu_req_bits_speculative = core_io_imem_req_bits_speculative; // @[RocketTile.scala 173:32]
+ assign frontend_io_cpu_resp_ready = core_io_imem_resp_ready; // @[RocketTile.scala 173:32]
+ assign frontend_io_cpu_btb_update_valid = core_io_imem_btb_update_valid; // @[RocketTile.scala 173:32]
+ assign frontend_io_cpu_bht_update_valid = core_io_imem_bht_update_valid; // @[RocketTile.scala 173:32]
+ assign frontend_io_cpu_flush_icache = core_io_imem_flush_icache; // @[RocketTile.scala 173:32]
+ assign frontend_io_ptw_status_debug = ptw_io_requestor_1_status_debug; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_0_cfg_l = ptw_io_requestor_1_pmp_0_cfg_l; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_0_cfg_a = ptw_io_requestor_1_pmp_0_cfg_a; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_0_cfg_x = ptw_io_requestor_1_pmp_0_cfg_x; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_0_addr = ptw_io_requestor_1_pmp_0_addr; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_0_mask = ptw_io_requestor_1_pmp_0_mask; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_1_cfg_l = ptw_io_requestor_1_pmp_1_cfg_l; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_1_cfg_a = ptw_io_requestor_1_pmp_1_cfg_a; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_1_cfg_x = ptw_io_requestor_1_pmp_1_cfg_x; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_1_addr = ptw_io_requestor_1_pmp_1_addr; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_1_mask = ptw_io_requestor_1_pmp_1_mask; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_2_cfg_l = ptw_io_requestor_1_pmp_2_cfg_l; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_2_cfg_a = ptw_io_requestor_1_pmp_2_cfg_a; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_2_cfg_x = ptw_io_requestor_1_pmp_2_cfg_x; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_2_addr = ptw_io_requestor_1_pmp_2_addr; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_2_mask = ptw_io_requestor_1_pmp_2_mask; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_3_cfg_l = ptw_io_requestor_1_pmp_3_cfg_l; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_3_cfg_a = ptw_io_requestor_1_pmp_3_cfg_a; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_3_cfg_x = ptw_io_requestor_1_pmp_3_cfg_x; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_3_addr = ptw_io_requestor_1_pmp_3_addr; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_3_mask = ptw_io_requestor_1_pmp_3_mask; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_4_cfg_l = ptw_io_requestor_1_pmp_4_cfg_l; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_4_cfg_a = ptw_io_requestor_1_pmp_4_cfg_a; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_4_cfg_x = ptw_io_requestor_1_pmp_4_cfg_x; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_4_addr = ptw_io_requestor_1_pmp_4_addr; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_4_mask = ptw_io_requestor_1_pmp_4_mask; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_5_cfg_l = ptw_io_requestor_1_pmp_5_cfg_l; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_5_cfg_a = ptw_io_requestor_1_pmp_5_cfg_a; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_5_cfg_x = ptw_io_requestor_1_pmp_5_cfg_x; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_5_addr = ptw_io_requestor_1_pmp_5_addr; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_5_mask = ptw_io_requestor_1_pmp_5_mask; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_6_cfg_l = ptw_io_requestor_1_pmp_6_cfg_l; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_6_cfg_a = ptw_io_requestor_1_pmp_6_cfg_a; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_6_cfg_x = ptw_io_requestor_1_pmp_6_cfg_x; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_6_addr = ptw_io_requestor_1_pmp_6_addr; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_6_mask = ptw_io_requestor_1_pmp_6_mask; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_7_cfg_l = ptw_io_requestor_1_pmp_7_cfg_l; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_7_cfg_a = ptw_io_requestor_1_pmp_7_cfg_a; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_7_cfg_x = ptw_io_requestor_1_pmp_7_cfg_x; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_7_addr = ptw_io_requestor_1_pmp_7_addr; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_pmp_7_mask = ptw_io_requestor_1_pmp_7_mask; // @[RocketTile.scala 198:20]
+ assign frontend_io_ptw_customCSRs_csrs_0_value = ptw_io_requestor_1_customCSRs_csrs_0_value; // @[RocketTile.scala 198:20]
+ assign dtim_adapter_clock = clock;
+ assign dtim_adapter_reset = reset;
+ assign dtim_adapter_auto_in_a_valid = fragmenter_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_auto_in_a_bits_opcode = fragmenter_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_auto_in_a_bits_param = fragmenter_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_auto_in_a_bits_size = fragmenter_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_auto_in_a_bits_source = fragmenter_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_auto_in_a_bits_address = fragmenter_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_auto_in_a_bits_mask = fragmenter_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_auto_in_a_bits_data = fragmenter_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_auto_in_d_ready = fragmenter_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign dtim_adapter_io_dmem_req_ready = dcacheArb_io_requestor_1_req_ready; // @[RocketTile.scala 197:26]
+ assign dtim_adapter_io_dmem_s2_nack = dcacheArb_io_requestor_1_s2_nack; // @[RocketTile.scala 197:26]
+ assign dtim_adapter_io_dmem_resp_valid = dcacheArb_io_requestor_1_resp_valid; // @[RocketTile.scala 197:26]
+ assign dtim_adapter_io_dmem_resp_bits_data_raw = dcacheArb_io_requestor_1_resp_bits_data_raw; // @[RocketTile.scala 197:26]
+ assign fragmenter_1_clock = clock;
+ assign fragmenter_1_reset = reset;
+ assign fragmenter_1_auto_in_a_valid = tlSlaveXbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_in_a_bits_opcode = tlSlaveXbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_in_a_bits_param = tlSlaveXbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_in_a_bits_size = tlSlaveXbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_in_a_bits_source = tlSlaveXbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_in_a_bits_address = tlSlaveXbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_in_a_bits_mask = tlSlaveXbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_in_a_bits_data = tlSlaveXbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_in_d_ready = tlSlaveXbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
+ assign fragmenter_1_auto_out_a_ready = dtim_adapter_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign fragmenter_1_auto_out_d_valid = dtim_adapter_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign fragmenter_1_auto_out_d_bits_opcode = dtim_adapter_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign fragmenter_1_auto_out_d_bits_size = dtim_adapter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign fragmenter_1_auto_out_d_bits_source = dtim_adapter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign fragmenter_1_auto_out_d_bits_data = dtim_adapter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign dcacheArb_clock = clock;
+ assign dcacheArb_io_requestor_0_req_valid = core_io_dmem_req_valid; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_0_req_bits_addr = core_io_dmem_req_bits_addr; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_0_req_bits_tag = core_io_dmem_req_bits_tag; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_0_req_bits_cmd = core_io_dmem_req_bits_cmd; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_0_req_bits_size = core_io_dmem_req_bits_size; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_0_req_bits_signed = core_io_dmem_req_bits_signed; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_0_s1_kill = core_io_dmem_s1_kill; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_0_s1_data_data = core_io_dmem_s1_data_data; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_1_req_valid = dtim_adapter_io_dmem_req_valid; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_1_req_bits_addr = dtim_adapter_io_dmem_req_bits_addr; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_1_req_bits_cmd = dtim_adapter_io_dmem_req_bits_cmd; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_1_req_bits_size = dtim_adapter_io_dmem_req_bits_size; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_1_s1_kill = dtim_adapter_io_dmem_s1_kill; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_1_s1_data_data = dtim_adapter_io_dmem_s1_data_data; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_requestor_1_s1_data_mask = dtim_adapter_io_dmem_s1_data_mask; // @[RocketTile.scala 197:26]
+ assign dcacheArb_io_mem_req_ready = dcache_io_cpu_req_ready; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_s2_nack = dcache_io_cpu_s2_nack; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_resp_valid = dcache_io_cpu_resp_valid; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_resp_bits_tag = dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_resp_bits_data = dcache_io_cpu_resp_bits_data; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_resp_bits_replay = dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_resp_bits_has_data = dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_resp_bits_data_word_bypass = dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_resp_bits_data_raw = dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_replay_next = dcache_io_cpu_replay_next; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_s2_xcpt_ma_ld = dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_s2_xcpt_ma_st = dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_s2_xcpt_pf_ld = dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_s2_xcpt_pf_st = dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_s2_xcpt_ae_ld = dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_s2_xcpt_ae_st = dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_ordered = dcache_io_cpu_ordered; // @[HellaCache.scala 281:30]
+ assign dcacheArb_io_mem_perf_grant = dcache_io_cpu_perf_grant; // @[HellaCache.scala 281:30]
+ assign ptw_clock = clock;
+ assign ptw_reset = reset;
+ assign ptw_io_dpath_status_debug = core_io_ptw_status_debug; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_0_cfg_l = core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_0_cfg_a = core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_0_cfg_x = core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_0_cfg_w = core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_0_cfg_r = core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_0_addr = core_io_ptw_pmp_0_addr; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_0_mask = core_io_ptw_pmp_0_mask; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_1_cfg_l = core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_1_cfg_a = core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_1_cfg_x = core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_1_cfg_w = core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_1_cfg_r = core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_1_addr = core_io_ptw_pmp_1_addr; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_1_mask = core_io_ptw_pmp_1_mask; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_2_cfg_l = core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_2_cfg_a = core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_2_cfg_x = core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_2_cfg_w = core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_2_cfg_r = core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_2_addr = core_io_ptw_pmp_2_addr; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_2_mask = core_io_ptw_pmp_2_mask; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_3_cfg_l = core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_3_cfg_a = core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_3_cfg_x = core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_3_cfg_w = core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_3_cfg_r = core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_3_addr = core_io_ptw_pmp_3_addr; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_3_mask = core_io_ptw_pmp_3_mask; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_4_cfg_l = core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_4_cfg_a = core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_4_cfg_x = core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_4_cfg_w = core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_4_cfg_r = core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_4_addr = core_io_ptw_pmp_4_addr; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_4_mask = core_io_ptw_pmp_4_mask; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_5_cfg_l = core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_5_cfg_a = core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_5_cfg_x = core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_5_cfg_w = core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_5_cfg_r = core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_5_addr = core_io_ptw_pmp_5_addr; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_5_mask = core_io_ptw_pmp_5_mask; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_6_cfg_l = core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_6_cfg_a = core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_6_cfg_x = core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_6_cfg_w = core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_6_cfg_r = core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_6_addr = core_io_ptw_pmp_6_addr; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_6_mask = core_io_ptw_pmp_6_mask; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_7_cfg_l = core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_7_cfg_a = core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_7_cfg_x = core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_7_cfg_w = core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_7_cfg_r = core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_7_addr = core_io_ptw_pmp_7_addr; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_pmp_7_mask = core_io_ptw_pmp_7_mask; // @[RocketTile.scala 176:15]
+ assign ptw_io_dpath_customCSRs_csrs_0_value = core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala 176:15]
+ assign core_clock = clock;
+ assign core_reset = reset;
+ assign core_io_hartid = broadcast_auto_out_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign core_io_interrupts_debug = intXbar_auto_int_out_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign core_io_interrupts_mtip = intXbar_auto_int_out_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign core_io_interrupts_msip = intXbar_auto_int_out_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign core_io_interrupts_meip = intXbar_auto_int_out_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign core_io_imem_resp_valid = frontend_io_cpu_resp_valid; // @[RocketTile.scala 173:32]
+ assign core_io_imem_resp_bits_pc = frontend_io_cpu_resp_bits_pc; // @[RocketTile.scala 173:32]
+ assign core_io_imem_resp_bits_data = frontend_io_cpu_resp_bits_data; // @[RocketTile.scala 173:32]
+ assign core_io_imem_resp_bits_xcpt_ae_inst = frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[RocketTile.scala 173:32]
+ assign core_io_imem_resp_bits_replay = frontend_io_cpu_resp_bits_replay; // @[RocketTile.scala 173:32]
+ assign core_io_dmem_req_ready = dcacheArb_io_requestor_0_req_ready; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_s2_nack = dcacheArb_io_requestor_0_s2_nack; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_resp_valid = dcacheArb_io_requestor_0_resp_valid; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_resp_bits_tag = dcacheArb_io_requestor_0_resp_bits_tag; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_resp_bits_data = dcacheArb_io_requestor_0_resp_bits_data; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_resp_bits_replay = dcacheArb_io_requestor_0_resp_bits_replay; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_resp_bits_has_data = dcacheArb_io_requestor_0_resp_bits_has_data; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_resp_bits_data_word_bypass = dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_replay_next = dcacheArb_io_requestor_0_replay_next; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_s2_xcpt_ma_ld = dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_s2_xcpt_ma_st = dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_s2_xcpt_pf_ld = dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_s2_xcpt_pf_st = dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_s2_xcpt_ae_ld = dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_s2_xcpt_ae_st = dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_ordered = dcacheArb_io_requestor_0_ordered; // @[RocketTile.scala 197:26]
+ assign core_io_dmem_perf_grant = dcacheArb_io_requestor_0_perf_grant; // @[RocketTile.scala 197:26]
+ always @(posedge clock) begin
+ if (reset) begin // @[Interrupts.scala 126:36]
+ bundleOut_0_0_REG <= 1'h0; // @[Interrupts.scala 126:36]
+ end else begin
+ bundleOut_0_0_REG <= core_io_wfi; // @[Interrupts.scala 126:36]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ bundleOut_0_0_REG = _RAND_0[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TileResetDomain(
+ output auto_tile_slave_in_a_ready,
+ input auto_tile_slave_in_a_valid,
+ input [2:0] auto_tile_slave_in_a_bits_opcode,
+ input [2:0] auto_tile_slave_in_a_bits_param,
+ input [2:0] auto_tile_slave_in_a_bits_size,
+ input [2:0] auto_tile_slave_in_a_bits_source,
+ input [31:0] auto_tile_slave_in_a_bits_address,
+ input [7:0] auto_tile_slave_in_a_bits_mask,
+ input [63:0] auto_tile_slave_in_a_bits_data,
+ input auto_tile_slave_in_d_ready,
+ output auto_tile_slave_in_d_valid,
+ output [2:0] auto_tile_slave_in_d_bits_opcode,
+ output [2:0] auto_tile_slave_in_d_bits_size,
+ output [2:0] auto_tile_slave_in_d_bits_source,
+ output [63:0] auto_tile_slave_in_d_bits_data,
+ output auto_tile_wfi_out_0,
+ input auto_tile_int_local_in_2_0,
+ input auto_tile_int_local_in_1_0,
+ input auto_tile_int_local_in_1_1,
+ input auto_tile_int_local_in_0_0,
+ input auto_tile_hartid_in,
+ input auto_tile_tl_other_masters_out_a_ready,
+ output auto_tile_tl_other_masters_out_a_valid,
+ output [2:0] auto_tile_tl_other_masters_out_a_bits_opcode,
+ output [2:0] auto_tile_tl_other_masters_out_a_bits_param,
+ output [3:0] auto_tile_tl_other_masters_out_a_bits_size,
+ output auto_tile_tl_other_masters_out_a_bits_source,
+ output [31:0] auto_tile_tl_other_masters_out_a_bits_address,
+ output [7:0] auto_tile_tl_other_masters_out_a_bits_mask,
+ output [63:0] auto_tile_tl_other_masters_out_a_bits_data,
+ output auto_tile_tl_other_masters_out_d_ready,
+ input auto_tile_tl_other_masters_out_d_valid,
+ input [2:0] auto_tile_tl_other_masters_out_d_bits_opcode,
+ input [1:0] auto_tile_tl_other_masters_out_d_bits_param,
+ input [3:0] auto_tile_tl_other_masters_out_d_bits_size,
+ input auto_tile_tl_other_masters_out_d_bits_source,
+ input auto_tile_tl_other_masters_out_d_bits_sink,
+ input auto_tile_tl_other_masters_out_d_bits_denied,
+ input [63:0] auto_tile_tl_other_masters_out_d_bits_data,
+ input auto_tile_tl_other_masters_out_d_bits_corrupt,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire tile_clock; // @[HasTiles.scala 253:53]
+ wire tile_reset; // @[HasTiles.scala 253:53]
+ wire tile_auto_slave_in_a_ready; // @[HasTiles.scala 253:53]
+ wire tile_auto_slave_in_a_valid; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_slave_in_a_bits_opcode; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_slave_in_a_bits_param; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_slave_in_a_bits_size; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_slave_in_a_bits_source; // @[HasTiles.scala 253:53]
+ wire [31:0] tile_auto_slave_in_a_bits_address; // @[HasTiles.scala 253:53]
+ wire [7:0] tile_auto_slave_in_a_bits_mask; // @[HasTiles.scala 253:53]
+ wire [63:0] tile_auto_slave_in_a_bits_data; // @[HasTiles.scala 253:53]
+ wire tile_auto_slave_in_d_ready; // @[HasTiles.scala 253:53]
+ wire tile_auto_slave_in_d_valid; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_slave_in_d_bits_opcode; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_slave_in_d_bits_size; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_slave_in_d_bits_source; // @[HasTiles.scala 253:53]
+ wire [63:0] tile_auto_slave_in_d_bits_data; // @[HasTiles.scala 253:53]
+ wire tile_auto_wfi_out_0; // @[HasTiles.scala 253:53]
+ wire tile_auto_int_local_in_2_0; // @[HasTiles.scala 253:53]
+ wire tile_auto_int_local_in_1_0; // @[HasTiles.scala 253:53]
+ wire tile_auto_int_local_in_1_1; // @[HasTiles.scala 253:53]
+ wire tile_auto_int_local_in_0_0; // @[HasTiles.scala 253:53]
+ wire tile_auto_hartid_in; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_a_ready; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_a_valid; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_tl_other_masters_out_a_bits_opcode; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_tl_other_masters_out_a_bits_param; // @[HasTiles.scala 253:53]
+ wire [3:0] tile_auto_tl_other_masters_out_a_bits_size; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_a_bits_source; // @[HasTiles.scala 253:53]
+ wire [31:0] tile_auto_tl_other_masters_out_a_bits_address; // @[HasTiles.scala 253:53]
+ wire [7:0] tile_auto_tl_other_masters_out_a_bits_mask; // @[HasTiles.scala 253:53]
+ wire [63:0] tile_auto_tl_other_masters_out_a_bits_data; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_d_ready; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_d_valid; // @[HasTiles.scala 253:53]
+ wire [2:0] tile_auto_tl_other_masters_out_d_bits_opcode; // @[HasTiles.scala 253:53]
+ wire [1:0] tile_auto_tl_other_masters_out_d_bits_param; // @[HasTiles.scala 253:53]
+ wire [3:0] tile_auto_tl_other_masters_out_d_bits_size; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_d_bits_source; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_d_bits_sink; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_d_bits_denied; // @[HasTiles.scala 253:53]
+ wire [63:0] tile_auto_tl_other_masters_out_d_bits_data; // @[HasTiles.scala 253:53]
+ wire tile_auto_tl_other_masters_out_d_bits_corrupt; // @[HasTiles.scala 253:53]
+ RocketTile tile ( // @[HasTiles.scala 253:53]
+ .clock(tile_clock),
+ .reset(tile_reset),
+ .auto_slave_in_a_ready(tile_auto_slave_in_a_ready),
+ .auto_slave_in_a_valid(tile_auto_slave_in_a_valid),
+ .auto_slave_in_a_bits_opcode(tile_auto_slave_in_a_bits_opcode),
+ .auto_slave_in_a_bits_param(tile_auto_slave_in_a_bits_param),
+ .auto_slave_in_a_bits_size(tile_auto_slave_in_a_bits_size),
+ .auto_slave_in_a_bits_source(tile_auto_slave_in_a_bits_source),
+ .auto_slave_in_a_bits_address(tile_auto_slave_in_a_bits_address),
+ .auto_slave_in_a_bits_mask(tile_auto_slave_in_a_bits_mask),
+ .auto_slave_in_a_bits_data(tile_auto_slave_in_a_bits_data),
+ .auto_slave_in_d_ready(tile_auto_slave_in_d_ready),
+ .auto_slave_in_d_valid(tile_auto_slave_in_d_valid),
+ .auto_slave_in_d_bits_opcode(tile_auto_slave_in_d_bits_opcode),
+ .auto_slave_in_d_bits_size(tile_auto_slave_in_d_bits_size),
+ .auto_slave_in_d_bits_source(tile_auto_slave_in_d_bits_source),
+ .auto_slave_in_d_bits_data(tile_auto_slave_in_d_bits_data),
+ .auto_wfi_out_0(tile_auto_wfi_out_0),
+ .auto_int_local_in_2_0(tile_auto_int_local_in_2_0),
+ .auto_int_local_in_1_0(tile_auto_int_local_in_1_0),
+ .auto_int_local_in_1_1(tile_auto_int_local_in_1_1),
+ .auto_int_local_in_0_0(tile_auto_int_local_in_0_0),
+ .auto_hartid_in(tile_auto_hartid_in),
+ .auto_tl_other_masters_out_a_ready(tile_auto_tl_other_masters_out_a_ready),
+ .auto_tl_other_masters_out_a_valid(tile_auto_tl_other_masters_out_a_valid),
+ .auto_tl_other_masters_out_a_bits_opcode(tile_auto_tl_other_masters_out_a_bits_opcode),
+ .auto_tl_other_masters_out_a_bits_param(tile_auto_tl_other_masters_out_a_bits_param),
+ .auto_tl_other_masters_out_a_bits_size(tile_auto_tl_other_masters_out_a_bits_size),
+ .auto_tl_other_masters_out_a_bits_source(tile_auto_tl_other_masters_out_a_bits_source),
+ .auto_tl_other_masters_out_a_bits_address(tile_auto_tl_other_masters_out_a_bits_address),
+ .auto_tl_other_masters_out_a_bits_mask(tile_auto_tl_other_masters_out_a_bits_mask),
+ .auto_tl_other_masters_out_a_bits_data(tile_auto_tl_other_masters_out_a_bits_data),
+ .auto_tl_other_masters_out_d_ready(tile_auto_tl_other_masters_out_d_ready),
+ .auto_tl_other_masters_out_d_valid(tile_auto_tl_other_masters_out_d_valid),
+ .auto_tl_other_masters_out_d_bits_opcode(tile_auto_tl_other_masters_out_d_bits_opcode),
+ .auto_tl_other_masters_out_d_bits_param(tile_auto_tl_other_masters_out_d_bits_param),
+ .auto_tl_other_masters_out_d_bits_size(tile_auto_tl_other_masters_out_d_bits_size),
+ .auto_tl_other_masters_out_d_bits_source(tile_auto_tl_other_masters_out_d_bits_source),
+ .auto_tl_other_masters_out_d_bits_sink(tile_auto_tl_other_masters_out_d_bits_sink),
+ .auto_tl_other_masters_out_d_bits_denied(tile_auto_tl_other_masters_out_d_bits_denied),
+ .auto_tl_other_masters_out_d_bits_data(tile_auto_tl_other_masters_out_d_bits_data),
+ .auto_tl_other_masters_out_d_bits_corrupt(tile_auto_tl_other_masters_out_d_bits_corrupt)
+ );
+ assign auto_tile_slave_in_a_ready = tile_auto_slave_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_tile_slave_in_d_valid = tile_auto_slave_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_tile_slave_in_d_bits_opcode = tile_auto_slave_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_tile_slave_in_d_bits_size = tile_auto_slave_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_tile_slave_in_d_bits_source = tile_auto_slave_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_tile_slave_in_d_bits_data = tile_auto_slave_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_tile_wfi_out_0 = tile_auto_wfi_out_0; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_a_valid = tile_auto_tl_other_masters_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_a_bits_opcode = tile_auto_tl_other_masters_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_a_bits_param = tile_auto_tl_other_masters_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_a_bits_size = tile_auto_tl_other_masters_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_a_bits_source = tile_auto_tl_other_masters_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_a_bits_address = tile_auto_tl_other_masters_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_a_bits_mask = tile_auto_tl_other_masters_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_a_bits_data = tile_auto_tl_other_masters_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_tile_tl_other_masters_out_d_ready = tile_auto_tl_other_masters_out_d_ready; // @[LazyModule.scala 311:12]
+ assign tile_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tile_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign tile_auto_slave_in_a_valid = auto_tile_slave_in_a_valid; // @[LazyModule.scala 309:16]
+ assign tile_auto_slave_in_a_bits_opcode = auto_tile_slave_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign tile_auto_slave_in_a_bits_param = auto_tile_slave_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign tile_auto_slave_in_a_bits_size = auto_tile_slave_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign tile_auto_slave_in_a_bits_source = auto_tile_slave_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign tile_auto_slave_in_a_bits_address = auto_tile_slave_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign tile_auto_slave_in_a_bits_mask = auto_tile_slave_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign tile_auto_slave_in_a_bits_data = auto_tile_slave_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign tile_auto_slave_in_d_ready = auto_tile_slave_in_d_ready; // @[LazyModule.scala 309:16]
+ assign tile_auto_int_local_in_2_0 = auto_tile_int_local_in_2_0; // @[LazyModule.scala 309:16]
+ assign tile_auto_int_local_in_1_0 = auto_tile_int_local_in_1_0; // @[LazyModule.scala 309:16]
+ assign tile_auto_int_local_in_1_1 = auto_tile_int_local_in_1_1; // @[LazyModule.scala 309:16]
+ assign tile_auto_int_local_in_0_0 = auto_tile_int_local_in_0_0; // @[LazyModule.scala 309:16]
+ assign tile_auto_hartid_in = auto_tile_hartid_in; // @[LazyModule.scala 309:16]
+ assign tile_auto_tl_other_masters_out_a_ready = auto_tile_tl_other_masters_out_a_ready; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_valid = auto_tile_tl_other_masters_out_d_valid; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_bits_opcode = auto_tile_tl_other_masters_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_bits_param = auto_tile_tl_other_masters_out_d_bits_param; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_bits_size = auto_tile_tl_other_masters_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_bits_source = auto_tile_tl_other_masters_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_bits_sink = auto_tile_tl_other_masters_out_d_bits_sink; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_bits_denied = auto_tile_tl_other_masters_out_d_bits_denied; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_bits_data = auto_tile_tl_other_masters_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign tile_auto_tl_other_masters_out_d_bits_corrupt = auto_tile_tl_other_masters_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
+endmodule
+module FixedClockBroadcast_4(
+ input auto_in_clock,
+ input auto_in_reset,
+ output auto_out_clock,
+ output auto_out_reset
+);
+ assign auto_out_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLBuffer_15(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_42(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [3:0] io_in_a_bits_size,
+ input io_in_a_bits_source,
+ input [31:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [3:0] io_in_d_bits_size,
+ input io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_1 = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
+ wire source_ok = io_in_a_bits_source | _source_ok_T_1; // @[Parameters.scala 1125:46]
+ wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
+ wire [31:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [31:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 4'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire [32:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_24 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire _T_26 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
+ wire _T_31 = _T_26 & source_ok; // @[Parameters.scala 1160:30]
+ wire [32:0] _T_37 = $signed(_T_7) & -33'sh5000; // @[Parameters.scala 137:52]
+ wire _T_38 = $signed(_T_37) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_39 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_40 = {1'b0,$signed(_T_39)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_42 = $signed(_T_40) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_43 = $signed(_T_42) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_44 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_45 = {1'b0,$signed(_T_44)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_47 = $signed(_T_45) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_48 = $signed(_T_47) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_49 = io_in_a_bits_address ^ 32'h20000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_50 = {1'b0,$signed(_T_49)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_52 = $signed(_T_50) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_53 = $signed(_T_52) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_54 = io_in_a_bits_address ^ 32'h100000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_55 = {1'b0,$signed(_T_54)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_57 = $signed(_T_55) & -33'sh11000; // @[Parameters.scala 137:52]
+ wire _T_58 = $signed(_T_57) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_59 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_60 = {1'b0,$signed(_T_59)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_62 = $signed(_T_60) & -33'sh10000; // @[Parameters.scala 137:52]
+ wire _T_63 = $signed(_T_62) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_64 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_67 = $signed(_T_65) & -33'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_68 = $signed(_T_67) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_69 = io_in_a_bits_address ^ 32'h10000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_72 = $signed(_T_70) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_73 = $signed(_T_72) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_74 = io_in_a_bits_address ^ 32'h10010000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_75 = {1'b0,$signed(_T_74)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_77 = $signed(_T_75) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_78 = $signed(_T_77) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_79 = io_in_a_bits_address ^ 32'h10014000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_80 = {1'b0,$signed(_T_79)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_82 = $signed(_T_80) & -33'sh1000; // @[Parameters.scala 137:52]
+ wire _T_83 = $signed(_T_82) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_84 = io_in_a_bits_address ^ 32'h20000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_85 = {1'b0,$signed(_T_84)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_87 = $signed(_T_85) & -33'sh20000000; // @[Parameters.scala 137:52]
+ wire _T_88 = $signed(_T_87) == 33'sh0; // @[Parameters.scala 137:67]
+ wire [31:0] _T_89 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 137:31]
+ wire [32:0] _T_90 = {1'b0,$signed(_T_89)}; // @[Parameters.scala 137:49]
+ wire [32:0] _T_92 = $signed(_T_90) & -33'sh4000; // @[Parameters.scala 137:52]
+ wire _T_93 = $signed(_T_92) == 33'sh0; // @[Parameters.scala 137:67]
+ wire _T_202 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_206 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_207 = _T_206 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_215 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_397 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_410 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_431 = _T_26 & _T_43; // @[Parameters.scala 670:56]
+ wire _T_433 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
+ wire _T_500 = _T_38 | _T_48 | _T_53 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_88 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_501 = _T_433 & _T_500; // @[Parameters.scala 670:56]
+ wire _T_503 = _T_431 | _T_501; // @[Parameters.scala 672:30]
+ wire _T_513 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_517 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_525 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_594 = _T_38 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_595 = _T_433 & _T_594; // @[Parameters.scala 670:56]
+ wire _T_616 = _T_431 | _T_595; // @[Parameters.scala 672:30]
+ wire _T_618 = _T_31 & _T_616; // @[Monitor.scala 115:71]
+ wire _T_636 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_743 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_744 = io_in_a_bits_mask & _T_743; // @[Monitor.scala 127:31]
+ wire _T_745 = _T_744 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_749 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_759 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 92:42]
+ wire _T_814 = _T_38 | _T_43 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_93; // @[Parameters.scala 671:42]
+ wire _T_815 = _T_759 & _T_814; // @[Parameters.scala 670:56]
+ wire _T_837 = _T_31 & _T_815; // @[Monitor.scala 131:74]
+ wire _T_847 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_855 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_953 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_961 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_1049 = _T_31 & _T_431; // @[Monitor.scala 147:68]
+ wire _T_1059 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_1071 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_3 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
+ wire source_ok_1 = io_in_d_bits_source | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire _T_1075 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_1079 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 312:27]
+ wire _T_1083 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_1087 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_1091 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_1095 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_1106 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_1110 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_1123 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_1143 = _T_1091 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_1152 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_1169 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_1187 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [8:0] a_first_beats1_decode = is_aligned_mask[11:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [8:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1 = a_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [3:0] size; // @[Monitor.scala 386:22]
+ reg source; // @[Monitor.scala 387:22]
+ reg [31:0] address; // @[Monitor.scala 388:22]
+ wire _T_1217 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_1218 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_1222 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_1226 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_1230 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_1234 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [8:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1 = d_first_counter - 9'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 9'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [3:0] size_1; // @[Monitor.scala 537:22]
+ reg source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_1241 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_1242 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_1246 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_1250 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_1254 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_1258 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_1262 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [1:0] inflight; // @[Monitor.scala 611:27]
+ reg [7:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [15:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [8:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] a_first_counter1_1 = a_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ reg [8:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_1 = d_first_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire [2:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{8'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [3:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
+ wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_1268 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_1271 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
+ wire [2:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
+ wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
+ wire [19:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [19:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [1:0] _T_1273 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_1275 = ~_T_1273[0]; // @[Monitor.scala 658:17]
+ wire [1:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [19:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_1279 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_1281 = ~_T_1075; // @[Monitor.scala 671:74]
+ wire _T_1282 = io_in_d_valid & d_first_1 & ~_T_1075; // @[Monitor.scala 671:71]
+ wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_1075 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _GEN_3 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [30:0] _GEN_4 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [30:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [1:0] d_clr = _d_first_T & d_first_1 & _T_1281 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1281 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1281 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_1268 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [1:0] _T_1292 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_1294 = _T_1292[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_1299 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_1300 = io_in_d_bits_opcode == _GEN_32 | _T_1299; // @[Monitor.scala 685:77]
+ wire _T_1304 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_1311 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_1312 = io_in_d_bits_opcode == _GEN_48 | _T_1311; // @[Monitor.scala 689:72]
+ wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
+ wire [7:0] _GEN_78 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_1316 = _GEN_78 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_1326 = _T_1279 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1281; // @[Monitor.scala 694:116]
+ wire _T_1328 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire _T_1335 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [7:0] a_opcodes_set = _GEN_19[7:0];
+ wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [7:0] d_opcodes_clr = _GEN_23[7:0];
+ wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [15:0] a_sizes_set = _GEN_20[15:0];
+ wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [15:0] d_sizes_clr = _GEN_24[15:0];
+ wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_1344 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [1:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [15:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [8:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [8:0] d_first_counter1_2 = d_first_counter_2 - 9'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala 230:25]
+ wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
+ wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_1370 = io_in_d_valid & d_first_2 & _T_1075; // @[Monitor.scala 779:71]
+ wire [1:0] d_clr_1 = _d_first_T & d_first_2 & _T_1075 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 783:90 784:21]
+ wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1075 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
+ wire [1:0] _T_1378 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
+ wire _T_1388 = _GEN_78 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [1:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [15:0] d_sizes_clr_1 = _GEN_69[15:0];
+ wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
+ wire [15:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_1413 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 9'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 9'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 2'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 8'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 16'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 2'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 16'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 9'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_202 & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_T_202) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_207 & (io_in_a_valid & _T_24 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_24 & ~reset & ~_T_207) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_202 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_202) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_207 & (io_in_a_valid & _T_215 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_215 & ~reset & ~_T_207) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_31 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_31) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_410 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_410 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_525 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_525 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_513 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_513) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_745 & (io_in_a_valid & _T_636 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_636 & ~reset & ~_T_745) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_837 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_837) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_847 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_847) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_749 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_749 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_837 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_837) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_953 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_953) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_855 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_855 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1049 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_1049) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1059 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_1059) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (io_in_a_valid & _T_961 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_961 & ~reset & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1071 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_1071) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1091 & (io_in_d_valid & _T_1075 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1075 & _T_2 & ~_T_1091) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1106 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1106) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1110 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1110) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1095 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1095 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1079 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1079) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1106 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1106) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1110 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1110) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_1123 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1123 & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1152 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1152 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1143 & (io_in_d_valid & _T_1169 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1169 & _T_2 & ~_T_1143) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1083 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~_T_1083) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1087 & (io_in_d_valid & _T_1187 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_1187 & _T_2 & ~_T_1087) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1218 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1222 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1222) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1226 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1226) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1230 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1230) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1234 & (_T_1217 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1217 & ~reset & ~_T_1234) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1242 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1246 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1246) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1250 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1254 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1254) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1258 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1258) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1262 & (_T_1241 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1241 & _T_2 & ~_T_1262) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1275 & (_T_1271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1271 & ~reset & ~_T_1275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1294 & (_T_1282 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & _T_2 & ~_T_1294) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1300 & (_T_1282 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & same_cycle_resp & _T_2 & ~_T_1300) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1304 & (_T_1282 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & same_cycle_resp & _T_2 & ~_T_1304) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1312 & (_T_1282 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & ~same_cycle_resp & _T_2 & ~_T_1312) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1316 & (_T_1282 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1282 & ~same_cycle_resp & _T_2 & ~_T_1316) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1328 & (_T_1326 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1326 & _T_2 & ~_T_1328) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1335 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_1335) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1344 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1344) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1378[0] & (_T_1370 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1370 & _T_2 & ~_T_1378[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1388 & (_T_1370 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_1370 & _T_2 & ~_T_1388) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_1413 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_1413) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:61:80)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[8:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[1:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[7:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[15:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[8:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[8:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[1:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[15:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[8:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_16(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [3:0] auto_in_a_bits_size,
+ input auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [3:0] auto_in_d_bits_size,
+ output auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [3:0] auto_out_a_bits_size,
+ output auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [3:0] auto_out_d_bits_size,
+ input auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [31:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [3:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_42 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_6 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_7 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = 1'h0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLBuffer_17(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module Queue_21(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [31:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input [63:0] io_enq_bits_data,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [31:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output [63:0] io_deq_bits_data
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [31:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [31:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [31:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_address_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_address_io_deq_bits_MPORT_addr = value_1;
+ assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_address_MPORT_data = io_enq_bits_address;
+ assign ram_address_MPORT_addr = value;
+ assign ram_address_MPORT_mask = 1'h1;
+ assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = value_1;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = value;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
+ ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_address[initvar] = _RAND_4[31:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_5[7:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_7 = {1{`RANDOM}};
+ value = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ value_1 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ maybe_full = _RAND_9[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_18(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [31:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [31:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [31:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ Queue_21 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data)
+ );
+ Queue_1 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = 2'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module NonSyncResetSynchronizerPrimitiveShiftReg_d3(
+ input clock,
+ input io_d,
+ output io_q
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+`endif // RANDOMIZE_REG_INIT
+ reg sync_0; // @[SynchronizerReg.scala 51:66]
+ reg sync_1; // @[SynchronizerReg.scala 51:66]
+ reg sync_2; // @[SynchronizerReg.scala 51:66]
+ assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
+ always @(posedge clock) begin
+ sync_0 <= sync_1; // @[SynchronizerReg.scala 57:10]
+ sync_1 <= sync_2; // @[SynchronizerReg.scala 57:10]
+ sync_2 <= io_d; // @[SynchronizerReg.scala 54:22]
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ sync_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ sync_1 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ sync_2 = _RAND_2[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module SynchronizerShiftReg_w1_d3(
+ input clock,
+ input io_d,
+ output io_q
+);
+ wire output_chain_clock; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_d; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_q; // @[ShiftReg.scala 45:23]
+ NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala 45:23]
+ .clock(output_chain_clock),
+ .io_d(output_chain_io_d),
+ .io_q(output_chain_io_q)
+ );
+ assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
+ assign output_chain_clock = clock;
+ assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 173:39]
+endmodule
+module IntSyncAsyncCrossingSink(
+ input clock,
+ input auto_in_sync_0,
+ output auto_out_0
+);
+ wire chain_clock; // @[ShiftReg.scala 45:23]
+ wire chain_io_d; // @[ShiftReg.scala 45:23]
+ wire chain_io_q; // @[ShiftReg.scala 45:23]
+ SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala 45:23]
+ .clock(chain_clock),
+ .io_d(chain_io_d),
+ .io_q(chain_io_q)
+ );
+ assign auto_out_0 = chain_io_q; // @[ShiftReg.scala 48:24]
+ assign chain_clock = clock;
+ assign chain_io_d = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module IntSyncSyncCrossingSink(
+ input auto_in_sync_0,
+ input auto_in_sync_1,
+ output auto_out_0,
+ output auto_out_1
+);
+ assign auto_out_0 = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1 = auto_in_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module IntSyncSyncCrossingSink_1(
+ input auto_in_sync_0,
+ output auto_out_0
+);
+ assign auto_out_0 = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module AsyncResetRegVec_w1_i0(
+ input clock,
+ input reset,
+ input io_d,
+ output io_q
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg reg_; // @[AsyncResetReg.scala 64:50]
+ assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncResetReg.scala 65:16]
+ reg_ <= 1'h0; // @[AsyncResetReg.scala 66:9]
+ end else begin
+ reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ reg_ = _RAND_0[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ reg_ = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module IntSyncCrossingSource_1(
+ input clock,
+ input reset,
+ input auto_in_0,
+ output auto_out_sync_0
+);
+ wire reg__clock; // @[AsyncResetReg.scala 89:21]
+ wire reg__reset; // @[AsyncResetReg.scala 89:21]
+ wire reg__io_d; // @[AsyncResetReg.scala 89:21]
+ wire reg__io_q; // @[AsyncResetReg.scala 89:21]
+ AsyncResetRegVec_w1_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
+ .clock(reg__clock),
+ .reset(reg__reset),
+ .io_d(reg__io_d),
+ .io_q(reg__io_q)
+ );
+ assign auto_out_sync_0 = reg__io_q; // @[Crossing.scala 41:52]
+ assign reg__clock = clock;
+ assign reg__reset = reset;
+ assign reg__io_d = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TilePRCIDomain(
+ input auto_intsink_in_sync_0,
+ input auto_tile_reset_domain_tile_hartid_in,
+ output auto_int_out_clock_xing_out_2_sync_0,
+ output auto_int_out_clock_xing_out_1_sync_0,
+ output auto_int_out_clock_xing_out_0_sync_0,
+ input auto_int_in_clock_xing_in_1_sync_0,
+ input auto_int_in_clock_xing_in_0_sync_0,
+ input auto_int_in_clock_xing_in_0_sync_1,
+ output auto_tl_slave_clock_xing_in_a_ready,
+ input auto_tl_slave_clock_xing_in_a_valid,
+ input [2:0] auto_tl_slave_clock_xing_in_a_bits_opcode,
+ input [2:0] auto_tl_slave_clock_xing_in_a_bits_param,
+ input [2:0] auto_tl_slave_clock_xing_in_a_bits_size,
+ input [2:0] auto_tl_slave_clock_xing_in_a_bits_source,
+ input [31:0] auto_tl_slave_clock_xing_in_a_bits_address,
+ input [7:0] auto_tl_slave_clock_xing_in_a_bits_mask,
+ input [63:0] auto_tl_slave_clock_xing_in_a_bits_data,
+ input auto_tl_slave_clock_xing_in_d_ready,
+ output auto_tl_slave_clock_xing_in_d_valid,
+ output [2:0] auto_tl_slave_clock_xing_in_d_bits_opcode,
+ output [1:0] auto_tl_slave_clock_xing_in_d_bits_param,
+ output [2:0] auto_tl_slave_clock_xing_in_d_bits_size,
+ output [2:0] auto_tl_slave_clock_xing_in_d_bits_source,
+ output auto_tl_slave_clock_xing_in_d_bits_sink,
+ output auto_tl_slave_clock_xing_in_d_bits_denied,
+ output [63:0] auto_tl_slave_clock_xing_in_d_bits_data,
+ output auto_tl_slave_clock_xing_in_d_bits_corrupt,
+ input auto_tl_master_clock_xing_out_a_ready,
+ output auto_tl_master_clock_xing_out_a_valid,
+ output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode,
+ output [2:0] auto_tl_master_clock_xing_out_a_bits_param,
+ output [3:0] auto_tl_master_clock_xing_out_a_bits_size,
+ output auto_tl_master_clock_xing_out_a_bits_source,
+ output [31:0] auto_tl_master_clock_xing_out_a_bits_address,
+ output [7:0] auto_tl_master_clock_xing_out_a_bits_mask,
+ output [63:0] auto_tl_master_clock_xing_out_a_bits_data,
+ output auto_tl_master_clock_xing_out_a_bits_corrupt,
+ output auto_tl_master_clock_xing_out_d_ready,
+ input auto_tl_master_clock_xing_out_d_valid,
+ input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode,
+ input [1:0] auto_tl_master_clock_xing_out_d_bits_param,
+ input [3:0] auto_tl_master_clock_xing_out_d_bits_size,
+ input auto_tl_master_clock_xing_out_d_bits_source,
+ input auto_tl_master_clock_xing_out_d_bits_sink,
+ input auto_tl_master_clock_xing_out_d_bits_denied,
+ input [63:0] auto_tl_master_clock_xing_out_d_bits_data,
+ input auto_tl_master_clock_xing_out_d_bits_corrupt,
+ input auto_tap_clock_in_clock,
+ input auto_tap_clock_in_reset
+);
+ wire tile_reset_domain_auto_tile_slave_in_a_ready; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_slave_in_a_valid; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_slave_in_a_bits_opcode; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_slave_in_a_bits_param; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_slave_in_a_bits_size; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_slave_in_a_bits_source; // @[TilePRCIDomain.scala 45:37]
+ wire [31:0] tile_reset_domain_auto_tile_slave_in_a_bits_address; // @[TilePRCIDomain.scala 45:37]
+ wire [7:0] tile_reset_domain_auto_tile_slave_in_a_bits_mask; // @[TilePRCIDomain.scala 45:37]
+ wire [63:0] tile_reset_domain_auto_tile_slave_in_a_bits_data; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_slave_in_d_ready; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_slave_in_d_valid; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_slave_in_d_bits_opcode; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_slave_in_d_bits_size; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_slave_in_d_bits_source; // @[TilePRCIDomain.scala 45:37]
+ wire [63:0] tile_reset_domain_auto_tile_slave_in_d_bits_data; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_wfi_out_0; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_int_local_in_2_0; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_int_local_in_1_0; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_int_local_in_1_1; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_int_local_in_0_0; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_hartid_in; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_a_ready; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_a_valid; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_opcode; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_param; // @[TilePRCIDomain.scala 45:37]
+ wire [3:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_size; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_source; // @[TilePRCIDomain.scala 45:37]
+ wire [31:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_address; // @[TilePRCIDomain.scala 45:37]
+ wire [7:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_mask; // @[TilePRCIDomain.scala 45:37]
+ wire [63:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_data; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_d_ready; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_d_valid; // @[TilePRCIDomain.scala 45:37]
+ wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_opcode; // @[TilePRCIDomain.scala 45:37]
+ wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_param; // @[TilePRCIDomain.scala 45:37]
+ wire [3:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_size; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_source; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_sink; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_denied; // @[TilePRCIDomain.scala 45:37]
+ wire [63:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_data; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_corrupt; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_clock_in_clock; // @[TilePRCIDomain.scala 45:37]
+ wire tile_reset_domain_auto_clock_in_reset; // @[TilePRCIDomain.scala 45:37]
+ wire clockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
+ wire clockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
+ wire clockNode_auto_out_clock; // @[ClockGroup.scala 106:107]
+ wire clockNode_auto_out_reset; // @[ClockGroup.scala 106:107]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_clock; // @[Buffer.scala 68:28]
+ wire buffer_1_reset; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_2_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_2_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_2_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_2_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_2_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_2_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_2_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_2_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_2_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_2_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_2_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_2_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_2_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_2_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_2_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_2_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_2_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_3_clock; // @[Buffer.scala 68:28]
+ wire buffer_3_reset; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_3_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_3_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_3_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_3_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_3_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [31:0] buffer_3_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_3_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_3_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_3_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_3_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_3_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire intsink_clock; // @[Crossing.scala 74:29]
+ wire intsink_auto_in_sync_0; // @[Crossing.scala 74:29]
+ wire intsink_auto_out_0; // @[Crossing.scala 74:29]
+ wire intsink_1_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_1_auto_in_sync_1; // @[Crossing.scala 94:29]
+ wire intsink_1_auto_out_0; // @[Crossing.scala 94:29]
+ wire intsink_1_auto_out_1; // @[Crossing.scala 94:29]
+ wire intsink_2_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_2_auto_out_0; // @[Crossing.scala 94:29]
+ wire intsource_1_clock; // @[Crossing.scala 26:31]
+ wire intsource_1_reset; // @[Crossing.scala 26:31]
+ wire intsource_1_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_1_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire intsource_2_clock; // @[Crossing.scala 26:31]
+ wire intsource_2_reset; // @[Crossing.scala 26:31]
+ wire intsource_2_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_2_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire intsource_3_clock; // @[Crossing.scala 26:31]
+ wire intsource_3_reset; // @[Crossing.scala 26:31]
+ wire intsource_3_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_3_auto_out_sync_0; // @[Crossing.scala 26:31]
+ TileResetDomain tile_reset_domain ( // @[TilePRCIDomain.scala 45:37]
+ .auto_tile_slave_in_a_ready(tile_reset_domain_auto_tile_slave_in_a_ready),
+ .auto_tile_slave_in_a_valid(tile_reset_domain_auto_tile_slave_in_a_valid),
+ .auto_tile_slave_in_a_bits_opcode(tile_reset_domain_auto_tile_slave_in_a_bits_opcode),
+ .auto_tile_slave_in_a_bits_param(tile_reset_domain_auto_tile_slave_in_a_bits_param),
+ .auto_tile_slave_in_a_bits_size(tile_reset_domain_auto_tile_slave_in_a_bits_size),
+ .auto_tile_slave_in_a_bits_source(tile_reset_domain_auto_tile_slave_in_a_bits_source),
+ .auto_tile_slave_in_a_bits_address(tile_reset_domain_auto_tile_slave_in_a_bits_address),
+ .auto_tile_slave_in_a_bits_mask(tile_reset_domain_auto_tile_slave_in_a_bits_mask),
+ .auto_tile_slave_in_a_bits_data(tile_reset_domain_auto_tile_slave_in_a_bits_data),
+ .auto_tile_slave_in_d_ready(tile_reset_domain_auto_tile_slave_in_d_ready),
+ .auto_tile_slave_in_d_valid(tile_reset_domain_auto_tile_slave_in_d_valid),
+ .auto_tile_slave_in_d_bits_opcode(tile_reset_domain_auto_tile_slave_in_d_bits_opcode),
+ .auto_tile_slave_in_d_bits_size(tile_reset_domain_auto_tile_slave_in_d_bits_size),
+ .auto_tile_slave_in_d_bits_source(tile_reset_domain_auto_tile_slave_in_d_bits_source),
+ .auto_tile_slave_in_d_bits_data(tile_reset_domain_auto_tile_slave_in_d_bits_data),
+ .auto_tile_wfi_out_0(tile_reset_domain_auto_tile_wfi_out_0),
+ .auto_tile_int_local_in_2_0(tile_reset_domain_auto_tile_int_local_in_2_0),
+ .auto_tile_int_local_in_1_0(tile_reset_domain_auto_tile_int_local_in_1_0),
+ .auto_tile_int_local_in_1_1(tile_reset_domain_auto_tile_int_local_in_1_1),
+ .auto_tile_int_local_in_0_0(tile_reset_domain_auto_tile_int_local_in_0_0),
+ .auto_tile_hartid_in(tile_reset_domain_auto_tile_hartid_in),
+ .auto_tile_tl_other_masters_out_a_ready(tile_reset_domain_auto_tile_tl_other_masters_out_a_ready),
+ .auto_tile_tl_other_masters_out_a_valid(tile_reset_domain_auto_tile_tl_other_masters_out_a_valid),
+ .auto_tile_tl_other_masters_out_a_bits_opcode(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_opcode),
+ .auto_tile_tl_other_masters_out_a_bits_param(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_param),
+ .auto_tile_tl_other_masters_out_a_bits_size(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_size),
+ .auto_tile_tl_other_masters_out_a_bits_source(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_source),
+ .auto_tile_tl_other_masters_out_a_bits_address(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_address),
+ .auto_tile_tl_other_masters_out_a_bits_mask(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_mask),
+ .auto_tile_tl_other_masters_out_a_bits_data(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_data),
+ .auto_tile_tl_other_masters_out_d_ready(tile_reset_domain_auto_tile_tl_other_masters_out_d_ready),
+ .auto_tile_tl_other_masters_out_d_valid(tile_reset_domain_auto_tile_tl_other_masters_out_d_valid),
+ .auto_tile_tl_other_masters_out_d_bits_opcode(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_opcode),
+ .auto_tile_tl_other_masters_out_d_bits_param(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_param),
+ .auto_tile_tl_other_masters_out_d_bits_size(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_size),
+ .auto_tile_tl_other_masters_out_d_bits_source(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_source),
+ .auto_tile_tl_other_masters_out_d_bits_sink(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_sink),
+ .auto_tile_tl_other_masters_out_d_bits_denied(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_denied),
+ .auto_tile_tl_other_masters_out_d_bits_data(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_data),
+ .auto_tile_tl_other_masters_out_d_bits_corrupt(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_corrupt),
+ .auto_clock_in_clock(tile_reset_domain_auto_clock_in_clock),
+ .auto_clock_in_reset(tile_reset_domain_auto_clock_in_reset)
+ );
+ FixedClockBroadcast_4 clockNode ( // @[ClockGroup.scala 106:107]
+ .auto_in_clock(clockNode_auto_in_clock),
+ .auto_in_reset(clockNode_auto_in_reset),
+ .auto_out_clock(clockNode_auto_out_clock),
+ .auto_out_reset(clockNode_auto_out_reset)
+ );
+ TLBuffer_15 buffer ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
+ );
+ TLBuffer_16 buffer_1 ( // @[Buffer.scala 68:28]
+ .clock(buffer_1_clock),
+ .reset(buffer_1_reset),
+ .auto_in_a_ready(buffer_1_auto_in_a_ready),
+ .auto_in_a_valid(buffer_1_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
+ .auto_in_d_ready(buffer_1_auto_in_d_ready),
+ .auto_in_d_valid(buffer_1_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_1_auto_out_a_ready),
+ .auto_out_a_valid(buffer_1_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_1_auto_out_d_ready),
+ .auto_out_d_valid(buffer_1_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt)
+ );
+ TLBuffer_17 buffer_2 ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_2_auto_in_a_ready),
+ .auto_in_a_valid(buffer_2_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_2_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_2_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_2_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_2_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_2_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_2_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_2_auto_in_a_bits_data),
+ .auto_in_d_ready(buffer_2_auto_in_d_ready),
+ .auto_in_d_valid(buffer_2_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_2_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(buffer_2_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_2_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_2_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_2_auto_out_a_ready),
+ .auto_out_a_valid(buffer_2_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_2_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_2_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_2_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_2_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_2_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_2_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_2_auto_out_a_bits_data),
+ .auto_out_d_ready(buffer_2_auto_out_d_ready),
+ .auto_out_d_valid(buffer_2_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_2_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_2_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_2_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_2_auto_out_d_bits_data)
+ );
+ TLBuffer_18 buffer_3 ( // @[Buffer.scala 68:28]
+ .clock(buffer_3_clock),
+ .reset(buffer_3_reset),
+ .auto_in_a_ready(buffer_3_auto_in_a_ready),
+ .auto_in_a_valid(buffer_3_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_3_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_3_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_3_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_3_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_3_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_3_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_3_auto_in_a_bits_data),
+ .auto_in_d_ready(buffer_3_auto_in_d_ready),
+ .auto_in_d_valid(buffer_3_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_3_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_3_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_3_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_3_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_3_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_3_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_3_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_3_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_3_auto_out_a_ready),
+ .auto_out_a_valid(buffer_3_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_3_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_3_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_3_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_3_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_3_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_3_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_3_auto_out_a_bits_data),
+ .auto_out_d_ready(buffer_3_auto_out_d_ready),
+ .auto_out_d_valid(buffer_3_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_3_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_3_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_3_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_3_auto_out_d_bits_data)
+ );
+ IntSyncAsyncCrossingSink intsink ( // @[Crossing.scala 74:29]
+ .clock(intsink_clock),
+ .auto_in_sync_0(intsink_auto_in_sync_0),
+ .auto_out_0(intsink_auto_out_0)
+ );
+ IntSyncSyncCrossingSink intsink_1 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_1_auto_in_sync_0),
+ .auto_in_sync_1(intsink_1_auto_in_sync_1),
+ .auto_out_0(intsink_1_auto_out_0),
+ .auto_out_1(intsink_1_auto_out_1)
+ );
+ IntSyncSyncCrossingSink_1 intsink_2 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_2_auto_in_sync_0),
+ .auto_out_0(intsink_2_auto_out_0)
+ );
+ IntSyncCrossingSource_1 intsource_1 ( // @[Crossing.scala 26:31]
+ .clock(intsource_1_clock),
+ .reset(intsource_1_reset),
+ .auto_in_0(intsource_1_auto_in_0),
+ .auto_out_sync_0(intsource_1_auto_out_sync_0)
+ );
+ IntSyncCrossingSource_1 intsource_2 ( // @[Crossing.scala 26:31]
+ .clock(intsource_2_clock),
+ .reset(intsource_2_reset),
+ .auto_in_0(intsource_2_auto_in_0),
+ .auto_out_sync_0(intsource_2_auto_out_sync_0)
+ );
+ IntSyncCrossingSource_1 intsource_3 ( // @[Crossing.scala 26:31]
+ .clock(intsource_3_clock),
+ .reset(intsource_3_reset),
+ .auto_in_0(intsource_3_auto_in_0),
+ .auto_out_sync_0(intsource_3_auto_out_sync_0)
+ );
+ assign auto_int_out_clock_xing_out_2_sync_0 = intsource_3_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_int_out_clock_xing_out_1_sync_0 = intsource_2_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_int_out_clock_xing_out_0_sync_0 = intsource_1_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_slave_clock_xing_in_a_ready = buffer_3_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_valid = buffer_3_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_bits_opcode = buffer_3_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_bits_param = buffer_3_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_bits_size = buffer_3_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_bits_source = buffer_3_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_bits_sink = buffer_3_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_bits_denied = buffer_3_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_bits_data = buffer_3_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_slave_clock_xing_in_d_bits_corrupt = buffer_3_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tl_master_clock_xing_out_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_a_bits_param = buffer_1_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_a_bits_data = buffer_1_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_tl_master_clock_xing_out_d_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_a_valid = buffer_2_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_a_bits_opcode = buffer_2_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_a_bits_param = buffer_2_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_a_bits_size = buffer_2_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_a_bits_source = buffer_2_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_a_bits_address = buffer_2_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_a_bits_mask = buffer_2_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_a_bits_data = buffer_2_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_slave_in_d_ready = buffer_2_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_int_local_in_2_0 = intsink_2_auto_out_0; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_int_local_in_1_0 = intsink_1_auto_out_0; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_int_local_in_1_1 = intsink_1_auto_out_1; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_int_local_in_0_0 = intsink_auto_out_0; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_tile_hartid_in = auto_tile_reset_domain_tile_hartid_in; // @[LazyModule.scala 309:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign tile_reset_domain_auto_clock_in_clock = clockNode_auto_out_clock; // @[LazyModule.scala 296:16]
+ assign tile_reset_domain_auto_clock_in_reset = clockNode_auto_out_reset; // @[LazyModule.scala 296:16]
+ assign clockNode_auto_in_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign clockNode_auto_in_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_valid = tile_reset_domain_auto_tile_tl_other_masters_out_a_valid; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_opcode = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_param = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_size = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_source = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_address = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_mask = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_a_bits_data = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign buffer_auto_in_d_ready = tile_reset_domain_auto_tile_tl_other_masters_out_d_ready; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_a_ready = buffer_1_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_valid = buffer_1_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_bits_param = buffer_1_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_bits_size = buffer_1_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_bits_source = buffer_1_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_bits_data = buffer_1_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign buffer_auto_out_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign buffer_1_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 298:16]
+ assign buffer_1_auto_out_a_ready = auto_tl_master_clock_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_valid = auto_tl_master_clock_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_1_auto_out_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign buffer_2_auto_in_a_valid = buffer_3_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_in_a_bits_opcode = buffer_3_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_in_a_bits_param = buffer_3_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_in_a_bits_size = buffer_3_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_in_a_bits_source = buffer_3_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_in_a_bits_address = buffer_3_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_in_a_bits_mask = buffer_3_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_in_a_bits_data = buffer_3_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_in_d_ready = buffer_3_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_out_a_ready = tile_reset_domain_auto_tile_slave_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_out_d_valid = tile_reset_domain_auto_tile_slave_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_out_d_bits_opcode = tile_reset_domain_auto_tile_slave_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_out_d_bits_size = tile_reset_domain_auto_tile_slave_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_out_d_bits_source = tile_reset_domain_auto_tile_slave_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_2_auto_out_d_bits_data = tile_reset_domain_auto_tile_slave_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_3_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_a_valid = auto_tl_slave_clock_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_a_bits_opcode = auto_tl_slave_clock_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_a_bits_param = auto_tl_slave_clock_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_a_bits_size = auto_tl_slave_clock_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_a_bits_source = auto_tl_slave_clock_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_a_bits_address = auto_tl_slave_clock_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_a_bits_mask = auto_tl_slave_clock_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_a_bits_data = auto_tl_slave_clock_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_in_d_ready = auto_tl_slave_clock_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_3_auto_out_a_ready = buffer_2_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_3_auto_out_d_valid = buffer_2_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_3_auto_out_d_bits_opcode = buffer_2_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_3_auto_out_d_bits_size = buffer_2_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_3_auto_out_d_bits_source = buffer_2_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_3_auto_out_d_bits_data = buffer_2_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign intsink_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsink_auto_in_sync_0 = auto_intsink_in_sync_0; // @[LazyModule.scala 309:16]
+ assign intsink_1_auto_in_sync_0 = auto_int_in_clock_xing_in_0_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsink_1_auto_in_sync_1 = auto_int_in_clock_xing_in_0_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsink_2_auto_in_sync_0 = auto_int_in_clock_xing_in_1_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsource_1_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsource_1_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsource_1_auto_in_0 = 1'h0; // @[LazyModule.scala 298:16]
+ assign intsource_2_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsource_2_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsource_2_auto_in_0 = tile_reset_domain_auto_tile_wfi_out_0; // @[LazyModule.scala 298:16]
+ assign intsource_3_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsource_3_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign intsource_3_auto_in_0 = 1'h0; // @[LazyModule.scala 298:16]
+endmodule
+module TLMonitor_43(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [27:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [27:0] _GEN_71 = {{25'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [27:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [27:0] _T_33 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 137:31]
+ wire [28:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [28:0] _T_36 = $signed(_T_34) & -29'sh4000000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 29'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [27:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [127:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [127:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 671:90 672:22]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set_wo_ready = _GEN_15[79:0];
+ wire [79:0] d_clr_wo_ready = _GEN_21[79:0];
+ wire _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_714 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_661 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_661) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_670 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_670) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_704[0] & (_T_696 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_696 & _T_2 & ~_T_704[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_714 & (_T_696 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_696 & _T_2 & ~_T_714) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:15)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_739 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_739) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Plic.scala:363:15)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[27:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module LevelGateway(
+ input clock,
+ input reset,
+ input io_interrupt,
+ output io_plic_valid,
+ input io_plic_ready,
+ input io_plic_complete
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg inFlight; // @[Plic.scala 34:21]
+ wire _GEN_0 = io_interrupt & io_plic_ready | inFlight; // @[Plic.scala 34:21 35:{40,51}]
+ assign io_plic_valid = io_interrupt & ~inFlight; // @[Plic.scala 37:33]
+ always @(posedge clock) begin
+ if (reset) begin // @[Plic.scala 34:21]
+ inFlight <= 1'h0; // @[Plic.scala 34:21]
+ end else if (io_plic_complete) begin // @[Plic.scala 36:27]
+ inFlight <= 1'h0; // @[Plic.scala 36:38]
+ end else begin
+ inFlight <= _GEN_0;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ inFlight = _RAND_0[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module PLICFanIn(
+ input [2:0] io_prio_0,
+ input [2:0] io_prio_1,
+ input [2:0] io_prio_2,
+ input [2:0] io_prio_3,
+ input [2:0] io_prio_4,
+ input [2:0] io_prio_5,
+ input [2:0] io_prio_6,
+ input [2:0] io_prio_7,
+ input [7:0] io_ip,
+ output [3:0] io_dev,
+ output [2:0] io_max
+);
+ wire [3:0] effectivePriority_1 = {io_ip[0],io_prio_0}; // @[Cat.scala 31:58]
+ wire [3:0] effectivePriority_2 = {io_ip[1],io_prio_1}; // @[Cat.scala 31:58]
+ wire [3:0] effectivePriority_3 = {io_ip[2],io_prio_2}; // @[Cat.scala 31:58]
+ wire [3:0] effectivePriority_4 = {io_ip[3],io_prio_3}; // @[Cat.scala 31:58]
+ wire [3:0] effectivePriority_5 = {io_ip[4],io_prio_4}; // @[Cat.scala 31:58]
+ wire [3:0] effectivePriority_6 = {io_ip[5],io_prio_5}; // @[Cat.scala 31:58]
+ wire [3:0] effectivePriority_7 = {io_ip[6],io_prio_6}; // @[Cat.scala 31:58]
+ wire [3:0] effectivePriority_8 = {io_ip[7],io_prio_7}; // @[Cat.scala 31:58]
+ wire _T = 4'h8 >= effectivePriority_1; // @[Plic.scala 345:20]
+ wire [3:0] _T_2 = _T ? 4'h8 : effectivePriority_1; // @[Misc.scala 34:9]
+ wire _T_3 = _T ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
+ wire _T_4 = effectivePriority_2 >= effectivePriority_3; // @[Plic.scala 345:20]
+ wire [3:0] _T_6 = _T_4 ? effectivePriority_2 : effectivePriority_3; // @[Misc.scala 34:9]
+ wire _T_7 = _T_4 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
+ wire _T_8 = _T_2 >= _T_6; // @[Plic.scala 345:20]
+ wire [1:0] _GEN_0 = {{1'd0}, _T_7}; // @[Plic.scala 345:61]
+ wire [1:0] _T_9 = 2'h2 | _GEN_0; // @[Plic.scala 345:61]
+ wire [3:0] _T_10 = _T_8 ? _T_2 : _T_6; // @[Misc.scala 34:9]
+ wire [1:0] _T_11 = _T_8 ? {{1'd0}, _T_3} : _T_9; // @[Misc.scala 34:36]
+ wire _T_12 = effectivePriority_4 >= effectivePriority_5; // @[Plic.scala 345:20]
+ wire [3:0] _T_14 = _T_12 ? effectivePriority_4 : effectivePriority_5; // @[Misc.scala 34:9]
+ wire _T_15 = _T_12 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
+ wire _T_16 = effectivePriority_6 >= effectivePriority_7; // @[Plic.scala 345:20]
+ wire [3:0] _T_18 = _T_16 ? effectivePriority_6 : effectivePriority_7; // @[Misc.scala 34:9]
+ wire _T_19 = _T_16 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
+ wire _T_20 = _T_14 >= _T_18; // @[Plic.scala 345:20]
+ wire [1:0] _GEN_1 = {{1'd0}, _T_19}; // @[Plic.scala 345:61]
+ wire [1:0] _T_21 = 2'h2 | _GEN_1; // @[Plic.scala 345:61]
+ wire [3:0] _T_22 = _T_20 ? _T_14 : _T_18; // @[Misc.scala 34:9]
+ wire [1:0] _T_23 = _T_20 ? {{1'd0}, _T_15} : _T_21; // @[Misc.scala 34:36]
+ wire _T_24 = _T_10 >= _T_22; // @[Plic.scala 345:20]
+ wire [2:0] _GEN_2 = {{1'd0}, _T_23}; // @[Plic.scala 345:61]
+ wire [2:0] _T_25 = 3'h4 | _GEN_2; // @[Plic.scala 345:61]
+ wire [3:0] _T_26 = _T_24 ? _T_10 : _T_22; // @[Misc.scala 34:9]
+ wire [2:0] _T_27 = _T_24 ? {{1'd0}, _T_11} : _T_25; // @[Misc.scala 34:36]
+ wire _T_28 = _T_26 >= effectivePriority_8; // @[Plic.scala 345:20]
+ wire [3:0] maxPri = _T_28 ? _T_26 : effectivePriority_8; // @[Misc.scala 34:9]
+ assign io_dev = _T_28 ? {{1'd0}, _T_27} : 4'h8; // @[Misc.scala 34:36]
+ assign io_max = maxPri[2:0]; // @[Plic.scala 351:10]
+endmodule
+module Queue_23(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input io_enq_bits_read,
+ input [22:0] io_enq_bits_index,
+ input [63:0] io_enq_bits_data,
+ input [7:0] io_enq_bits_mask,
+ input [6:0] io_enq_bits_extra_tlrr_extra_source,
+ input [1:0] io_enq_bits_extra_tlrr_extra_size,
+ input io_deq_ready,
+ output io_deq_valid,
+ output io_deq_bits_read,
+ output [22:0] io_deq_bits_index,
+ output [63:0] io_deq_bits_data,
+ output [7:0] io_deq_bits_mask,
+ output [6:0] io_deq_bits_extra_tlrr_extra_source,
+ output [1:0] io_deq_bits_extra_tlrr_extra_size
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [63:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_6;
+`endif // RANDOMIZE_REG_INIT
+ reg ram_read [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_read_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_read_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_read_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_read_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_read_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_read_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_read_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [22:0] ram_index [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_index_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_index_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [22:0] ram_index_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [22:0] ram_index_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_index_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_index_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_index_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] ram_mask [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [6:0] ram_extra_tlrr_extra_source [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [6:0] ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [6:0] ram_extra_tlrr_extra_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [1:0] ram_extra_tlrr_extra_size [0:0]; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [1:0] ram_extra_tlrr_extra_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_extra_tlrr_extra_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire empty = ~maybe_full; // @[Decoupled.scala 264:28]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_read_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_read_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_read_io_deq_bits_MPORT_data = ram_read[ram_read_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_read_MPORT_data = io_enq_bits_read;
+ assign ram_read_MPORT_addr = 1'h0;
+ assign ram_read_MPORT_mask = 1'h1;
+ assign ram_read_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_index_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_index_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_index_io_deq_bits_MPORT_data = ram_index[ram_index_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_index_MPORT_data = io_enq_bits_index;
+ assign ram_index_MPORT_addr = 1'h0;
+ assign ram_index_MPORT_mask = 1'h1;
+ assign ram_index_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = 1'h0;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = 1'h0;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data =
+ ram_extra_tlrr_extra_source[ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_extra_tlrr_extra_source_MPORT_data = io_enq_bits_extra_tlrr_extra_source;
+ assign ram_extra_tlrr_extra_source_MPORT_addr = 1'h0;
+ assign ram_extra_tlrr_extra_source_MPORT_mask = 1'h1;
+ assign ram_extra_tlrr_extra_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr = 1'h0;
+ assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data =
+ ram_extra_tlrr_extra_size[ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_extra_tlrr_extra_size_MPORT_data = io_enq_bits_extra_tlrr_extra_size;
+ assign ram_extra_tlrr_extra_size_MPORT_addr = 1'h0;
+ assign ram_extra_tlrr_extra_size_MPORT_mask = 1'h1;
+ assign ram_extra_tlrr_extra_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_read = ram_read_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_index = ram_index_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_extra_tlrr_extra_source = ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_extra_tlrr_extra_size = ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_read_MPORT_en & ram_read_MPORT_mask) begin
+ ram_read[ram_read_MPORT_addr] <= ram_read_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_index_MPORT_en & ram_index_MPORT_mask) begin
+ ram_index[ram_index_MPORT_addr] <= ram_index_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_extra_tlrr_extra_source_MPORT_en & ram_extra_tlrr_extra_source_MPORT_mask) begin
+ ram_extra_tlrr_extra_source[ram_extra_tlrr_extra_source_MPORT_addr] <= ram_extra_tlrr_extra_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_extra_tlrr_extra_size_MPORT_en & ram_extra_tlrr_extra_size_MPORT_mask) begin
+ ram_extra_tlrr_extra_size[ram_extra_tlrr_extra_size_MPORT_addr] <= ram_extra_tlrr_extra_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_read[initvar] = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_index[initvar] = _RAND_1[22:0];
+ _RAND_2 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_data[initvar] = _RAND_2[63:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_3[7:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_extra_tlrr_extra_source[initvar] = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 1; initvar = initvar+1)
+ ram_extra_tlrr_extra_size[initvar] = _RAND_5[1:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_6 = {1{`RANDOM}};
+ maybe_full = _RAND_6[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLPLIC(
+ input clock,
+ input reset,
+ input auto_int_in_0,
+ input auto_int_in_1,
+ input auto_int_in_2,
+ input auto_int_in_3,
+ input auto_int_in_4,
+ input auto_int_in_5,
+ input auto_int_in_6,
+ input auto_int_in_7,
+ output auto_int_out_0,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [1:0] auto_in_a_bits_size,
+ input [6:0] auto_in_a_bits_source,
+ input [27:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_size,
+ output [6:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [27:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire gateways_gateway_clock; // @[Plic.scala 156:27]
+ wire gateways_gateway_reset; // @[Plic.scala 156:27]
+ wire gateways_gateway_io_interrupt; // @[Plic.scala 156:27]
+ wire gateways_gateway_io_plic_valid; // @[Plic.scala 156:27]
+ wire gateways_gateway_io_plic_ready; // @[Plic.scala 156:27]
+ wire gateways_gateway_io_plic_complete; // @[Plic.scala 156:27]
+ wire gateways_gateway_1_clock; // @[Plic.scala 156:27]
+ wire gateways_gateway_1_reset; // @[Plic.scala 156:27]
+ wire gateways_gateway_1_io_interrupt; // @[Plic.scala 156:27]
+ wire gateways_gateway_1_io_plic_valid; // @[Plic.scala 156:27]
+ wire gateways_gateway_1_io_plic_ready; // @[Plic.scala 156:27]
+ wire gateways_gateway_1_io_plic_complete; // @[Plic.scala 156:27]
+ wire gateways_gateway_2_clock; // @[Plic.scala 156:27]
+ wire gateways_gateway_2_reset; // @[Plic.scala 156:27]
+ wire gateways_gateway_2_io_interrupt; // @[Plic.scala 156:27]
+ wire gateways_gateway_2_io_plic_valid; // @[Plic.scala 156:27]
+ wire gateways_gateway_2_io_plic_ready; // @[Plic.scala 156:27]
+ wire gateways_gateway_2_io_plic_complete; // @[Plic.scala 156:27]
+ wire gateways_gateway_3_clock; // @[Plic.scala 156:27]
+ wire gateways_gateway_3_reset; // @[Plic.scala 156:27]
+ wire gateways_gateway_3_io_interrupt; // @[Plic.scala 156:27]
+ wire gateways_gateway_3_io_plic_valid; // @[Plic.scala 156:27]
+ wire gateways_gateway_3_io_plic_ready; // @[Plic.scala 156:27]
+ wire gateways_gateway_3_io_plic_complete; // @[Plic.scala 156:27]
+ wire gateways_gateway_4_clock; // @[Plic.scala 156:27]
+ wire gateways_gateway_4_reset; // @[Plic.scala 156:27]
+ wire gateways_gateway_4_io_interrupt; // @[Plic.scala 156:27]
+ wire gateways_gateway_4_io_plic_valid; // @[Plic.scala 156:27]
+ wire gateways_gateway_4_io_plic_ready; // @[Plic.scala 156:27]
+ wire gateways_gateway_4_io_plic_complete; // @[Plic.scala 156:27]
+ wire gateways_gateway_5_clock; // @[Plic.scala 156:27]
+ wire gateways_gateway_5_reset; // @[Plic.scala 156:27]
+ wire gateways_gateway_5_io_interrupt; // @[Plic.scala 156:27]
+ wire gateways_gateway_5_io_plic_valid; // @[Plic.scala 156:27]
+ wire gateways_gateway_5_io_plic_ready; // @[Plic.scala 156:27]
+ wire gateways_gateway_5_io_plic_complete; // @[Plic.scala 156:27]
+ wire gateways_gateway_6_clock; // @[Plic.scala 156:27]
+ wire gateways_gateway_6_reset; // @[Plic.scala 156:27]
+ wire gateways_gateway_6_io_interrupt; // @[Plic.scala 156:27]
+ wire gateways_gateway_6_io_plic_valid; // @[Plic.scala 156:27]
+ wire gateways_gateway_6_io_plic_ready; // @[Plic.scala 156:27]
+ wire gateways_gateway_6_io_plic_complete; // @[Plic.scala 156:27]
+ wire gateways_gateway_7_clock; // @[Plic.scala 156:27]
+ wire gateways_gateway_7_reset; // @[Plic.scala 156:27]
+ wire gateways_gateway_7_io_interrupt; // @[Plic.scala 156:27]
+ wire gateways_gateway_7_io_plic_valid; // @[Plic.scala 156:27]
+ wire gateways_gateway_7_io_plic_ready; // @[Plic.scala 156:27]
+ wire gateways_gateway_7_io_plic_complete; // @[Plic.scala 156:27]
+ wire [2:0] fanin_io_prio_0; // @[Plic.scala 184:25]
+ wire [2:0] fanin_io_prio_1; // @[Plic.scala 184:25]
+ wire [2:0] fanin_io_prio_2; // @[Plic.scala 184:25]
+ wire [2:0] fanin_io_prio_3; // @[Plic.scala 184:25]
+ wire [2:0] fanin_io_prio_4; // @[Plic.scala 184:25]
+ wire [2:0] fanin_io_prio_5; // @[Plic.scala 184:25]
+ wire [2:0] fanin_io_prio_6; // @[Plic.scala 184:25]
+ wire [2:0] fanin_io_prio_7; // @[Plic.scala 184:25]
+ wire [7:0] fanin_io_ip; // @[Plic.scala 184:25]
+ wire [3:0] fanin_io_dev; // @[Plic.scala 184:25]
+ wire [2:0] fanin_io_max; // @[Plic.scala 184:25]
+ wire out_back_clock; // @[Decoupled.scala 361:21]
+ wire out_back_reset; // @[Decoupled.scala 361:21]
+ wire out_back_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire out_back_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire out_back_io_enq_bits_read; // @[Decoupled.scala 361:21]
+ wire [22:0] out_back_io_enq_bits_index; // @[Decoupled.scala 361:21]
+ wire [63:0] out_back_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire [7:0] out_back_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [6:0] out_back_io_enq_bits_extra_tlrr_extra_source; // @[Decoupled.scala 361:21]
+ wire [1:0] out_back_io_enq_bits_extra_tlrr_extra_size; // @[Decoupled.scala 361:21]
+ wire out_back_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire out_back_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire out_back_io_deq_bits_read; // @[Decoupled.scala 361:21]
+ wire [22:0] out_back_io_deq_bits_index; // @[Decoupled.scala 361:21]
+ wire [63:0] out_back_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire [7:0] out_back_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [6:0] out_back_io_deq_bits_extra_tlrr_extra_source; // @[Decoupled.scala 361:21]
+ wire [1:0] out_back_io_deq_bits_extra_tlrr_extra_size; // @[Decoupled.scala 361:21]
+ reg [2:0] priority_0; // @[Plic.scala 163:31]
+ reg [2:0] priority_1; // @[Plic.scala 163:31]
+ reg [2:0] priority_2; // @[Plic.scala 163:31]
+ reg [2:0] priority_3; // @[Plic.scala 163:31]
+ reg [2:0] priority_4; // @[Plic.scala 163:31]
+ reg [2:0] priority_5; // @[Plic.scala 163:31]
+ reg [2:0] priority_6; // @[Plic.scala 163:31]
+ reg [2:0] priority_7; // @[Plic.scala 163:31]
+ reg [2:0] threshold_0; // @[Plic.scala 166:31]
+ reg pending_0; // @[Plic.scala 168:22]
+ reg pending_1; // @[Plic.scala 168:22]
+ reg pending_2; // @[Plic.scala 168:22]
+ reg pending_3; // @[Plic.scala 168:22]
+ reg pending_4; // @[Plic.scala 168:22]
+ reg pending_5; // @[Plic.scala 168:22]
+ reg pending_6; // @[Plic.scala 168:22]
+ reg pending_7; // @[Plic.scala 168:22]
+ reg [6:0] enables_0_0; // @[Plic.scala 174:26]
+ reg enables_0_1; // @[Plic.scala 176:51]
+ wire [7:0] enableVec_0 = {enables_0_1,enables_0_0}; // @[Cat.scala 31:58]
+ wire [8:0] enableVec0_0 = {enables_0_1,enables_0_0,1'h0}; // @[Cat.scala 31:58]
+ reg [3:0] maxDevs_0; // @[Plic.scala 181:22]
+ wire [7:0] pendingUInt = {pending_7,pending_6,pending_5,pending_4,pending_3,pending_2,pending_1,pending_0}; // @[Cat.scala 31:58]
+ reg [2:0] bundleOut_0_0_REG; // @[Plic.scala 188:41]
+ wire [5:0] out_oindex = {out_back_io_deq_bits_index[18],out_back_io_deq_bits_index[10],out_back_io_deq_bits_index[9],
+ out_back_io_deq_bits_index[2],out_back_io_deq_bits_index[1],out_back_io_deq_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [63:0] _out_backSel_T = 64'h1 << out_oindex; // @[OneHot.scala 57:35]
+ wire out_backSel_32 = _out_backSel_T[32]; // @[RegisterRouter.scala 83:24]
+ wire [22:0] out_bindex = out_back_io_deq_bits_index & 23'h7bf9f8; // @[RegisterRouter.scala 83:24]
+ wire _out_T_13 = out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire out_roready_21 = out_back_io_deq_valid & auto_in_d_ready & out_back_io_deq_bits_read & out_backSel_32 &
+ out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] _out_backMask_T_23 = out_back_io_deq_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_21 = out_back_io_deq_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_19 = out_back_io_deq_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_17 = out_back_io_deq_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_15 = out_back_io_deq_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_13 = out_back_io_deq_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_11 = out_back_io_deq_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_9 = out_back_io_deq_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_backMask = {_out_backMask_T_23,_out_backMask_T_21,_out_backMask_T_19,_out_backMask_T_17,
+ _out_backMask_T_15,_out_backMask_T_13,_out_backMask_T_11,_out_backMask_T_9}; // @[Cat.scala 31:58]
+ wire out_romask_21 = |out_backMask[63:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala 83:24]
+ wire _T_5 = ~reset; // @[Plic.scala 245:11]
+ wire [3:0] claiming = out_f_roready_21 ? maxDevs_0 : 4'h0; // @[Plic.scala 246:49]
+ wire [15:0] _claimedDevs_T = 16'h1 << claiming; // @[OneHot.scala 64:12]
+ wire claimedDevs_1 = _claimedDevs_T[1]; // @[Plic.scala 247:58]
+ wire claimedDevs_2 = _claimedDevs_T[2]; // @[Plic.scala 247:58]
+ wire claimedDevs_3 = _claimedDevs_T[3]; // @[Plic.scala 247:58]
+ wire claimedDevs_4 = _claimedDevs_T[4]; // @[Plic.scala 247:58]
+ wire claimedDevs_5 = _claimedDevs_T[5]; // @[Plic.scala 247:58]
+ wire claimedDevs_6 = _claimedDevs_T[6]; // @[Plic.scala 247:58]
+ wire claimedDevs_7 = _claimedDevs_T[7]; // @[Plic.scala 247:58]
+ wire claimedDevs_8 = _claimedDevs_T[8]; // @[Plic.scala 247:58]
+ wire out_woready_21 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_32 &
+ out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire out_womask_21 = &out_backMask[63:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala 83:24]
+ wire [3:0] completerDev = out_back_io_deq_bits_data[35:32]; // @[package.scala 154:13]
+ wire [8:0] _out_completer_0_T = enableVec0_0 >> completerDev; // @[Plic.scala 295:51]
+ wire completer_0 = out_f_woready_21 & _out_completer_0_T[0]; // @[Plic.scala 295:35]
+ wire [15:0] _completedDevs_T = 16'h1 << completerDev; // @[OneHot.scala 64:12]
+ wire [8:0] completedDevs = completer_0 ? _completedDevs_T[8:0] : 9'h0; // @[Plic.scala 264:28]
+ wire out_backSel_16 = _out_backSel_T[16]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_0 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_16 &
+ out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire out_womask_1 = &out_backMask[7:1]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_1 = out_woready_0 & out_womask_1; // @[RegisterRouter.scala 83:24]
+ wire out_womask_2 = &out_backMask[8]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_2 = out_woready_0 & out_womask_2; // @[RegisterRouter.scala 83:24]
+ wire [8:0] out_prepend_1 = {enables_0_1,enables_0_0,1'h0}; // @[Cat.scala 31:58]
+ wire out_womask_3 = &out_backMask[34:32]; // @[RegisterRouter.scala 83:24]
+ wire out_backSel_0 = _out_backSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_3 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_0 &
+ out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala 83:24]
+ wire [34:0] out_prepend_2 = {priority_0,32'h0}; // @[Cat.scala 31:58]
+ wire out_womask_4 = &out_backMask[2:0]; // @[RegisterRouter.scala 83:24]
+ wire out_backSel_1 = _out_backSel_T[1]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_4 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_1 &
+ out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_5 = out_woready_4 & out_womask_3; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_3 = {{29'd0}, priority_1}; // @[RegisterRouter.scala 83:24]
+ wire [34:0] out_prepend_3 = {priority_2,_out_prepend_T_3}; // @[Cat.scala 31:58]
+ wire [8:0] out_prepend_11 = {pending_7,pending_6,pending_5,pending_4,pending_3,pending_2,pending_1,pending_0,1'h0}; // @[Cat.scala 31:58]
+ wire out_backSel_2 = _out_backSel_T[2]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_15 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_2 &
+ out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_15 = out_woready_15 & out_womask_4; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_16 = out_woready_15 & out_womask_3; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_12 = {{29'd0}, priority_3}; // @[RegisterRouter.scala 83:24]
+ wire [34:0] out_prepend_12 = {priority_4,_out_prepend_T_12}; // @[Cat.scala 31:58]
+ wire out_backSel_3 = _out_backSel_T[3]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_17 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_3 &
+ out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_17 = out_woready_17 & out_womask_4; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_18 = out_woready_17 & out_womask_3; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_13 = {{29'd0}, priority_5}; // @[RegisterRouter.scala 83:24]
+ wire [34:0] out_prepend_13 = {priority_6,_out_prepend_T_13}; // @[Cat.scala 31:58]
+ wire out_f_woready_19 = out_woready_21 & out_womask_4; // @[RegisterRouter.scala 83:24]
+ wire [3:0] out_prepend_14 = {1'h0,threshold_0}; // @[Cat.scala 31:58]
+ wire [31:0] _out_T_223 = {{28'd0}, out_prepend_14}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_15 = {maxDevs_0,_out_T_223}; // @[Cat.scala 31:58]
+ wire [63:0] _out_T_239 = {{28'd0}, out_prepend_15}; // @[RegisterRouter.scala 83:24]
+ wire out_backSel_4 = _out_backSel_T[4]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_22 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_4 &
+ out_bindex == 23'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_22 = out_woready_22 & out_womask_4; // @[RegisterRouter.scala 83:24]
+ wire _GEN_275 = 6'h20 == out_oindex ? _out_T_13 : 1'h1; // @[MuxLiteral.scala 53:{26,32}]
+ wire _GEN_276 = 6'h10 == out_oindex ? _out_T_13 : _GEN_275; // @[MuxLiteral.scala 53:{26,32}]
+ wire _GEN_277 = 6'h8 == out_oindex ? _out_T_13 : _GEN_276; // @[MuxLiteral.scala 53:{26,32}]
+ wire _GEN_278 = 6'h4 == out_oindex ? _out_T_13 : _GEN_277; // @[MuxLiteral.scala 53:{26,32}]
+ wire _GEN_279 = 6'h3 == out_oindex ? _out_T_13 : _GEN_278; // @[MuxLiteral.scala 53:{26,32}]
+ wire _GEN_280 = 6'h2 == out_oindex ? _out_T_13 : _GEN_279; // @[MuxLiteral.scala 53:{26,32}]
+ wire _GEN_281 = 6'h1 == out_oindex ? _out_T_13 : _GEN_280; // @[MuxLiteral.scala 53:{26,32}]
+ wire out_out_bits_data_out = 6'h0 == out_oindex ? _out_T_13 : _GEN_281; // @[MuxLiteral.scala 53:{26,32}]
+ wire [63:0] _GEN_283 = 6'h20 == out_oindex ? _out_T_239 : 64'h0; // @[MuxLiteral.scala 53:{26,32}]
+ wire [63:0] _GEN_284 = 6'h10 == out_oindex ? {{55'd0}, out_prepend_1} : _GEN_283; // @[MuxLiteral.scala 53:{26,32}]
+ wire [63:0] _GEN_285 = 6'h8 == out_oindex ? {{55'd0}, out_prepend_11} : _GEN_284; // @[MuxLiteral.scala 53:{26,32}]
+ wire [63:0] _GEN_286 = 6'h4 == out_oindex ? {{61'd0}, priority_7} : _GEN_285; // @[MuxLiteral.scala 53:{26,32}]
+ wire [63:0] _GEN_287 = 6'h3 == out_oindex ? {{29'd0}, out_prepend_13} : _GEN_286; // @[MuxLiteral.scala 53:{26,32}]
+ wire [63:0] _GEN_288 = 6'h2 == out_oindex ? {{29'd0}, out_prepend_12} : _GEN_287; // @[MuxLiteral.scala 53:{26,32}]
+ wire [63:0] _GEN_289 = 6'h1 == out_oindex ? {{29'd0}, out_prepend_3} : _GEN_288; // @[MuxLiteral.scala 53:{26,32}]
+ wire [63:0] out_out_bits_data_out_1 = 6'h0 == out_oindex ? {{29'd0}, out_prepend_2} : _GEN_289; // @[MuxLiteral.scala 53:{26,32}]
+ wire out_bits_read = out_back_io_deq_bits_read; // @[RegisterRouter.scala 83:{24,24}]
+ TLMonitor_43 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ LevelGateway gateways_gateway ( // @[Plic.scala 156:27]
+ .clock(gateways_gateway_clock),
+ .reset(gateways_gateway_reset),
+ .io_interrupt(gateways_gateway_io_interrupt),
+ .io_plic_valid(gateways_gateway_io_plic_valid),
+ .io_plic_ready(gateways_gateway_io_plic_ready),
+ .io_plic_complete(gateways_gateway_io_plic_complete)
+ );
+ LevelGateway gateways_gateway_1 ( // @[Plic.scala 156:27]
+ .clock(gateways_gateway_1_clock),
+ .reset(gateways_gateway_1_reset),
+ .io_interrupt(gateways_gateway_1_io_interrupt),
+ .io_plic_valid(gateways_gateway_1_io_plic_valid),
+ .io_plic_ready(gateways_gateway_1_io_plic_ready),
+ .io_plic_complete(gateways_gateway_1_io_plic_complete)
+ );
+ LevelGateway gateways_gateway_2 ( // @[Plic.scala 156:27]
+ .clock(gateways_gateway_2_clock),
+ .reset(gateways_gateway_2_reset),
+ .io_interrupt(gateways_gateway_2_io_interrupt),
+ .io_plic_valid(gateways_gateway_2_io_plic_valid),
+ .io_plic_ready(gateways_gateway_2_io_plic_ready),
+ .io_plic_complete(gateways_gateway_2_io_plic_complete)
+ );
+ LevelGateway gateways_gateway_3 ( // @[Plic.scala 156:27]
+ .clock(gateways_gateway_3_clock),
+ .reset(gateways_gateway_3_reset),
+ .io_interrupt(gateways_gateway_3_io_interrupt),
+ .io_plic_valid(gateways_gateway_3_io_plic_valid),
+ .io_plic_ready(gateways_gateway_3_io_plic_ready),
+ .io_plic_complete(gateways_gateway_3_io_plic_complete)
+ );
+ LevelGateway gateways_gateway_4 ( // @[Plic.scala 156:27]
+ .clock(gateways_gateway_4_clock),
+ .reset(gateways_gateway_4_reset),
+ .io_interrupt(gateways_gateway_4_io_interrupt),
+ .io_plic_valid(gateways_gateway_4_io_plic_valid),
+ .io_plic_ready(gateways_gateway_4_io_plic_ready),
+ .io_plic_complete(gateways_gateway_4_io_plic_complete)
+ );
+ LevelGateway gateways_gateway_5 ( // @[Plic.scala 156:27]
+ .clock(gateways_gateway_5_clock),
+ .reset(gateways_gateway_5_reset),
+ .io_interrupt(gateways_gateway_5_io_interrupt),
+ .io_plic_valid(gateways_gateway_5_io_plic_valid),
+ .io_plic_ready(gateways_gateway_5_io_plic_ready),
+ .io_plic_complete(gateways_gateway_5_io_plic_complete)
+ );
+ LevelGateway gateways_gateway_6 ( // @[Plic.scala 156:27]
+ .clock(gateways_gateway_6_clock),
+ .reset(gateways_gateway_6_reset),
+ .io_interrupt(gateways_gateway_6_io_interrupt),
+ .io_plic_valid(gateways_gateway_6_io_plic_valid),
+ .io_plic_ready(gateways_gateway_6_io_plic_ready),
+ .io_plic_complete(gateways_gateway_6_io_plic_complete)
+ );
+ LevelGateway gateways_gateway_7 ( // @[Plic.scala 156:27]
+ .clock(gateways_gateway_7_clock),
+ .reset(gateways_gateway_7_reset),
+ .io_interrupt(gateways_gateway_7_io_interrupt),
+ .io_plic_valid(gateways_gateway_7_io_plic_valid),
+ .io_plic_ready(gateways_gateway_7_io_plic_ready),
+ .io_plic_complete(gateways_gateway_7_io_plic_complete)
+ );
+ PLICFanIn fanin ( // @[Plic.scala 184:25]
+ .io_prio_0(fanin_io_prio_0),
+ .io_prio_1(fanin_io_prio_1),
+ .io_prio_2(fanin_io_prio_2),
+ .io_prio_3(fanin_io_prio_3),
+ .io_prio_4(fanin_io_prio_4),
+ .io_prio_5(fanin_io_prio_5),
+ .io_prio_6(fanin_io_prio_6),
+ .io_prio_7(fanin_io_prio_7),
+ .io_ip(fanin_io_ip),
+ .io_dev(fanin_io_dev),
+ .io_max(fanin_io_max)
+ );
+ Queue_23 out_back ( // @[Decoupled.scala 361:21]
+ .clock(out_back_clock),
+ .reset(out_back_reset),
+ .io_enq_ready(out_back_io_enq_ready),
+ .io_enq_valid(out_back_io_enq_valid),
+ .io_enq_bits_read(out_back_io_enq_bits_read),
+ .io_enq_bits_index(out_back_io_enq_bits_index),
+ .io_enq_bits_data(out_back_io_enq_bits_data),
+ .io_enq_bits_mask(out_back_io_enq_bits_mask),
+ .io_enq_bits_extra_tlrr_extra_source(out_back_io_enq_bits_extra_tlrr_extra_source),
+ .io_enq_bits_extra_tlrr_extra_size(out_back_io_enq_bits_extra_tlrr_extra_size),
+ .io_deq_ready(out_back_io_deq_ready),
+ .io_deq_valid(out_back_io_deq_valid),
+ .io_deq_bits_read(out_back_io_deq_bits_read),
+ .io_deq_bits_index(out_back_io_deq_bits_index),
+ .io_deq_bits_data(out_back_io_deq_bits_data),
+ .io_deq_bits_mask(out_back_io_deq_bits_mask),
+ .io_deq_bits_extra_tlrr_extra_source(out_back_io_deq_bits_extra_tlrr_extra_source),
+ .io_deq_bits_extra_tlrr_extra_size(out_back_io_deq_bits_extra_tlrr_extra_size)
+ );
+ assign auto_int_out_0 = bundleOut_0_0_REG > threshold_0; // @[Plic.scala 188:63]
+ assign auto_in_a_ready = out_back_io_enq_ready; // @[Decoupled.scala 365:17 RegisterRouter.scala 83:24]
+ assign auto_in_d_valid = out_back_io_deq_valid; // @[RegisterRouter.scala 83:24]
+ assign auto_in_d_bits_opcode = {{2'd0}, out_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign auto_in_d_bits_size = out_back_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala 83:{24,24}]
+ assign auto_in_d_bits_source = out_back_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala 83:{24,24}]
+ assign auto_in_d_bits_data = out_out_bits_data_out ? out_out_bits_data_out_1 : 64'h0; // @[RegisterRouter.scala 83:24]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = out_back_io_enq_ready; // @[Decoupled.scala 365:17 RegisterRouter.scala 83:24]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = out_back_io_deq_valid; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, out_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = out_back_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala 83:{24,24}]
+ assign monitor_io_in_d_bits_source = out_back_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala 83:{24,24}]
+ assign gateways_gateway_clock = clock;
+ assign gateways_gateway_reset = reset;
+ assign gateways_gateway_io_interrupt = auto_int_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gateways_gateway_io_plic_ready = ~pending_0; // @[Plic.scala 250:18]
+ assign gateways_gateway_io_plic_complete = completedDevs[1]; // @[Plic.scala 265:33]
+ assign gateways_gateway_1_clock = clock;
+ assign gateways_gateway_1_reset = reset;
+ assign gateways_gateway_1_io_interrupt = auto_int_in_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gateways_gateway_1_io_plic_ready = ~pending_1; // @[Plic.scala 250:18]
+ assign gateways_gateway_1_io_plic_complete = completedDevs[2]; // @[Plic.scala 265:33]
+ assign gateways_gateway_2_clock = clock;
+ assign gateways_gateway_2_reset = reset;
+ assign gateways_gateway_2_io_interrupt = auto_int_in_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gateways_gateway_2_io_plic_ready = ~pending_2; // @[Plic.scala 250:18]
+ assign gateways_gateway_2_io_plic_complete = completedDevs[3]; // @[Plic.scala 265:33]
+ assign gateways_gateway_3_clock = clock;
+ assign gateways_gateway_3_reset = reset;
+ assign gateways_gateway_3_io_interrupt = auto_int_in_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gateways_gateway_3_io_plic_ready = ~pending_3; // @[Plic.scala 250:18]
+ assign gateways_gateway_3_io_plic_complete = completedDevs[4]; // @[Plic.scala 265:33]
+ assign gateways_gateway_4_clock = clock;
+ assign gateways_gateway_4_reset = reset;
+ assign gateways_gateway_4_io_interrupt = auto_int_in_4; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gateways_gateway_4_io_plic_ready = ~pending_4; // @[Plic.scala 250:18]
+ assign gateways_gateway_4_io_plic_complete = completedDevs[5]; // @[Plic.scala 265:33]
+ assign gateways_gateway_5_clock = clock;
+ assign gateways_gateway_5_reset = reset;
+ assign gateways_gateway_5_io_interrupt = auto_int_in_5; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gateways_gateway_5_io_plic_ready = ~pending_5; // @[Plic.scala 250:18]
+ assign gateways_gateway_5_io_plic_complete = completedDevs[6]; // @[Plic.scala 265:33]
+ assign gateways_gateway_6_clock = clock;
+ assign gateways_gateway_6_reset = reset;
+ assign gateways_gateway_6_io_interrupt = auto_int_in_6; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gateways_gateway_6_io_plic_ready = ~pending_6; // @[Plic.scala 250:18]
+ assign gateways_gateway_6_io_plic_complete = completedDevs[7]; // @[Plic.scala 265:33]
+ assign gateways_gateway_7_clock = clock;
+ assign gateways_gateway_7_reset = reset;
+ assign gateways_gateway_7_io_interrupt = auto_int_in_7; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gateways_gateway_7_io_plic_ready = ~pending_7; // @[Plic.scala 250:18]
+ assign gateways_gateway_7_io_plic_complete = completedDevs[8]; // @[Plic.scala 265:33]
+ assign fanin_io_prio_0 = priority_0; // @[Plic.scala 185:21]
+ assign fanin_io_prio_1 = priority_1; // @[Plic.scala 185:21]
+ assign fanin_io_prio_2 = priority_2; // @[Plic.scala 185:21]
+ assign fanin_io_prio_3 = priority_3; // @[Plic.scala 185:21]
+ assign fanin_io_prio_4 = priority_4; // @[Plic.scala 185:21]
+ assign fanin_io_prio_5 = priority_5; // @[Plic.scala 185:21]
+ assign fanin_io_prio_6 = priority_6; // @[Plic.scala 185:21]
+ assign fanin_io_prio_7 = priority_7; // @[Plic.scala 185:21]
+ assign fanin_io_ip = enableVec_0 & pendingUInt; // @[Plic.scala 186:40]
+ assign out_back_clock = clock;
+ assign out_back_reset = reset;
+ assign out_back_io_enq_valid = auto_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign out_back_io_enq_bits_read = auto_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ assign out_back_io_enq_bits_index = auto_in_a_bits_address[25:3]; // @[RegisterRouter.scala 71:18 73:19]
+ assign out_back_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign out_back_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign out_back_io_enq_bits_extra_tlrr_extra_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign out_back_io_enq_bits_extra_tlrr_extra_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign out_back_io_deq_ready = auto_in_d_ready; // @[RegisterRouter.scala 83:24]
+ always @(posedge clock) begin
+ if (out_f_woready_3) begin // @[RegField.scala 74:88]
+ priority_0 <= out_back_io_deq_bits_data[34:32]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_4) begin // @[RegField.scala 74:88]
+ priority_1 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_5) begin // @[RegField.scala 74:88]
+ priority_2 <= out_back_io_deq_bits_data[34:32]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_15) begin // @[RegField.scala 74:88]
+ priority_3 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_16) begin // @[RegField.scala 74:88]
+ priority_4 <= out_back_io_deq_bits_data[34:32]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_17) begin // @[RegField.scala 74:88]
+ priority_5 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_18) begin // @[RegField.scala 74:88]
+ priority_6 <= out_back_io_deq_bits_data[34:32]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_22) begin // @[RegField.scala 74:88]
+ priority_7 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_19) begin // @[RegField.scala 74:88]
+ threshold_0 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[Plic.scala 168:22]
+ pending_0 <= 1'h0; // @[Plic.scala 168:22]
+ end else if (claimedDevs_1 | gateways_gateway_io_plic_valid) begin // @[Plic.scala 251:27]
+ pending_0 <= ~claimedDevs_1; // @[Plic.scala 251:31]
+ end
+ if (reset) begin // @[Plic.scala 168:22]
+ pending_1 <= 1'h0; // @[Plic.scala 168:22]
+ end else if (claimedDevs_2 | gateways_gateway_1_io_plic_valid) begin // @[Plic.scala 251:27]
+ pending_1 <= ~claimedDevs_2; // @[Plic.scala 251:31]
+ end
+ if (reset) begin // @[Plic.scala 168:22]
+ pending_2 <= 1'h0; // @[Plic.scala 168:22]
+ end else if (claimedDevs_3 | gateways_gateway_2_io_plic_valid) begin // @[Plic.scala 251:27]
+ pending_2 <= ~claimedDevs_3; // @[Plic.scala 251:31]
+ end
+ if (reset) begin // @[Plic.scala 168:22]
+ pending_3 <= 1'h0; // @[Plic.scala 168:22]
+ end else if (claimedDevs_4 | gateways_gateway_3_io_plic_valid) begin // @[Plic.scala 251:27]
+ pending_3 <= ~claimedDevs_4; // @[Plic.scala 251:31]
+ end
+ if (reset) begin // @[Plic.scala 168:22]
+ pending_4 <= 1'h0; // @[Plic.scala 168:22]
+ end else if (claimedDevs_5 | gateways_gateway_4_io_plic_valid) begin // @[Plic.scala 251:27]
+ pending_4 <= ~claimedDevs_5; // @[Plic.scala 251:31]
+ end
+ if (reset) begin // @[Plic.scala 168:22]
+ pending_5 <= 1'h0; // @[Plic.scala 168:22]
+ end else if (claimedDevs_6 | gateways_gateway_5_io_plic_valid) begin // @[Plic.scala 251:27]
+ pending_5 <= ~claimedDevs_6; // @[Plic.scala 251:31]
+ end
+ if (reset) begin // @[Plic.scala 168:22]
+ pending_6 <= 1'h0; // @[Plic.scala 168:22]
+ end else if (claimedDevs_7 | gateways_gateway_6_io_plic_valid) begin // @[Plic.scala 251:27]
+ pending_6 <= ~claimedDevs_7; // @[Plic.scala 251:31]
+ end
+ if (reset) begin // @[Plic.scala 168:22]
+ pending_7 <= 1'h0; // @[Plic.scala 168:22]
+ end else if (claimedDevs_8 | gateways_gateway_7_io_plic_valid) begin // @[Plic.scala 251:27]
+ pending_7 <= ~claimedDevs_8; // @[Plic.scala 251:31]
+ end
+ if (out_f_woready_1) begin // @[RegField.scala 74:88]
+ enables_0_0 <= out_back_io_deq_bits_data[7:1]; // @[RegField.scala 74:92]
+ end
+ if (out_f_woready_2) begin // @[RegField.scala 74:88]
+ enables_0_1 <= out_back_io_deq_bits_data[8]; // @[RegField.scala 74:92]
+ end
+ maxDevs_0 <= fanin_io_dev; // @[Plic.scala 187:21]
+ bundleOut_0_0_REG <= fanin_io_max; // @[Plic.scala 188:41]
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(out_f_roready_21 & out_f_roready_21 - 1'h1)) & ~reset) begin
+ $fatal; // @[Plic.scala 245:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(~(out_f_roready_21 & out_f_roready_21 - 1'h1))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Plic.scala:245 assert((claimer.asUInt & (claimer.asUInt - UInt(1))) === UInt(0)) // One-Hot\n"
+ ); // @[Plic.scala 245:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(completer_0 & completer_0 - 1'h1)) & _T_5) begin
+ $fatal; // @[Plic.scala 262:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(~(completer_0 & completer_0 - 1'h1))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Plic.scala:262 assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot\n"
+ ); // @[Plic.scala 262:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(completerDev == completerDev) & _T_5) begin
+ $fatal; // @[Plic.scala 292:19]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_5 & ~(completerDev == completerDev)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:292 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n"
+ ); // @[Plic.scala 292:19]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ priority_0 = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ priority_1 = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ priority_2 = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ priority_3 = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ priority_4 = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ priority_5 = _RAND_5[2:0];
+ _RAND_6 = {1{`RANDOM}};
+ priority_6 = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ priority_7 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ threshold_0 = _RAND_8[2:0];
+ _RAND_9 = {1{`RANDOM}};
+ pending_0 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ pending_1 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ pending_2 = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ pending_3 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ pending_4 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ pending_5 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ pending_6 = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ pending_7 = _RAND_16[0:0];
+ _RAND_17 = {1{`RANDOM}};
+ enables_0_0 = _RAND_17[6:0];
+ _RAND_18 = {1{`RANDOM}};
+ enables_0_1 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ maxDevs_0 = _RAND_19[3:0];
+ _RAND_20 = {1{`RANDOM}};
+ bundleOut_0_0_REG = _RAND_20[2:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockSinkDomain(
+ input auto_plic_int_in_0,
+ input auto_plic_int_in_1,
+ input auto_plic_int_in_2,
+ input auto_plic_int_in_3,
+ input auto_plic_int_in_4,
+ input auto_plic_int_in_5,
+ input auto_plic_int_in_6,
+ input auto_plic_int_in_7,
+ output auto_plic_int_out_0,
+ output auto_plic_in_a_ready,
+ input auto_plic_in_a_valid,
+ input [2:0] auto_plic_in_a_bits_opcode,
+ input [2:0] auto_plic_in_a_bits_param,
+ input [1:0] auto_plic_in_a_bits_size,
+ input [6:0] auto_plic_in_a_bits_source,
+ input [27:0] auto_plic_in_a_bits_address,
+ input [7:0] auto_plic_in_a_bits_mask,
+ input [63:0] auto_plic_in_a_bits_data,
+ input auto_plic_in_a_bits_corrupt,
+ input auto_plic_in_d_ready,
+ output auto_plic_in_d_valid,
+ output [2:0] auto_plic_in_d_bits_opcode,
+ output [1:0] auto_plic_in_d_bits_size,
+ output [6:0] auto_plic_in_d_bits_source,
+ output [63:0] auto_plic_in_d_bits_data,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire plic_clock; // @[Plic.scala 362:46]
+ wire plic_reset; // @[Plic.scala 362:46]
+ wire plic_auto_int_in_0; // @[Plic.scala 362:46]
+ wire plic_auto_int_in_1; // @[Plic.scala 362:46]
+ wire plic_auto_int_in_2; // @[Plic.scala 362:46]
+ wire plic_auto_int_in_3; // @[Plic.scala 362:46]
+ wire plic_auto_int_in_4; // @[Plic.scala 362:46]
+ wire plic_auto_int_in_5; // @[Plic.scala 362:46]
+ wire plic_auto_int_in_6; // @[Plic.scala 362:46]
+ wire plic_auto_int_in_7; // @[Plic.scala 362:46]
+ wire plic_auto_int_out_0; // @[Plic.scala 362:46]
+ wire plic_auto_in_a_ready; // @[Plic.scala 362:46]
+ wire plic_auto_in_a_valid; // @[Plic.scala 362:46]
+ wire [2:0] plic_auto_in_a_bits_opcode; // @[Plic.scala 362:46]
+ wire [2:0] plic_auto_in_a_bits_param; // @[Plic.scala 362:46]
+ wire [1:0] plic_auto_in_a_bits_size; // @[Plic.scala 362:46]
+ wire [6:0] plic_auto_in_a_bits_source; // @[Plic.scala 362:46]
+ wire [27:0] plic_auto_in_a_bits_address; // @[Plic.scala 362:46]
+ wire [7:0] plic_auto_in_a_bits_mask; // @[Plic.scala 362:46]
+ wire [63:0] plic_auto_in_a_bits_data; // @[Plic.scala 362:46]
+ wire plic_auto_in_a_bits_corrupt; // @[Plic.scala 362:46]
+ wire plic_auto_in_d_ready; // @[Plic.scala 362:46]
+ wire plic_auto_in_d_valid; // @[Plic.scala 362:46]
+ wire [2:0] plic_auto_in_d_bits_opcode; // @[Plic.scala 362:46]
+ wire [1:0] plic_auto_in_d_bits_size; // @[Plic.scala 362:46]
+ wire [6:0] plic_auto_in_d_bits_source; // @[Plic.scala 362:46]
+ wire [63:0] plic_auto_in_d_bits_data; // @[Plic.scala 362:46]
+ TLPLIC plic ( // @[Plic.scala 362:46]
+ .clock(plic_clock),
+ .reset(plic_reset),
+ .auto_int_in_0(plic_auto_int_in_0),
+ .auto_int_in_1(plic_auto_int_in_1),
+ .auto_int_in_2(plic_auto_int_in_2),
+ .auto_int_in_3(plic_auto_int_in_3),
+ .auto_int_in_4(plic_auto_int_in_4),
+ .auto_int_in_5(plic_auto_int_in_5),
+ .auto_int_in_6(plic_auto_int_in_6),
+ .auto_int_in_7(plic_auto_int_in_7),
+ .auto_int_out_0(plic_auto_int_out_0),
+ .auto_in_a_ready(plic_auto_in_a_ready),
+ .auto_in_a_valid(plic_auto_in_a_valid),
+ .auto_in_a_bits_opcode(plic_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(plic_auto_in_a_bits_param),
+ .auto_in_a_bits_size(plic_auto_in_a_bits_size),
+ .auto_in_a_bits_source(plic_auto_in_a_bits_source),
+ .auto_in_a_bits_address(plic_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(plic_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(plic_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(plic_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(plic_auto_in_d_ready),
+ .auto_in_d_valid(plic_auto_in_d_valid),
+ .auto_in_d_bits_opcode(plic_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(plic_auto_in_d_bits_size),
+ .auto_in_d_bits_source(plic_auto_in_d_bits_source),
+ .auto_in_d_bits_data(plic_auto_in_d_bits_data)
+ );
+ assign auto_plic_int_out_0 = plic_auto_int_out_0; // @[LazyModule.scala 311:12]
+ assign auto_plic_in_a_ready = plic_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_plic_in_d_valid = plic_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_plic_in_d_bits_opcode = plic_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_plic_in_d_bits_size = plic_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_plic_in_d_bits_source = plic_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_plic_in_d_bits_data = plic_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign plic_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign plic_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign plic_auto_int_in_0 = auto_plic_int_in_0; // @[LazyModule.scala 309:16]
+ assign plic_auto_int_in_1 = auto_plic_int_in_1; // @[LazyModule.scala 309:16]
+ assign plic_auto_int_in_2 = auto_plic_int_in_2; // @[LazyModule.scala 309:16]
+ assign plic_auto_int_in_3 = auto_plic_int_in_3; // @[LazyModule.scala 309:16]
+ assign plic_auto_int_in_4 = auto_plic_int_in_4; // @[LazyModule.scala 309:16]
+ assign plic_auto_int_in_5 = auto_plic_int_in_5; // @[LazyModule.scala 309:16]
+ assign plic_auto_int_in_6 = auto_plic_int_in_6; // @[LazyModule.scala 309:16]
+ assign plic_auto_int_in_7 = auto_plic_int_in_7; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_valid = auto_plic_in_a_valid; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_bits_opcode = auto_plic_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_bits_param = auto_plic_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_bits_size = auto_plic_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_bits_source = auto_plic_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_bits_address = auto_plic_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_bits_mask = auto_plic_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_bits_data = auto_plic_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_a_bits_corrupt = auto_plic_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign plic_auto_in_d_ready = auto_plic_in_d_ready; // @[LazyModule.scala 309:16]
+endmodule
+module TLMonitor_44(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [25:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [25:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [25:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [25:0] _T_33 = io_in_a_bits_address ^ 26'h2000000; // @[Parameters.scala 137:31]
+ wire [26:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [26:0] _T_36 = $signed(_T_34) & -27'sh10000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 27'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [25:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CLINT.scala:111:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[25:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module CLINT(
+ input clock,
+ input reset,
+ output auto_int_out_0,
+ output auto_int_out_1,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [1:0] auto_in_a_bits_size,
+ input [6:0] auto_in_a_bits_source,
+ input [25:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_size,
+ output [6:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input io_rtcTick
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [63:0] _RAND_0;
+ reg [63:0] _RAND_1;
+ reg [31:0] _RAND_2;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [25:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ reg [63:0] time_; // @[CLINT.scala 69:23]
+ wire [63:0] _time_T_1 = time_ + 64'h1; // @[CLINT.scala 70:38]
+ reg [63:0] timecmp_0; // @[CLINT.scala 73:41]
+ reg ipi_0; // @[CLINT.scala 74:41]
+ wire [7:0] oldBytes__0 = timecmp_0[7:0]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes__1 = timecmp_0[15:8]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes__2 = timecmp_0[23:16]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes__3 = timecmp_0[31:24]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes__4 = timecmp_0[39:32]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes__5 = timecmp_0[47:40]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes__6 = timecmp_0[55:48]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes__7 = timecmp_0[63:56]; // @[RegField.scala 151:53]
+ wire in_bits_read = auto_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [12:0] in_bits_index = auto_in_a_bits_address[15:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire [1:0] out_iindex = {in_bits_index[12],in_bits_index[11]}; // @[Cat.scala 31:58]
+ wire [12:0] out_findex = in_bits_index & 13'h7ff; // @[RegisterRouter.scala 83:24]
+ wire _out_T_2 = out_findex == 13'h7ff; // @[RegisterRouter.scala 83:24]
+ wire _out_T = out_findex == 13'h0; // @[RegisterRouter.scala 83:24]
+ wire [3:0] _out_backSel_T = 4'h1 << out_iindex; // @[OneHot.scala 57:35]
+ wire out_backSel_1 = _out_backSel_T[1]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_0 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read & out_backSel_1 & out_findex == 13'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] _out_backMask_T_23 = auto_in_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_21 = auto_in_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_19 = auto_in_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_17 = auto_in_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_15 = auto_in_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_13 = auto_in_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_11 = auto_in_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_9 = auto_in_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_backMask = {_out_backMask_T_23,_out_backMask_T_21,_out_backMask_T_19,_out_backMask_T_17,
+ _out_backMask_T_15,_out_backMask_T_13,_out_backMask_T_11,_out_backMask_T_9}; // @[Cat.scala 31:58]
+ wire out_womask = &out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala 83:24]
+ wire out_womask_1 = &out_backMask[15:8]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_1 = out_woready_0 & out_womask_1; // @[RegisterRouter.scala 83:24]
+ wire out_womask_2 = &out_backMask[23:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_2 = out_woready_0 & out_womask_2; // @[RegisterRouter.scala 83:24]
+ wire out_womask_3 = &out_backMask[31:24]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_3 = out_woready_0 & out_womask_3; // @[RegisterRouter.scala 83:24]
+ wire out_womask_4 = &out_backMask[39:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_4 = out_woready_0 & out_womask_4; // @[RegisterRouter.scala 83:24]
+ wire out_womask_5 = &out_backMask[47:40]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_5 = out_woready_0 & out_womask_5; // @[RegisterRouter.scala 83:24]
+ wire out_womask_6 = &out_backMask[55:48]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_6 = out_woready_0 & out_womask_6; // @[RegisterRouter.scala 83:24]
+ wire out_womask_7 = &out_backMask[63:56]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_7 = out_woready_0 & out_womask_7; // @[RegisterRouter.scala 83:24]
+ wire [7:0] newBytes__1 = out_f_woready_1 ? auto_in_a_bits_data[15:8] : oldBytes__1; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes__0 = out_f_woready ? auto_in_a_bits_data[7:0] : oldBytes__0; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes__3 = out_f_woready_3 ? auto_in_a_bits_data[31:24] : oldBytes__3; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes__2 = out_f_woready_2 ? auto_in_a_bits_data[23:16] : oldBytes__2; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes__5 = out_f_woready_5 ? auto_in_a_bits_data[47:40] : oldBytes__5; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes__4 = out_f_woready_4 ? auto_in_a_bits_data[39:32] : oldBytes__4; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes__7 = out_f_woready_7 ? auto_in_a_bits_data[63:56] : oldBytes__7; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes__6 = out_f_woready_6 ? auto_in_a_bits_data[55:48] : oldBytes__6; // @[RegField.scala 158:{20,33}]
+ wire [63:0] _timecmp_0_T = {newBytes__7,newBytes__6,newBytes__5,newBytes__4,newBytes__3,newBytes__2,newBytes__1,
+ newBytes__0}; // @[RegField.scala 154:52]
+ wire [7:0] oldBytes_1_0 = time_[7:0]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_1_1 = time_[15:8]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_1_2 = time_[23:16]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_1_3 = time_[31:24]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_1_4 = time_[39:32]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_1_5 = time_[47:40]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_1_6 = time_[55:48]; // @[RegField.scala 151:53]
+ wire [7:0] oldBytes_1_7 = time_[63:56]; // @[RegField.scala 151:53]
+ wire out_backSel_2 = _out_backSel_T[2]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_8 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read & out_backSel_2 & out_findex == 13'h7ff; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_8 = out_woready_8 & out_womask; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_9 = out_woready_8 & out_womask_1; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_10 = out_woready_8 & out_womask_2; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_11 = out_woready_8 & out_womask_3; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_12 = out_woready_8 & out_womask_4; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_13 = out_woready_8 & out_womask_5; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_14 = out_woready_8 & out_womask_6; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_15 = out_woready_8 & out_womask_7; // @[RegisterRouter.scala 83:24]
+ wire [7:0] newBytes_1_1 = out_f_woready_9 ? auto_in_a_bits_data[15:8] : oldBytes_1_1; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_1_0 = out_f_woready_8 ? auto_in_a_bits_data[7:0] : oldBytes_1_0; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_1_3 = out_f_woready_11 ? auto_in_a_bits_data[31:24] : oldBytes_1_3; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_1_2 = out_f_woready_10 ? auto_in_a_bits_data[23:16] : oldBytes_1_2; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_1_5 = out_f_woready_13 ? auto_in_a_bits_data[47:40] : oldBytes_1_5; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_1_4 = out_f_woready_12 ? auto_in_a_bits_data[39:32] : oldBytes_1_4; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_1_7 = out_f_woready_15 ? auto_in_a_bits_data[63:56] : oldBytes_1_7; // @[RegField.scala 158:{20,33}]
+ wire [7:0] newBytes_1_6 = out_f_woready_14 ? auto_in_a_bits_data[55:48] : oldBytes_1_6; // @[RegField.scala 158:{20,33}]
+ wire [63:0] _time_T_2 = {newBytes_1_7,newBytes_1_6,newBytes_1_5,newBytes_1_4,newBytes_1_3,newBytes_1_2,newBytes_1_1,
+ newBytes_1_0}; // @[RegField.scala 154:52]
+ wire [63:0] out_prepend_6 = {oldBytes__7,oldBytes__6,oldBytes__5,oldBytes__4,oldBytes__3,oldBytes__2,oldBytes__1,
+ oldBytes__0}; // @[Cat.scala 31:58]
+ wire [63:0] out_prepend_13 = {oldBytes_1_7,oldBytes_1_6,oldBytes_1_5,oldBytes_1_4,oldBytes_1_3,oldBytes_1_2,
+ oldBytes_1_1,oldBytes_1_0}; // @[Cat.scala 31:58]
+ wire out_wimask_16 = &out_backMask[0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_0 = _out_backSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_16 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 13'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala 83:24]
+ wire [1:0] out_prepend_14 = {1'h0,ipi_0}; // @[Cat.scala 31:58]
+ wire [31:0] _out_T_200 = {{30'd0}, out_prepend_14}; // @[RegisterRouter.scala 83:24]
+ wire _GEN_37 = 2'h1 == out_iindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_38 = 2'h2 == out_iindex ? _out_T_2 : _GEN_37; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_39 = 2'h3 == out_iindex | _GEN_38; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_0 = {{32'd0}, _out_T_200}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_41 = 2'h1 == out_iindex ? out_prepend_6 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_42 = 2'h2 == out_iindex ? out_prepend_13 : _GEN_41; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_43 = 2'h3 == out_iindex ? 64'h0 : _GEN_42; // @[MuxLiteral.scala 48:{10,10}]
+ TLMonitor_44 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ assign auto_int_out_0 = ipi_0; // @[CLINT.scala 78:37]
+ assign auto_int_out_1 = time_ >= timecmp_0; // @[CLINT.scala 79:43]
+ assign auto_in_a_ready = auto_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign auto_in_d_valid = auto_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign auto_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign auto_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_in_d_bits_data = _GEN_39 ? _GEN_43 : 64'h0; // @[RegisterRouter.scala 83:24]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ always @(posedge clock) begin
+ if (reset) begin // @[CLINT.scala 69:23]
+ time_ <= 64'h0; // @[CLINT.scala 69:23]
+ end else if (out_f_woready_8 | out_f_woready_9 | out_f_woready_10 | out_f_woready_11 | out_f_woready_12 |
+ out_f_woready_13 | out_f_woready_14 | out_f_woready_15) begin // @[RegField.scala 154:34]
+ time_ <= _time_T_2; // @[RegField.scala 154:40]
+ end else if (io_rtcTick) begin // @[CLINT.scala 70:23]
+ time_ <= _time_T_1; // @[CLINT.scala 70:30]
+ end
+ if (out_f_woready | out_f_woready_1 | out_f_woready_2 | out_f_woready_3 | out_f_woready_4 | out_f_woready_5 |
+ out_f_woready_6 | out_f_woready_7) begin // @[RegField.scala 154:34]
+ timecmp_0 <= _timecmp_0_T; // @[RegField.scala 154:40]
+ end
+ if (reset) begin // @[CLINT.scala 74:41]
+ ipi_0 <= 1'h0; // @[CLINT.scala 74:41]
+ end else if (out_f_wivalid_16) begin // @[RegField.scala 74:88]
+ ipi_0 <= auto_in_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {2{`RANDOM}};
+ time_ = _RAND_0[63:0];
+ _RAND_1 = {2{`RANDOM}};
+ timecmp_0 = _RAND_1[63:0];
+ _RAND_2 = {1{`RANDOM}};
+ ipi_0 = _RAND_2[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_45(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [8:0] io_in_a_bits_address,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [1:0] io_in_d_bits_size,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire [8:0] _is_aligned_T = io_in_a_bits_address & 9'h3; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala 20:24]
+ wire [9:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [9:0] _T_23 = $signed(_T_7) & 10'sh200; // @[Parameters.scala 137:52]
+ wire _T_24 = $signed(_T_23) == 10'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_127 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_167 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_201 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_236 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_266 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_296 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_330 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _T_334 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_338 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
+ wire _T_342 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_346 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_350 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_354 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_365 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_369 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_382 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_402 = _T_350 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_411 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_428 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_446 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [8:0] address; // @[Monitor.scala 388:22]
+ wire _T_476 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_477 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_493 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_500 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_501 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_505 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_509 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_517 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_521 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [15:0] _GEN_73 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_527 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire _T_530 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire _T_534 = ~inflight; // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_538 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_540 = ~_T_334; // @[Monitor.scala 671:74]
+ wire _T_541 = io_in_d_valid & d_first_1 & ~_T_334; // @[Monitor.scala 671:71]
+ wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_540 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_540 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire _T_553 = inflight | _T_527; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_558 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_559 = io_in_d_bits_opcode == _GEN_32 | _T_558; // @[Monitor.scala 685:77]
+ wire _T_563 = 2'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_570 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_571 = io_in_d_bits_opcode == _GEN_48 | _T_570; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_75 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_575 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_585 = _T_538 & a_first_1 & io_in_a_valid & _T_540; // @[Monitor.scala 694:116]
+ wire _T_587 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [3:0] a_sizes_set = _GEN_20[3:0];
+ wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_596 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [15:0] _GEN_78 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_78 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_622 = io_in_d_valid & d_first_2 & _T_334; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_334 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_640 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
+ wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_69 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_69 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_69 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_69 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_69 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_69 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_69 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_69 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_24 & (io_in_a_valid & _T_127 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_127 & ~reset & ~_T_24) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_127 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_127 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_24 & (io_in_a_valid & _T_167 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_167 & ~reset & ~_T_24) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_167 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_167 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_201 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_201 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_201 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_201 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_266 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_266 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_266 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_266 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_296 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_296 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_296 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_296 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_330 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_330) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_338 & (io_in_d_valid & _T_334 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_334 & _T_2 & ~_T_338) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_342 & (io_in_d_valid & _T_334 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_334 & _T_2 & ~_T_342) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_346 & (io_in_d_valid & _T_334 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_334 & _T_2 & ~_T_346) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_350 & (io_in_d_valid & _T_334 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_334 & _T_2 & ~_T_350) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_354 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_354 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_338 & (io_in_d_valid & _T_354 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_354 & _T_2 & ~_T_338) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_365 & (io_in_d_valid & _T_354 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_354 & _T_2 & ~_T_365) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_369 & (io_in_d_valid & _T_354 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_354 & _T_2 & ~_T_369) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_346 & (io_in_d_valid & _T_354 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_354 & _T_2 & ~_T_346) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_382 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_382 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_338 & (io_in_d_valid & _T_382 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_382 & _T_2 & ~_T_338) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_365 & (io_in_d_valid & _T_382 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_382 & _T_2 & ~_T_365) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_369 & (io_in_d_valid & _T_382 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_382 & _T_2 & ~_T_369) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_402 & (io_in_d_valid & _T_382 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_382 & _T_2 & ~_T_402) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_342 & (io_in_d_valid & _T_411 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_411 & _T_2 & ~_T_342) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_346 & (io_in_d_valid & _T_411 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_411 & _T_2 & ~_T_346) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_342 & (io_in_d_valid & _T_428 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_428 & _T_2 & ~_T_342) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_402 & (io_in_d_valid & _T_428 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_428 & _T_2 & ~_T_402) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_342 & (io_in_d_valid & _T_446 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_446 & _T_2 & ~_T_342) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_346 & (io_in_d_valid & _T_446 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_446 & _T_2 & ~_T_346) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_477 & (_T_476 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_476 & ~reset & ~_T_477) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_493 & (_T_476 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_476 & ~reset & ~_T_493) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_501 & (_T_500 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_500 & _T_2 & ~_T_501) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_505 & (_T_500 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_500 & _T_2 & ~_T_505) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_509 & (_T_500 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_500 & _T_2 & ~_T_509) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_517 & (_T_500 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_500 & _T_2 & ~_T_517) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_521 & (_T_500 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_500 & _T_2 & ~_T_521) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_534 & (_T_530 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_530 & ~reset & ~_T_534) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_553 & (_T_541 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_541 & _T_2 & ~_T_553) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_559 & (_T_541 & _T_527 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_541 & _T_527 & _T_2 & ~_T_559) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_563 & (_T_541 & _T_527 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_541 & _T_527 & _T_2 & ~_T_563) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_571 & (_T_541 & ~_T_527 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_541 & ~_T_527 & _T_2 & ~_T_571) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_575 & (_T_541 & ~_T_527 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_541 & ~_T_527 & _T_2 & ~_T_575) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_587 & (_T_585 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_585 & _T_2 & ~_T_587) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_596 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_596) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Debug.scala:628:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_622 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_622 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_640 & (_T_622 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_622 & _T_2 & ~_T_640) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:628:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ address = _RAND_2[8:0];
+ _RAND_3 = {1{`RANDOM}};
+ d_first_counter = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ opcode_1 = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ param_1 = _RAND_5[1:0];
+ _RAND_6 = {1{`RANDOM}};
+ size_1 = _RAND_6[1:0];
+ _RAND_7 = {1{`RANDOM}};
+ sink = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ denied = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_10[3:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes = _RAND_11[3:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_15[3:0];
+ _RAND_16 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_16[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLXbar_8(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [8:0] auto_in_a_bits_address,
+ input [31:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output auto_in_d_bits_denied,
+ output [31:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_1_a_ready,
+ output auto_out_1_a_valid,
+ output [2:0] auto_out_1_a_bits_opcode,
+ output [6:0] auto_out_1_a_bits_address,
+ output [31:0] auto_out_1_a_bits_data,
+ output auto_out_1_d_ready,
+ input auto_out_1_d_valid,
+ input [2:0] auto_out_1_d_bits_opcode,
+ input [31:0] auto_out_1_d_bits_data,
+ input auto_out_0_a_ready,
+ output auto_out_0_a_valid,
+ output [2:0] auto_out_0_a_bits_opcode,
+ output [8:0] auto_out_0_a_bits_address,
+ output [31:0] auto_out_0_a_bits_data,
+ output auto_out_0_d_ready,
+ input auto_out_0_d_valid,
+ input [2:0] auto_out_0_d_bits_opcode,
+ input [1:0] auto_out_0_d_bits_param,
+ input [1:0] auto_out_0_d_bits_size,
+ input auto_out_0_d_bits_sink,
+ input auto_out_0_d_bits_denied,
+ input [31:0] auto_out_0_d_bits_data,
+ input auto_out_0_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [8:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire [9:0] _requestAIO_T_1 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire [9:0] _requestAIO_T_3 = $signed(_requestAIO_T_1) & 10'sh1c0; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_4 = $signed(_requestAIO_T_3) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _requestAIO_T_5 = auto_in_a_bits_address ^ 9'h44; // @[Parameters.scala 137:31]
+ wire [9:0] _requestAIO_T_6 = {1'b0,$signed(_requestAIO_T_5)}; // @[Parameters.scala 137:49]
+ wire [9:0] _requestAIO_T_8 = $signed(_requestAIO_T_6) & 10'sh1f4; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_9 = $signed(_requestAIO_T_8) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _requestAIO_T_10 = auto_in_a_bits_address ^ 9'h58; // @[Parameters.scala 137:31]
+ wire [9:0] _requestAIO_T_11 = {1'b0,$signed(_requestAIO_T_10)}; // @[Parameters.scala 137:49]
+ wire [9:0] _requestAIO_T_13 = $signed(_requestAIO_T_11) & 10'sh1f8; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_14 = $signed(_requestAIO_T_13) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _requestAIO_T_15 = auto_in_a_bits_address ^ 9'h60; // @[Parameters.scala 137:31]
+ wire [9:0] _requestAIO_T_16 = {1'b0,$signed(_requestAIO_T_15)}; // @[Parameters.scala 137:49]
+ wire [9:0] _requestAIO_T_18 = $signed(_requestAIO_T_16) & 10'sh1e0; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_19 = $signed(_requestAIO_T_18) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _requestAIO_T_20 = auto_in_a_bits_address ^ 9'h80; // @[Parameters.scala 137:31]
+ wire [9:0] _requestAIO_T_21 = {1'b0,$signed(_requestAIO_T_20)}; // @[Parameters.scala 137:49]
+ wire [9:0] _requestAIO_T_23 = $signed(_requestAIO_T_21) & 10'sh180; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_24 = $signed(_requestAIO_T_23) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _requestAIO_T_25 = auto_in_a_bits_address ^ 9'h100; // @[Parameters.scala 137:31]
+ wire [9:0] _requestAIO_T_26 = {1'b0,$signed(_requestAIO_T_25)}; // @[Parameters.scala 137:49]
+ wire [9:0] _requestAIO_T_28 = $signed(_requestAIO_T_26) & 10'sh100; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_29 = $signed(_requestAIO_T_28) == 10'sh0; // @[Parameters.scala 137:67]
+ wire requestAIO_0_0 = _requestAIO_T_4 | _requestAIO_T_9 | _requestAIO_T_14 | _requestAIO_T_19 | _requestAIO_T_24 |
+ _requestAIO_T_29; // @[Xbar.scala 363:92]
+ wire [8:0] _requestAIO_T_35 = auto_in_a_bits_address ^ 9'h40; // @[Parameters.scala 137:31]
+ wire [9:0] _requestAIO_T_36 = {1'b0,$signed(_requestAIO_T_35)}; // @[Parameters.scala 137:49]
+ wire [9:0] _requestAIO_T_38 = $signed(_requestAIO_T_36) & 10'sh1f4; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_39 = $signed(_requestAIO_T_38) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _requestAIO_T_40 = auto_in_a_bits_address ^ 9'h50; // @[Parameters.scala 137:31]
+ wire [9:0] _requestAIO_T_41 = {1'b0,$signed(_requestAIO_T_40)}; // @[Parameters.scala 137:49]
+ wire [9:0] _requestAIO_T_43 = $signed(_requestAIO_T_41) & 10'sh1f8; // @[Parameters.scala 137:52]
+ wire _requestAIO_T_44 = $signed(_requestAIO_T_43) == 10'sh0; // @[Parameters.scala 137:67]
+ wire requestAIO_0_1 = _requestAIO_T_39 | _requestAIO_T_44; // @[Xbar.scala 363:92]
+ reg beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle = ~beatsLeft; // @[Arbiter.scala 88:28]
+ wire latch = idle & auto_in_d_ready; // @[Arbiter.scala 89:24]
+ wire [1:0] readys_valid = {auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
+ wire _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
+ reg [1:0] readys_mask; // @[Arbiter.scala 23:23]
+ wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
+ wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
+ wire [3:0] readys_filter = {_readys_filter_T_1,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
+ wire [3:0] _GEN_1 = {{1'd0}, readys_filter[3:1]}; // @[package.scala 253:43]
+ wire [3:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
+ wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
+ wire [3:0] _GEN_2 = {{1'd0}, _readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
+ wire [3:0] readys_unready = _GEN_2 | _readys_unready_T_4; // @[Arbiter.scala 25:58]
+ wire [1:0] _readys_readys_T_2 = readys_unready[3:2] & readys_unready[1:0]; // @[Arbiter.scala 26:39]
+ wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
+ wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
+ wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
+ wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[1:0]; // @[package.scala 244:43]
+ wire readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
+ wire readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
+ wire earlyWinner_0 = readys_0 & auto_out_0_d_valid; // @[Arbiter.scala 97:79]
+ wire earlyWinner_1 = readys_1 & auto_out_1_d_valid; // @[Arbiter.scala 97:79]
+ wire _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
+ wire _T_10 = auto_out_0_d_valid | auto_out_1_d_valid; // @[Arbiter.scala 107:36]
+ wire _T_11 = ~(auto_out_0_d_valid | auto_out_1_d_valid); // @[Arbiter.scala 107:15]
+ reg state_0; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire _sink_ACancel_earlyValid_T_3 = state_0 & auto_out_0_d_valid | state_1 & auto_out_1_d_valid; // @[Mux.scala 27:73]
+ wire sink_ACancel_5_earlyValid = idle ? _T_10 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_5_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
+ wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire [31:0] _T_27 = muxStateEarly_0 ? auto_out_0_d_bits_data : 32'h0; // @[Mux.scala 27:73]
+ wire [31:0] _T_28 = muxStateEarly_1 ? auto_out_1_d_bits_data : 32'h0; // @[Mux.scala 27:73]
+ wire [1:0] _T_39 = muxStateEarly_0 ? auto_out_0_d_bits_size : 2'h0; // @[Mux.scala 27:73]
+ wire [1:0] _T_40 = muxStateEarly_1 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_45 = muxStateEarly_0 ? auto_out_0_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ wire [2:0] _T_46 = muxStateEarly_1 ? auto_out_1_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ TLMonitor_45 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready; // @[Mux.scala 27:73]
+ assign auto_in_d_valid = idle ? _T_10 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ assign auto_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_data = _T_27 | _T_28; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt; // @[Mux.scala 27:73]
+ assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[Xbar.scala 428:50]
+ assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_address = auto_in_a_bits_address[6:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
+ assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_d_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
+ assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[Xbar.scala 428:50]
+ assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_d_ready = auto_in_d_ready & allowed_0; // @[Arbiter.scala 123:31]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready; // @[Mux.scala 27:73]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = idle ? _T_10 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
+ assign monitor_io_in_d_bits_opcode = _T_45 | _T_46; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_param = muxStateEarly_0 ? auto_out_0_d_bits_param : 2'h0; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_size = _T_39 | _T_40; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_sink = muxStateEarly_0 & auto_out_0_d_bits_sink; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt; // @[Mux.scala 27:73]
+ always @(posedge clock) begin
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 1'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ beatsLeft <= 1'h0;
+ end else begin
+ beatsLeft <= beatsLeft - _beatsLeft_T_2;
+ end
+ if (reset) begin // @[Arbiter.scala 23:23]
+ readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
+ end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
+ readys_mask <= _readys_mask_T_3; // @[Arbiter.scala 28:12]
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_0 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_0 <= earlyWinner_0;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~earlyWinner_0 | ~earlyWinner_1) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 105:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
+ ); // @[Arbiter.scala 105:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(auto_out_0_d_valid | auto_out_1_d_valid) | _prefixOR_T) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(~(auto_out_0_d_valid | auto_out_1_d_valid) | _prefixOR_T)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_11 | _T_10) & _readys_T_3) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_readys_T_3 & ~(_T_11 | _T_10)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ beatsLeft = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ readys_mask = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ state_0 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ state_1 = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module DMIToTL(
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [8:0] auto_out_a_bits_address,
+ output [31:0] auto_out_a_bits_data,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input auto_out_d_bits_denied,
+ input [31:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt,
+ output io_dmi_req_ready,
+ input io_dmi_req_valid,
+ input [6:0] io_dmi_req_bits_addr,
+ input [31:0] io_dmi_req_bits_data,
+ input [1:0] io_dmi_req_bits_op,
+ input io_dmi_resp_ready,
+ output io_dmi_resp_valid,
+ output [31:0] io_dmi_resp_bits_data,
+ output [1:0] io_dmi_resp_bits_resp
+);
+ wire [8:0] addr = {io_dmi_req_bits_addr, 2'h0}; // @[DMI.scala 94:46]
+ wire [8:0] _GEN_3 = io_dmi_req_bits_op == 2'h1 ? addr : 9'h48; // @[DMI.scala 109:{64,76} 110:76]
+ wire [2:0] _GEN_7 = io_dmi_req_bits_op == 2'h1 ? 3'h4 : 3'h0; // @[DMI.scala 109:{64,76} 110:76]
+ wire _io_dmi_resp_bits_resp_T = auto_out_d_bits_corrupt | auto_out_d_bits_denied; // @[DMI.scala 118:53]
+ assign auto_out_a_valid = io_dmi_req_valid; // @[DMI.scala 113:22 Nodes.scala 1207:84]
+ assign auto_out_a_bits_opcode = io_dmi_req_bits_op == 2'h2 ? 3'h0 : _GEN_7; // @[DMI.scala 108:{64,76}]
+ assign auto_out_a_bits_address = io_dmi_req_bits_op == 2'h2 ? addr : _GEN_3; // @[DMI.scala 108:{64,76}]
+ assign auto_out_a_bits_data = io_dmi_req_bits_op == 2'h2 ? io_dmi_req_bits_data : 32'h0; // @[DMI.scala 108:{64,76}]
+ assign auto_out_d_ready = io_dmi_resp_ready; // @[DMI.scala 117:28 Nodes.scala 1207:84]
+ assign io_dmi_req_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign io_dmi_resp_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign io_dmi_resp_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign io_dmi_resp_bits_resp = {{1'd0}, _io_dmi_resp_bits_resp_T}; // @[DMI.scala 118:28]
+endmodule
+module TLMonitor_46(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [6:0] io_in_a_bits_address,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire [6:0] _is_aligned_T = io_in_a_bits_address & 7'h3; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala 20:24]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [6:0] _T_20 = io_in_a_bits_address ^ 7'h40; // @[Parameters.scala 137:31]
+ wire [7:0] _T_21 = {1'b0,$signed(_T_20)}; // @[Parameters.scala 137:49]
+ wire [7:0] _T_23 = $signed(_T_21) & -8'shc; // @[Parameters.scala 137:52]
+ wire _T_24 = $signed(_T_23) == 8'sh0; // @[Parameters.scala 137:67]
+ wire [6:0] _T_25 = io_in_a_bits_address ^ 7'h50; // @[Parameters.scala 137:31]
+ wire [7:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49]
+ wire [7:0] _T_28 = $signed(_T_26) & -8'sh8; // @[Parameters.scala 137:52]
+ wire _T_29 = $signed(_T_28) == 8'sh0; // @[Parameters.scala 137:67]
+ wire _T_30 = _T_24 | _T_29; // @[Parameters.scala 671:42]
+ wire _T_81 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_151 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_197 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_237 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_278 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_314 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_350 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_390 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [6:0] address; // @[Monitor.scala 388:22]
+ wire _T_536 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_537 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_553 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ wire _T_560 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_561 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [15:0] _GEN_73 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_587 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire _T_590 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire _T_594 = ~inflight; // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_598 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_600 = ~_T_394; // @[Monitor.scala 671:74]
+ wire _T_601 = io_in_d_valid & d_first_1 & ~_T_394; // @[Monitor.scala 671:71]
+ wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_600 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_600 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire _T_613 = inflight | _T_587; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_618 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_619 = io_in_d_bits_opcode == _GEN_32 | _T_618; // @[Monitor.scala 685:77]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_630 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_631 = io_in_d_bits_opcode == _GEN_48 | _T_630; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire _T_635 = 4'h2 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_645 = _T_598 & a_first_1 & io_in_a_valid & _T_600; // @[Monitor.scala 694:116]
+ wire _T_647 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [3:0] a_sizes_set = _GEN_20[3:0];
+ wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_656 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [15:0] _GEN_77 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_77 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_682 = io_in_d_valid & d_first_2 & _T_394; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_394 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_700 = 4'h2 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
+ wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_81 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_81 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_81 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_81 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_81 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_81 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_81 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_81 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_30 & (io_in_a_valid & _T_151 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_151 & ~reset & ~_T_30) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_151 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_151 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_30 & (io_in_a_valid & _T_197 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_197 & ~reset & ~_T_30) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_197 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_197 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_237 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_237 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_278 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_278 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_278 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_278 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_314 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_314 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_314 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_314 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_350 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_350 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_350 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_350 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_390 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_390) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_414 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_414 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_442 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_442 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_537 & (_T_536 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_536 & ~reset & ~_T_537) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_553 & (_T_536 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_536 & ~reset & ~_T_553) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_561 & (_T_560 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_560 & _T_2 & ~_T_561) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_594 & (_T_590 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_590 & ~reset & ~_T_594) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_613 & (_T_601 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_601 & _T_2 & ~_T_613) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_619 & (_T_601 & _T_587 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_601 & _T_587 & _T_2 & ~_T_619) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_631 & (_T_601 & ~_T_587 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_601 & ~_T_587 & _T_2 & ~_T_631) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_635 & (_T_601 & ~_T_587 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_601 & ~_T_587 & _T_2 & ~_T_635) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_647 & (_T_645 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_645 & _T_2 & ~_T_647) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_656 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_656) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Debug.scala:654:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_682 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_700 & (_T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_682 & _T_2 & ~_T_700) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:654:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ address = _RAND_2[6:0];
+ _RAND_3 = {1{`RANDOM}};
+ d_first_counter = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ opcode_1 = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ inflight = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_6[3:0];
+ _RAND_7 = {1{`RANDOM}};
+ inflight_sizes = _RAND_7[3:0];
+ _RAND_8 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ watchdog = _RAND_10[31:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_11[3:0];
+ _RAND_12 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_12[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLDebugModuleOuter(
+ input clock,
+ input reset,
+ output auto_dmi_in_a_ready,
+ input auto_dmi_in_a_valid,
+ input [2:0] auto_dmi_in_a_bits_opcode,
+ input [6:0] auto_dmi_in_a_bits_address,
+ input [31:0] auto_dmi_in_a_bits_data,
+ input auto_dmi_in_d_ready,
+ output auto_dmi_in_d_valid,
+ output [2:0] auto_dmi_in_d_bits_opcode,
+ output [31:0] auto_dmi_in_d_bits_data,
+ output auto_int_out_0,
+ output io_ctrl_dmactive,
+ input io_ctrl_dmactiveAck,
+ input io_innerCtrl_ready,
+ output io_innerCtrl_valid,
+ output io_innerCtrl_bits_resumereq,
+ output [9:0] io_innerCtrl_bits_hartsel,
+ output io_innerCtrl_bits_ackhavereset,
+ output io_innerCtrl_bits_hrmask_0,
+ input io_hgDebugInt_0
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ reg DMCONTROLReg_haltreq; // @[Debug.scala 336:31]
+ reg DMCONTROLReg_ndmreset; // @[Debug.scala 336:31]
+ reg DMCONTROLReg_dmactive; // @[Debug.scala 336:31]
+ wire _T_1 = ~DMCONTROLReg_dmactive; // @[Debug.scala 354:11]
+ wire in_bits_read = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [2:0] in_bits_index = auto_dmi_in_a_bits_address[4:2]; // @[RegisterRouter.scala 71:18 73:19]
+ wire out_iindex = in_bits_index[1]; // @[RegisterRouter.scala 83:24]
+ wire [2:0] out_findex = in_bits_index & 3'h5; // @[RegisterRouter.scala 83:24]
+ wire _out_T = out_findex == 3'h0; // @[RegisterRouter.scala 83:24]
+ wire [1:0] _out_backSel_T = 2'h1 << out_iindex; // @[OneHot.scala 57:35]
+ wire out_backSel_0 = _out_backSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_6 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_0 & out_findex == 3'h0; // @[RegisterRouter.scala 83:24]
+ wire DMCONTROLWrData_ndmreset = auto_dmi_in_a_bits_data[1]; // @[RegisterRouter.scala 83:24]
+ wire DMCONTROLWrData_haltreq = auto_dmi_in_a_bits_data[31]; // @[RegisterRouter.scala 83:24]
+ wire DMCONTROLWrData_dmactive = auto_dmi_in_a_bits_data[0]; // @[RegisterRouter.scala 83:24]
+ reg hrmaskReg_0; // @[Debug.scala 471:28]
+ wire DMCONTROLWrData_clrresethaltreq = auto_dmi_in_a_bits_data[2]; // @[RegisterRouter.scala 83:24]
+ wire _T_11 = io_innerCtrl_bits_hartsel == 10'h0; // @[Debug.scala 400:35]
+ wire DMCONTROLWrData_setresethaltreq = auto_dmi_in_a_bits_data[3]; // @[RegisterRouter.scala 83:24]
+ wire _GEN_23 = out_woready_6 & DMCONTROLWrData_setresethaltreq & _T_11 | hrmaskReg_0; // @[Debug.scala 479:102 473:15 480:30]
+ wire _GEN_24 = out_woready_6 & DMCONTROLWrData_clrresethaltreq & _T_11 ? 1'h0 : _GEN_23; // @[Debug.scala 477:102 478:30]
+ wire _T_18 = DMCONTROLReg_dmactive & io_ctrl_dmactiveAck; // @[Debug.scala 487:43]
+ wire [4:0] out_prepend_7 = {1'h0,1'h0,1'h0,DMCONTROLReg_ndmreset,_T_18}; // @[Cat.scala 31:58]
+ wire [15:0] _out_T_96 = {{11'd0}, out_prepend_7}; // @[RegisterRouter.scala 83:24]
+ wire [17:0] out_prepend_9 = {1'h0,1'h0,_out_T_96}; // @[Cat.scala 31:58]
+ wire [25:0] _out_T_114 = {{8'd0}, out_prepend_9}; // @[RegisterRouter.scala 83:24]
+ wire DMCONTROLWrData_ackhavereset = auto_dmi_in_a_bits_data[28]; // @[RegisterRouter.scala 83:24]
+ wire DMCONTROLWrData_resumereq = auto_dmi_in_a_bits_data[30]; // @[RegisterRouter.scala 83:24]
+ wire [31:0] out_prepend_15 = {DMCONTROLReg_haltreq,1'h0,1'h0,1'h0,1'h0,1'h0,_out_T_114}; // @[Cat.scala 31:58]
+ wire _GEN_35 = out_iindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_37 = out_iindex ? 32'h112380 : out_prepend_15; // @[MuxLiteral.scala 48:{10,10}]
+ reg debugIntRegs_0; // @[Debug.scala 552:31]
+ reg innerCtrlValidReg; // @[Debug.scala 583:36]
+ reg innerCtrlResumeReqReg; // @[Debug.scala 584:40]
+ reg innerCtrlAckHaveResetReg; // @[Debug.scala 585:43]
+ wire _innerCtrlValidReg_T = ~io_innerCtrl_ready; // @[Debug.scala 590:54]
+ TLMonitor_46 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode)
+ );
+ assign auto_dmi_in_a_ready = auto_dmi_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign auto_dmi_in_d_valid = auto_dmi_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign auto_dmi_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign auto_dmi_in_d_bits_data = _GEN_35 ? _GEN_37 : 32'h0; // @[RegisterRouter.scala 83:24]
+ assign auto_int_out_0 = debugIntRegs_0 | io_hgDebugInt_0; // @[Debug.scala 558:60]
+ assign io_ctrl_dmactive = DMCONTROLReg_dmactive; // @[Debug.scala 605:22]
+ assign io_innerCtrl_valid = out_woready_6 | innerCtrlValidReg; // @[Debug.scala 594:54]
+ assign io_innerCtrl_bits_resumereq = out_woready_6 & DMCONTROLWrData_resumereq | innerCtrlResumeReqReg; // @[Debug.scala 596:83]
+ assign io_innerCtrl_bits_hartsel = 10'h0; // @[Debug.scala 595:42]
+ assign io_innerCtrl_bits_ackhavereset = out_woready_6 & DMCONTROLWrData_ackhavereset | innerCtrlAckHaveResetReg; // @[Debug.scala 597:89]
+ assign io_innerCtrl_bits_hrmask_0 = _T_1 ? 1'h0 : _GEN_24; // @[Debug.scala 475:44 476:30]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_dmi_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_a_valid = auto_dmi_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_dmi_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_dmi_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_dmi_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_dmi_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 354:22]
+ DMCONTROLReg_haltreq <= 1'h0; // @[Debug.scala 355:20]
+ end else if (~DMCONTROLReg_dmactive) begin // @[Debug.scala 361:47]
+ DMCONTROLReg_haltreq <= 1'h0; // @[Debug.scala 361:75]
+ end else if (out_woready_6) begin // @[Debug.scala 353:18]
+ DMCONTROLReg_haltreq <= DMCONTROLWrData_haltreq;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 354:22]
+ DMCONTROLReg_ndmreset <= 1'h0; // @[Debug.scala 355:20]
+ end else if (~DMCONTROLReg_dmactive) begin // @[Debug.scala 357:47]
+ DMCONTROLReg_ndmreset <= 1'h0; // @[Debug.scala 357:75]
+ end else if (out_woready_6) begin // @[Debug.scala 353:18]
+ DMCONTROLReg_ndmreset <= DMCONTROLWrData_ndmreset;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 365:25]
+ DMCONTROLReg_dmactive <= 1'h0; // @[Debug.scala 366:29]
+ end else if (out_woready_6) begin // @[Debug.scala 354:22]
+ DMCONTROLReg_dmactive <= DMCONTROLWrData_dmactive; // @[Debug.scala 355:20]
+ end else if (~DMCONTROLReg_dmactive) begin // @[Debug.scala 353:18]
+ DMCONTROLReg_dmactive <= 1'h0;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 475:44]
+ hrmaskReg_0 <= 1'h0; // @[Debug.scala 476:30]
+ end else if (_T_1) begin // @[Debug.scala 477:102]
+ hrmaskReg_0 <= 1'h0; // @[Debug.scala 478:30]
+ end else if (out_woready_6 & DMCONTROLWrData_clrresethaltreq & _T_11) begin
+ hrmaskReg_0 <= 1'h0;
+ end else begin
+ hrmaskReg_0 <= _GEN_23;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 568:44]
+ debugIntRegs_0 <= 1'h0; // @[Debug.scala 569:32]
+ end else if (_T_1) begin // @[Debug.scala 572:96]
+ debugIntRegs_0 <= 1'h0; // @[Debug.scala 573:34]
+ end else if (out_woready_6) begin // @[Debug.scala 554:17]
+ debugIntRegs_0 <= DMCONTROLWrData_haltreq;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 590:52]
+ innerCtrlValidReg <= 1'h0;
+ end else begin
+ innerCtrlValidReg <= io_innerCtrl_valid & ~io_innerCtrl_ready;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 591:61]
+ innerCtrlResumeReqReg <= 1'h0;
+ end else begin
+ innerCtrlResumeReqReg <= io_innerCtrl_bits_resumereq & _innerCtrlValidReg_T;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 592:64]
+ innerCtrlAckHaveResetReg <= 1'h0;
+ end else begin
+ innerCtrlAckHaveResetReg <= io_innerCtrl_bits_ackhavereset & _innerCtrlValidReg_T;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ DMCONTROLReg_haltreq = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ DMCONTROLReg_ndmreset = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ DMCONTROLReg_dmactive = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ hrmaskReg_0 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ debugIntRegs_0 = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ innerCtrlValidReg = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ innerCtrlResumeReqReg = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ innerCtrlAckHaveResetReg = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ DMCONTROLReg_haltreq = 1'h0;
+ end
+ if (reset) begin
+ DMCONTROLReg_ndmreset = 1'h0;
+ end
+ if (reset) begin
+ DMCONTROLReg_dmactive = 1'h0;
+ end
+ if (reset) begin
+ hrmaskReg_0 = 1'h0;
+ end
+ if (reset) begin
+ debugIntRegs_0 = 1'h0;
+ end
+ if (reset) begin
+ innerCtrlValidReg = 1'h0;
+ end
+ if (reset) begin
+ innerCtrlResumeReqReg = 1'h0;
+ end
+ if (reset) begin
+ innerCtrlAckHaveResetReg = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module IntSyncCrossingSource_4(
+ input auto_in_0,
+ output auto_out_sync_0
+);
+ assign auto_out_sync_0 = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_47(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [8:0] io_in_a_bits_address,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [1:0] io_in_d_bits_size,
+ input io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire [8:0] _is_aligned_T = io_in_a_bits_address & 9'h3; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala 20:24]
+ wire [9:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [9:0] _T_23 = $signed(_T_7) & -10'sh40; // @[Parameters.scala 137:52]
+ wire _T_24 = $signed(_T_23) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_25 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 137:31]
+ wire [9:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_28 = $signed(_T_26) & -10'shc; // @[Parameters.scala 137:52]
+ wire _T_29 = $signed(_T_28) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_30 = io_in_a_bits_address ^ 9'h58; // @[Parameters.scala 137:31]
+ wire [9:0] _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_33 = $signed(_T_31) & -10'sh8; // @[Parameters.scala 137:52]
+ wire _T_34 = $signed(_T_33) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_35 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 137:31]
+ wire [9:0] _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_38 = $signed(_T_36) & -10'sh20; // @[Parameters.scala 137:52]
+ wire _T_39 = $signed(_T_38) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_40 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 137:31]
+ wire [9:0] _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_43 = $signed(_T_41) & -10'sh80; // @[Parameters.scala 137:52]
+ wire _T_44 = $signed(_T_43) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_45 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 137:31]
+ wire [9:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_48 = $signed(_T_46) & -10'sh100; // @[Parameters.scala 137:52]
+ wire _T_49 = $signed(_T_48) == 10'sh0; // @[Parameters.scala 137:67]
+ wire _T_54 = _T_24 | _T_29 | _T_34 | _T_39 | _T_44 | _T_49; // @[Parameters.scala 671:42]
+ wire _T_129 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_247 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_317 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_381 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_446 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_506 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_566 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_630 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
+ wire _T_634 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_638 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
+ wire _T_642 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_646 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_650 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_654 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_665 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_669 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_682 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_702 = _T_650 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_711 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_728 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_746 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [8:0] address; // @[Monitor.scala 388:22]
+ wire _T_776 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_777 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_793 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_800 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_801 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_805 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_809 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_813 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_817 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_821 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [2:0] _GEN_71 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_72 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _GEN_75 = {{12'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_75 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_827 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire _T_830 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire _T_834 = ~inflight; // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_838 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_840 = ~_T_634; // @[Monitor.scala 671:74]
+ wire _T_841 = io_in_d_valid & d_first_1 & ~_T_634; // @[Monitor.scala 671:71]
+ wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [30:0] _GEN_1 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_opcodes_clr_T_5 = _GEN_1 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_840 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_840 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire same_cycle_resp = _T_827 & _source_ok_T_1; // @[Monitor.scala 681:88]
+ wire _T_853 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_858 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_859 = io_in_d_bits_opcode == _GEN_32 | _T_858; // @[Monitor.scala 685:77]
+ wire _T_863 = 2'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_870 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_871 = io_in_d_bits_opcode == _GEN_48 | _T_870; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_79 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_875 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_885 = _T_838 & a_first_1 & io_in_a_valid & _source_ok_T_1 & _T_840; // @[Monitor.scala 694:116]
+ wire _T_887 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [3:0] a_sizes_set = _GEN_20[3:0];
+ wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_896 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [15:0] _GEN_84 = {{12'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_84 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_922 = io_in_d_valid & d_first_2 & _T_634; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_634 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
+ wire _T_930 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_940 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
+ wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_54 & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~_T_54) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_54 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_54) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_381 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_446 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_506 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_566 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_665 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_665) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_669 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_669) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_665 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_665) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_669 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_669) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_702 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_702) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_711 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_711 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (io_in_d_valid & _T_711 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_711 & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (io_in_d_valid & _T_711 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_711 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_728 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_728 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (io_in_d_valid & _T_728 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_728 & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_702 & (io_in_d_valid & _T_728 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_728 & _T_2 & ~_T_702) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_746 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (io_in_d_valid & _T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_746 & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (io_in_d_valid & _T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_746 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_777 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_777) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_793 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_793) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_801 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_801) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_805 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_805) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_809 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_809) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_813 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_813) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_817 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_817) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_821 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_821) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_834 & (_T_830 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_830 & ~reset & ~_T_834) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_853 & (_T_841 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & _T_2 & ~_T_853) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_859 & (_T_841 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & same_cycle_resp & _T_2 & ~_T_859) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_863 & (_T_841 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & same_cycle_resp & _T_2 & ~_T_863) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_871 & (_T_841 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_871) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_875 & (_T_841 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_875) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_887 & (_T_885 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_885 & _T_2 & ~_T_887) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_896 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_896) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusBypass.scala:32:12)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_930 & (_T_922 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_922 & _T_2 & ~_T_930) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_940 & (_T_922 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_922 & _T_2 & ~_T_940) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:32:12)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ address = _RAND_2[8:0];
+ _RAND_3 = {1{`RANDOM}};
+ d_first_counter = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ opcode_1 = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ param_1 = _RAND_5[1:0];
+ _RAND_6 = {1{`RANDOM}};
+ size_1 = _RAND_6[1:0];
+ _RAND_7 = {1{`RANDOM}};
+ source_1 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ sink = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ denied = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[3:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[3:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_16[3:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_17[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBusBypassBar(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [8:0] auto_in_a_bits_address,
+ input [31:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [1:0] auto_in_d_bits_size,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [31:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_1_a_ready,
+ output auto_out_1_a_valid,
+ output [2:0] auto_out_1_a_bits_opcode,
+ output [8:0] auto_out_1_a_bits_address,
+ output [31:0] auto_out_1_a_bits_data,
+ output auto_out_1_d_ready,
+ input auto_out_1_d_valid,
+ input [2:0] auto_out_1_d_bits_opcode,
+ input [1:0] auto_out_1_d_bits_param,
+ input [1:0] auto_out_1_d_bits_size,
+ input auto_out_1_d_bits_source,
+ input auto_out_1_d_bits_sink,
+ input auto_out_1_d_bits_denied,
+ input [31:0] auto_out_1_d_bits_data,
+ input auto_out_1_d_bits_corrupt,
+ input auto_out_0_a_ready,
+ output auto_out_0_a_valid,
+ output [2:0] auto_out_0_a_bits_opcode,
+ output [127:0] auto_out_0_a_bits_address,
+ output auto_out_0_d_ready,
+ input auto_out_0_d_valid,
+ input [2:0] auto_out_0_d_bits_opcode,
+ input [1:0] auto_out_0_d_bits_size,
+ input auto_out_0_d_bits_denied,
+ input auto_out_0_d_bits_corrupt,
+ input io_bypass
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [8:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ reg in_reset; // @[BusBypass.scala 77:27]
+ reg bypass_reg; // @[BusBypass.scala 78:25]
+ wire bypass = in_reset ? io_bypass : bypass_reg; // @[BusBypass.scala 79:21]
+ reg [1:0] flight; // @[Edges.scala 294:25]
+ reg stall_counter; // @[Edges.scala 228:27]
+ wire stall_first = ~stall_counter; // @[Edges.scala 230:25]
+ wire stall = bypass != io_bypass & stall_first; // @[BusBypass.scala 84:40]
+ wire _bundleIn_0_a_ready_T = ~stall; // @[BusBypass.scala 88:21]
+ wire _bundleIn_0_a_ready_T_1 = bypass ? auto_out_0_a_ready : auto_out_1_a_ready; // @[BusBypass.scala 88:34]
+ wire in_a_ready = ~stall & _bundleIn_0_a_ready_T_1; // @[BusBypass.scala 88:28]
+ wire done = in_a_ready & auto_in_a_valid; // @[Decoupled.scala 50:35]
+ reg counter; // @[Edges.scala 228:27]
+ wire counter1 = counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~counter; // @[Edges.scala 230:25]
+ wire in_d_valid = bypass ? auto_out_0_d_valid : auto_out_1_d_valid; // @[BusBypass.scala 94:24]
+ wire done_3 = auto_in_d_ready & in_d_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] in_d_bits_opcode = bypass ? auto_out_0_d_bits_opcode : auto_out_1_d_bits_opcode; // @[BusBypass.scala 96:21]
+ reg counter_3; // @[Edges.scala 228:27]
+ wire counter1_3 = counter_3 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~counter_3; // @[Edges.scala 230:25]
+ wire d_request = in_d_bits_opcode[2] & ~in_d_bits_opcode[1]; // @[Edges.scala 70:40]
+ wire a_inc = done & a_first; // @[Edges.scala 309:28]
+ wire d_inc = done_3 & d_first & d_request; // @[Edges.scala 312:39]
+ wire [1:0] inc = {a_inc,d_inc}; // @[Cat.scala 31:58]
+ wire [1:0] dec = {1'h0,done_3}; // @[Cat.scala 31:58]
+ wire [1:0] _next_flight_T_2 = inc[0] + inc[1]; // @[Bitwise.scala 48:55]
+ wire [1:0] _next_flight_T_5 = flight + _next_flight_T_2; // @[Edges.scala 323:30]
+ wire [1:0] _next_flight_T_8 = dec[0] + dec[1]; // @[Bitwise.scala 48:55]
+ wire [1:0] next_flight = _next_flight_T_5 - _next_flight_T_8; // @[Edges.scala 323:46]
+ wire stall_counter1 = stall_counter - 1'h1; // @[Edges.scala 229:28]
+ wire _bundleOut_0_a_valid_T_1 = _bundleIn_0_a_ready_T & auto_in_a_valid; // @[BusBypass.scala 86:28]
+ wire _bundleOut_1_a_valid_T_2 = ~bypass; // @[BusBypass.scala 87:45]
+ TLMonitor_47 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = ~stall & _bundleIn_0_a_ready_T_1; // @[BusBypass.scala 88:28]
+ assign auto_in_d_valid = bypass ? auto_out_0_d_valid : auto_out_1_d_valid; // @[BusBypass.scala 94:24]
+ assign auto_in_d_bits_opcode = bypass ? auto_out_0_d_bits_opcode : auto_out_1_d_bits_opcode; // @[BusBypass.scala 96:21]
+ assign auto_in_d_bits_param = bypass ? 2'h0 : auto_out_1_d_bits_param; // @[BusBypass.scala 96:21]
+ assign auto_in_d_bits_size = bypass ? auto_out_0_d_bits_size : auto_out_1_d_bits_size; // @[BusBypass.scala 96:21]
+ assign auto_in_d_bits_sink = bypass ? 1'h0 : auto_out_1_d_bits_sink; // @[BusBypass.scala 96:21]
+ assign auto_in_d_bits_denied = bypass ? auto_out_0_d_bits_denied : auto_out_1_d_bits_denied; // @[BusBypass.scala 96:21]
+ assign auto_in_d_bits_data = bypass ? 32'h0 : auto_out_1_d_bits_data; // @[BusBypass.scala 96:21]
+ assign auto_in_d_bits_corrupt = bypass ? auto_out_0_d_bits_corrupt : auto_out_1_d_bits_corrupt; // @[BusBypass.scala 96:21]
+ assign auto_out_1_a_valid = _bundleOut_0_a_valid_T_1 & ~bypass; // @[BusBypass.scala 87:42]
+ assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_d_ready = auto_in_d_ready & _bundleOut_1_a_valid_T_2; // @[BusBypass.scala 93:32]
+ assign auto_out_0_a_valid = _bundleIn_0_a_ready_T & auto_in_a_valid & bypass; // @[BusBypass.scala 86:42]
+ assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_a_bits_address = {{119'd0}, auto_in_a_bits_address}; // @[Nodes.scala 1207:84 BusBypass.scala 89:18]
+ assign auto_out_0_d_ready = auto_in_d_ready & bypass; // @[BusBypass.scala 92:32]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = ~stall & _bundleIn_0_a_ready_T_1; // @[BusBypass.scala 88:28]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bypass ? auto_out_0_d_valid : auto_out_1_d_valid; // @[BusBypass.scala 94:24]
+ assign monitor_io_in_d_bits_opcode = bypass ? auto_out_0_d_bits_opcode : auto_out_1_d_bits_opcode; // @[BusBypass.scala 96:21]
+ assign monitor_io_in_d_bits_param = bypass ? 2'h0 : auto_out_1_d_bits_param; // @[BusBypass.scala 96:21]
+ assign monitor_io_in_d_bits_size = bypass ? auto_out_0_d_bits_size : auto_out_1_d_bits_size; // @[BusBypass.scala 96:21]
+ assign monitor_io_in_d_bits_source = bypass ? 1'h0 : auto_out_1_d_bits_source; // @[BusBypass.scala 96:21]
+ assign monitor_io_in_d_bits_sink = bypass ? 1'h0 : auto_out_1_d_bits_sink; // @[BusBypass.scala 96:21]
+ assign monitor_io_in_d_bits_denied = bypass ? auto_out_0_d_bits_denied : auto_out_1_d_bits_denied; // @[BusBypass.scala 96:21]
+ assign monitor_io_in_d_bits_corrupt = bypass ? auto_out_0_d_bits_corrupt : auto_out_1_d_bits_corrupt; // @[BusBypass.scala 96:21]
+ always @(posedge clock) begin
+ in_reset <= reset; // @[BusBypass.scala 77:{27,27,27}]
+ if (in_reset | next_flight == 2'h0) begin // @[BusBypass.scala 83:50]
+ bypass_reg <= io_bypass; // @[BusBypass.scala 83:63]
+ end
+ if (reset) begin // @[Edges.scala 294:25]
+ flight <= 2'h0; // @[Edges.scala 294:25]
+ end else begin
+ flight <= next_flight; // @[Edges.scala 324:12]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ stall_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (done) begin // @[Edges.scala 234:17]
+ if (stall_first) begin // @[Edges.scala 235:21]
+ stall_counter <= 1'h0;
+ end else begin
+ stall_counter <= stall_counter1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ counter <= 1'h0;
+ end else begin
+ counter <= counter1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ counter_3 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (done_3) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ counter_3 <= 1'h0;
+ end else begin
+ counter_3 <= counter1_3;
+ end
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ in_reset = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ bypass_reg = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ flight = _RAND_2[1:0];
+ _RAND_3 = {1{`RANDOM}};
+ stall_counter = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ counter = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ counter_3 = _RAND_5[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_48(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [127:0] io_in_a_bits_address,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [127:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire [127:0] _is_aligned_T = io_in_a_bits_address & 128'h3; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala 20:24]
+ wire [128:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [128:0] _T_26 = $signed(_T_7) & 129'sh100000000000000000000000000000000; // @[Parameters.scala 137:52]
+ wire _T_27 = $signed(_T_26) == 129'sh0; // @[Parameters.scala 137:67]
+ wire _T_72 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_133 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_173 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_207 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_242 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_272 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_302 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_339 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _T_343 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_347 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
+ wire _T_355 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_359 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_363 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_391 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_411 = _T_359 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_420 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_437 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_455 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [127:0] address; // @[Monitor.scala 388:22]
+ wire _T_485 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_486 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_502 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_509 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_510 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_518 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_530 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [15:0] _GEN_73 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_536 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire _T_539 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire _T_543 = ~inflight; // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_547 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_549 = ~_T_343; // @[Monitor.scala 671:74]
+ wire _T_550 = io_in_d_valid & d_first_1 & ~_T_343; // @[Monitor.scala 671:71]
+ wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_549 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_549 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire _T_562 = inflight | _T_536; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_567 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_568 = io_in_d_bits_opcode == _GEN_32 | _T_567; // @[Monitor.scala 685:77]
+ wire _T_572 = 2'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_579 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_580 = io_in_d_bits_opcode == _GEN_48 | _T_579; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_75 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_584 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_594 = _T_547 & a_first_1 & io_in_a_valid & _T_549; // @[Monitor.scala 694:116]
+ wire _T_596 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [3:0] a_sizes_set = _GEN_20[3:0];
+ wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_605 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [15:0] _GEN_78 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_78 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_631 = io_in_d_valid & d_first_2 & _T_343; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_343 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_649 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
+ wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_72 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_72 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_72 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_72 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_72 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_72 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_72 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_72 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_27 & (io_in_a_valid & _T_133 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_133 & ~reset & ~_T_27) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_133 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_133 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_27 & (io_in_a_valid & _T_173 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_173 & ~reset & ~_T_27) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_173 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_173 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_207 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_207 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_207 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_207 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_242 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_242 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_242 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_242 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_272 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_272 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_272 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_272 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_302 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_302 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_302 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_302 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_339 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_339) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_d_valid & _T_343 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_343 & _T_2 & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_355 & (io_in_d_valid & _T_343 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_343 & _T_2 & ~_T_355) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_359 & (io_in_d_valid & _T_343 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_343 & _T_2 & ~_T_359) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_d_valid & _T_363 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_363 & _T_2 & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_355 & (io_in_d_valid & _T_363 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_363 & _T_2 & ~_T_355) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_d_valid & _T_391 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_391 & _T_2 & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_411 & (io_in_d_valid & _T_391 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_391 & _T_2 & ~_T_411) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_355 & (io_in_d_valid & _T_420 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_420 & _T_2 & ~_T_355) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_411 & (io_in_d_valid & _T_437 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_437 & _T_2 & ~_T_411) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_355 & (io_in_d_valid & _T_455 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_455 & _T_2 & ~_T_355) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_486 & (_T_485 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_485 & ~reset & ~_T_486) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_502 & (_T_485 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_485 & ~reset & ~_T_502) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_510 & (_T_509 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_509 & _T_2 & ~_T_510) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_518 & (_T_509 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_509 & _T_2 & ~_T_518) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_530 & (_T_509 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_509 & _T_2 & ~_T_530) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_543 & (_T_539 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_539 & ~reset & ~_T_543) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_562 & (_T_550 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_550 & _T_2 & ~_T_562) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_550 & _T_536 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_550 & _T_536 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_550 & _T_536 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_550 & _T_536 & _T_2 & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_550 & ~_T_536 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_550 & ~_T_536 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_584 & (_T_550 & ~_T_536 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_550 & ~_T_536 & _T_2 & ~_T_584) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_596 & (_T_594 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_594 & _T_2 & ~_T_596) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_605 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_605) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BusBypass.scala:33:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_631 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_631 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_649 & (_T_631 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_631 & _T_2 & ~_T_649) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:33:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {4{`RANDOM}};
+ address = _RAND_2[127:0];
+ _RAND_3 = {1{`RANDOM}};
+ d_first_counter = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ opcode_1 = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ size_1 = _RAND_5[1:0];
+ _RAND_6 = {1{`RANDOM}};
+ denied = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ inflight = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_8[3:0];
+ _RAND_9 = {1{`RANDOM}};
+ inflight_sizes = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ watchdog = _RAND_12[31:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_13[3:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_14[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLError_1(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [127:0] auto_in_a_bits_address,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_size,
+ output auto_in_d_bits_denied,
+ output auto_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [127:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ reg idle; // @[Error.scala 44:23]
+ reg beatsLeft; // @[Arbiter.scala 87:30]
+ wire idle_1 = ~beatsLeft; // @[Arbiter.scala 88:28]
+ wire da_valid = auto_in_a_valid & idle; // @[Error.scala 51:35]
+ wire [1:0] _readys_T = {da_valid,1'h0}; // @[Cat.scala 31:58]
+ wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala 244:48]
+ wire [1:0] _readys_T_3 = _readys_T | _readys_T_1[1:0]; // @[package.scala 244:43]
+ wire [2:0] _readys_T_5 = {_readys_T_3, 1'h0}; // @[Arbiter.scala 16:78]
+ wire [1:0] _readys_T_7 = ~_readys_T_5[1:0]; // @[Arbiter.scala 16:61]
+ wire readys_1 = _readys_T_7[1]; // @[Arbiter.scala 95:86]
+ reg state_1; // @[Arbiter.scala 116:26]
+ wire allowed_1 = idle_1 ? readys_1 : state_1; // @[Arbiter.scala 121:24]
+ wire out_1_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
+ reg counter; // @[Edges.scala 228:27]
+ wire [2:0] _GEN_4 = 3'h2 == auto_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Error.scala 53:{21,21}]
+ wire [2:0] _GEN_5 = 3'h3 == auto_in_a_bits_opcode ? 3'h1 : _GEN_4; // @[Error.scala 53:{21,21}]
+ wire [2:0] _GEN_6 = 3'h4 == auto_in_a_bits_opcode ? 3'h1 : _GEN_5; // @[Error.scala 53:{21,21}]
+ wire [2:0] _GEN_7 = 3'h5 == auto_in_a_bits_opcode ? 3'h2 : _GEN_6; // @[Error.scala 53:{21,21}]
+ wire [2:0] _GEN_8 = 3'h6 == auto_in_a_bits_opcode ? 3'h4 : _GEN_7; // @[Error.scala 53:{21,21}]
+ wire [2:0] da_bits_opcode = 3'h7 == auto_in_a_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 53:{21,21}]
+ wire beats1_opdata = da_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire done = out_1_ready & da_valid; // @[Decoupled.scala 50:35]
+ wire counter1 = counter - 1'h1; // @[Edges.scala 229:28]
+ wire da_first = ~counter; // @[Edges.scala 230:25]
+ wire _T_3 = ~reset; // @[Error.scala 49:12]
+ wire _GEN_12 = done & da_bits_opcode == 3'h4 ? 1'h0 : idle; // @[Error.scala 44:23 70:{52,59}]
+ wire latch = idle_1 & auto_in_d_ready; // @[Arbiter.scala 89:24]
+ wire earlyWinner_1 = readys_1 & da_valid; // @[Arbiter.scala 97:79]
+ wire _T_22 = ~da_valid; // @[Arbiter.scala 107:15]
+ wire muxStateEarly_1 = idle_1 ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ wire _sink_ACancel_earlyValid_T_2 = state_1 & da_valid; // @[Mux.scala 27:73]
+ wire sink_ACancel_earlyValid = idle_1 ? da_valid : _sink_ACancel_earlyValid_T_2; // @[Arbiter.scala 125:29]
+ wire _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_earlyValid; // @[ReadyValidCancel.scala 49:33]
+ TLMonitor_48 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ assign auto_in_a_ready = out_1_ready & idle; // @[Error.scala 50:37]
+ assign auto_in_d_valid = idle_1 ? da_valid : _sink_ACancel_earlyValid_T_2; // @[Arbiter.scala 125:29]
+ assign auto_in_d_bits_opcode = muxStateEarly_1 ? da_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_size = muxStateEarly_1 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
+ assign auto_in_d_bits_denied = idle_1 ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ assign auto_in_d_bits_corrupt = muxStateEarly_1 & beats1_opdata; // @[Mux.scala 27:73]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = out_1_ready & idle; // @[Error.scala 50:37]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = idle_1 ? da_valid : _sink_ACancel_earlyValid_T_2; // @[Arbiter.scala 125:29]
+ assign monitor_io_in_d_bits_opcode = muxStateEarly_1 ? da_bits_opcode : 3'h0; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_size = muxStateEarly_1 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
+ assign monitor_io_in_d_bits_denied = idle_1 ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
+ assign monitor_io_in_d_bits_corrupt = muxStateEarly_1 & beats1_opdata; // @[Mux.scala 27:73]
+ always @(posedge clock) begin
+ idle <= reset | _GEN_12; // @[Error.scala 44:{23,23}]
+ if (reset) begin // @[Arbiter.scala 87:30]
+ beatsLeft <= 1'h0; // @[Arbiter.scala 87:30]
+ end else if (latch) begin // @[Arbiter.scala 113:23]
+ beatsLeft <= 1'h0;
+ end else begin
+ beatsLeft <= beatsLeft - _beatsLeft_T_2;
+ end
+ if (reset) begin // @[Arbiter.scala 116:26]
+ state_1 <= 1'h0; // @[Arbiter.scala 116:26]
+ end else if (idle_1) begin // @[Arbiter.scala 117:30]
+ state_1 <= earlyWinner_1;
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (done) begin // @[Edges.scala 234:17]
+ if (da_first) begin // @[Edges.scala 235:21]
+ counter <= 1'h0;
+ end else begin
+ counter <= counter1;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(idle | da_first) & ~reset) begin
+ $fatal; // @[Error.scala 49:12]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~(idle | da_first)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Error.scala:49 assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below\n"
+ ); // @[Error.scala 49:12]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~da_valid | earlyWinner_1) & _T_3) begin
+ $fatal; // @[Arbiter.scala 107:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_3 & ~(~da_valid | earlyWinner_1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
+ ); // @[Arbiter.scala 107:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_22 | da_valid) & _T_3) begin
+ $fatal; // @[Arbiter.scala 108:14]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_3 & ~(_T_22 | da_valid)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
+ ); // @[Arbiter.scala 108:14]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ idle = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ beatsLeft = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ state_1 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ counter = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBusBypass(
+ input clock,
+ input reset,
+ input auto_node_out_out_a_ready,
+ output auto_node_out_out_a_valid,
+ output [2:0] auto_node_out_out_a_bits_opcode,
+ output [8:0] auto_node_out_out_a_bits_address,
+ output [31:0] auto_node_out_out_a_bits_data,
+ output auto_node_out_out_d_ready,
+ input auto_node_out_out_d_valid,
+ input [2:0] auto_node_out_out_d_bits_opcode,
+ input [1:0] auto_node_out_out_d_bits_param,
+ input [1:0] auto_node_out_out_d_bits_size,
+ input auto_node_out_out_d_bits_source,
+ input auto_node_out_out_d_bits_sink,
+ input auto_node_out_out_d_bits_denied,
+ input [31:0] auto_node_out_out_d_bits_data,
+ input auto_node_out_out_d_bits_corrupt,
+ output auto_node_in_in_a_ready,
+ input auto_node_in_in_a_valid,
+ input [2:0] auto_node_in_in_a_bits_opcode,
+ input [8:0] auto_node_in_in_a_bits_address,
+ input [31:0] auto_node_in_in_a_bits_data,
+ input auto_node_in_in_d_ready,
+ output auto_node_in_in_d_valid,
+ output [2:0] auto_node_in_in_d_bits_opcode,
+ output [1:0] auto_node_in_in_d_bits_param,
+ output [1:0] auto_node_in_in_d_bits_size,
+ output auto_node_in_in_d_bits_sink,
+ output auto_node_in_in_d_bits_denied,
+ output [31:0] auto_node_in_in_d_bits_data,
+ output auto_node_in_in_d_bits_corrupt,
+ input io_bypass
+);
+ wire bar_clock; // @[BusBypass.scala 17:33]
+ wire bar_reset; // @[BusBypass.scala 17:33]
+ wire bar_auto_in_a_ready; // @[BusBypass.scala 17:33]
+ wire bar_auto_in_a_valid; // @[BusBypass.scala 17:33]
+ wire [2:0] bar_auto_in_a_bits_opcode; // @[BusBypass.scala 17:33]
+ wire [8:0] bar_auto_in_a_bits_address; // @[BusBypass.scala 17:33]
+ wire [31:0] bar_auto_in_a_bits_data; // @[BusBypass.scala 17:33]
+ wire bar_auto_in_d_ready; // @[BusBypass.scala 17:33]
+ wire bar_auto_in_d_valid; // @[BusBypass.scala 17:33]
+ wire [2:0] bar_auto_in_d_bits_opcode; // @[BusBypass.scala 17:33]
+ wire [1:0] bar_auto_in_d_bits_param; // @[BusBypass.scala 17:33]
+ wire [1:0] bar_auto_in_d_bits_size; // @[BusBypass.scala 17:33]
+ wire bar_auto_in_d_bits_sink; // @[BusBypass.scala 17:33]
+ wire bar_auto_in_d_bits_denied; // @[BusBypass.scala 17:33]
+ wire [31:0] bar_auto_in_d_bits_data; // @[BusBypass.scala 17:33]
+ wire bar_auto_in_d_bits_corrupt; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_1_a_ready; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_1_a_valid; // @[BusBypass.scala 17:33]
+ wire [2:0] bar_auto_out_1_a_bits_opcode; // @[BusBypass.scala 17:33]
+ wire [8:0] bar_auto_out_1_a_bits_address; // @[BusBypass.scala 17:33]
+ wire [31:0] bar_auto_out_1_a_bits_data; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_1_d_ready; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_1_d_valid; // @[BusBypass.scala 17:33]
+ wire [2:0] bar_auto_out_1_d_bits_opcode; // @[BusBypass.scala 17:33]
+ wire [1:0] bar_auto_out_1_d_bits_param; // @[BusBypass.scala 17:33]
+ wire [1:0] bar_auto_out_1_d_bits_size; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_1_d_bits_source; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_1_d_bits_sink; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_1_d_bits_denied; // @[BusBypass.scala 17:33]
+ wire [31:0] bar_auto_out_1_d_bits_data; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_1_d_bits_corrupt; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_0_a_ready; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_0_a_valid; // @[BusBypass.scala 17:33]
+ wire [2:0] bar_auto_out_0_a_bits_opcode; // @[BusBypass.scala 17:33]
+ wire [127:0] bar_auto_out_0_a_bits_address; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_0_d_ready; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_0_d_valid; // @[BusBypass.scala 17:33]
+ wire [2:0] bar_auto_out_0_d_bits_opcode; // @[BusBypass.scala 17:33]
+ wire [1:0] bar_auto_out_0_d_bits_size; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_0_d_bits_denied; // @[BusBypass.scala 17:33]
+ wire bar_auto_out_0_d_bits_corrupt; // @[BusBypass.scala 17:33]
+ wire bar_io_bypass; // @[BusBypass.scala 17:33]
+ wire error_clock; // @[BusBypass.scala 27:40]
+ wire error_reset; // @[BusBypass.scala 27:40]
+ wire error_auto_in_a_ready; // @[BusBypass.scala 27:40]
+ wire error_auto_in_a_valid; // @[BusBypass.scala 27:40]
+ wire [2:0] error_auto_in_a_bits_opcode; // @[BusBypass.scala 27:40]
+ wire [127:0] error_auto_in_a_bits_address; // @[BusBypass.scala 27:40]
+ wire error_auto_in_d_ready; // @[BusBypass.scala 27:40]
+ wire error_auto_in_d_valid; // @[BusBypass.scala 27:40]
+ wire [2:0] error_auto_in_d_bits_opcode; // @[BusBypass.scala 27:40]
+ wire [1:0] error_auto_in_d_bits_size; // @[BusBypass.scala 27:40]
+ wire error_auto_in_d_bits_denied; // @[BusBypass.scala 27:40]
+ wire error_auto_in_d_bits_corrupt; // @[BusBypass.scala 27:40]
+ TLBusBypassBar bar ( // @[BusBypass.scala 17:33]
+ .clock(bar_clock),
+ .reset(bar_reset),
+ .auto_in_a_ready(bar_auto_in_a_ready),
+ .auto_in_a_valid(bar_auto_in_a_valid),
+ .auto_in_a_bits_opcode(bar_auto_in_a_bits_opcode),
+ .auto_in_a_bits_address(bar_auto_in_a_bits_address),
+ .auto_in_a_bits_data(bar_auto_in_a_bits_data),
+ .auto_in_d_ready(bar_auto_in_d_ready),
+ .auto_in_d_valid(bar_auto_in_d_valid),
+ .auto_in_d_bits_opcode(bar_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(bar_auto_in_d_bits_param),
+ .auto_in_d_bits_size(bar_auto_in_d_bits_size),
+ .auto_in_d_bits_sink(bar_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(bar_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(bar_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(bar_auto_in_d_bits_corrupt),
+ .auto_out_1_a_ready(bar_auto_out_1_a_ready),
+ .auto_out_1_a_valid(bar_auto_out_1_a_valid),
+ .auto_out_1_a_bits_opcode(bar_auto_out_1_a_bits_opcode),
+ .auto_out_1_a_bits_address(bar_auto_out_1_a_bits_address),
+ .auto_out_1_a_bits_data(bar_auto_out_1_a_bits_data),
+ .auto_out_1_d_ready(bar_auto_out_1_d_ready),
+ .auto_out_1_d_valid(bar_auto_out_1_d_valid),
+ .auto_out_1_d_bits_opcode(bar_auto_out_1_d_bits_opcode),
+ .auto_out_1_d_bits_param(bar_auto_out_1_d_bits_param),
+ .auto_out_1_d_bits_size(bar_auto_out_1_d_bits_size),
+ .auto_out_1_d_bits_source(bar_auto_out_1_d_bits_source),
+ .auto_out_1_d_bits_sink(bar_auto_out_1_d_bits_sink),
+ .auto_out_1_d_bits_denied(bar_auto_out_1_d_bits_denied),
+ .auto_out_1_d_bits_data(bar_auto_out_1_d_bits_data),
+ .auto_out_1_d_bits_corrupt(bar_auto_out_1_d_bits_corrupt),
+ .auto_out_0_a_ready(bar_auto_out_0_a_ready),
+ .auto_out_0_a_valid(bar_auto_out_0_a_valid),
+ .auto_out_0_a_bits_opcode(bar_auto_out_0_a_bits_opcode),
+ .auto_out_0_a_bits_address(bar_auto_out_0_a_bits_address),
+ .auto_out_0_d_ready(bar_auto_out_0_d_ready),
+ .auto_out_0_d_valid(bar_auto_out_0_d_valid),
+ .auto_out_0_d_bits_opcode(bar_auto_out_0_d_bits_opcode),
+ .auto_out_0_d_bits_size(bar_auto_out_0_d_bits_size),
+ .auto_out_0_d_bits_denied(bar_auto_out_0_d_bits_denied),
+ .auto_out_0_d_bits_corrupt(bar_auto_out_0_d_bits_corrupt),
+ .io_bypass(bar_io_bypass)
+ );
+ TLError_1 error ( // @[BusBypass.scala 27:40]
+ .clock(error_clock),
+ .reset(error_reset),
+ .auto_in_a_ready(error_auto_in_a_ready),
+ .auto_in_a_valid(error_auto_in_a_valid),
+ .auto_in_a_bits_opcode(error_auto_in_a_bits_opcode),
+ .auto_in_a_bits_address(error_auto_in_a_bits_address),
+ .auto_in_d_ready(error_auto_in_d_ready),
+ .auto_in_d_valid(error_auto_in_d_valid),
+ .auto_in_d_bits_opcode(error_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(error_auto_in_d_bits_size),
+ .auto_in_d_bits_denied(error_auto_in_d_bits_denied),
+ .auto_in_d_bits_corrupt(error_auto_in_d_bits_corrupt)
+ );
+ assign auto_node_out_out_a_valid = bar_auto_out_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_node_out_out_a_bits_opcode = bar_auto_out_1_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_node_out_out_a_bits_address = bar_auto_out_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_node_out_out_a_bits_data = bar_auto_out_1_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_node_out_out_d_ready = bar_auto_out_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_node_in_in_a_ready = bar_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_node_in_in_d_valid = bar_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_node_in_in_d_bits_opcode = bar_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_node_in_in_d_bits_param = bar_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_node_in_in_d_bits_size = bar_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_node_in_in_d_bits_sink = bar_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_node_in_in_d_bits_denied = bar_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_node_in_in_d_bits_data = bar_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_node_in_in_d_bits_corrupt = bar_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign bar_clock = clock;
+ assign bar_reset = reset;
+ assign bar_auto_in_a_valid = auto_node_in_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bar_auto_in_a_bits_opcode = auto_node_in_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bar_auto_in_a_bits_address = auto_node_in_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bar_auto_in_a_bits_data = auto_node_in_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bar_auto_in_d_ready = auto_node_in_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bar_auto_out_1_a_ready = auto_node_out_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_valid = auto_node_out_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_bits_opcode = auto_node_out_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_bits_param = auto_node_out_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_bits_size = auto_node_out_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_bits_source = auto_node_out_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_bits_sink = auto_node_out_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_bits_denied = auto_node_out_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_bits_data = auto_node_out_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_1_d_bits_corrupt = auto_node_out_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bar_auto_out_0_a_ready = error_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign bar_auto_out_0_d_valid = error_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign bar_auto_out_0_d_bits_opcode = error_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign bar_auto_out_0_d_bits_size = error_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign bar_auto_out_0_d_bits_denied = error_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign bar_auto_out_0_d_bits_corrupt = error_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign bar_io_bypass = io_bypass; // @[BusBypass.scala 44:26]
+ assign error_clock = clock;
+ assign error_reset = reset;
+ assign error_auto_in_a_valid = bar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
+ assign error_auto_in_a_bits_opcode = bar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign error_auto_in_a_bits_address = bar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
+ assign error_auto_in_d_ready = bar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
+endmodule
+module TLMonitor_49(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [8:0] io_in_a_bits_address,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [1:0] io_in_d_bits_size,
+ input io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire [8:0] _is_aligned_T = io_in_a_bits_address & 9'h3; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala 20:24]
+ wire [9:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [9:0] _T_23 = $signed(_T_7) & -10'sh40; // @[Parameters.scala 137:52]
+ wire _T_24 = $signed(_T_23) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_25 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 137:31]
+ wire [9:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_28 = $signed(_T_26) & -10'shc; // @[Parameters.scala 137:52]
+ wire _T_29 = $signed(_T_28) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_30 = io_in_a_bits_address ^ 9'h58; // @[Parameters.scala 137:31]
+ wire [9:0] _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_33 = $signed(_T_31) & -10'sh8; // @[Parameters.scala 137:52]
+ wire _T_34 = $signed(_T_33) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_35 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 137:31]
+ wire [9:0] _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_38 = $signed(_T_36) & -10'sh20; // @[Parameters.scala 137:52]
+ wire _T_39 = $signed(_T_38) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_40 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 137:31]
+ wire [9:0] _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_43 = $signed(_T_41) & -10'sh80; // @[Parameters.scala 137:52]
+ wire _T_44 = $signed(_T_43) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_45 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 137:31]
+ wire [9:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_48 = $signed(_T_46) & -10'sh100; // @[Parameters.scala 137:52]
+ wire _T_49 = $signed(_T_48) == 10'sh0; // @[Parameters.scala 137:67]
+ wire _T_54 = _T_24 | _T_29 | _T_34 | _T_39 | _T_44 | _T_49; // @[Parameters.scala 671:42]
+ wire _T_129 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_247 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_317 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_381 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_446 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_506 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_566 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_630 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
+ wire _T_634 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_638 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
+ wire _T_642 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_646 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_650 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_654 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_665 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_669 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_682 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_702 = _T_650 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_711 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_728 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_746 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [8:0] address; // @[Monitor.scala 388:22]
+ wire _T_776 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_777 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_793 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_800 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_801 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_805 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_809 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_813 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_817 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_821 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [2:0] _GEN_71 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_72 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _GEN_75 = {{12'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_75 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_827 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_830 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire _T_834 = ~inflight; // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_838 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_840 = ~_T_634; // @[Monitor.scala 671:74]
+ wire _T_841 = io_in_d_valid & d_first_1 & ~_T_634; // @[Monitor.scala 671:71]
+ wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_634 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
+ wire [30:0] _GEN_1 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_opcodes_clr_T_5 = _GEN_1 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_840 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_840 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire same_cycle_resp = _T_827 & _source_ok_T_1; // @[Monitor.scala 681:88]
+ wire _T_853 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_858 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_859 = io_in_d_bits_opcode == _GEN_32 | _T_858; // @[Monitor.scala 685:77]
+ wire _T_863 = 2'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_870 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_871 = io_in_d_bits_opcode == _GEN_48 | _T_870; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_79 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_875 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_885 = _T_838 & a_first_1 & io_in_a_valid & _source_ok_T_1 & _T_840; // @[Monitor.scala 694:116]
+ wire _T_887 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set_wo_ready = _GEN_15[0];
+ wire d_clr_wo_ready = _GEN_21[0];
+ wire _T_894 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [3:0] a_sizes_set = _GEN_20[3:0];
+ wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_903 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [15:0] _GEN_84 = {{12'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_84 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_929 = io_in_d_valid & d_first_2 & _T_634; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_634 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
+ wire _T_937 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_947 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
+ wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_54 & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~_T_54) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_54 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_54) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_381 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_446 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_506 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_566 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_665 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_665) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_669 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_669) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_665 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_665) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_669 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_669) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_702 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_702) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_711 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_711 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (io_in_d_valid & _T_711 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_711 & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (io_in_d_valid & _T_711 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_711 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_d_valid & _T_711 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_711 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_728 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_728 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (io_in_d_valid & _T_728 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_728 & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_702 & (io_in_d_valid & _T_728 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_728 & _T_2 & ~_T_702) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_d_valid & _T_728 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_728 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_746 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (io_in_d_valid & _T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_746 & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (io_in_d_valid & _T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_746 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (io_in_d_valid & _T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_746 & _T_2 & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_777 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_777) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_793 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_793) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_801 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_801) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_805 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_805) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_809 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_809) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_813 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_813) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_817 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_817) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_821 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_821) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_834 & (_T_830 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_830 & ~reset & ~_T_834) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_853 & (_T_841 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & _T_2 & ~_T_853) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_859 & (_T_841 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & same_cycle_resp & _T_2 & ~_T_859) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_863 & (_T_841 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & same_cycle_resp & _T_2 & ~_T_863) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_871 & (_T_841 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_871) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_875 & (_T_841 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_875) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_887 & (_T_885 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_885 & _T_2 & ~_T_887) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_894 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_894) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_903 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_903) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Debug.scala:653:46)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_937 & (_T_929 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_929 & _T_2 & ~_T_937) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_947 & (_T_929 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_929 & _T_2 & ~_T_947) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:653:46)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ address = _RAND_2[8:0];
+ _RAND_3 = {1{`RANDOM}};
+ d_first_counter = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ opcode_1 = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ param_1 = _RAND_5[1:0];
+ _RAND_6 = {1{`RANDOM}};
+ size_1 = _RAND_6[1:0];
+ _RAND_7 = {1{`RANDOM}};
+ source_1 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ sink = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ denied = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[3:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[3:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_16[3:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_17[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0(
+ input clock,
+ input reset,
+ input io_d,
+ output io_q
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+`endif // RANDOMIZE_REG_INIT
+ reg sync_0; // @[SynchronizerReg.scala 51:87]
+ reg sync_1; // @[SynchronizerReg.scala 51:87]
+ reg sync_2; // @[SynchronizerReg.scala 51:87]
+ assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[SynchronizerReg.scala 51:87]
+ sync_0 <= 1'h0; // @[SynchronizerReg.scala 51:87]
+ end else begin
+ sync_0 <= sync_1; // @[SynchronizerReg.scala 57:10]
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[SynchronizerReg.scala 51:87]
+ sync_1 <= 1'h0; // @[SynchronizerReg.scala 51:87]
+ end else begin
+ sync_1 <= sync_2; // @[SynchronizerReg.scala 57:10]
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[SynchronizerReg.scala 54:22]
+ sync_2 <= 1'h0;
+ end else begin
+ sync_2 <= io_d;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ sync_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ sync_1 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ sync_2 = _RAND_2[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ sync_0 = 1'h0;
+ end
+ if (reset) begin
+ sync_1 = 1'h0;
+ end
+ if (reset) begin
+ sync_2 = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module AsyncResetSynchronizerShiftReg_w1_d3_i0(
+ input clock,
+ input reset,
+ input io_d,
+ output io_q
+);
+ wire output_chain_clock; // @[ShiftReg.scala 45:23]
+ wire output_chain_reset; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_d; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_q; // @[ShiftReg.scala 45:23]
+ AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
+ .clock(output_chain_clock),
+ .reset(output_chain_reset),
+ .io_d(output_chain_io_d),
+ .io_q(output_chain_io_q)
+ );
+ assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
+ assign output_chain_clock = clock;
+ assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
+ assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
+endmodule
+module AsyncResetSynchronizerShiftReg_w1_d3_i0_1(
+ input clock,
+ input reset,
+ input io_d,
+ output io_q
+);
+ wire output_chain_clock; // @[ShiftReg.scala 45:23]
+ wire output_chain_reset; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_d; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_q; // @[ShiftReg.scala 45:23]
+ AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
+ .clock(output_chain_clock),
+ .reset(output_chain_reset),
+ .io_d(output_chain_io_d),
+ .io_q(output_chain_io_q)
+ );
+ assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
+ assign output_chain_clock = clock;
+ assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
+ assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
+endmodule
+module AsyncValidSync(
+ input io_in,
+ output io_out,
+ input clock,
+ input reset
+);
+ wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
+ wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
+ wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
+ wire io_out_source_valid_0_io_q; // @[ShiftReg.scala 45:23]
+ AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 ( // @[ShiftReg.scala 45:23]
+ .clock(io_out_source_valid_0_clock),
+ .reset(io_out_source_valid_0_reset),
+ .io_d(io_out_source_valid_0_io_d),
+ .io_q(io_out_source_valid_0_io_q)
+ );
+ assign io_out = io_out_source_valid_0_io_q; // @[ShiftReg.scala 48:{24,24}]
+ assign io_out_source_valid_0_clock = clock;
+ assign io_out_source_valid_0_reset = reset;
+ assign io_out_source_valid_0_io_d = io_in; // @[ShiftReg.scala 47:16]
+endmodule
+module AsyncQueueSource(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [8:0] io_enq_bits_address,
+ input [31:0] io_enq_bits_data,
+ output [2:0] io_async_mem_0_opcode,
+ output [8:0] io_async_mem_0_address,
+ output [31:0] io_async_mem_0_data,
+ input io_async_ridx,
+ output io_async_widx,
+ input io_async_safe_ridx_valid,
+ output io_async_safe_widx_valid,
+ output io_async_safe_source_reset_n,
+ input io_async_safe_sink_reset_n
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+`endif // RANDOMIZE_REG_INIT
+ wire ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
+ wire source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_clock; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_reset; // @[AsyncQueue.scala 100:32]
+ wire source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_clock; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_reset; // @[AsyncQueue.scala 101:32]
+ wire sink_extend_io_in; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_io_out; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_clock; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_reset; // @[AsyncQueue.scala 103:30]
+ wire sink_valid_io_in; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_io_out; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_clock; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_reset; // @[AsyncQueue.scala 104:30]
+ reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 80:16]
+ reg [8:0] mem_0_address; // @[AsyncQueue.scala 80:16]
+ reg [31:0] mem_0_data; // @[AsyncQueue.scala 80:16]
+ wire _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire sink_ready = sink_valid_io_out;
+ wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
+ reg widx_widx_bin; // @[AsyncQueue.scala 52:25]
+ wire widx_incremented = _widx_T_2 ? 1'h0 : widx_widx_bin + _widx_T_1; // @[AsyncQueue.scala 53:23]
+ wire ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
+ reg ready_reg; // @[AsyncQueue.scala 88:56]
+ reg widx_gray; // @[AsyncQueue.scala 91:55]
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
+ .clock(ridx_ridx_gray_clock),
+ .reset(ridx_ridx_gray_reset),
+ .io_d(ridx_ridx_gray_io_d),
+ .io_q(ridx_ridx_gray_io_q)
+ );
+ AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
+ .io_in(source_valid_0_io_in),
+ .io_out(source_valid_0_io_out),
+ .clock(source_valid_0_clock),
+ .reset(source_valid_0_reset)
+ );
+ AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
+ .io_in(source_valid_1_io_in),
+ .io_out(source_valid_1_io_out),
+ .clock(source_valid_1_clock),
+ .reset(source_valid_1_reset)
+ );
+ AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
+ .io_in(sink_extend_io_in),
+ .io_out(sink_extend_io_out),
+ .clock(sink_extend_clock),
+ .reset(sink_extend_reset)
+ );
+ AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
+ .io_in(sink_valid_io_in),
+ .io_out(sink_valid_io_out),
+ .clock(sink_valid_clock),
+ .reset(sink_valid_reset)
+ );
+ assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
+ assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 96:31]
+ assign io_async_mem_0_address = mem_0_address; // @[AsyncQueue.scala 96:31]
+ assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 96:31]
+ assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
+ assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
+ assign io_async_safe_source_reset_n = ~reset; // @[AsyncQueue.scala 121:27]
+ assign ridx_ridx_gray_clock = clock;
+ assign ridx_ridx_gray_reset = reset;
+ assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
+ assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
+ assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
+ assign source_valid_0_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 105:65]
+ assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
+ assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
+ assign source_valid_1_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 106:65]
+ assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
+ assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
+ assign sink_extend_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 107:65]
+ assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
+ assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
+ assign sink_valid_reset = reset; // @[AsyncQueue.scala 108:35]
+ always @(posedge clock) begin
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_opcode <= io_enq_bits_opcode; // @[AsyncQueue.scala 86:37]
+ end
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_address <= io_enq_bits_address; // @[AsyncQueue.scala 86:37]
+ end
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_data <= io_enq_bits_data; // @[AsyncQueue.scala 86:37]
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ widx_widx_bin <= 1'h0;
+ end else if (_widx_T_2) begin
+ widx_widx_bin <= 1'h0;
+ end else begin
+ widx_widx_bin <= widx_widx_bin + _widx_T_1;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 83:26]
+ ready_reg <= 1'h0;
+ end else begin
+ ready_reg <= sink_ready & widx_incremented != (ridx ^ 1'h1);
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ widx_gray <= 1'h0;
+ end else if (_widx_T_2) begin
+ widx_gray <= 1'h0;
+ end else begin
+ widx_gray <= widx_widx_bin + _widx_T_1;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ mem_0_opcode = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ mem_0_address = _RAND_1[8:0];
+ _RAND_2 = {1{`RANDOM}};
+ mem_0_data = _RAND_2[31:0];
+ _RAND_3 = {1{`RANDOM}};
+ widx_widx_bin = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ ready_reg = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ widx_gray = _RAND_5[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ widx_widx_bin = 1'h0;
+ end
+ if (reset) begin
+ ready_reg = 1'h0;
+ end
+ if (reset) begin
+ widx_gray = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockCrossingReg_w43(
+ input clock,
+ input [42:0] io_d,
+ output [42:0] io_q,
+ input io_en
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [63:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg [42:0] cdc_reg; // @[Reg.scala 16:16]
+ assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
+ always @(posedge clock) begin
+ if (io_en) begin // @[Reg.scala 17:18]
+ cdc_reg <= io_d; // @[Reg.scala 17:22]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {2{`RANDOM}};
+ cdc_reg = _RAND_0[42:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module AsyncQueueSink(
+ input clock,
+ input reset,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [1:0] io_deq_bits_param,
+ output [1:0] io_deq_bits_size,
+ output io_deq_bits_source,
+ output io_deq_bits_sink,
+ output io_deq_bits_denied,
+ output [31:0] io_deq_bits_data,
+ output io_deq_bits_corrupt,
+ input [2:0] io_async_mem_0_opcode,
+ input [1:0] io_async_mem_0_size,
+ input io_async_mem_0_source,
+ input [31:0] io_async_mem_0_data,
+ output io_async_ridx,
+ input io_async_widx,
+ output io_async_safe_ridx_valid,
+ input io_async_safe_widx_valid,
+ input io_async_safe_source_reset_n,
+ output io_async_safe_sink_reset_n
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+`endif // RANDOMIZE_REG_INIT
+ wire widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
+ wire io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
+ wire [42:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
+ wire [42:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
+ wire io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
+ wire sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
+ wire source_extend_io_in; // @[AsyncQueue.scala 171:31]
+ wire source_extend_io_out; // @[AsyncQueue.scala 171:31]
+ wire source_extend_clock; // @[AsyncQueue.scala 171:31]
+ wire source_extend_reset; // @[AsyncQueue.scala 171:31]
+ wire source_valid_io_in; // @[AsyncQueue.scala 172:31]
+ wire source_valid_io_out; // @[AsyncQueue.scala 172:31]
+ wire source_valid_clock; // @[AsyncQueue.scala 172:31]
+ wire source_valid_reset; // @[AsyncQueue.scala 172:31]
+ wire _ridx_T_1 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ wire source_ready = source_valid_io_out;
+ wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
+ reg ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
+ wire ridx_incremented = _ridx_T_2 ? 1'h0 : ridx_ridx_bin + _ridx_T_1; // @[AsyncQueue.scala 53:23]
+ wire widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire [34:0] io_deq_bits_deq_bits_reg_io_d_lo = {2'h0,io_async_mem_0_data,1'h0}; // @[SynchronizerReg.scala 209:24]
+ wire [7:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_async_mem_0_opcode,2'h0,io_async_mem_0_size,io_async_mem_0_source}; // @[SynchronizerReg.scala 209:24]
+ wire [42:0] _io_deq_bits_WIRE_1 = io_deq_bits_deq_bits_reg_io_q;
+ reg valid_reg; // @[AsyncQueue.scala 161:56]
+ reg ridx_gray; // @[AsyncQueue.scala 164:55]
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
+ .clock(widx_widx_gray_clock),
+ .reset(widx_widx_gray_reset),
+ .io_d(widx_widx_gray_io_d),
+ .io_q(widx_widx_gray_io_q)
+ );
+ ClockCrossingReg_w43 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
+ .clock(io_deq_bits_deq_bits_reg_clock),
+ .io_d(io_deq_bits_deq_bits_reg_io_d),
+ .io_q(io_deq_bits_deq_bits_reg_io_q),
+ .io_en(io_deq_bits_deq_bits_reg_io_en)
+ );
+ AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
+ .io_in(sink_valid_0_io_in),
+ .io_out(sink_valid_0_io_out),
+ .clock(sink_valid_0_clock),
+ .reset(sink_valid_0_reset)
+ );
+ AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
+ .io_in(sink_valid_1_io_in),
+ .io_out(sink_valid_1_io_out),
+ .clock(sink_valid_1_clock),
+ .reset(sink_valid_1_reset)
+ );
+ AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
+ .io_in(source_extend_io_in),
+ .io_out(source_extend_io_out),
+ .clock(source_extend_clock),
+ .reset(source_extend_reset)
+ );
+ AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
+ .io_in(source_valid_io_in),
+ .io_out(source_valid_io_out),
+ .clock(source_valid_clock),
+ .reset(source_valid_reset)
+ );
+ assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
+ assign io_deq_bits_opcode = _io_deq_bits_WIRE_1[42:40]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_param = _io_deq_bits_WIRE_1[39:38]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_size = _io_deq_bits_WIRE_1[37:36]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_source = _io_deq_bits_WIRE_1[35]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_sink = _io_deq_bits_WIRE_1[34]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_denied = _io_deq_bits_WIRE_1[33]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_data = _io_deq_bits_WIRE_1[32:1]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_corrupt = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala 211:26]
+ assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
+ assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
+ assign io_async_safe_sink_reset_n = ~reset; // @[AsyncQueue.scala 189:25]
+ assign widx_widx_gray_clock = clock;
+ assign widx_widx_gray_reset = reset;
+ assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
+ assign io_deq_bits_deq_bits_reg_clock = clock;
+ assign io_deq_bits_deq_bits_reg_io_d = {io_deq_bits_deq_bits_reg_io_d_hi,io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala 209:24]
+ assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx_incremented != widx; // @[AsyncQueue.scala 146:28]
+ assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
+ assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
+ assign sink_valid_0_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 173:66]
+ assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
+ assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
+ assign sink_valid_1_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 174:66]
+ assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
+ assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
+ assign source_extend_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 175:66]
+ assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
+ assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
+ assign source_valid_reset = reset; // @[AsyncQueue.scala 176:34]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ ridx_ridx_bin <= 1'h0;
+ end else if (_ridx_T_2) begin
+ ridx_ridx_bin <= 1'h0;
+ end else begin
+ ridx_ridx_bin <= ridx_ridx_bin + _ridx_T_1;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 146:28]
+ valid_reg <= 1'h0;
+ end else begin
+ valid_reg <= source_ready & ridx_incremented != widx;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ ridx_gray <= 1'h0;
+ end else if (_ridx_T_2) begin
+ ridx_gray <= 1'h0;
+ end else begin
+ ridx_gray <= ridx_ridx_bin + _ridx_T_1;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ ridx_ridx_bin = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ valid_reg = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ ridx_gray = _RAND_2[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ ridx_ridx_bin = 1'h0;
+ end
+ if (reset) begin
+ valid_reg = 1'h0;
+ end
+ if (reset) begin
+ ridx_gray = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLAsyncCrossingSource(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [8:0] auto_in_a_bits_address,
+ input [31:0] auto_in_a_bits_data,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [1:0] auto_in_d_bits_size,
+ output auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [31:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ output [2:0] auto_out_a_mem_0_opcode,
+ output [8:0] auto_out_a_mem_0_address,
+ output [31:0] auto_out_a_mem_0_data,
+ input auto_out_a_ridx,
+ output auto_out_a_widx,
+ input auto_out_a_safe_ridx_valid,
+ output auto_out_a_safe_widx_valid,
+ output auto_out_a_safe_source_reset_n,
+ input auto_out_a_safe_sink_reset_n,
+ input [2:0] auto_out_d_mem_0_opcode,
+ input [1:0] auto_out_d_mem_0_size,
+ input auto_out_d_mem_0_source,
+ input [31:0] auto_out_d_mem_0_data,
+ output auto_out_d_ridx,
+ input auto_out_d_widx,
+ output auto_out_d_safe_ridx_valid,
+ input auto_out_d_safe_widx_valid,
+ input auto_out_d_safe_source_reset_n,
+ output auto_out_d_safe_sink_reset_n
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [8:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_source_clock; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_reset; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_io_enq_ready; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_io_enq_valid; // @[AsyncQueue.scala 216:24]
+ wire [2:0] bundleOut_0_a_source_io_enq_bits_opcode; // @[AsyncQueue.scala 216:24]
+ wire [8:0] bundleOut_0_a_source_io_enq_bits_address; // @[AsyncQueue.scala 216:24]
+ wire [31:0] bundleOut_0_a_source_io_enq_bits_data; // @[AsyncQueue.scala 216:24]
+ wire [2:0] bundleOut_0_a_source_io_async_mem_0_opcode; // @[AsyncQueue.scala 216:24]
+ wire [8:0] bundleOut_0_a_source_io_async_mem_0_address; // @[AsyncQueue.scala 216:24]
+ wire [31:0] bundleOut_0_a_source_io_async_mem_0_data; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_io_async_ridx; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_io_async_widx; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_io_async_safe_widx_valid; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 216:24]
+ wire bundleOut_0_a_source_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_sink_clock; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_reset; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_deq_ready; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_deq_valid; // @[AsyncQueue.scala 207:22]
+ wire [2:0] bundleIn_0_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala 207:22]
+ wire [1:0] bundleIn_0_d_sink_io_deq_bits_param; // @[AsyncQueue.scala 207:22]
+ wire [1:0] bundleIn_0_d_sink_io_deq_bits_size; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_deq_bits_source; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala 207:22]
+ wire [31:0] bundleIn_0_d_sink_io_deq_bits_data; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala 207:22]
+ wire [2:0] bundleIn_0_d_sink_io_async_mem_0_opcode; // @[AsyncQueue.scala 207:22]
+ wire [1:0] bundleIn_0_d_sink_io_async_mem_0_size; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_async_mem_0_source; // @[AsyncQueue.scala 207:22]
+ wire [31:0] bundleIn_0_d_sink_io_async_mem_0_data; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_async_ridx; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_async_widx; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 207:22]
+ TLMonitor_49 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ AsyncQueueSource bundleOut_0_a_source ( // @[AsyncQueue.scala 216:24]
+ .clock(bundleOut_0_a_source_clock),
+ .reset(bundleOut_0_a_source_reset),
+ .io_enq_ready(bundleOut_0_a_source_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_source_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_source_io_enq_bits_opcode),
+ .io_enq_bits_address(bundleOut_0_a_source_io_enq_bits_address),
+ .io_enq_bits_data(bundleOut_0_a_source_io_enq_bits_data),
+ .io_async_mem_0_opcode(bundleOut_0_a_source_io_async_mem_0_opcode),
+ .io_async_mem_0_address(bundleOut_0_a_source_io_async_mem_0_address),
+ .io_async_mem_0_data(bundleOut_0_a_source_io_async_mem_0_data),
+ .io_async_ridx(bundleOut_0_a_source_io_async_ridx),
+ .io_async_widx(bundleOut_0_a_source_io_async_widx),
+ .io_async_safe_ridx_valid(bundleOut_0_a_source_io_async_safe_ridx_valid),
+ .io_async_safe_widx_valid(bundleOut_0_a_source_io_async_safe_widx_valid),
+ .io_async_safe_source_reset_n(bundleOut_0_a_source_io_async_safe_source_reset_n),
+ .io_async_safe_sink_reset_n(bundleOut_0_a_source_io_async_safe_sink_reset_n)
+ );
+ AsyncQueueSink bundleIn_0_d_sink ( // @[AsyncQueue.scala 207:22]
+ .clock(bundleIn_0_d_sink_clock),
+ .reset(bundleIn_0_d_sink_reset),
+ .io_deq_ready(bundleIn_0_d_sink_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_sink_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_sink_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_sink_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_sink_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_sink_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_sink_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_sink_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_sink_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_sink_io_deq_bits_corrupt),
+ .io_async_mem_0_opcode(bundleIn_0_d_sink_io_async_mem_0_opcode),
+ .io_async_mem_0_size(bundleIn_0_d_sink_io_async_mem_0_size),
+ .io_async_mem_0_source(bundleIn_0_d_sink_io_async_mem_0_source),
+ .io_async_mem_0_data(bundleIn_0_d_sink_io_async_mem_0_data),
+ .io_async_ridx(bundleIn_0_d_sink_io_async_ridx),
+ .io_async_widx(bundleIn_0_d_sink_io_async_widx),
+ .io_async_safe_ridx_valid(bundleIn_0_d_sink_io_async_safe_ridx_valid),
+ .io_async_safe_widx_valid(bundleIn_0_d_sink_io_async_safe_widx_valid),
+ .io_async_safe_source_reset_n(bundleIn_0_d_sink_io_async_safe_source_reset_n),
+ .io_async_safe_sink_reset_n(bundleIn_0_d_sink_io_async_safe_sink_reset_n)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_source_io_enq_ready; // @[Nodes.scala 1210:84 AsyncQueue.scala 217:19]
+ assign auto_in_d_valid = bundleIn_0_d_sink_io_deq_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_sink_io_deq_bits_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_in_d_bits_param = bundleIn_0_d_sink_io_deq_bits_param; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_in_d_bits_size = bundleIn_0_d_sink_io_deq_bits_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_in_d_bits_source = bundleIn_0_d_sink_io_deq_bits_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_in_d_bits_sink = bundleIn_0_d_sink_io_deq_bits_sink; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_in_d_bits_denied = bundleIn_0_d_sink_io_deq_bits_denied; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_in_d_bits_data = bundleIn_0_d_sink_io_deq_bits_data; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_sink_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign auto_out_a_mem_0_opcode = bundleOut_0_a_source_io_async_mem_0_opcode; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
+ assign auto_out_a_mem_0_address = bundleOut_0_a_source_io_async_mem_0_address; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
+ assign auto_out_a_mem_0_data = bundleOut_0_a_source_io_async_mem_0_data; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
+ assign auto_out_a_widx = bundleOut_0_a_source_io_async_widx; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
+ assign auto_out_a_safe_widx_valid = bundleOut_0_a_source_io_async_safe_widx_valid; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
+ assign auto_out_a_safe_source_reset_n = bundleOut_0_a_source_io_async_safe_source_reset_n; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
+ assign auto_out_d_ridx = bundleIn_0_d_sink_io_async_ridx; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
+ assign auto_out_d_safe_ridx_valid = bundleIn_0_d_sink_io_async_safe_ridx_valid; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
+ assign auto_out_d_safe_sink_reset_n = bundleIn_0_d_sink_io_async_safe_sink_reset_n; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_source_io_enq_ready; // @[Nodes.scala 1210:84 AsyncQueue.scala 217:19]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_sink_io_deq_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_sink_io_deq_bits_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_sink_io_deq_bits_param; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_sink_io_deq_bits_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_sink_io_deq_bits_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_sink_io_deq_bits_sink; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_sink_io_deq_bits_denied; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_sink_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
+ assign bundleOut_0_a_source_clock = clock;
+ assign bundleOut_0_a_source_reset = reset;
+ assign bundleOut_0_a_source_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_source_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_source_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_source_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_source_io_async_ridx = auto_out_a_ridx; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleOut_0_a_source_io_async_safe_ridx_valid = auto_out_a_safe_ridx_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleOut_0_a_source_io_async_safe_sink_reset_n = auto_out_a_safe_sink_reset_n; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_sink_clock = clock;
+ assign bundleIn_0_d_sink_reset = reset;
+ assign bundleIn_0_d_sink_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleIn_0_d_sink_io_async_mem_0_opcode = auto_out_d_mem_0_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_sink_io_async_mem_0_size = auto_out_d_mem_0_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_sink_io_async_mem_0_source = auto_out_d_mem_0_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_sink_io_async_mem_0_data = auto_out_d_mem_0_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_sink_io_async_widx = auto_out_d_widx; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_sink_io_async_safe_widx_valid = auto_out_d_safe_widx_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_sink_io_async_safe_source_reset_n = auto_out_d_safe_source_reset_n; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+endmodule
+module AsyncQueueSource_1(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input io_enq_bits_resumereq,
+ input io_enq_bits_ackhavereset,
+ input io_enq_bits_hrmask_0,
+ output io_async_mem_0_resumereq,
+ output io_async_mem_0_ackhavereset,
+ output io_async_mem_0_hrmask_0,
+ input io_async_ridx,
+ output io_async_widx,
+ input io_async_safe_ridx_valid,
+ output io_async_safe_widx_valid,
+ output io_async_safe_source_reset_n,
+ input io_async_safe_sink_reset_n
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+`endif // RANDOMIZE_REG_INIT
+ wire ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
+ wire source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_clock; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_reset; // @[AsyncQueue.scala 100:32]
+ wire source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_clock; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_reset; // @[AsyncQueue.scala 101:32]
+ wire sink_extend_io_in; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_io_out; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_clock; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_reset; // @[AsyncQueue.scala 103:30]
+ wire sink_valid_io_in; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_io_out; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_clock; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_reset; // @[AsyncQueue.scala 104:30]
+ reg mem_0_resumereq; // @[AsyncQueue.scala 80:16]
+ reg mem_0_ackhavereset; // @[AsyncQueue.scala 80:16]
+ reg mem_0_hrmask_0; // @[AsyncQueue.scala 80:16]
+ wire _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire sink_ready = sink_valid_io_out;
+ wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
+ reg widx_widx_bin; // @[AsyncQueue.scala 52:25]
+ wire widx_incremented = _widx_T_2 ? 1'h0 : widx_widx_bin + _widx_T_1; // @[AsyncQueue.scala 53:23]
+ wire ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
+ reg ready_reg; // @[AsyncQueue.scala 88:56]
+ reg widx_gray; // @[AsyncQueue.scala 91:55]
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
+ .clock(ridx_ridx_gray_clock),
+ .reset(ridx_ridx_gray_reset),
+ .io_d(ridx_ridx_gray_io_d),
+ .io_q(ridx_ridx_gray_io_q)
+ );
+ AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
+ .io_in(source_valid_0_io_in),
+ .io_out(source_valid_0_io_out),
+ .clock(source_valid_0_clock),
+ .reset(source_valid_0_reset)
+ );
+ AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
+ .io_in(source_valid_1_io_in),
+ .io_out(source_valid_1_io_out),
+ .clock(source_valid_1_clock),
+ .reset(source_valid_1_reset)
+ );
+ AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
+ .io_in(sink_extend_io_in),
+ .io_out(sink_extend_io_out),
+ .clock(sink_extend_clock),
+ .reset(sink_extend_reset)
+ );
+ AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
+ .io_in(sink_valid_io_in),
+ .io_out(sink_valid_io_out),
+ .clock(sink_valid_clock),
+ .reset(sink_valid_reset)
+ );
+ assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
+ assign io_async_mem_0_resumereq = mem_0_resumereq; // @[AsyncQueue.scala 96:31]
+ assign io_async_mem_0_ackhavereset = mem_0_ackhavereset; // @[AsyncQueue.scala 96:31]
+ assign io_async_mem_0_hrmask_0 = mem_0_hrmask_0; // @[AsyncQueue.scala 96:31]
+ assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
+ assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
+ assign io_async_safe_source_reset_n = ~reset; // @[AsyncQueue.scala 121:27]
+ assign ridx_ridx_gray_clock = clock;
+ assign ridx_ridx_gray_reset = reset;
+ assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
+ assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
+ assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
+ assign source_valid_0_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 105:65]
+ assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
+ assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
+ assign source_valid_1_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 106:65]
+ assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
+ assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
+ assign sink_extend_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 107:65]
+ assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
+ assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
+ assign sink_valid_reset = reset; // @[AsyncQueue.scala 108:35]
+ always @(posedge clock) begin
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_resumereq <= io_enq_bits_resumereq; // @[AsyncQueue.scala 86:37]
+ end
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_ackhavereset <= io_enq_bits_ackhavereset; // @[AsyncQueue.scala 86:37]
+ end
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_hrmask_0 <= io_enq_bits_hrmask_0; // @[AsyncQueue.scala 86:37]
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ widx_widx_bin <= 1'h0;
+ end else if (_widx_T_2) begin
+ widx_widx_bin <= 1'h0;
+ end else begin
+ widx_widx_bin <= widx_widx_bin + _widx_T_1;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 83:26]
+ ready_reg <= 1'h0;
+ end else begin
+ ready_reg <= sink_ready & widx_incremented != (ridx ^ 1'h1);
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ widx_gray <= 1'h0;
+ end else if (_widx_T_2) begin
+ widx_gray <= 1'h0;
+ end else begin
+ widx_gray <= widx_widx_bin + _widx_T_1;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ mem_0_resumereq = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ mem_0_ackhavereset = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ mem_0_hrmask_0 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ widx_widx_bin = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ ready_reg = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ widx_gray = _RAND_5[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ widx_widx_bin = 1'h0;
+ end
+ if (reset) begin
+ ready_reg = 1'h0;
+ end
+ if (reset) begin
+ widx_gray = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLDebugModuleOuterAsync(
+ output [2:0] auto_asource_out_a_mem_0_opcode,
+ output [8:0] auto_asource_out_a_mem_0_address,
+ output [31:0] auto_asource_out_a_mem_0_data,
+ input auto_asource_out_a_ridx,
+ output auto_asource_out_a_widx,
+ input auto_asource_out_a_safe_ridx_valid,
+ output auto_asource_out_a_safe_widx_valid,
+ output auto_asource_out_a_safe_source_reset_n,
+ input auto_asource_out_a_safe_sink_reset_n,
+ input [2:0] auto_asource_out_d_mem_0_opcode,
+ input [1:0] auto_asource_out_d_mem_0_size,
+ input auto_asource_out_d_mem_0_source,
+ input [31:0] auto_asource_out_d_mem_0_data,
+ output auto_asource_out_d_ridx,
+ input auto_asource_out_d_widx,
+ output auto_asource_out_d_safe_ridx_valid,
+ input auto_asource_out_d_safe_widx_valid,
+ input auto_asource_out_d_safe_source_reset_n,
+ output auto_asource_out_d_safe_sink_reset_n,
+ output auto_intsource_out_sync_0,
+ input io_dmi_clock,
+ input io_dmi_reset,
+ output io_dmi_req_ready,
+ input io_dmi_req_valid,
+ input [6:0] io_dmi_req_bits_addr,
+ input [31:0] io_dmi_req_bits_data,
+ input [1:0] io_dmi_req_bits_op,
+ input io_dmi_resp_ready,
+ output io_dmi_resp_valid,
+ output [31:0] io_dmi_resp_bits_data,
+ output [1:0] io_dmi_resp_bits_resp,
+ output io_ctrl_dmactive,
+ input io_ctrl_dmactiveAck,
+ output io_innerCtrl_mem_0_resumereq,
+ output io_innerCtrl_mem_0_ackhavereset,
+ output io_innerCtrl_mem_0_hrmask_0,
+ input io_innerCtrl_ridx,
+ output io_innerCtrl_widx,
+ input io_innerCtrl_safe_ridx_valid,
+ output io_innerCtrl_safe_widx_valid,
+ output io_innerCtrl_safe_source_reset_n,
+ input io_innerCtrl_safe_sink_reset_n,
+ input io_hgDebugInt_0
+);
+ wire dmiXbar_clock; // @[Debug.scala 624:28]
+ wire dmiXbar_reset; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_in_a_ready; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_in_a_valid; // @[Debug.scala 624:28]
+ wire [2:0] dmiXbar_auto_in_a_bits_opcode; // @[Debug.scala 624:28]
+ wire [8:0] dmiXbar_auto_in_a_bits_address; // @[Debug.scala 624:28]
+ wire [31:0] dmiXbar_auto_in_a_bits_data; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_in_d_ready; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_in_d_valid; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_in_d_bits_denied; // @[Debug.scala 624:28]
+ wire [31:0] dmiXbar_auto_in_d_bits_data; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_in_d_bits_corrupt; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_1_a_ready; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_1_a_valid; // @[Debug.scala 624:28]
+ wire [2:0] dmiXbar_auto_out_1_a_bits_opcode; // @[Debug.scala 624:28]
+ wire [6:0] dmiXbar_auto_out_1_a_bits_address; // @[Debug.scala 624:28]
+ wire [31:0] dmiXbar_auto_out_1_a_bits_data; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_1_d_ready; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_1_d_valid; // @[Debug.scala 624:28]
+ wire [2:0] dmiXbar_auto_out_1_d_bits_opcode; // @[Debug.scala 624:28]
+ wire [31:0] dmiXbar_auto_out_1_d_bits_data; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_0_a_ready; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_0_a_valid; // @[Debug.scala 624:28]
+ wire [2:0] dmiXbar_auto_out_0_a_bits_opcode; // @[Debug.scala 624:28]
+ wire [8:0] dmiXbar_auto_out_0_a_bits_address; // @[Debug.scala 624:28]
+ wire [31:0] dmiXbar_auto_out_0_a_bits_data; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_0_d_ready; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_0_d_valid; // @[Debug.scala 624:28]
+ wire [2:0] dmiXbar_auto_out_0_d_bits_opcode; // @[Debug.scala 624:28]
+ wire [1:0] dmiXbar_auto_out_0_d_bits_param; // @[Debug.scala 624:28]
+ wire [1:0] dmiXbar_auto_out_0_d_bits_size; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_0_d_bits_sink; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_0_d_bits_denied; // @[Debug.scala 624:28]
+ wire [31:0] dmiXbar_auto_out_0_d_bits_data; // @[Debug.scala 624:28]
+ wire dmiXbar_auto_out_0_d_bits_corrupt; // @[Debug.scala 624:28]
+ wire dmi2tl_auto_out_a_ready; // @[Debug.scala 627:28]
+ wire dmi2tl_auto_out_a_valid; // @[Debug.scala 627:28]
+ wire [2:0] dmi2tl_auto_out_a_bits_opcode; // @[Debug.scala 627:28]
+ wire [8:0] dmi2tl_auto_out_a_bits_address; // @[Debug.scala 627:28]
+ wire [31:0] dmi2tl_auto_out_a_bits_data; // @[Debug.scala 627:28]
+ wire dmi2tl_auto_out_d_ready; // @[Debug.scala 627:28]
+ wire dmi2tl_auto_out_d_valid; // @[Debug.scala 627:28]
+ wire dmi2tl_auto_out_d_bits_denied; // @[Debug.scala 627:28]
+ wire [31:0] dmi2tl_auto_out_d_bits_data; // @[Debug.scala 627:28]
+ wire dmi2tl_auto_out_d_bits_corrupt; // @[Debug.scala 627:28]
+ wire dmi2tl_io_dmi_req_ready; // @[Debug.scala 627:28]
+ wire dmi2tl_io_dmi_req_valid; // @[Debug.scala 627:28]
+ wire [6:0] dmi2tl_io_dmi_req_bits_addr; // @[Debug.scala 627:28]
+ wire [31:0] dmi2tl_io_dmi_req_bits_data; // @[Debug.scala 627:28]
+ wire [1:0] dmi2tl_io_dmi_req_bits_op; // @[Debug.scala 627:28]
+ wire dmi2tl_io_dmi_resp_ready; // @[Debug.scala 627:28]
+ wire dmi2tl_io_dmi_resp_valid; // @[Debug.scala 627:28]
+ wire [31:0] dmi2tl_io_dmi_resp_bits_data; // @[Debug.scala 627:28]
+ wire [1:0] dmi2tl_io_dmi_resp_bits_resp; // @[Debug.scala 627:28]
+ wire dmOuter_clock; // @[Debug.scala 649:27]
+ wire dmOuter_reset; // @[Debug.scala 649:27]
+ wire dmOuter_auto_dmi_in_a_ready; // @[Debug.scala 649:27]
+ wire dmOuter_auto_dmi_in_a_valid; // @[Debug.scala 649:27]
+ wire [2:0] dmOuter_auto_dmi_in_a_bits_opcode; // @[Debug.scala 649:27]
+ wire [6:0] dmOuter_auto_dmi_in_a_bits_address; // @[Debug.scala 649:27]
+ wire [31:0] dmOuter_auto_dmi_in_a_bits_data; // @[Debug.scala 649:27]
+ wire dmOuter_auto_dmi_in_d_ready; // @[Debug.scala 649:27]
+ wire dmOuter_auto_dmi_in_d_valid; // @[Debug.scala 649:27]
+ wire [2:0] dmOuter_auto_dmi_in_d_bits_opcode; // @[Debug.scala 649:27]
+ wire [31:0] dmOuter_auto_dmi_in_d_bits_data; // @[Debug.scala 649:27]
+ wire dmOuter_auto_int_out_0; // @[Debug.scala 649:27]
+ wire dmOuter_io_ctrl_dmactive; // @[Debug.scala 649:27]
+ wire dmOuter_io_ctrl_dmactiveAck; // @[Debug.scala 649:27]
+ wire dmOuter_io_innerCtrl_ready; // @[Debug.scala 649:27]
+ wire dmOuter_io_innerCtrl_valid; // @[Debug.scala 649:27]
+ wire dmOuter_io_innerCtrl_bits_resumereq; // @[Debug.scala 649:27]
+ wire [9:0] dmOuter_io_innerCtrl_bits_hartsel; // @[Debug.scala 649:27]
+ wire dmOuter_io_innerCtrl_bits_ackhavereset; // @[Debug.scala 649:27]
+ wire dmOuter_io_innerCtrl_bits_hrmask_0; // @[Debug.scala 649:27]
+ wire dmOuter_io_hgDebugInt_0; // @[Debug.scala 649:27]
+ wire intsource_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire dmiBypass_clock; // @[Debug.scala 652:29]
+ wire dmiBypass_reset; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_out_out_a_ready; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_out_out_a_valid; // @[Debug.scala 652:29]
+ wire [2:0] dmiBypass_auto_node_out_out_a_bits_opcode; // @[Debug.scala 652:29]
+ wire [8:0] dmiBypass_auto_node_out_out_a_bits_address; // @[Debug.scala 652:29]
+ wire [31:0] dmiBypass_auto_node_out_out_a_bits_data; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_out_out_d_ready; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_out_out_d_valid; // @[Debug.scala 652:29]
+ wire [2:0] dmiBypass_auto_node_out_out_d_bits_opcode; // @[Debug.scala 652:29]
+ wire [1:0] dmiBypass_auto_node_out_out_d_bits_param; // @[Debug.scala 652:29]
+ wire [1:0] dmiBypass_auto_node_out_out_d_bits_size; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_out_out_d_bits_source; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_out_out_d_bits_sink; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_out_out_d_bits_denied; // @[Debug.scala 652:29]
+ wire [31:0] dmiBypass_auto_node_out_out_d_bits_data; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_out_out_d_bits_corrupt; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_in_in_a_ready; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_in_in_a_valid; // @[Debug.scala 652:29]
+ wire [2:0] dmiBypass_auto_node_in_in_a_bits_opcode; // @[Debug.scala 652:29]
+ wire [8:0] dmiBypass_auto_node_in_in_a_bits_address; // @[Debug.scala 652:29]
+ wire [31:0] dmiBypass_auto_node_in_in_a_bits_data; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_in_in_d_ready; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_in_in_d_valid; // @[Debug.scala 652:29]
+ wire [2:0] dmiBypass_auto_node_in_in_d_bits_opcode; // @[Debug.scala 652:29]
+ wire [1:0] dmiBypass_auto_node_in_in_d_bits_param; // @[Debug.scala 652:29]
+ wire [1:0] dmiBypass_auto_node_in_in_d_bits_size; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_in_in_d_bits_sink; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_in_in_d_bits_denied; // @[Debug.scala 652:29]
+ wire [31:0] dmiBypass_auto_node_in_in_d_bits_data; // @[Debug.scala 652:29]
+ wire dmiBypass_auto_node_in_in_d_bits_corrupt; // @[Debug.scala 652:29]
+ wire dmiBypass_io_bypass; // @[Debug.scala 652:29]
+ wire asource_clock; // @[AsyncCrossing.scala 87:29]
+ wire asource_reset; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_in_a_ready; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_in_a_valid; // @[AsyncCrossing.scala 87:29]
+ wire [2:0] asource_auto_in_a_bits_opcode; // @[AsyncCrossing.scala 87:29]
+ wire [8:0] asource_auto_in_a_bits_address; // @[AsyncCrossing.scala 87:29]
+ wire [31:0] asource_auto_in_a_bits_data; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_in_d_ready; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_in_d_valid; // @[AsyncCrossing.scala 87:29]
+ wire [2:0] asource_auto_in_d_bits_opcode; // @[AsyncCrossing.scala 87:29]
+ wire [1:0] asource_auto_in_d_bits_param; // @[AsyncCrossing.scala 87:29]
+ wire [1:0] asource_auto_in_d_bits_size; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_in_d_bits_source; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_in_d_bits_sink; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_in_d_bits_denied; // @[AsyncCrossing.scala 87:29]
+ wire [31:0] asource_auto_in_d_bits_data; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_in_d_bits_corrupt; // @[AsyncCrossing.scala 87:29]
+ wire [2:0] asource_auto_out_a_mem_0_opcode; // @[AsyncCrossing.scala 87:29]
+ wire [8:0] asource_auto_out_a_mem_0_address; // @[AsyncCrossing.scala 87:29]
+ wire [31:0] asource_auto_out_a_mem_0_data; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_a_ridx; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_a_widx; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_a_safe_widx_valid; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_a_safe_source_reset_n; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala 87:29]
+ wire [2:0] asource_auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala 87:29]
+ wire [1:0] asource_auto_out_d_mem_0_size; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_d_mem_0_source; // @[AsyncCrossing.scala 87:29]
+ wire [31:0] asource_auto_out_d_mem_0_data; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_d_ridx; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_d_widx; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_d_safe_ridx_valid; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala 87:29]
+ wire asource_auto_out_d_safe_sink_reset_n; // @[AsyncCrossing.scala 87:29]
+ wire dmactiveAck_dmactiveAckSync_clock; // @[ShiftReg.scala 45:23]
+ wire dmactiveAck_dmactiveAckSync_reset; // @[ShiftReg.scala 45:23]
+ wire dmactiveAck_dmactiveAckSync_io_d; // @[ShiftReg.scala 45:23]
+ wire dmactiveAck_dmactiveAckSync_io_q; // @[ShiftReg.scala 45:23]
+ wire io_innerCtrl_source_clock; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_reset; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_enq_ready; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_enq_valid; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_enq_bits_resumereq; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_enq_bits_ackhavereset; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_enq_bits_hrmask_0; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_mem_0_resumereq; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_mem_0_ackhavereset; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_mem_0_hrmask_0; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_ridx; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_widx; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_safe_widx_valid; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 216:24]
+ wire io_innerCtrl_source_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 216:24]
+ wire dmactiveAck = dmactiveAck_dmactiveAckSync_io_q; // @[ShiftReg.scala 48:{24,24}]
+ TLXbar_8 dmiXbar ( // @[Debug.scala 624:28]
+ .clock(dmiXbar_clock),
+ .reset(dmiXbar_reset),
+ .auto_in_a_ready(dmiXbar_auto_in_a_ready),
+ .auto_in_a_valid(dmiXbar_auto_in_a_valid),
+ .auto_in_a_bits_opcode(dmiXbar_auto_in_a_bits_opcode),
+ .auto_in_a_bits_address(dmiXbar_auto_in_a_bits_address),
+ .auto_in_a_bits_data(dmiXbar_auto_in_a_bits_data),
+ .auto_in_d_ready(dmiXbar_auto_in_d_ready),
+ .auto_in_d_valid(dmiXbar_auto_in_d_valid),
+ .auto_in_d_bits_denied(dmiXbar_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(dmiXbar_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(dmiXbar_auto_in_d_bits_corrupt),
+ .auto_out_1_a_ready(dmiXbar_auto_out_1_a_ready),
+ .auto_out_1_a_valid(dmiXbar_auto_out_1_a_valid),
+ .auto_out_1_a_bits_opcode(dmiXbar_auto_out_1_a_bits_opcode),
+ .auto_out_1_a_bits_address(dmiXbar_auto_out_1_a_bits_address),
+ .auto_out_1_a_bits_data(dmiXbar_auto_out_1_a_bits_data),
+ .auto_out_1_d_ready(dmiXbar_auto_out_1_d_ready),
+ .auto_out_1_d_valid(dmiXbar_auto_out_1_d_valid),
+ .auto_out_1_d_bits_opcode(dmiXbar_auto_out_1_d_bits_opcode),
+ .auto_out_1_d_bits_data(dmiXbar_auto_out_1_d_bits_data),
+ .auto_out_0_a_ready(dmiXbar_auto_out_0_a_ready),
+ .auto_out_0_a_valid(dmiXbar_auto_out_0_a_valid),
+ .auto_out_0_a_bits_opcode(dmiXbar_auto_out_0_a_bits_opcode),
+ .auto_out_0_a_bits_address(dmiXbar_auto_out_0_a_bits_address),
+ .auto_out_0_a_bits_data(dmiXbar_auto_out_0_a_bits_data),
+ .auto_out_0_d_ready(dmiXbar_auto_out_0_d_ready),
+ .auto_out_0_d_valid(dmiXbar_auto_out_0_d_valid),
+ .auto_out_0_d_bits_opcode(dmiXbar_auto_out_0_d_bits_opcode),
+ .auto_out_0_d_bits_param(dmiXbar_auto_out_0_d_bits_param),
+ .auto_out_0_d_bits_size(dmiXbar_auto_out_0_d_bits_size),
+ .auto_out_0_d_bits_sink(dmiXbar_auto_out_0_d_bits_sink),
+ .auto_out_0_d_bits_denied(dmiXbar_auto_out_0_d_bits_denied),
+ .auto_out_0_d_bits_data(dmiXbar_auto_out_0_d_bits_data),
+ .auto_out_0_d_bits_corrupt(dmiXbar_auto_out_0_d_bits_corrupt)
+ );
+ DMIToTL dmi2tl ( // @[Debug.scala 627:28]
+ .auto_out_a_ready(dmi2tl_auto_out_a_ready),
+ .auto_out_a_valid(dmi2tl_auto_out_a_valid),
+ .auto_out_a_bits_opcode(dmi2tl_auto_out_a_bits_opcode),
+ .auto_out_a_bits_address(dmi2tl_auto_out_a_bits_address),
+ .auto_out_a_bits_data(dmi2tl_auto_out_a_bits_data),
+ .auto_out_d_ready(dmi2tl_auto_out_d_ready),
+ .auto_out_d_valid(dmi2tl_auto_out_d_valid),
+ .auto_out_d_bits_denied(dmi2tl_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(dmi2tl_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(dmi2tl_auto_out_d_bits_corrupt),
+ .io_dmi_req_ready(dmi2tl_io_dmi_req_ready),
+ .io_dmi_req_valid(dmi2tl_io_dmi_req_valid),
+ .io_dmi_req_bits_addr(dmi2tl_io_dmi_req_bits_addr),
+ .io_dmi_req_bits_data(dmi2tl_io_dmi_req_bits_data),
+ .io_dmi_req_bits_op(dmi2tl_io_dmi_req_bits_op),
+ .io_dmi_resp_ready(dmi2tl_io_dmi_resp_ready),
+ .io_dmi_resp_valid(dmi2tl_io_dmi_resp_valid),
+ .io_dmi_resp_bits_data(dmi2tl_io_dmi_resp_bits_data),
+ .io_dmi_resp_bits_resp(dmi2tl_io_dmi_resp_bits_resp)
+ );
+ TLDebugModuleOuter dmOuter ( // @[Debug.scala 649:27]
+ .clock(dmOuter_clock),
+ .reset(dmOuter_reset),
+ .auto_dmi_in_a_ready(dmOuter_auto_dmi_in_a_ready),
+ .auto_dmi_in_a_valid(dmOuter_auto_dmi_in_a_valid),
+ .auto_dmi_in_a_bits_opcode(dmOuter_auto_dmi_in_a_bits_opcode),
+ .auto_dmi_in_a_bits_address(dmOuter_auto_dmi_in_a_bits_address),
+ .auto_dmi_in_a_bits_data(dmOuter_auto_dmi_in_a_bits_data),
+ .auto_dmi_in_d_ready(dmOuter_auto_dmi_in_d_ready),
+ .auto_dmi_in_d_valid(dmOuter_auto_dmi_in_d_valid),
+ .auto_dmi_in_d_bits_opcode(dmOuter_auto_dmi_in_d_bits_opcode),
+ .auto_dmi_in_d_bits_data(dmOuter_auto_dmi_in_d_bits_data),
+ .auto_int_out_0(dmOuter_auto_int_out_0),
+ .io_ctrl_dmactive(dmOuter_io_ctrl_dmactive),
+ .io_ctrl_dmactiveAck(dmOuter_io_ctrl_dmactiveAck),
+ .io_innerCtrl_ready(dmOuter_io_innerCtrl_ready),
+ .io_innerCtrl_valid(dmOuter_io_innerCtrl_valid),
+ .io_innerCtrl_bits_resumereq(dmOuter_io_innerCtrl_bits_resumereq),
+ .io_innerCtrl_bits_hartsel(dmOuter_io_innerCtrl_bits_hartsel),
+ .io_innerCtrl_bits_ackhavereset(dmOuter_io_innerCtrl_bits_ackhavereset),
+ .io_innerCtrl_bits_hrmask_0(dmOuter_io_innerCtrl_bits_hrmask_0),
+ .io_hgDebugInt_0(dmOuter_io_hgDebugInt_0)
+ );
+ IntSyncCrossingSource_4 intsource ( // @[Crossing.scala 26:31]
+ .auto_in_0(intsource_auto_in_0),
+ .auto_out_sync_0(intsource_auto_out_sync_0)
+ );
+ TLBusBypass dmiBypass ( // @[Debug.scala 652:29]
+ .clock(dmiBypass_clock),
+ .reset(dmiBypass_reset),
+ .auto_node_out_out_a_ready(dmiBypass_auto_node_out_out_a_ready),
+ .auto_node_out_out_a_valid(dmiBypass_auto_node_out_out_a_valid),
+ .auto_node_out_out_a_bits_opcode(dmiBypass_auto_node_out_out_a_bits_opcode),
+ .auto_node_out_out_a_bits_address(dmiBypass_auto_node_out_out_a_bits_address),
+ .auto_node_out_out_a_bits_data(dmiBypass_auto_node_out_out_a_bits_data),
+ .auto_node_out_out_d_ready(dmiBypass_auto_node_out_out_d_ready),
+ .auto_node_out_out_d_valid(dmiBypass_auto_node_out_out_d_valid),
+ .auto_node_out_out_d_bits_opcode(dmiBypass_auto_node_out_out_d_bits_opcode),
+ .auto_node_out_out_d_bits_param(dmiBypass_auto_node_out_out_d_bits_param),
+ .auto_node_out_out_d_bits_size(dmiBypass_auto_node_out_out_d_bits_size),
+ .auto_node_out_out_d_bits_source(dmiBypass_auto_node_out_out_d_bits_source),
+ .auto_node_out_out_d_bits_sink(dmiBypass_auto_node_out_out_d_bits_sink),
+ .auto_node_out_out_d_bits_denied(dmiBypass_auto_node_out_out_d_bits_denied),
+ .auto_node_out_out_d_bits_data(dmiBypass_auto_node_out_out_d_bits_data),
+ .auto_node_out_out_d_bits_corrupt(dmiBypass_auto_node_out_out_d_bits_corrupt),
+ .auto_node_in_in_a_ready(dmiBypass_auto_node_in_in_a_ready),
+ .auto_node_in_in_a_valid(dmiBypass_auto_node_in_in_a_valid),
+ .auto_node_in_in_a_bits_opcode(dmiBypass_auto_node_in_in_a_bits_opcode),
+ .auto_node_in_in_a_bits_address(dmiBypass_auto_node_in_in_a_bits_address),
+ .auto_node_in_in_a_bits_data(dmiBypass_auto_node_in_in_a_bits_data),
+ .auto_node_in_in_d_ready(dmiBypass_auto_node_in_in_d_ready),
+ .auto_node_in_in_d_valid(dmiBypass_auto_node_in_in_d_valid),
+ .auto_node_in_in_d_bits_opcode(dmiBypass_auto_node_in_in_d_bits_opcode),
+ .auto_node_in_in_d_bits_param(dmiBypass_auto_node_in_in_d_bits_param),
+ .auto_node_in_in_d_bits_size(dmiBypass_auto_node_in_in_d_bits_size),
+ .auto_node_in_in_d_bits_sink(dmiBypass_auto_node_in_in_d_bits_sink),
+ .auto_node_in_in_d_bits_denied(dmiBypass_auto_node_in_in_d_bits_denied),
+ .auto_node_in_in_d_bits_data(dmiBypass_auto_node_in_in_d_bits_data),
+ .auto_node_in_in_d_bits_corrupt(dmiBypass_auto_node_in_in_d_bits_corrupt),
+ .io_bypass(dmiBypass_io_bypass)
+ );
+ TLAsyncCrossingSource asource ( // @[AsyncCrossing.scala 87:29]
+ .clock(asource_clock),
+ .reset(asource_reset),
+ .auto_in_a_ready(asource_auto_in_a_ready),
+ .auto_in_a_valid(asource_auto_in_a_valid),
+ .auto_in_a_bits_opcode(asource_auto_in_a_bits_opcode),
+ .auto_in_a_bits_address(asource_auto_in_a_bits_address),
+ .auto_in_a_bits_data(asource_auto_in_a_bits_data),
+ .auto_in_d_ready(asource_auto_in_d_ready),
+ .auto_in_d_valid(asource_auto_in_d_valid),
+ .auto_in_d_bits_opcode(asource_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(asource_auto_in_d_bits_param),
+ .auto_in_d_bits_size(asource_auto_in_d_bits_size),
+ .auto_in_d_bits_source(asource_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(asource_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(asource_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(asource_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(asource_auto_in_d_bits_corrupt),
+ .auto_out_a_mem_0_opcode(asource_auto_out_a_mem_0_opcode),
+ .auto_out_a_mem_0_address(asource_auto_out_a_mem_0_address),
+ .auto_out_a_mem_0_data(asource_auto_out_a_mem_0_data),
+ .auto_out_a_ridx(asource_auto_out_a_ridx),
+ .auto_out_a_widx(asource_auto_out_a_widx),
+ .auto_out_a_safe_ridx_valid(asource_auto_out_a_safe_ridx_valid),
+ .auto_out_a_safe_widx_valid(asource_auto_out_a_safe_widx_valid),
+ .auto_out_a_safe_source_reset_n(asource_auto_out_a_safe_source_reset_n),
+ .auto_out_a_safe_sink_reset_n(asource_auto_out_a_safe_sink_reset_n),
+ .auto_out_d_mem_0_opcode(asource_auto_out_d_mem_0_opcode),
+ .auto_out_d_mem_0_size(asource_auto_out_d_mem_0_size),
+ .auto_out_d_mem_0_source(asource_auto_out_d_mem_0_source),
+ .auto_out_d_mem_0_data(asource_auto_out_d_mem_0_data),
+ .auto_out_d_ridx(asource_auto_out_d_ridx),
+ .auto_out_d_widx(asource_auto_out_d_widx),
+ .auto_out_d_safe_ridx_valid(asource_auto_out_d_safe_ridx_valid),
+ .auto_out_d_safe_widx_valid(asource_auto_out_d_safe_widx_valid),
+ .auto_out_d_safe_source_reset_n(asource_auto_out_d_safe_source_reset_n),
+ .auto_out_d_safe_sink_reset_n(asource_auto_out_d_safe_sink_reset_n)
+ );
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 dmactiveAck_dmactiveAckSync ( // @[ShiftReg.scala 45:23]
+ .clock(dmactiveAck_dmactiveAckSync_clock),
+ .reset(dmactiveAck_dmactiveAckSync_reset),
+ .io_d(dmactiveAck_dmactiveAckSync_io_d),
+ .io_q(dmactiveAck_dmactiveAckSync_io_q)
+ );
+ AsyncQueueSource_1 io_innerCtrl_source ( // @[AsyncQueue.scala 216:24]
+ .clock(io_innerCtrl_source_clock),
+ .reset(io_innerCtrl_source_reset),
+ .io_enq_ready(io_innerCtrl_source_io_enq_ready),
+ .io_enq_valid(io_innerCtrl_source_io_enq_valid),
+ .io_enq_bits_resumereq(io_innerCtrl_source_io_enq_bits_resumereq),
+ .io_enq_bits_ackhavereset(io_innerCtrl_source_io_enq_bits_ackhavereset),
+ .io_enq_bits_hrmask_0(io_innerCtrl_source_io_enq_bits_hrmask_0),
+ .io_async_mem_0_resumereq(io_innerCtrl_source_io_async_mem_0_resumereq),
+ .io_async_mem_0_ackhavereset(io_innerCtrl_source_io_async_mem_0_ackhavereset),
+ .io_async_mem_0_hrmask_0(io_innerCtrl_source_io_async_mem_0_hrmask_0),
+ .io_async_ridx(io_innerCtrl_source_io_async_ridx),
+ .io_async_widx(io_innerCtrl_source_io_async_widx),
+ .io_async_safe_ridx_valid(io_innerCtrl_source_io_async_safe_ridx_valid),
+ .io_async_safe_widx_valid(io_innerCtrl_source_io_async_safe_widx_valid),
+ .io_async_safe_source_reset_n(io_innerCtrl_source_io_async_safe_source_reset_n),
+ .io_async_safe_sink_reset_n(io_innerCtrl_source_io_async_safe_sink_reset_n)
+ );
+ assign auto_asource_out_a_mem_0_opcode = asource_auto_out_a_mem_0_opcode; // @[LazyModule.scala 311:12]
+ assign auto_asource_out_a_mem_0_address = asource_auto_out_a_mem_0_address; // @[LazyModule.scala 311:12]
+ assign auto_asource_out_a_mem_0_data = asource_auto_out_a_mem_0_data; // @[LazyModule.scala 311:12]
+ assign auto_asource_out_a_widx = asource_auto_out_a_widx; // @[LazyModule.scala 311:12]
+ assign auto_asource_out_a_safe_widx_valid = asource_auto_out_a_safe_widx_valid; // @[LazyModule.scala 311:12]
+ assign auto_asource_out_a_safe_source_reset_n = asource_auto_out_a_safe_source_reset_n; // @[LazyModule.scala 311:12]
+ assign auto_asource_out_d_ridx = asource_auto_out_d_ridx; // @[LazyModule.scala 311:12]
+ assign auto_asource_out_d_safe_ridx_valid = asource_auto_out_d_safe_ridx_valid; // @[LazyModule.scala 311:12]
+ assign auto_asource_out_d_safe_sink_reset_n = asource_auto_out_d_safe_sink_reset_n; // @[LazyModule.scala 311:12]
+ assign auto_intsource_out_sync_0 = intsource_auto_out_sync_0; // @[LazyModule.scala 311:12]
+ assign io_dmi_req_ready = dmi2tl_io_dmi_req_ready; // @[Debug.scala 677:43]
+ assign io_dmi_resp_valid = dmi2tl_io_dmi_resp_valid; // @[Debug.scala 677:43]
+ assign io_dmi_resp_bits_data = dmi2tl_io_dmi_resp_bits_data; // @[Debug.scala 677:43]
+ assign io_dmi_resp_bits_resp = dmi2tl_io_dmi_resp_bits_resp; // @[Debug.scala 677:43]
+ assign io_ctrl_dmactive = dmOuter_io_ctrl_dmactive; // @[Debug.scala 682:15]
+ assign io_innerCtrl_mem_0_resumereq = io_innerCtrl_source_io_async_mem_0_resumereq; // @[Debug.scala 684:20]
+ assign io_innerCtrl_mem_0_ackhavereset = io_innerCtrl_source_io_async_mem_0_ackhavereset; // @[Debug.scala 684:20]
+ assign io_innerCtrl_mem_0_hrmask_0 = io_innerCtrl_source_io_async_mem_0_hrmask_0; // @[Debug.scala 684:20]
+ assign io_innerCtrl_widx = io_innerCtrl_source_io_async_widx; // @[Debug.scala 684:20]
+ assign io_innerCtrl_safe_widx_valid = io_innerCtrl_source_io_async_safe_widx_valid; // @[Debug.scala 684:20]
+ assign io_innerCtrl_safe_source_reset_n = io_innerCtrl_source_io_async_safe_source_reset_n; // @[Debug.scala 684:20]
+ assign dmiXbar_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
+ assign dmiXbar_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
+ assign dmiXbar_auto_in_a_valid = dmi2tl_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign dmiXbar_auto_in_a_bits_opcode = dmi2tl_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign dmiXbar_auto_in_a_bits_address = dmi2tl_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign dmiXbar_auto_in_a_bits_data = dmi2tl_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign dmiXbar_auto_in_d_ready = dmi2tl_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign dmiXbar_auto_out_1_a_ready = dmOuter_auto_dmi_in_a_ready; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_1_d_valid = dmOuter_auto_dmi_in_d_valid; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_1_d_bits_opcode = dmOuter_auto_dmi_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_1_d_bits_data = dmOuter_auto_dmi_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_a_ready = dmiBypass_auto_node_in_in_a_ready; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_d_valid = dmiBypass_auto_node_in_in_d_valid; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_d_bits_opcode = dmiBypass_auto_node_in_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_d_bits_param = dmiBypass_auto_node_in_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_d_bits_size = dmiBypass_auto_node_in_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_d_bits_sink = dmiBypass_auto_node_in_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_d_bits_denied = dmiBypass_auto_node_in_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_d_bits_data = dmiBypass_auto_node_in_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign dmiXbar_auto_out_0_d_bits_corrupt = dmiBypass_auto_node_in_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign dmi2tl_auto_out_a_ready = dmiXbar_auto_in_a_ready; // @[LazyModule.scala 296:16]
+ assign dmi2tl_auto_out_d_valid = dmiXbar_auto_in_d_valid; // @[LazyModule.scala 296:16]
+ assign dmi2tl_auto_out_d_bits_denied = dmiXbar_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign dmi2tl_auto_out_d_bits_data = dmiXbar_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign dmi2tl_auto_out_d_bits_corrupt = dmiXbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign dmi2tl_io_dmi_req_valid = io_dmi_req_valid; // @[Debug.scala 677:43]
+ assign dmi2tl_io_dmi_req_bits_addr = io_dmi_req_bits_addr; // @[Debug.scala 677:43]
+ assign dmi2tl_io_dmi_req_bits_data = io_dmi_req_bits_data; // @[Debug.scala 677:43]
+ assign dmi2tl_io_dmi_req_bits_op = io_dmi_req_bits_op; // @[Debug.scala 677:43]
+ assign dmi2tl_io_dmi_resp_ready = io_dmi_resp_ready; // @[Debug.scala 677:43]
+ assign dmOuter_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
+ assign dmOuter_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
+ assign dmOuter_auto_dmi_in_a_valid = dmiXbar_auto_out_1_a_valid; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_dmi_in_a_bits_opcode = dmiXbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_dmi_in_a_bits_address = dmiXbar_auto_out_1_a_bits_address; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_dmi_in_a_bits_data = dmiXbar_auto_out_1_a_bits_data; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_dmi_in_d_ready = dmiXbar_auto_out_1_d_ready; // @[LazyModule.scala 298:16]
+ assign dmOuter_io_ctrl_dmactiveAck = dmactiveAck_dmactiveAckSync_io_q; // @[ShiftReg.scala 48:{24,24}]
+ assign dmOuter_io_innerCtrl_ready = io_innerCtrl_source_io_enq_ready; // @[AsyncQueue.scala 217:19]
+ assign dmOuter_io_hgDebugInt_0 = io_hgDebugInt_0; // @[Debug.scala 685:36]
+ assign intsource_auto_in_0 = dmOuter_auto_int_out_0; // @[LazyModule.scala 298:16]
+ assign dmiBypass_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
+ assign dmiBypass_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
+ assign dmiBypass_auto_node_out_out_a_ready = asource_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_valid = asource_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_bits_opcode = asource_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_bits_param = asource_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_bits_size = asource_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_bits_source = asource_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_bits_sink = asource_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_bits_denied = asource_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_bits_data = asource_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_out_out_d_bits_corrupt = asource_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_in_in_a_valid = dmiXbar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_in_in_a_bits_opcode = dmiXbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_in_in_a_bits_address = dmiXbar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_in_in_a_bits_data = dmiXbar_auto_out_0_a_bits_data; // @[LazyModule.scala 298:16]
+ assign dmiBypass_auto_node_in_in_d_ready = dmiXbar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
+ assign dmiBypass_io_bypass = ~io_ctrl_dmactive | ~dmactiveAck; // @[Debug.scala 680:55]
+ assign asource_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
+ assign asource_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
+ assign asource_auto_in_a_valid = dmiBypass_auto_node_out_out_a_valid; // @[LazyModule.scala 298:16]
+ assign asource_auto_in_a_bits_opcode = dmiBypass_auto_node_out_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign asource_auto_in_a_bits_address = dmiBypass_auto_node_out_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign asource_auto_in_a_bits_data = dmiBypass_auto_node_out_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign asource_auto_in_d_ready = dmiBypass_auto_node_out_out_d_ready; // @[LazyModule.scala 298:16]
+ assign asource_auto_out_a_ridx = auto_asource_out_a_ridx; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_a_safe_ridx_valid = auto_asource_out_a_safe_ridx_valid; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_a_safe_sink_reset_n = auto_asource_out_a_safe_sink_reset_n; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_d_mem_0_opcode = auto_asource_out_d_mem_0_opcode; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_d_mem_0_size = auto_asource_out_d_mem_0_size; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_d_mem_0_source = auto_asource_out_d_mem_0_source; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_d_mem_0_data = auto_asource_out_d_mem_0_data; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_d_widx = auto_asource_out_d_widx; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_d_safe_widx_valid = auto_asource_out_d_safe_widx_valid; // @[LazyModule.scala 311:12]
+ assign asource_auto_out_d_safe_source_reset_n = auto_asource_out_d_safe_source_reset_n; // @[LazyModule.scala 311:12]
+ assign dmactiveAck_dmactiveAckSync_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
+ assign dmactiveAck_dmactiveAckSync_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
+ assign dmactiveAck_dmactiveAckSync_io_d = io_ctrl_dmactiveAck; // @[ShiftReg.scala 47:16]
+ assign io_innerCtrl_source_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
+ assign io_innerCtrl_source_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
+ assign io_innerCtrl_source_io_enq_valid = dmOuter_io_innerCtrl_valid; // @[AsyncQueue.scala 217:19]
+ assign io_innerCtrl_source_io_enq_bits_resumereq = dmOuter_io_innerCtrl_bits_resumereq; // @[AsyncQueue.scala 217:19]
+ assign io_innerCtrl_source_io_enq_bits_ackhavereset = dmOuter_io_innerCtrl_bits_ackhavereset; // @[AsyncQueue.scala 217:19]
+ assign io_innerCtrl_source_io_enq_bits_hrmask_0 = dmOuter_io_innerCtrl_bits_hrmask_0; // @[AsyncQueue.scala 217:19]
+ assign io_innerCtrl_source_io_async_ridx = io_innerCtrl_ridx; // @[Debug.scala 684:20]
+ assign io_innerCtrl_source_io_async_safe_ridx_valid = io_innerCtrl_safe_ridx_valid; // @[Debug.scala 684:20]
+ assign io_innerCtrl_source_io_async_safe_sink_reset_n = io_innerCtrl_safe_sink_reset_n; // @[Debug.scala 684:20]
+endmodule
+module TLMonitor_50(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input io_in_a_bits_source,
+ input [8:0] io_in_a_bits_address,
+ input [3:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
+ wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
+ wire [8:0] _GEN_71 = {{7'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [8:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala 20:24]
+ wire mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
+ wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
+ wire _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
+ wire [9:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [9:0] _T_23 = $signed(_T_7) & -10'sh40; // @[Parameters.scala 137:52]
+ wire _T_24 = $signed(_T_23) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_25 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 137:31]
+ wire [9:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_28 = $signed(_T_26) & -10'shc; // @[Parameters.scala 137:52]
+ wire _T_29 = $signed(_T_28) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_30 = io_in_a_bits_address ^ 9'h58; // @[Parameters.scala 137:31]
+ wire [9:0] _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_33 = $signed(_T_31) & -10'sh8; // @[Parameters.scala 137:52]
+ wire _T_34 = $signed(_T_33) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_35 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 137:31]
+ wire [9:0] _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_38 = $signed(_T_36) & -10'sh20; // @[Parameters.scala 137:52]
+ wire _T_39 = $signed(_T_38) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_40 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 137:31]
+ wire [9:0] _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_43 = $signed(_T_41) & -10'sh80; // @[Parameters.scala 137:52]
+ wire _T_44 = $signed(_T_43) == 10'sh0; // @[Parameters.scala 137:67]
+ wire [8:0] _T_45 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 137:31]
+ wire [9:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
+ wire [9:0] _T_48 = $signed(_T_46) & -10'sh100; // @[Parameters.scala 137:52]
+ wire _T_49 = $signed(_T_48) == 10'sh0; // @[Parameters.scala 137:67]
+ wire _T_54 = _T_24 | _T_29 | _T_34 | _T_39 | _T_44 | _T_49; // @[Parameters.scala 671:42]
+ wire _T_116 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [3:0] _T_120 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_121 = _T_120 == 4'h0; // @[Monitor.scala 88:31]
+ wire _T_125 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_129 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_234 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_247 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_248 = 2'h2 == io_in_a_bits_size; // @[Parameters.scala 91:48]
+ wire _T_250 = _T_248 & _source_ok_T; // @[Parameters.scala 1160:30]
+ wire _T_256 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
+ wire _T_294 = _T_256 & _T_54; // @[Parameters.scala 670:56]
+ wire _T_305 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_309 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_317 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_363 = _T_250 & _T_294; // @[Monitor.scala 115:71]
+ wire _T_381 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [3:0] _T_440 = ~mask; // @[Monitor.scala 127:33]
+ wire [3:0] _T_441 = io_in_a_bits_mask & _T_440; // @[Monitor.scala 127:31]
+ wire _T_442 = _T_441 == 4'h0; // @[Monitor.scala 127:40]
+ wire _T_446 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_498 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_506 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_558 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_566 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_618 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_630 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
+ wire _T_634 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_638 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
+ wire _T_654 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_682 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_711 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_728 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_746 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg source; // @[Monitor.scala 387:22]
+ reg [8:0] address; // @[Monitor.scala 388:22]
+ wire _T_776 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_777 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_781 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_785 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_789 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_793 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg source_1; // @[Monitor.scala 538:22]
+ wire _T_800 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_801 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_809 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_813 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg inflight; // @[Monitor.scala 611:27]
+ reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [2:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [15:0] _GEN_73 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
+ wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
+ wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [15:0] _GEN_76 = {{12'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
+ wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
+ wire _T_827 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_830 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [2:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [17:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [17:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire _T_834 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
+ wire [1:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
+ wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
+ wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_838 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_840 = ~_T_634; // @[Monitor.scala 671:74]
+ wire _T_841 = io_in_d_valid & d_first_1 & ~_T_634; // @[Monitor.scala 671:71]
+ wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [30:0] _GEN_3 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [30:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_840 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
+ wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_840 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_827 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire _T_853 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_858 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_859 = io_in_d_bits_opcode == _GEN_32 | _T_858; // @[Monitor.scala 685:77]
+ wire _T_863 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_870 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_871 = io_in_d_bits_opcode == _GEN_48 | _T_870; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_875 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_885 = _T_838 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_840; // @[Monitor.scala 694:116]
+ wire _T_887 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire a_set = _GEN_16[0];
+ wire d_clr = _GEN_22[0];
+ wire [3:0] a_opcodes_set = _GEN_19[3:0];
+ wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [3:0] d_opcodes_clr = _GEN_23[3:0];
+ wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [3:0] a_sizes_set = _GEN_20[3:0];
+ wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_896 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [15:0] _GEN_87 = {{12'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
+ wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
+ wire _T_922 = io_in_d_valid & d_first_2 & _T_634; // @[Monitor.scala 779:71]
+ wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_634 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
+ wire _T_930 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_940 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
+ wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 1'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_116 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_116) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_121 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_121) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_125 & (io_in_a_valid & _T_15 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_15 & ~reset & ~_T_125) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_116 & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & ~_T_116) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_234 & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & ~_T_234) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_121 & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & ~_T_121) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_125 & (io_in_a_valid & _T_129 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_129 & ~reset & ~_T_125) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_250 & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~_T_250) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_294 & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~_T_294) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_305 & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~_T_305) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_125 & (io_in_a_valid & _T_247 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_247 & ~reset & ~_T_125) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_363 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_363) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_305 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_305) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_381 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_381 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_305 & (io_in_a_valid & _T_381 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset & ~_T_305) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_442 & (io_in_a_valid & _T_381 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_381 & ~reset & ~_T_442) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_446 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_446 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_498 & (io_in_a_valid & _T_446 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset & ~_T_498) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_446 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_446 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_506 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_506 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_558 & (io_in_a_valid & _T_506 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset & ~_T_558) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_506 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_506 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_5 & (io_in_a_valid & _T_566 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset & _T_5) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_566 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (io_in_a_valid & _T_566 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_566 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_125 & (io_in_a_valid & _T_566 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_566 & ~reset & ~_T_125) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_634 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_634 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_654 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_654 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (io_in_d_valid & _T_682 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_682 & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_711 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_711 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_728 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_728 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_1 & (io_in_d_valid & _T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_746 & _T_2 & ~_source_ok_T_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_777 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_777) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_781 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_781) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_785 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_785) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_789 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_789) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_793 & (_T_776 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_776 & ~reset & ~_T_793) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_801 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_801) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_809 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_809) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_813 & (_T_800 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_800 & _T_2 & ~_T_813) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_834 & (_T_830 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_830 & ~reset & ~_T_834) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_853 & (_T_841 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & _T_2 & ~_T_853) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_859 & (_T_841 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & same_cycle_resp & _T_2 & ~_T_859) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_863 & (_T_841 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & same_cycle_resp & _T_2 & ~_T_863) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_871 & (_T_841 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_871) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_875 & (_T_841 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_875) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_887 & (_T_885 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_885 & _T_2 & ~_T_887) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_896 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_896) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Debug.scala:1746:19)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_930 & (_T_922 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_922 & _T_2 & ~_T_930) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_940 & (_T_922 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_922 & _T_2 & ~_T_940) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:1746:19)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[8:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ inflight = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_11[3:0];
+ _RAND_12 = {1{`RANDOM}};
+ inflight_sizes = _RAND_12[3:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_16[3:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_17[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_51(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [11:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [11:0] _GEN_71 = {{9'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [11:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire [12:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [12:0] _T_36 = $signed(_T_12) & 13'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 13'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [11:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:16)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at Periphery.scala:88:16)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[11:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLDebugModuleInner(
+ input clock,
+ input reset,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [1:0] auto_tl_in_a_bits_size,
+ input [6:0] auto_tl_in_a_bits_source,
+ input [11:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [1:0] auto_tl_in_d_bits_size,
+ output [6:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data,
+ output auto_dmi_in_a_ready,
+ input auto_dmi_in_a_valid,
+ input [2:0] auto_dmi_in_a_bits_opcode,
+ input [2:0] auto_dmi_in_a_bits_param,
+ input [1:0] auto_dmi_in_a_bits_size,
+ input auto_dmi_in_a_bits_source,
+ input [8:0] auto_dmi_in_a_bits_address,
+ input [3:0] auto_dmi_in_a_bits_mask,
+ input [31:0] auto_dmi_in_a_bits_data,
+ input auto_dmi_in_a_bits_corrupt,
+ input auto_dmi_in_d_ready,
+ output auto_dmi_in_d_valid,
+ output [2:0] auto_dmi_in_d_bits_opcode,
+ output [1:0] auto_dmi_in_d_bits_size,
+ output auto_dmi_in_d_bits_source,
+ output [31:0] auto_dmi_in_d_bits_data,
+ input io_dmactive,
+ output io_innerCtrl_ready,
+ input io_innerCtrl_valid,
+ input io_innerCtrl_bits_resumereq,
+ input [9:0] io_innerCtrl_bits_hartsel,
+ input io_innerCtrl_bits_ackhavereset,
+ input io_innerCtrl_bits_hrmask_0,
+ output io_hgDebugInt_0,
+ input io_hartIsInReset_0
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [31:0] _RAND_30;
+ reg [31:0] _RAND_31;
+ reg [31:0] _RAND_32;
+ reg [31:0] _RAND_33;
+ reg [31:0] _RAND_34;
+ reg [31:0] _RAND_35;
+ reg [31:0] _RAND_36;
+ reg [31:0] _RAND_37;
+ reg [31:0] _RAND_38;
+ reg [31:0] _RAND_39;
+ reg [31:0] _RAND_40;
+ reg [31:0] _RAND_41;
+ reg [31:0] _RAND_42;
+ reg [31:0] _RAND_43;
+ reg [31:0] _RAND_44;
+ reg [31:0] _RAND_45;
+ reg [31:0] _RAND_46;
+ reg [31:0] _RAND_47;
+ reg [31:0] _RAND_48;
+ reg [31:0] _RAND_49;
+ reg [31:0] _RAND_50;
+ reg [31:0] _RAND_51;
+ reg [31:0] _RAND_52;
+ reg [31:0] _RAND_53;
+ reg [31:0] _RAND_54;
+ reg [31:0] _RAND_55;
+ reg [31:0] _RAND_56;
+ reg [31:0] _RAND_57;
+ reg [31:0] _RAND_58;
+ reg [31:0] _RAND_59;
+ reg [31:0] _RAND_60;
+ reg [31:0] _RAND_61;
+ reg [31:0] _RAND_62;
+ reg [31:0] _RAND_63;
+ reg [31:0] _RAND_64;
+ reg [31:0] _RAND_65;
+ reg [31:0] _RAND_66;
+ reg [31:0] _RAND_67;
+ reg [31:0] _RAND_68;
+ reg [31:0] _RAND_69;
+ reg [31:0] _RAND_70;
+ reg [31:0] _RAND_71;
+ reg [31:0] _RAND_72;
+ reg [31:0] _RAND_73;
+ reg [31:0] _RAND_74;
+ reg [31:0] _RAND_75;
+ reg [31:0] _RAND_76;
+ reg [31:0] _RAND_77;
+ reg [31:0] _RAND_78;
+ reg [31:0] _RAND_79;
+ reg [31:0] _RAND_80;
+ reg [31:0] _RAND_81;
+ reg [31:0] _RAND_82;
+ reg [31:0] _RAND_83;
+ reg [31:0] _RAND_84;
+ reg [31:0] _RAND_85;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [8:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_1_clock; // @[Nodes.scala 24:25]
+ wire monitor_1_reset; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [11:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_1_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire hartIsInResetSync_0_debug_hartReset_0_clock; // @[ShiftReg.scala 45:23]
+ wire hartIsInResetSync_0_debug_hartReset_0_reset; // @[ShiftReg.scala 45:23]
+ wire hartIsInResetSync_0_debug_hartReset_0_io_d; // @[ShiftReg.scala 45:23]
+ wire hartIsInResetSync_0_debug_hartReset_0_io_q; // @[ShiftReg.scala 45:23]
+ reg haltedBitRegs; // @[Debug.scala 778:31]
+ reg resumeReqRegs; // @[Debug.scala 779:31]
+ reg haveResetBitRegs; // @[Debug.scala 780:31]
+ wire hamaskWrSel_0 = io_innerCtrl_bits_hartsel == 10'h0; // @[Debug.scala 842:61]
+ reg hrmaskReg_0; // @[Debug.scala 854:29]
+ wire _T_1 = ~io_dmactive; // @[Debug.scala 861:11]
+ wire _T_4 = io_innerCtrl_ready & io_innerCtrl_valid; // @[Decoupled.scala 50:35]
+ reg hrDebugIntReg_0; // @[Debug.scala 868:34]
+ wire _T_10 = ~haltedBitRegs; // @[package.scala 70:38]
+ wire _T_11 = hrDebugIntReg_0 & _T_10; // @[package.scala 65:72]
+ wire hartIsInResetSync_0 = hartIsInResetSync_0_debug_hartReset_0_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire _T_12 = hartIsInResetSync_0 | _T_11; // @[package.scala 66:75]
+ wire _T_13 = hrmaskReg_0 & _T_12; // @[package.scala 65:72]
+ wire resumereq = _T_4 & io_innerCtrl_bits_resumereq; // @[Debug.scala 890:41]
+ wire _resumeAcks_T_1 = ~hamaskWrSel_0; // @[Debug.scala 1235:41]
+ wire resumeAcks = resumereq ? ~resumeReqRegs & ~hamaskWrSel_0 : ~resumeReqRegs; // @[Debug.scala 1234:24 1235:20 1237:20]
+ wire [31:0] haltedStatus_0 = {{31'd0}, haltedBitRegs}; // @[Debug.scala 1063:30]
+ wire haltedSummary = |haltedStatus_0; // @[Debug.scala 1073:48]
+ wire [31:0] HALTSUM1RdData_haltsum1 = {{31'd0}, haltedSummary};
+ reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala 1087:34]
+ wire in_bits_read = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [6:0] in_bits_index = auto_dmi_in_a_bits_address[8:2]; // @[Edges.scala 191:34]
+ wire [4:0] out_iindex = {in_bits_index[5],in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [6:0] out_findex = in_bits_index & 7'h50; // @[RegisterRouter.scala 83:24]
+ wire _out_T_46 = out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
+ wire _out_T_4 = out_findex == 7'h10; // @[RegisterRouter.scala 83:24]
+ wire _out_T_22 = out_findex == 7'h40; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_backSel_T = 32'h1 << out_iindex; // @[OneHot.scala 57:35]
+ wire out_backSel_6 = _out_backSel_T[6]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__65 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_6 & out_findex == 7'h10
+ ; // @[RegisterRouter.scala 83:24]
+ wire [7:0] _out_backMask_T_11 = auto_dmi_in_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_9 = auto_dmi_in_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_7 = auto_dmi_in_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_5 = auto_dmi_in_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [31:0] out_backMask = {_out_backMask_T_11,_out_backMask_T_9,_out_backMask_T_7,_out_backMask_T_5}; // @[Cat.scala 31:58]
+ wire out_womask_65 = &out_backMask[10:8]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_65 = out_woready__65 & out_womask_65; // @[RegisterRouter.scala 83:24]
+ reg [1:0] ctrlStateReg; // @[Debug.scala 1616:27]
+ wire ABSTRACTCSWrEnLegal = ctrlStateReg == 2'h0; // @[Debug.scala 1626:44]
+ wire ABSTRACTCSWrEn = out_f_woready_65 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1095:51]
+ wire [2:0] ABSTRACTCSWrData_cmderr = auto_dmi_in_a_bits_data[10:8]; // @[RegisterRouter.scala 83:24]
+ wire [2:0] _ABSTRACTCSReg_cmderr_T = ~ABSTRACTCSWrData_cmderr; // @[Debug.scala 1115:58]
+ wire [2:0] _ABSTRACTCSReg_cmderr_T_1 = ABSTRACTCSReg_cmderr & _ABSTRACTCSReg_cmderr_T; // @[Debug.scala 1115:56]
+ wire [2:0] _GEN_37 = ABSTRACTCSWrEn ? _ABSTRACTCSReg_cmderr_T_1 : ABSTRACTCSReg_cmderr; // @[Debug.scala 1114:30 1115:32 1087:34]
+ wire _T_1399 = ctrlStateReg == 2'h1; // @[Debug.scala 1681:30]
+ reg [7:0] COMMANDRdData_cmdtype; // @[Debug.scala 1172:25]
+ wire commandRegIsAccessRegister = COMMANDRdData_cmdtype == 8'h0; // @[Debug.scala 1641:58]
+ reg [23:0] COMMANDRdData_control; // @[Debug.scala 1172:25]
+ wire [31:0] _accessRegisterCommandReg_T = {COMMANDRdData_cmdtype,COMMANDRdData_control}; // @[Debug.scala 1417:62]
+ wire accessRegisterCommandReg_transfer = _accessRegisterCommandReg_T[17]; // @[Debug.scala 1417:73]
+ wire accessRegisterCommandReg_write = _accessRegisterCommandReg_T[16]; // @[Debug.scala 1417:73]
+ wire [15:0] accessRegisterCommandReg_regno = _accessRegisterCommandReg_T[15:0]; // @[Debug.scala 1417:73]
+ wire [2:0] accessRegisterCommandReg_size = _accessRegisterCommandReg_T[22:20]; // @[Debug.scala 1417:73]
+ wire accessRegIsLegalSize = accessRegisterCommandReg_size == 3'h2 | accessRegisterCommandReg_size == 3'h3; // @[Debug.scala 1649:72]
+ wire accessRegIsGPR = accessRegisterCommandReg_regno >= 16'h1000 & accessRegisterCommandReg_regno <= 16'h101f &
+ accessRegIsLegalSize; // @[Debug.scala 1650:117]
+ wire _GEN_2094 = ~accessRegisterCommandReg_transfer | accessRegIsGPR ? 1'h0 : 1'h1; // @[Debug.scala 1660:73 1661:33]
+ wire commandRegIsUnsupported = commandRegIsAccessRegister ? _GEN_2094 : 1'h1; // @[Debug.scala 1657:39]
+ wire _GEN_2095 = (~accessRegisterCommandReg_transfer | accessRegIsGPR) & _T_10; // @[Debug.scala 1660:73 1662:33]
+ wire commandRegBadHaltResume = commandRegIsAccessRegister & _GEN_2095; // @[Debug.scala 1657:39]
+ wire _GEN_2111 = commandRegIsUnsupported ? 1'h0 : commandRegBadHaltResume; // @[Debug.scala 1688:38]
+ wire _GEN_2124 = ctrlStateReg == 2'h1 & _GEN_2111; // @[Debug.scala 1681:59]
+ wire errorHaltResume = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_2124; // @[Debug.scala 1673:47]
+ wire [2:0] _GEN_38 = errorHaltResume ? 3'h4 : _GEN_37; // @[Debug.scala 1111:36 1112:30]
+ wire out_backSel_7 = _out_backSel_T[7]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__90 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_7 & out_findex == 7'h10
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_womask_90 = &out_backMask; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_90 = out_woready__90 & out_womask_90; // @[RegisterRouter.scala 83:24]
+ wire COMMANDWrEn = out_f_woready_90 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1180:40]
+ wire [31:0] COMMANDWrDataVal = out_f_woready_90 ? auto_dmi_in_a_bits_data : 32'h0; // @[Debug.scala 265:{24,30}]
+ wire [7:0] COMMANDWrData_cmdtype = COMMANDWrDataVal[31:24]; // @[Debug.scala 1175:65]
+ wire commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala 1640:60]
+ wire _wrAccessRegisterCommand_T_1 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala 1666:103]
+ wire wrAccessRegisterCommand = COMMANDWrEn & commandWrIsAccessRegister & ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala 1666:78]
+ wire out_backSel_4 = _out_backSel_T[4]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__96 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_4 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_womask_96 = &out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_96 = out_woready__96 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__96 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_4 & out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
+ wire out_romask_96 = |out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_96 = out_roready__96 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiAbstractDataAccessVec_0 = out_f_woready_96 | out_f_roready_96; // @[Debug.scala 1153:105]
+ reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala 1131:36]
+ wire autoexecData_0 = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala 1164:140]
+ wire out_backSel_5 = _out_backSel_T[5]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__0 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_5 & out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready = out_woready__0 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__0 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_5 & out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready = out_roready__0 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiAbstractDataAccessVec_4 = out_f_woready | out_f_roready; // @[Debug.scala 1153:105]
+ wire autoexecData_1 = dmiAbstractDataAccessVec_4 & ABSTRACTAUTOReg_autoexecdata[1]; // @[Debug.scala 1164:140]
+ wire out_backSel_16 = _out_backSel_T[16]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__31 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_16 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_31 = out_woready__31 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__31 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_16 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_31 = out_roready__31 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_0 = out_f_woready_31 | out_f_roready_31; // @[Debug.scala 1156:108]
+ reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala 1131:36]
+ wire autoexecProg_0 = dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala 1165:144]
+ wire out_backSel_17 = _out_backSel_T[17]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__23 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_17 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_23 = out_woready__23 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__23 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_17 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_23 = out_roready__23 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_4 = out_f_woready_23 | out_f_roready_23; // @[Debug.scala 1156:108]
+ wire autoexecProg_1 = dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala 1165:144]
+ wire out_backSel_18 = _out_backSel_T[18]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__35 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_18 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_35 = out_woready__35 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__35 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_18 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_35 = out_roready__35 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_8 = out_f_woready_35 | out_f_roready_35; // @[Debug.scala 1156:108]
+ wire autoexecProg_2 = dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala 1165:144]
+ wire out_backSel_19 = _out_backSel_T[19]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__78 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_19 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_78 = out_woready__78 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__78 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_19 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_78 = out_roready__78 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_12 = out_f_woready_78 | out_f_roready_78; // @[Debug.scala 1156:108]
+ wire autoexecProg_3 = dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala 1165:144]
+ wire out_backSel_20 = _out_backSel_T[20]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__91 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_20 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_91 = out_woready__91 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__91 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_20 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_91 = out_roready__91 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_16 = out_f_woready_91 | out_f_roready_91; // @[Debug.scala 1156:108]
+ wire autoexecProg_4 = dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala 1165:144]
+ wire out_backSel_21 = _out_backSel_T[21]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__11 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_21 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_11 = out_woready__11 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__11 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_21 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_11 = out_roready__11 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_20 = out_f_woready_11 | out_f_roready_11; // @[Debug.scala 1156:108]
+ wire autoexecProg_5 = dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala 1165:144]
+ wire out_backSel_22 = _out_backSel_T[22]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__19 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_22 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_19 = out_woready__19 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__19 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_22 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_19 = out_roready__19 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_24 = out_f_woready_19 | out_f_roready_19; // @[Debug.scala 1156:108]
+ wire autoexecProg_6 = dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala 1165:144]
+ wire out_backSel_23 = _out_backSel_T[23]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__74 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_23 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_74 = out_woready__74 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__74 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_23 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_74 = out_roready__74 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_28 = out_f_woready_74 | out_f_roready_74; // @[Debug.scala 1156:108]
+ wire autoexecProg_7 = dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala 1165:144]
+ wire out_backSel_24 = _out_backSel_T[24]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__86 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_24 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_86 = out_woready__86 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__86 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_24 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_86 = out_roready__86 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_32 = out_f_woready_86 | out_f_roready_86; // @[Debug.scala 1156:108]
+ wire autoexecProg_8 = dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala 1165:144]
+ wire out_backSel_25 = _out_backSel_T[25]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__27 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_25 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_27 = out_woready__27 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__27 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_25 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_27 = out_roready__27 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_36 = out_f_woready_27 | out_f_roready_27; // @[Debug.scala 1156:108]
+ wire autoexecProg_9 = dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala 1165:144]
+ wire out_backSel_26 = _out_backSel_T[26]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__4 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_26 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_4 = out_woready__4 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__4 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_26 & out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_4 = out_roready__4 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_40 = out_f_woready_4 | out_f_roready_4; // @[Debug.scala 1156:108]
+ wire autoexecProg_10 = dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala 1165:144]
+ wire out_backSel_27 = _out_backSel_T[27]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__82 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_27 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_82 = out_woready__82 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__82 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_27 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_82 = out_roready__82 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_44 = out_f_woready_82 | out_f_roready_82; // @[Debug.scala 1156:108]
+ wire autoexecProg_11 = dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala 1165:144]
+ wire out_backSel_28 = _out_backSel_T[28]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__70 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_28 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_70 = out_woready__70 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__70 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_28 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_70 = out_roready__70 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_48 = out_f_woready_70 | out_f_roready_70; // @[Debug.scala 1156:108]
+ wire autoexecProg_12 = dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala 1165:144]
+ wire out_backSel_29 = _out_backSel_T[29]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__39 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_29 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_39 = out_woready__39 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__39 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_29 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_39 = out_roready__39 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_52 = out_f_woready_39 | out_f_roready_39; // @[Debug.scala 1156:108]
+ wire autoexecProg_13 = dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala 1165:144]
+ wire out_backSel_30 = _out_backSel_T[30]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__15 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_30 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_15 = out_woready__15 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__15 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_30 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_15 = out_roready__15 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_56 = out_f_woready_15 | out_f_roready_15; // @[Debug.scala 1156:108]
+ wire autoexecProg_14 = dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala 1165:144]
+ wire out_backSel_31 = _out_backSel_T[31]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__100 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_31 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_100 = out_woready__100 & out_womask_96; // @[RegisterRouter.scala 83:24]
+ wire out_roready__100 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_31 & out_findex == 7'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_100 = out_roready__100 & out_romask_96; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_60 = out_f_woready_100 | out_f_roready_100; // @[Debug.scala 1156:108]
+ wire autoexecProg_15 = dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala 1165:144]
+ wire autoexec = autoexecData_0 | autoexecData_1 | (autoexecProg_0 | autoexecProg_1 | autoexecProg_2 | autoexecProg_3
+ | autoexecProg_4 | autoexecProg_5 | autoexecProg_6 | autoexecProg_7 | autoexecProg_8 | autoexecProg_9 |
+ autoexecProg_10 | autoexecProg_11 | autoexecProg_12 | autoexecProg_13 | autoexecProg_14 | autoexecProg_15); // @[Debug.scala 1167:48]
+ wire regAccessRegisterCommand = autoexec & commandRegIsAccessRegister & _wrAccessRegisterCommand_T_1; // @[Debug.scala 1667:78]
+ wire commandWrIsUnsupported = COMMANDWrEn & ~commandWrIsAccessRegister; // @[Debug.scala 1643:46]
+ wire _T_1398 = autoexec & commandRegIsUnsupported; // @[Debug.scala 1678:28]
+ wire _GEN_2101 = commandWrIsUnsupported | _T_1398; // @[Debug.scala 1676:43 1677:26]
+ wire _GEN_2103 = wrAccessRegisterCommand | regAccessRegisterCommand ? 1'h0 : _GEN_2101; // @[Debug.scala 1674:66]
+ wire _GEN_2122 = ctrlStateReg == 2'h1 & commandRegIsUnsupported; // @[Debug.scala 1681:59]
+ wire errorUnsupported = ABSTRACTCSWrEnLegal ? _GEN_2103 : _GEN_2122; // @[Debug.scala 1673:47]
+ wire _T_1400 = ctrlStateReg == 2'h2; // @[Debug.scala 1702:30]
+ wire in_1_bits_read = auto_tl_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [8:0] in_1_bits_index = auto_tl_in_a_bits_address[11:3]; // @[Edges.scala 191:34]
+ wire [7:0] out_iindex_1 = {in_1_bits_index[7],in_1_bits_index[6],in_1_bits_index[5],in_1_bits_index[4],in_1_bits_index
+ [3],in_1_bits_index[2],in_1_bits_index[1],in_1_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [8:0] out_findex_1 = in_1_bits_index & 9'h100; // @[RegisterRouter.scala 83:24]
+ wire _out_T_1342 = out_findex_1 == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire _out_T_1266 = out_findex_1 == 9'h100; // @[RegisterRouter.scala 83:24]
+ wire [255:0] _out_backSel_T_1 = 256'h1 << out_iindex_1; // @[OneHot.scala 57:35]
+ wire out_backSel_33 = _out_backSel_T_1[33]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_1_345 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_backSel_33 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] _out_backMask_T_35 = auto_tl_in_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_33 = auto_tl_in_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_31 = auto_tl_in_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_29 = auto_tl_in_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_27 = auto_tl_in_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_25 = auto_tl_in_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_23 = auto_tl_in_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_backMask_T_21 = auto_tl_in_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_backMask_1 = {_out_backMask_T_35,_out_backMask_T_33,_out_backMask_T_31,_out_backMask_T_29,
+ _out_backMask_T_27,_out_backMask_T_25,_out_backMask_T_23,_out_backMask_T_21}; // @[Cat.scala 31:58]
+ wire out_womask_449 = &out_backMask_1[41:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_449 = out_woready_1_345 & out_womask_449; // @[RegisterRouter.scala 83:24]
+ wire _GEN_2120 = ctrlStateReg == 2'h2 & out_f_woready_449; // @[Debug.scala 1702:51]
+ wire _GEN_2126 = ctrlStateReg == 2'h1 ? 1'h0 : _GEN_2120; // @[Debug.scala 1681:59]
+ wire errorException = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_2126; // @[Debug.scala 1673:47]
+ wire _errorBusy_T = ~ABSTRACTCSWrEnLegal; // @[Debug.scala 1632:45]
+ wire out_backSel_8 = _out_backSel_T[8]; // @[RegisterRouter.scala 83:24]
+ wire out_woready__8 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_8 & out_findex == 7'h10
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_womask_8 = &out_backMask[1:0]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_8 = out_woready__8 & out_womask_8; // @[RegisterRouter.scala 83:24]
+ wire _errorBusy_T_3 = out_f_woready_8 & _errorBusy_T; // @[Debug.scala 1633:42]
+ wire _errorBusy_T_4 = out_f_woready_65 & ~ABSTRACTCSWrEnLegal | _errorBusy_T_3; // @[Debug.scala 1632:74]
+ wire out_womask_10 = &out_backMask[31:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_10 = out_woready__8 & out_womask_10; // @[RegisterRouter.scala 83:24]
+ wire _errorBusy_T_6 = out_f_woready_10 & _errorBusy_T; // @[Debug.scala 1634:44]
+ wire _errorBusy_T_7 = _errorBusy_T_4 | _errorBusy_T_6; // @[Debug.scala 1633:74]
+ wire _errorBusy_T_9 = out_f_woready_90 & _errorBusy_T; // @[Debug.scala 1635:42]
+ wire _errorBusy_T_10 = _errorBusy_T_7 | _errorBusy_T_9; // @[Debug.scala 1634:74]
+ wire out_womask_97 = &out_backMask[15:8]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_97 = out_woready__96 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_romask_97 = |out_backMask[15:8]; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_97 = out_roready__96 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiAbstractDataAccessVec_1 = out_f_woready_97 | out_f_roready_97; // @[Debug.scala 1153:105]
+ wire out_womask_98 = &out_backMask[23:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_98 = out_woready__96 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_romask_98 = |out_backMask[23:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_98 = out_roready__96 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiAbstractDataAccessVec_2 = out_f_woready_98 | out_f_roready_98; // @[Debug.scala 1153:105]
+ wire out_womask_99 = &out_backMask[31:24]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_99 = out_woready__96 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_romask_99 = |out_backMask[31:24]; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_99 = out_roready__96 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiAbstractDataAccessVec_3 = out_f_woready_99 | out_f_roready_99; // @[Debug.scala 1153:105]
+ wire out_f_woready_1 = out_woready__0 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_1 = out_roready__0 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiAbstractDataAccessVec_5 = out_f_woready_1 | out_f_roready_1; // @[Debug.scala 1153:105]
+ wire out_f_woready_2 = out_woready__0 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_2 = out_roready__0 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiAbstractDataAccessVec_6 = out_f_woready_2 | out_f_roready_2; // @[Debug.scala 1153:105]
+ wire out_f_woready_3 = out_woready__0 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_3 = out_roready__0 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiAbstractDataAccessVec_7 = out_f_woready_3 | out_f_roready_3; // @[Debug.scala 1153:105]
+ wire dmiAbstractDataAccess = dmiAbstractDataAccessVec_0 | dmiAbstractDataAccessVec_1 | dmiAbstractDataAccessVec_2 |
+ dmiAbstractDataAccessVec_3 | dmiAbstractDataAccessVec_4 | dmiAbstractDataAccessVec_5 | dmiAbstractDataAccessVec_6 |
+ dmiAbstractDataAccessVec_7; // @[Debug.scala 1158:68]
+ wire _errorBusy_T_12 = dmiAbstractDataAccess & _errorBusy_T; // @[Debug.scala 1636:42]
+ wire _errorBusy_T_13 = _errorBusy_T_10 | _errorBusy_T_12; // @[Debug.scala 1635:74]
+ wire out_f_woready_32 = out_woready__31 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_32 = out_roready__31 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_1 = out_f_woready_32 | out_f_roready_32; // @[Debug.scala 1156:108]
+ wire out_f_woready_33 = out_woready__31 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_33 = out_roready__31 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_2 = out_f_woready_33 | out_f_roready_33; // @[Debug.scala 1156:108]
+ wire out_f_woready_34 = out_woready__31 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_34 = out_roready__31 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_3 = out_f_woready_34 | out_f_roready_34; // @[Debug.scala 1156:108]
+ wire out_f_woready_24 = out_woready__23 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_24 = out_roready__23 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_5 = out_f_woready_24 | out_f_roready_24; // @[Debug.scala 1156:108]
+ wire out_f_woready_25 = out_woready__23 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_25 = out_roready__23 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_6 = out_f_woready_25 | out_f_roready_25; // @[Debug.scala 1156:108]
+ wire out_f_woready_26 = out_woready__23 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_26 = out_roready__23 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_7 = out_f_woready_26 | out_f_roready_26; // @[Debug.scala 1156:108]
+ wire out_f_woready_36 = out_woready__35 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_36 = out_roready__35 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_9 = out_f_woready_36 | out_f_roready_36; // @[Debug.scala 1156:108]
+ wire out_f_woready_37 = out_woready__35 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_37 = out_roready__35 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_10 = out_f_woready_37 | out_f_roready_37; // @[Debug.scala 1156:108]
+ wire out_f_woready_38 = out_woready__35 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_38 = out_roready__35 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_11 = out_f_woready_38 | out_f_roready_38; // @[Debug.scala 1156:108]
+ wire out_f_woready_79 = out_woready__78 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_79 = out_roready__78 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_13 = out_f_woready_79 | out_f_roready_79; // @[Debug.scala 1156:108]
+ wire out_f_woready_80 = out_woready__78 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_80 = out_roready__78 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_14 = out_f_woready_80 | out_f_roready_80; // @[Debug.scala 1156:108]
+ wire out_f_woready_81 = out_woready__78 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_81 = out_roready__78 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_15 = out_f_woready_81 | out_f_roready_81; // @[Debug.scala 1156:108]
+ wire out_f_woready_92 = out_woready__91 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_92 = out_roready__91 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_17 = out_f_woready_92 | out_f_roready_92; // @[Debug.scala 1156:108]
+ wire out_f_woready_93 = out_woready__91 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_93 = out_roready__91 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_18 = out_f_woready_93 | out_f_roready_93; // @[Debug.scala 1156:108]
+ wire out_f_woready_94 = out_woready__91 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_94 = out_roready__91 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_19 = out_f_woready_94 | out_f_roready_94; // @[Debug.scala 1156:108]
+ wire out_f_woready_12 = out_woready__11 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_12 = out_roready__11 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_21 = out_f_woready_12 | out_f_roready_12; // @[Debug.scala 1156:108]
+ wire out_f_woready_13 = out_woready__11 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_13 = out_roready__11 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_22 = out_f_woready_13 | out_f_roready_13; // @[Debug.scala 1156:108]
+ wire out_f_woready_14 = out_woready__11 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_14 = out_roready__11 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_23 = out_f_woready_14 | out_f_roready_14; // @[Debug.scala 1156:108]
+ wire out_f_woready_20 = out_woready__19 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_20 = out_roready__19 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_25 = out_f_woready_20 | out_f_roready_20; // @[Debug.scala 1156:108]
+ wire out_f_woready_21 = out_woready__19 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_21 = out_roready__19 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_26 = out_f_woready_21 | out_f_roready_21; // @[Debug.scala 1156:108]
+ wire out_f_woready_22 = out_woready__19 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_22 = out_roready__19 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_27 = out_f_woready_22 | out_f_roready_22; // @[Debug.scala 1156:108]
+ wire out_f_woready_75 = out_woready__74 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_75 = out_roready__74 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_29 = out_f_woready_75 | out_f_roready_75; // @[Debug.scala 1156:108]
+ wire out_f_woready_76 = out_woready__74 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_76 = out_roready__74 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_30 = out_f_woready_76 | out_f_roready_76; // @[Debug.scala 1156:108]
+ wire _dmiProgramBufferAccess_T_29 = dmiProgramBufferAccessVec_0 | dmiProgramBufferAccessVec_1 |
+ dmiProgramBufferAccessVec_2 | dmiProgramBufferAccessVec_3 | dmiProgramBufferAccessVec_4 |
+ dmiProgramBufferAccessVec_5 | dmiProgramBufferAccessVec_6 | dmiProgramBufferAccessVec_7 |
+ dmiProgramBufferAccessVec_8 | dmiProgramBufferAccessVec_9 | dmiProgramBufferAccessVec_10 |
+ dmiProgramBufferAccessVec_11 | dmiProgramBufferAccessVec_12 | dmiProgramBufferAccessVec_13 |
+ dmiProgramBufferAccessVec_14 | dmiProgramBufferAccessVec_15 | dmiProgramBufferAccessVec_16 |
+ dmiProgramBufferAccessVec_17 | dmiProgramBufferAccessVec_18 | dmiProgramBufferAccessVec_19 |
+ dmiProgramBufferAccessVec_20 | dmiProgramBufferAccessVec_21 | dmiProgramBufferAccessVec_22 |
+ dmiProgramBufferAccessVec_23 | dmiProgramBufferAccessVec_24 | dmiProgramBufferAccessVec_25 |
+ dmiProgramBufferAccessVec_26 | dmiProgramBufferAccessVec_27 | dmiProgramBufferAccessVec_28 |
+ dmiProgramBufferAccessVec_29 | dmiProgramBufferAccessVec_30; // @[Debug.scala 1159:69]
+ wire out_f_woready_77 = out_woready__74 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_77 = out_roready__74 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_31 = out_f_woready_77 | out_f_roready_77; // @[Debug.scala 1156:108]
+ wire out_f_woready_87 = out_woready__86 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_87 = out_roready__86 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_33 = out_f_woready_87 | out_f_roready_87; // @[Debug.scala 1156:108]
+ wire out_f_woready_88 = out_woready__86 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_88 = out_roready__86 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_34 = out_f_woready_88 | out_f_roready_88; // @[Debug.scala 1156:108]
+ wire out_f_woready_89 = out_woready__86 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_89 = out_roready__86 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_35 = out_f_woready_89 | out_f_roready_89; // @[Debug.scala 1156:108]
+ wire out_f_woready_28 = out_woready__27 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_28 = out_roready__27 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_37 = out_f_woready_28 | out_f_roready_28; // @[Debug.scala 1156:108]
+ wire out_f_woready_29 = out_woready__27 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_29 = out_roready__27 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_38 = out_f_woready_29 | out_f_roready_29; // @[Debug.scala 1156:108]
+ wire out_f_woready_30 = out_woready__27 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_30 = out_roready__27 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_39 = out_f_woready_30 | out_f_roready_30; // @[Debug.scala 1156:108]
+ wire out_f_woready_5 = out_woready__4 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_5 = out_roready__4 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_41 = out_f_woready_5 | out_f_roready_5; // @[Debug.scala 1156:108]
+ wire out_f_woready_6 = out_woready__4 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_6 = out_roready__4 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_42 = out_f_woready_6 | out_f_roready_6; // @[Debug.scala 1156:108]
+ wire out_f_woready_7 = out_woready__4 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_7 = out_roready__4 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_43 = out_f_woready_7 | out_f_roready_7; // @[Debug.scala 1156:108]
+ wire out_f_woready_83 = out_woready__82 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_83 = out_roready__82 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_45 = out_f_woready_83 | out_f_roready_83; // @[Debug.scala 1156:108]
+ wire out_f_woready_84 = out_woready__82 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_84 = out_roready__82 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_46 = out_f_woready_84 | out_f_roready_84; // @[Debug.scala 1156:108]
+ wire out_f_woready_85 = out_woready__82 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_85 = out_roready__82 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_47 = out_f_woready_85 | out_f_roready_85; // @[Debug.scala 1156:108]
+ wire out_f_woready_71 = out_woready__70 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_71 = out_roready__70 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_49 = out_f_woready_71 | out_f_roready_71; // @[Debug.scala 1156:108]
+ wire out_f_woready_72 = out_woready__70 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_72 = out_roready__70 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_50 = out_f_woready_72 | out_f_roready_72; // @[Debug.scala 1156:108]
+ wire out_f_woready_73 = out_woready__70 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_73 = out_roready__70 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_51 = out_f_woready_73 | out_f_roready_73; // @[Debug.scala 1156:108]
+ wire out_f_woready_40 = out_woready__39 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_40 = out_roready__39 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_53 = out_f_woready_40 | out_f_roready_40; // @[Debug.scala 1156:108]
+ wire out_f_woready_41 = out_woready__39 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_41 = out_roready__39 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_54 = out_f_woready_41 | out_f_roready_41; // @[Debug.scala 1156:108]
+ wire out_f_woready_42 = out_woready__39 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_42 = out_roready__39 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_55 = out_f_woready_42 | out_f_roready_42; // @[Debug.scala 1156:108]
+ wire out_f_woready_16 = out_woready__15 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_16 = out_roready__15 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_57 = out_f_woready_16 | out_f_roready_16; // @[Debug.scala 1156:108]
+ wire out_f_woready_17 = out_woready__15 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_17 = out_roready__15 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_58 = out_f_woready_17 | out_f_roready_17; // @[Debug.scala 1156:108]
+ wire out_f_woready_18 = out_woready__15 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_18 = out_roready__15 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_59 = out_f_woready_18 | out_f_roready_18; // @[Debug.scala 1156:108]
+ wire _dmiProgramBufferAccess_T_59 = _dmiProgramBufferAccess_T_29 | dmiProgramBufferAccessVec_31 |
+ dmiProgramBufferAccessVec_32 | dmiProgramBufferAccessVec_33 | dmiProgramBufferAccessVec_34 |
+ dmiProgramBufferAccessVec_35 | dmiProgramBufferAccessVec_36 | dmiProgramBufferAccessVec_37 |
+ dmiProgramBufferAccessVec_38 | dmiProgramBufferAccessVec_39 | dmiProgramBufferAccessVec_40 |
+ dmiProgramBufferAccessVec_41 | dmiProgramBufferAccessVec_42 | dmiProgramBufferAccessVec_43 |
+ dmiProgramBufferAccessVec_44 | dmiProgramBufferAccessVec_45 | dmiProgramBufferAccessVec_46 |
+ dmiProgramBufferAccessVec_47 | dmiProgramBufferAccessVec_48 | dmiProgramBufferAccessVec_49 |
+ dmiProgramBufferAccessVec_50 | dmiProgramBufferAccessVec_51 | dmiProgramBufferAccessVec_52 |
+ dmiProgramBufferAccessVec_53 | dmiProgramBufferAccessVec_54 | dmiProgramBufferAccessVec_55 |
+ dmiProgramBufferAccessVec_56 | dmiProgramBufferAccessVec_57 | dmiProgramBufferAccessVec_58 |
+ dmiProgramBufferAccessVec_59 | dmiProgramBufferAccessVec_60; // @[Debug.scala 1159:69]
+ wire out_f_woready_101 = out_woready__100 & out_womask_97; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_101 = out_roready__100 & out_romask_97; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_61 = out_f_woready_101 | out_f_roready_101; // @[Debug.scala 1156:108]
+ wire out_f_woready_102 = out_woready__100 & out_womask_98; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_102 = out_roready__100 & out_romask_98; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_62 = out_f_woready_102 | out_f_roready_102; // @[Debug.scala 1156:108]
+ wire out_f_woready_103 = out_woready__100 & out_womask_99; // @[RegisterRouter.scala 83:24]
+ wire out_f_roready_103 = out_roready__100 & out_romask_99; // @[RegisterRouter.scala 83:24]
+ wire dmiProgramBufferAccessVec_63 = out_f_woready_103 | out_f_roready_103; // @[Debug.scala 1156:108]
+ wire dmiProgramBufferAccess = _dmiProgramBufferAccess_T_59 | dmiProgramBufferAccessVec_61 |
+ dmiProgramBufferAccessVec_62 | dmiProgramBufferAccessVec_63; // @[Debug.scala 1159:69]
+ wire _errorBusy_T_15 = dmiProgramBufferAccess & _errorBusy_T; // @[Debug.scala 1637:42]
+ wire errorBusy = _errorBusy_T_13 | _errorBusy_T_15; // @[Debug.scala 1636:74]
+ wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf = auto_dmi_in_a_bits_data[31:16]; // @[RegisterRouter.scala 83:24]
+ wire [11:0] ABSTRACTAUTOWrData_autoexecdata = {{10'd0}, auto_dmi_in_a_bits_data[1:0]};
+ wire [11:0] _ABSTRACTAUTOReg_autoexecdata_T = ABSTRACTAUTOWrData_autoexecdata & 12'h3; // @[Debug.scala 1148:73]
+ wire [23:0] COMMANDWrData_control = COMMANDWrDataVal[23:0]; // @[Debug.scala 1175:65]
+ reg [7:0] abstractDataMem_0; // @[Debug.scala 1195:36]
+ reg [7:0] abstractDataMem_1; // @[Debug.scala 1195:36]
+ reg [7:0] abstractDataMem_2; // @[Debug.scala 1195:36]
+ reg [7:0] abstractDataMem_3; // @[Debug.scala 1195:36]
+ reg [7:0] abstractDataMem_4; // @[Debug.scala 1195:36]
+ reg [7:0] abstractDataMem_5; // @[Debug.scala 1195:36]
+ reg [7:0] abstractDataMem_6; // @[Debug.scala 1195:36]
+ reg [7:0] abstractDataMem_7; // @[Debug.scala 1195:36]
+ reg [7:0] programBufferMem_0; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_1; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_2; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_3; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_4; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_5; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_6; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_7; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_8; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_9; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_10; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_11; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_12; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_13; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_14; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_15; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_16; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_17; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_18; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_19; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_20; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_21; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_22; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_23; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_24; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_25; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_26; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_27; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_28; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_29; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_30; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_31; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_32; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_33; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_34; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_35; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_36; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_37; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_38; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_39; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_40; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_41; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_42; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_43; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_44; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_45; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_46; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_47; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_48; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_49; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_50; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_51; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_52; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_53; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_54; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_55; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_56; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_57; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_58; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_59; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_60; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_61; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_62; // @[Debug.scala 1199:34]
+ reg [7:0] programBufferMem_63; // @[Debug.scala 1199:34]
+ wire _resumeReqRegs_T = ~hartIsInResetSync_0; // @[Debug.scala 1212:42]
+ wire _resumeReqRegs_T_1 = resumeReqRegs & ~hartIsInResetSync_0; // @[Debug.scala 1212:40]
+ wire [1:0] _GEN_2135 = {{1'd0}, haltedBitRegs}; // @[Debug.scala 1218:43]
+ wire [1:0] _haltedBitRegs_T = _GEN_2135 | 2'h1; // @[Debug.scala 1218:43]
+ wire [1:0] _GEN_2136 = {{1'd0}, _resumeReqRegs_T}; // @[Debug.scala 1218:64]
+ wire [1:0] _haltedBitRegs_T_2 = _haltedBitRegs_T & _GEN_2136; // @[Debug.scala 1218:64]
+ wire [1:0] _haltedBitRegs_T_4 = _GEN_2135 & 2'h2; // @[Debug.scala 1220:43]
+ wire [1:0] _haltedBitRegs_T_6 = _haltedBitRegs_T_4 & _GEN_2136; // @[Debug.scala 1220:69]
+ wire _haltedBitRegs_T_8 = haltedBitRegs & _resumeReqRegs_T; // @[Debug.scala 1222:42]
+ wire out_womask_448 = &out_backMask_1[9:0]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_448 = out_woready_1_345 & out_womask_448; // @[RegisterRouter.scala 83:24]
+ wire [1:0] _GEN_61 = out_f_woready_448 ? _haltedBitRegs_T_6 : {{1'd0}, _haltedBitRegs_T_8}; // @[Debug.scala 1219:39 1220:25 1222:25]
+ wire out_backSel_32 = _out_backSel_T_1[32]; // @[RegisterRouter.scala 83:24]
+ wire out_woready_1_527 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_backSel_32 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_631 = out_woready_1_527 & out_womask_448; // @[RegisterRouter.scala 83:24]
+ wire [1:0] _GEN_62 = out_f_woready_631 ? _haltedBitRegs_T_2 : _GEN_61; // @[Debug.scala 1217:31 1218:25]
+ wire [1:0] _GEN_2139 = {{1'd0}, resumeReqRegs}; // @[Debug.scala 1226:43]
+ wire [1:0] _resumeReqRegs_T_3 = _GEN_2139 & 2'h2; // @[Debug.scala 1226:43]
+ wire [1:0] _resumeReqRegs_T_5 = _resumeReqRegs_T_3 & _GEN_2136; // @[Debug.scala 1226:69]
+ wire [1:0] _GEN_63 = out_f_woready_448 ? _resumeReqRegs_T_5 : {{1'd0}, _resumeReqRegs_T_1}; // @[Debug.scala 1212:23 1225:33 1226:25]
+ wire _resumeReqRegs_T_8 = (resumeReqRegs | hamaskWrSel_0) & _resumeReqRegs_T; // @[Debug.scala 1229:65]
+ wire [1:0] _GEN_64 = resumereq ? {{1'd0}, _resumeReqRegs_T_8} : _GEN_63; // @[Debug.scala 1228:26 1229:25]
+ wire [1:0] _GEN_65 = _T_1 ? 2'h0 : _GEN_62; // @[Debug.scala 1207:45 1208:23]
+ wire [1:0] _GEN_66 = _T_1 ? 2'h0 : _GEN_64; // @[Debug.scala 1207:45 1209:23]
+ wire [31:0] out_prepend_2 = {abstractDataMem_7,abstractDataMem_6,abstractDataMem_5,abstractDataMem_4}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_5 = {programBufferMem_43,programBufferMem_42,programBufferMem_41,programBufferMem_40}; // @[Cat.scala 31:58]
+ wire [2:0] out_prepend_6 = {1'h0,ABSTRACTAUTOReg_autoexecdata[1:0]}; // @[Cat.scala 31:58]
+ wire [15:0] _out_T_154 = {{13'd0}, out_prepend_6}; // @[RegisterRouter.scala 83:24]
+ wire [31:0] out_prepend_7 = {ABSTRACTAUTOReg_autoexecprogbuf,_out_T_154}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_10 = {programBufferMem_23,programBufferMem_22,programBufferMem_21,programBufferMem_20}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_13 = {programBufferMem_59,programBufferMem_58,programBufferMem_57,programBufferMem_56}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_16 = {programBufferMem_27,programBufferMem_26,programBufferMem_25,programBufferMem_24}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_19 = {programBufferMem_7,programBufferMem_6,programBufferMem_5,programBufferMem_4}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_22 = {programBufferMem_39,programBufferMem_38,programBufferMem_37,programBufferMem_36}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_25 = {programBufferMem_3,programBufferMem_2,programBufferMem_1,programBufferMem_0}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_28 = {programBufferMem_11,programBufferMem_10,programBufferMem_9,programBufferMem_8}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_31 = {programBufferMem_55,programBufferMem_54,programBufferMem_53,programBufferMem_52}; // @[Cat.scala 31:58]
+ wire [16:0] out_prepend_44 = {resumeAcks,1'h0,1'h0,1'h0,1'h0,_T_10,_T_10,haltedBitRegs,haltedBitRegs,8'ha2}; // @[Cat.scala 31:58]
+ wire [20:0] out_prepend_48 = {1'h0,haveResetBitRegs,haveResetBitRegs,resumeAcks,out_prepend_44}; // @[Cat.scala 31:58]
+ wire [21:0] _out_T_688 = {{1'd0}, out_prepend_48}; // @[RegisterRouter.scala 83:24]
+ wire [22:0] out_prepend_49 = {1'h0,_out_T_688}; // @[Cat.scala 31:58]
+ wire abstractCommandBusy = ctrlStateReg != 2'h0; // @[Debug.scala 1624:42]
+ wire [13:0] out_prepend_54 = {1'h0,abstractCommandBusy,1'h0,ABSTRACTCSReg_cmderr,8'h2}; // @[Cat.scala 31:58]
+ wire [23:0] _out_T_753 = {{10'd0}, out_prepend_54}; // @[RegisterRouter.scala 83:24]
+ wire [28:0] out_prepend_55 = {5'h10,_out_T_753}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_58 = {programBufferMem_51,programBufferMem_50,programBufferMem_49,programBufferMem_48}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_61 = {programBufferMem_31,programBufferMem_30,programBufferMem_29,programBufferMem_28}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_64 = {programBufferMem_15,programBufferMem_14,programBufferMem_13,programBufferMem_12}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_67 = {programBufferMem_47,programBufferMem_46,programBufferMem_45,programBufferMem_44}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_70 = {programBufferMem_35,programBufferMem_34,programBufferMem_33,programBufferMem_32}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_73 = {programBufferMem_19,programBufferMem_18,programBufferMem_17,programBufferMem_16}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_76 = {abstractDataMem_3,abstractDataMem_2,abstractDataMem_1,abstractDataMem_0}; // @[Cat.scala 31:58]
+ wire [31:0] out_prepend_79 = {programBufferMem_63,programBufferMem_62,programBufferMem_61,programBufferMem_60}; // @[Cat.scala 31:58]
+ wire _GEN_270 = 5'h1 == out_iindex ? _out_T_4 : _out_T_22; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_272 = 5'h3 == out_iindex ? _out_T_4 : 5'h2 == out_iindex | _GEN_270; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_273 = 5'h4 == out_iindex ? _out_T_46 : _GEN_272; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_274 = 5'h5 == out_iindex ? _out_T_46 : _GEN_273; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_275 = 5'h6 == out_iindex ? _out_T_4 : _GEN_274; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_276 = 5'h7 == out_iindex ? _out_T_4 : _GEN_275; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_277 = 5'h8 == out_iindex ? _out_T_4 : _GEN_276; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_285 = 5'h10 == out_iindex ? _out_T_46 : 5'hf == out_iindex | (5'he == out_iindex | (5'hd == out_iindex | (5'hc
+ == out_iindex | (5'hb == out_iindex | (5'ha == out_iindex | (5'h9 == out_iindex | _GEN_277)))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_286 = 5'h11 == out_iindex ? _out_T_46 : _GEN_285; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_287 = 5'h12 == out_iindex ? _out_T_46 : _GEN_286; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_288 = 5'h13 == out_iindex ? _out_T_46 : _GEN_287; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_289 = 5'h14 == out_iindex ? _out_T_46 : _GEN_288; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_290 = 5'h15 == out_iindex ? _out_T_46 : _GEN_289; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_291 = 5'h16 == out_iindex ? _out_T_46 : _GEN_290; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_292 = 5'h17 == out_iindex ? _out_T_46 : _GEN_291; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_293 = 5'h18 == out_iindex ? _out_T_46 : _GEN_292; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_294 = 5'h19 == out_iindex ? _out_T_46 : _GEN_293; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_295 = 5'h1a == out_iindex ? _out_T_46 : _GEN_294; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_296 = 5'h1b == out_iindex ? _out_T_46 : _GEN_295; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_297 = 5'h1c == out_iindex ? _out_T_46 : _GEN_296; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_298 = 5'h1d == out_iindex ? _out_T_46 : _GEN_297; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_299 = 5'h1e == out_iindex ? _out_T_46 : _GEN_298; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_300 = 5'h1f == out_iindex ? _out_T_46 : _GEN_299; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _out_out_bits_data_WIRE_1_1 = {{9'd0}, out_prepend_49}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [31:0] _GEN_302 = 5'h1 == out_iindex ? _out_out_bits_data_WIRE_1_1 : haltedStatus_0; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_303 = 5'h2 == out_iindex ? 32'h0 : _GEN_302; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_304 = 5'h3 == out_iindex ? HALTSUM1RdData_haltsum1 : _GEN_303; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_305 = 5'h4 == out_iindex ? out_prepend_76 : _GEN_304; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_306 = 5'h5 == out_iindex ? out_prepend_2 : _GEN_305; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _out_out_bits_data_WIRE_1_6 = {{3'd0}, out_prepend_55}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [31:0] _GEN_307 = 5'h6 == out_iindex ? _out_out_bits_data_WIRE_1_6 : _GEN_306; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_308 = 5'h7 == out_iindex ? _accessRegisterCommandReg_T : _GEN_307; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_309 = 5'h8 == out_iindex ? out_prepend_7 : _GEN_308; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_310 = 5'h9 == out_iindex ? 32'h0 : _GEN_309; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_311 = 5'ha == out_iindex ? 32'h0 : _GEN_310; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_312 = 5'hb == out_iindex ? 32'h0 : _GEN_311; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_313 = 5'hc == out_iindex ? 32'h0 : _GEN_312; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_314 = 5'hd == out_iindex ? 32'h0 : _GEN_313; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_315 = 5'he == out_iindex ? 32'h0 : _GEN_314; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_316 = 5'hf == out_iindex ? 32'h0 : _GEN_315; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_317 = 5'h10 == out_iindex ? out_prepend_25 : _GEN_316; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_318 = 5'h11 == out_iindex ? out_prepend_19 : _GEN_317; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_319 = 5'h12 == out_iindex ? out_prepend_28 : _GEN_318; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_320 = 5'h13 == out_iindex ? out_prepend_64 : _GEN_319; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_321 = 5'h14 == out_iindex ? out_prepend_73 : _GEN_320; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_322 = 5'h15 == out_iindex ? out_prepend_10 : _GEN_321; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_323 = 5'h16 == out_iindex ? out_prepend_16 : _GEN_322; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_324 = 5'h17 == out_iindex ? out_prepend_61 : _GEN_323; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_325 = 5'h18 == out_iindex ? out_prepend_70 : _GEN_324; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_326 = 5'h19 == out_iindex ? out_prepend_22 : _GEN_325; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_327 = 5'h1a == out_iindex ? out_prepend_5 : _GEN_326; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_328 = 5'h1b == out_iindex ? out_prepend_67 : _GEN_327; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_329 = 5'h1c == out_iindex ? out_prepend_58 : _GEN_328; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_330 = 5'h1d == out_iindex ? out_prepend_31 : _GEN_329; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_331 = 5'h1e == out_iindex ? out_prepend_13 : _GEN_330; // @[MuxLiteral.scala 48:{10,10}]
+ wire [31:0] _GEN_332 = 5'h1f == out_iindex ? out_prepend_79 : _GEN_331; // @[MuxLiteral.scala 48:{10,10}]
+ reg goReg; // @[Debug.scala 1379:27]
+ wire [9:0] hartGoingId = auto_tl_in_a_bits_data[41:32]; // @[RegisterRouter.scala 83:24]
+ wire _T_357 = ~reset; // @[Debug.scala 1391:15]
+ wire _T_358 = ~(hartGoingId == 10'h0); // @[Debug.scala 1391:15]
+ wire out_f_woready_632 = out_woready_1_527 & out_womask_449; // @[RegisterRouter.scala 83:24]
+ wire _GEN_405 = out_f_woready_632 ? 1'h0 : goReg; // @[Debug.scala 1390:33 1392:15 1379:27]
+ wire _GEN_2108 = commandRegBadHaltResume ? 1'h0 : 1'h1; // @[Debug.scala 1691:43]
+ wire _GEN_2112 = commandRegIsUnsupported ? 1'h0 : _GEN_2108; // @[Debug.scala 1688:38]
+ wire _GEN_2125 = ctrlStateReg == 2'h1 & _GEN_2112; // @[Debug.scala 1681:59]
+ wire goAbstract = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_2125; // @[Debug.scala 1673:47]
+ wire _GEN_406 = goAbstract | _GEN_405; // @[Debug.scala 1388:25 1389:15]
+ wire accessRegisterCommandReg_postexec = _accessRegisterCommandReg_T[18]; // @[Debug.scala 1417:73]
+ reg [31:0] abstractGeneratedMem_0; // @[Debug.scala 1470:35]
+ reg [31:0] abstractGeneratedMem_1; // @[Debug.scala 1470:35]
+ wire [15:0] _abstractGeneratedMem_0_inst_rd_T = accessRegisterCommandReg_regno & 16'h1f; // @[Debug.scala 1477:54]
+ wire [4:0] abstractGeneratedMem_0_inst_rd = _abstractGeneratedMem_0_inst_rd_T[4:0]; // @[Debug.scala 1473:22 1477:19]
+ wire [31:0] _abstractGeneratedMem_0_T = {17'h7000,accessRegisterCommandReg_size,abstractGeneratedMem_0_inst_rd,7'h3}; // @[Debug.scala 1481:12]
+ wire [31:0] _abstractGeneratedMem_0_T_1 = {7'h1c,abstractGeneratedMem_0_inst_rd,5'h0,accessRegisterCommandReg_size,5'h0
+ ,7'h23}; // @[Debug.scala 1494:12]
+ wire out_wimask_104 = &out_backMask_1[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_105 = &out_backMask_1[15:8]; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_106 = &out_backMask_1[23:16]; // @[RegisterRouter.scala 83:24]
+ wire [23:0] out_prepend_81 = {6'h0,resumeReqRegs,goReg,6'h0,resumeReqRegs,goReg,6'h0,resumeReqRegs,goReg}; // @[Cat.scala 31:58]
+ wire out_wimask_107 = &out_backMask_1[31:24]; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_108 = &out_backMask_1[39:32]; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_109 = &out_backMask_1[47:40]; // @[RegisterRouter.scala 83:24]
+ wire [47:0] out_prepend_84 = {6'h0,resumeReqRegs,goReg,6'h0,resumeReqRegs,goReg,6'h0,resumeReqRegs,goReg,
+ out_prepend_81}; // @[Cat.scala 31:58]
+ wire out_wimask_110 = &out_backMask_1[55:48]; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_111 = &out_backMask_1[63:56]; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_86 = {6'h0,resumeReqRegs,goReg,6'h0,resumeReqRegs,goReg,out_prepend_84}; // @[Cat.scala 31:58]
+ wire out_frontSel_110 = _out_backSel_T_1[110]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_104 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_110 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_208 = out_wivalid_1_104 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_209 = out_wivalid_1_104 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_210 = out_wivalid_1_104 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_211 = out_wivalid_1_104 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_212 = out_wivalid_1_104 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_213 = out_wivalid_1_104 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_214 = out_wivalid_1_104 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_215 = out_wivalid_1_104 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_177 = {programBufferMem_55,programBufferMem_54,programBufferMem_53,programBufferMem_52,
+ programBufferMem_51,programBufferMem_50,programBufferMem_49,programBufferMem_48}; // @[Cat.scala 31:58]
+ wire out_frontSel_106 = _out_backSel_T_1[106]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_200 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_106 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_304 = out_wivalid_1_200 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_305 = out_wivalid_1_200 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_306 = out_wivalid_1_200 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_307 = out_wivalid_1_200 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_308 = out_wivalid_1_200 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_309 = out_wivalid_1_200 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_310 = out_wivalid_1_200 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_311 = out_wivalid_1_200 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_261 = {programBufferMem_23,programBufferMem_22,programBufferMem_21,programBufferMem_20,
+ programBufferMem_19,programBufferMem_18,programBufferMem_17,programBufferMem_16}; // @[Cat.scala 31:58]
+ wire out_frontSel_109 = _out_backSel_T_1[109]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_410 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_109 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_514 = out_wivalid_1_410 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_515 = out_wivalid_1_410 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_516 = out_wivalid_1_410 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_517 = out_wivalid_1_410 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_518 = out_wivalid_1_410 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_519 = out_wivalid_1_410 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_520 = out_wivalid_1_410 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_521 = out_wivalid_1_410 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_444 = {programBufferMem_47,programBufferMem_46,programBufferMem_45,programBufferMem_44,
+ programBufferMem_43,programBufferMem_42,programBufferMem_41,programBufferMem_40}; // @[Cat.scala 31:58]
+ wire out_frontSel_105 = _out_backSel_T_1[105]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_491 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_105 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_595 = out_wivalid_1_491 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_596 = out_wivalid_1_491 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_597 = out_wivalid_1_491 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_598 = out_wivalid_1_491 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_599 = out_wivalid_1_491 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_600 = out_wivalid_1_491 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_601 = out_wivalid_1_491 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_602 = out_wivalid_1_491 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_514 = {programBufferMem_15,programBufferMem_14,programBufferMem_13,programBufferMem_12,
+ programBufferMem_11,programBufferMem_10,programBufferMem_9,programBufferMem_8}; // @[Cat.scala 31:58]
+ wire [63:0] out_prepend_673 = {abstractGeneratedMem_1,abstractGeneratedMem_0}; // @[Cat.scala 31:58]
+ wire out_frontSel_108 = _out_backSel_T_1[108]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_731 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_108 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_835 = out_wivalid_1_731 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_836 = out_wivalid_1_731 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_837 = out_wivalid_1_731 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_838 = out_wivalid_1_731 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_839 = out_wivalid_1_731 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_840 = out_wivalid_1_731 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_841 = out_wivalid_1_731 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_842 = out_wivalid_1_731 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_722 = {programBufferMem_39,programBufferMem_38,programBufferMem_37,programBufferMem_36,
+ programBufferMem_35,programBufferMem_34,programBufferMem_33,programBufferMem_32}; // @[Cat.scala 31:58]
+ wire out_frontSel_112 = _out_backSel_T_1[112]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_811 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_112 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_915 = out_wivalid_1_811 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_916 = out_wivalid_1_811 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_917 = out_wivalid_1_811 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_918 = out_wivalid_1_811 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_919 = out_wivalid_1_811 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_920 = out_wivalid_1_811 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_921 = out_wivalid_1_811 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_922 = out_wivalid_1_811 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_792 = {abstractDataMem_7,abstractDataMem_6,abstractDataMem_5,abstractDataMem_4,
+ abstractDataMem_3,abstractDataMem_2,abstractDataMem_1,abstractDataMem_0}; // @[Cat.scala 31:58]
+ wire out_frontSel_104 = _out_backSel_T_1[104]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_931 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_104 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1035 = out_wivalid_1_931 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1036 = out_wivalid_1_931 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1037 = out_wivalid_1_931 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1038 = out_wivalid_1_931 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1039 = out_wivalid_1_931 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1040 = out_wivalid_1_931 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1041 = out_wivalid_1_931 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1042 = out_wivalid_1_931 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_897 = {programBufferMem_7,programBufferMem_6,programBufferMem_5,programBufferMem_4,
+ programBufferMem_3,programBufferMem_2,programBufferMem_1,programBufferMem_0}; // @[Cat.scala 31:58]
+ wire out_frontSel_107 = _out_backSel_T_1[107]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_1067 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_107 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1171 = out_wivalid_1_1067 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1172 = out_wivalid_1_1067 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1173 = out_wivalid_1_1067 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1174 = out_wivalid_1_1067 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1175 = out_wivalid_1_1067 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1176 = out_wivalid_1_1067 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1177 = out_wivalid_1_1067 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1178 = out_wivalid_1_1067 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_1016 = {programBufferMem_31,programBufferMem_30,programBufferMem_29,programBufferMem_28,
+ programBufferMem_27,programBufferMem_26,programBufferMem_25,programBufferMem_24}; // @[Cat.scala 31:58]
+ wire out_frontSel_111 = _out_backSel_T_1[111]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1_1139 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_111 & out_findex_1
+ == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1243 = out_wivalid_1_1139 & out_wimask_104; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1244 = out_wivalid_1_1139 & out_wimask_105; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1245 = out_wivalid_1_1139 & out_wimask_106; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1246 = out_wivalid_1_1139 & out_wimask_107; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1247 = out_wivalid_1_1139 & out_wimask_108; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1248 = out_wivalid_1_1139 & out_wimask_109; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1249 = out_wivalid_1_1139 & out_wimask_110; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1250 = out_wivalid_1_1139 & out_wimask_111; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_1079 = {programBufferMem_63,programBufferMem_62,programBufferMem_61,programBufferMem_60,
+ programBufferMem_59,programBufferMem_58,programBufferMem_57,programBufferMem_56}; // @[Cat.scala 31:58]
+ wire _GEN_1511 = 8'h1 == out_iindex_1 ? _out_T_1266 : _out_T_1266; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1512 = 8'h2 == out_iindex_1 ? _out_T_1266 : _GEN_1511; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1513 = 8'h3 == out_iindex_1 ? _out_T_1266 : _GEN_1512; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1514 = 8'h4 == out_iindex_1 ? _out_T_1266 : _GEN_1513; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1515 = 8'h5 == out_iindex_1 ? _out_T_1266 : _GEN_1514; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1516 = 8'h6 == out_iindex_1 ? _out_T_1266 : _GEN_1515; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1517 = 8'h7 == out_iindex_1 ? _out_T_1266 : _GEN_1516; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1518 = 8'h8 == out_iindex_1 ? _out_T_1266 : _GEN_1517; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1519 = 8'h9 == out_iindex_1 ? _out_T_1266 : _GEN_1518; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1520 = 8'ha == out_iindex_1 ? _out_T_1266 : _GEN_1519; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1535 = 8'h19 == out_iindex_1 | (8'h18 == out_iindex_1 | (8'h17 == out_iindex_1 | (8'h16 == out_iindex_1 | (8'h15
+ == out_iindex_1 | (8'h14 == out_iindex_1 | (8'h13 == out_iindex_1 | (8'h12 == out_iindex_1 | (8'h11 == out_iindex_1
+ | (8'h10 == out_iindex_1 | (8'hf == out_iindex_1 | (8'he == out_iindex_1 | (8'hd == out_iindex_1 | (8'hc ==
+ out_iindex_1 | (8'hb == out_iindex_1 | _GEN_1520)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1542 = 8'h20 == out_iindex_1 ? _out_T_1342 : 8'h1f == out_iindex_1 | (8'h1e == out_iindex_1 | (8'h1d ==
+ out_iindex_1 | (8'h1c == out_iindex_1 | (8'h1b == out_iindex_1 | (8'h1a == out_iindex_1 | _GEN_1535))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1543 = 8'h21 == out_iindex_1 ? _out_T_1342 : _GEN_1542; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1558 = 8'h30 == out_iindex_1 | (8'h2f == out_iindex_1 | (8'h2e == out_iindex_1 | (8'h2d == out_iindex_1 | (8'h2c
+ == out_iindex_1 | (8'h2b == out_iindex_1 | (8'h2a == out_iindex_1 | (8'h29 == out_iindex_1 | (8'h28 == out_iindex_1
+ | (8'h27 == out_iindex_1 | (8'h26 == out_iindex_1 | (8'h25 == out_iindex_1 | (8'h24 == out_iindex_1 | (8'h23 ==
+ out_iindex_1 | (8'h22 == out_iindex_1 | _GEN_1543)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1573 = 8'h3f == out_iindex_1 | (8'h3e == out_iindex_1 | (8'h3d == out_iindex_1 | (8'h3c == out_iindex_1 | (8'h3b
+ == out_iindex_1 | (8'h3a == out_iindex_1 | (8'h39 == out_iindex_1 | (8'h38 == out_iindex_1 | (8'h37 == out_iindex_1
+ | (8'h36 == out_iindex_1 | (8'h35 == out_iindex_1 | (8'h34 == out_iindex_1 | (8'h33 == out_iindex_1 | (8'h32 ==
+ out_iindex_1 | (8'h31 == out_iindex_1 | _GEN_1558)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1588 = 8'h4e == out_iindex_1 | (8'h4d == out_iindex_1 | (8'h4c == out_iindex_1 | (8'h4b == out_iindex_1 | (8'h4a
+ == out_iindex_1 | (8'h49 == out_iindex_1 | (8'h48 == out_iindex_1 | (8'h47 == out_iindex_1 | (8'h46 == out_iindex_1
+ | (8'h45 == out_iindex_1 | (8'h44 == out_iindex_1 | (8'h43 == out_iindex_1 | (8'h42 == out_iindex_1 | (8'h41 ==
+ out_iindex_1 | (8'h40 == out_iindex_1 | _GEN_1573)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1603 = 8'h5d == out_iindex_1 | (8'h5c == out_iindex_1 | (8'h5b == out_iindex_1 | (8'h5a == out_iindex_1 | (8'h59
+ == out_iindex_1 | (8'h58 == out_iindex_1 | (8'h57 == out_iindex_1 | (8'h56 == out_iindex_1 | (8'h55 == out_iindex_1
+ | (8'h54 == out_iindex_1 | (8'h53 == out_iindex_1 | (8'h52 == out_iindex_1 | (8'h51 == out_iindex_1 | (8'h50 ==
+ out_iindex_1 | (8'h4f == out_iindex_1 | _GEN_1588)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1606 = 8'h60 == out_iindex_1 ? _out_T_1342 : 8'h5f == out_iindex_1 | (8'h5e == out_iindex_1 | _GEN_1603); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1613 = 8'h67 == out_iindex_1 ? _out_T_1342 : 8'h66 == out_iindex_1 | (8'h65 == out_iindex_1 | (8'h64 ==
+ out_iindex_1 | (8'h63 == out_iindex_1 | (8'h62 == out_iindex_1 | (8'h61 == out_iindex_1 | _GEN_1606))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1614 = 8'h68 == out_iindex_1 ? _out_T_1342 : _GEN_1613; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1615 = 8'h69 == out_iindex_1 ? _out_T_1342 : _GEN_1614; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1616 = 8'h6a == out_iindex_1 ? _out_T_1342 : _GEN_1615; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1617 = 8'h6b == out_iindex_1 ? _out_T_1342 : _GEN_1616; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1618 = 8'h6c == out_iindex_1 ? _out_T_1342 : _GEN_1617; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1619 = 8'h6d == out_iindex_1 ? _out_T_1342 : _GEN_1618; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1620 = 8'h6e == out_iindex_1 ? _out_T_1342 : _GEN_1619; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1621 = 8'h6f == out_iindex_1 ? _out_T_1342 : _GEN_1620; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1622 = 8'h70 == out_iindex_1 ? _out_T_1342 : _GEN_1621; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1637 = 8'h7f == out_iindex_1 | (8'h7e == out_iindex_1 | (8'h7d == out_iindex_1 | (8'h7c == out_iindex_1 | (8'h7b
+ == out_iindex_1 | (8'h7a == out_iindex_1 | (8'h79 == out_iindex_1 | (8'h78 == out_iindex_1 | (8'h77 == out_iindex_1
+ | (8'h76 == out_iindex_1 | (8'h75 == out_iindex_1 | (8'h74 == out_iindex_1 | (8'h73 == out_iindex_1 | (8'h72 ==
+ out_iindex_1 | (8'h71 == out_iindex_1 | _GEN_1622)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1638 = 8'h80 == out_iindex_1 ? _out_T_1342 : _GEN_1637; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1639 = 8'h81 == out_iindex_1 ? _out_T_1342 : _GEN_1638; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1640 = 8'h82 == out_iindex_1 ? _out_T_1342 : _GEN_1639; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1641 = 8'h83 == out_iindex_1 ? _out_T_1342 : _GEN_1640; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1642 = 8'h84 == out_iindex_1 ? _out_T_1342 : _GEN_1641; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1643 = 8'h85 == out_iindex_1 ? _out_T_1342 : _GEN_1642; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1644 = 8'h86 == out_iindex_1 ? _out_T_1342 : _GEN_1643; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1645 = 8'h87 == out_iindex_1 ? _out_T_1342 : _GEN_1644; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1646 = 8'h88 == out_iindex_1 ? _out_T_1342 : _GEN_1645; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1647 = 8'h89 == out_iindex_1 ? _out_T_1342 : _GEN_1646; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1648 = 8'h8a == out_iindex_1 ? _out_T_1342 : _GEN_1647; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1649 = 8'h8b == out_iindex_1 ? _out_T_1342 : _GEN_1648; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1650 = 8'h8c == out_iindex_1 ? _out_T_1342 : _GEN_1649; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1651 = 8'h8d == out_iindex_1 ? _out_T_1342 : _GEN_1650; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1652 = 8'h8e == out_iindex_1 ? _out_T_1342 : _GEN_1651; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1653 = 8'h8f == out_iindex_1 ? _out_T_1342 : _GEN_1652; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1654 = 8'h90 == out_iindex_1 ? _out_T_1342 : _GEN_1653; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1655 = 8'h91 == out_iindex_1 ? _out_T_1342 : _GEN_1654; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1656 = 8'h92 == out_iindex_1 ? _out_T_1342 : _GEN_1655; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1657 = 8'h93 == out_iindex_1 ? _out_T_1342 : _GEN_1656; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1658 = 8'h94 == out_iindex_1 ? _out_T_1342 : _GEN_1657; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1659 = 8'h95 == out_iindex_1 ? _out_T_1342 : _GEN_1658; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1660 = 8'h96 == out_iindex_1 ? _out_T_1342 : _GEN_1659; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1661 = 8'h97 == out_iindex_1 ? _out_T_1342 : _GEN_1660; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1662 = 8'h98 == out_iindex_1 ? _out_T_1342 : _GEN_1661; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1663 = 8'h99 == out_iindex_1 ? _out_T_1342 : _GEN_1662; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1664 = 8'h9a == out_iindex_1 ? _out_T_1342 : _GEN_1663; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1665 = 8'h9b == out_iindex_1 ? _out_T_1342 : _GEN_1664; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1666 = 8'h9c == out_iindex_1 ? _out_T_1342 : _GEN_1665; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1667 = 8'h9d == out_iindex_1 ? _out_T_1342 : _GEN_1666; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1668 = 8'h9e == out_iindex_1 ? _out_T_1342 : _GEN_1667; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1669 = 8'h9f == out_iindex_1 ? _out_T_1342 : _GEN_1668; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1670 = 8'ha0 == out_iindex_1 ? _out_T_1342 : _GEN_1669; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1671 = 8'ha1 == out_iindex_1 ? _out_T_1342 : _GEN_1670; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1672 = 8'ha2 == out_iindex_1 ? _out_T_1342 : _GEN_1671; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1673 = 8'ha3 == out_iindex_1 ? _out_T_1342 : _GEN_1672; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1674 = 8'ha4 == out_iindex_1 ? _out_T_1342 : _GEN_1673; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1675 = 8'ha5 == out_iindex_1 ? _out_T_1342 : _GEN_1674; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1676 = 8'ha6 == out_iindex_1 ? _out_T_1342 : _GEN_1675; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1677 = 8'ha7 == out_iindex_1 ? _out_T_1342 : _GEN_1676; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1678 = 8'ha8 == out_iindex_1 ? _out_T_1342 : _GEN_1677; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1679 = 8'ha9 == out_iindex_1 ? _out_T_1342 : _GEN_1678; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1680 = 8'haa == out_iindex_1 ? _out_T_1342 : _GEN_1679; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1681 = 8'hab == out_iindex_1 ? _out_T_1342 : _GEN_1680; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1682 = 8'hac == out_iindex_1 ? _out_T_1342 : _GEN_1681; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1683 = 8'had == out_iindex_1 ? _out_T_1342 : _GEN_1682; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1684 = 8'hae == out_iindex_1 ? _out_T_1342 : _GEN_1683; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1685 = 8'haf == out_iindex_1 ? _out_T_1342 : _GEN_1684; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1686 = 8'hb0 == out_iindex_1 ? _out_T_1342 : _GEN_1685; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1687 = 8'hb1 == out_iindex_1 ? _out_T_1342 : _GEN_1686; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1688 = 8'hb2 == out_iindex_1 ? _out_T_1342 : _GEN_1687; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1689 = 8'hb3 == out_iindex_1 ? _out_T_1342 : _GEN_1688; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1690 = 8'hb4 == out_iindex_1 ? _out_T_1342 : _GEN_1689; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1691 = 8'hb5 == out_iindex_1 ? _out_T_1342 : _GEN_1690; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1692 = 8'hb6 == out_iindex_1 ? _out_T_1342 : _GEN_1691; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1693 = 8'hb7 == out_iindex_1 ? _out_T_1342 : _GEN_1692; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1694 = 8'hb8 == out_iindex_1 ? _out_T_1342 : _GEN_1693; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1695 = 8'hb9 == out_iindex_1 ? _out_T_1342 : _GEN_1694; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1696 = 8'hba == out_iindex_1 ? _out_T_1342 : _GEN_1695; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1697 = 8'hbb == out_iindex_1 ? _out_T_1342 : _GEN_1696; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1698 = 8'hbc == out_iindex_1 ? _out_T_1342 : _GEN_1697; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1699 = 8'hbd == out_iindex_1 ? _out_T_1342 : _GEN_1698; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1700 = 8'hbe == out_iindex_1 ? _out_T_1342 : _GEN_1699; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1701 = 8'hbf == out_iindex_1 ? _out_T_1342 : _GEN_1700; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1702 = 8'hc0 == out_iindex_1 ? _out_T_1342 : _GEN_1701; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1703 = 8'hc1 == out_iindex_1 ? _out_T_1342 : _GEN_1702; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1704 = 8'hc2 == out_iindex_1 ? _out_T_1342 : _GEN_1703; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1705 = 8'hc3 == out_iindex_1 ? _out_T_1342 : _GEN_1704; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1706 = 8'hc4 == out_iindex_1 ? _out_T_1342 : _GEN_1705; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1707 = 8'hc5 == out_iindex_1 ? _out_T_1342 : _GEN_1706; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1708 = 8'hc6 == out_iindex_1 ? _out_T_1342 : _GEN_1707; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1709 = 8'hc7 == out_iindex_1 ? _out_T_1342 : _GEN_1708; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1710 = 8'hc8 == out_iindex_1 ? _out_T_1342 : _GEN_1709; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1711 = 8'hc9 == out_iindex_1 ? _out_T_1342 : _GEN_1710; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1712 = 8'hca == out_iindex_1 ? _out_T_1342 : _GEN_1711; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1713 = 8'hcb == out_iindex_1 ? _out_T_1342 : _GEN_1712; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1714 = 8'hcc == out_iindex_1 ? _out_T_1342 : _GEN_1713; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1715 = 8'hcd == out_iindex_1 ? _out_T_1342 : _GEN_1714; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1716 = 8'hce == out_iindex_1 ? _out_T_1342 : _GEN_1715; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1717 = 8'hcf == out_iindex_1 ? _out_T_1342 : _GEN_1716; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1718 = 8'hd0 == out_iindex_1 ? _out_T_1342 : _GEN_1717; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1719 = 8'hd1 == out_iindex_1 ? _out_T_1342 : _GEN_1718; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1720 = 8'hd2 == out_iindex_1 ? _out_T_1342 : _GEN_1719; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1721 = 8'hd3 == out_iindex_1 ? _out_T_1342 : _GEN_1720; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1722 = 8'hd4 == out_iindex_1 ? _out_T_1342 : _GEN_1721; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1723 = 8'hd5 == out_iindex_1 ? _out_T_1342 : _GEN_1722; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1724 = 8'hd6 == out_iindex_1 ? _out_T_1342 : _GEN_1723; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1725 = 8'hd7 == out_iindex_1 ? _out_T_1342 : _GEN_1724; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1726 = 8'hd8 == out_iindex_1 ? _out_T_1342 : _GEN_1725; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1727 = 8'hd9 == out_iindex_1 ? _out_T_1342 : _GEN_1726; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1728 = 8'hda == out_iindex_1 ? _out_T_1342 : _GEN_1727; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1729 = 8'hdb == out_iindex_1 ? _out_T_1342 : _GEN_1728; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1730 = 8'hdc == out_iindex_1 ? _out_T_1342 : _GEN_1729; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1731 = 8'hdd == out_iindex_1 ? _out_T_1342 : _GEN_1730; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1732 = 8'hde == out_iindex_1 ? _out_T_1342 : _GEN_1731; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1733 = 8'hdf == out_iindex_1 ? _out_T_1342 : _GEN_1732; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1734 = 8'he0 == out_iindex_1 ? _out_T_1342 : _GEN_1733; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1735 = 8'he1 == out_iindex_1 ? _out_T_1342 : _GEN_1734; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1736 = 8'he2 == out_iindex_1 ? _out_T_1342 : _GEN_1735; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1737 = 8'he3 == out_iindex_1 ? _out_T_1342 : _GEN_1736; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1738 = 8'he4 == out_iindex_1 ? _out_T_1342 : _GEN_1737; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1739 = 8'he5 == out_iindex_1 ? _out_T_1342 : _GEN_1738; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1740 = 8'he6 == out_iindex_1 ? _out_T_1342 : _GEN_1739; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1741 = 8'he7 == out_iindex_1 ? _out_T_1342 : _GEN_1740; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1742 = 8'he8 == out_iindex_1 ? _out_T_1342 : _GEN_1741; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1743 = 8'he9 == out_iindex_1 ? _out_T_1342 : _GEN_1742; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1744 = 8'hea == out_iindex_1 ? _out_T_1342 : _GEN_1743; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1745 = 8'heb == out_iindex_1 ? _out_T_1342 : _GEN_1744; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1746 = 8'hec == out_iindex_1 ? _out_T_1342 : _GEN_1745; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1747 = 8'hed == out_iindex_1 ? _out_T_1342 : _GEN_1746; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1748 = 8'hee == out_iindex_1 ? _out_T_1342 : _GEN_1747; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1749 = 8'hef == out_iindex_1 ? _out_T_1342 : _GEN_1748; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1750 = 8'hf0 == out_iindex_1 ? _out_T_1342 : _GEN_1749; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1751 = 8'hf1 == out_iindex_1 ? _out_T_1342 : _GEN_1750; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1752 = 8'hf2 == out_iindex_1 ? _out_T_1342 : _GEN_1751; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1753 = 8'hf3 == out_iindex_1 ? _out_T_1342 : _GEN_1752; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1754 = 8'hf4 == out_iindex_1 ? _out_T_1342 : _GEN_1753; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1755 = 8'hf5 == out_iindex_1 ? _out_T_1342 : _GEN_1754; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1756 = 8'hf6 == out_iindex_1 ? _out_T_1342 : _GEN_1755; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1757 = 8'hf7 == out_iindex_1 ? _out_T_1342 : _GEN_1756; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1758 = 8'hf8 == out_iindex_1 ? _out_T_1342 : _GEN_1757; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1759 = 8'hf9 == out_iindex_1 ? _out_T_1342 : _GEN_1758; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1760 = 8'hfa == out_iindex_1 ? _out_T_1342 : _GEN_1759; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1761 = 8'hfb == out_iindex_1 ? _out_T_1342 : _GEN_1760; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1762 = 8'hfc == out_iindex_1 ? _out_T_1342 : _GEN_1761; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1763 = 8'hfd == out_iindex_1 ? _out_T_1342 : _GEN_1762; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1764 = 8'hfe == out_iindex_1 ? _out_T_1342 : _GEN_1763; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_1765 = 8'hff == out_iindex_1 ? _out_T_1342 : _GEN_1764; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1767 = 8'h1 == out_iindex_1 ? 64'hff0000f0440006f : 64'h380006f00c0006f; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1768 = 8'h2 == out_iindex_1 ? 64'hf14024737b241073 : _GEN_1767; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1769 = 8'h3 == out_iindex_1 ? 64'h4004440310802023 : _GEN_1768; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1770 = 8'h4 == out_iindex_1 ? 64'hfe0408e300347413 : _GEN_1769; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1771 = 8'h5 == out_iindex_1 ? 64'h4086300147413 : _GEN_1770; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1772 = 8'h6 == out_iindex_1 ? 64'h100022237b202473 : _GEN_1771; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1773 = 8'h7 == out_iindex_1 ? 64'hf140247330000067 : _GEN_1772; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1774 = 8'h8 == out_iindex_1 ? 64'h7b20247310802423 : _GEN_1773; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1775 = 8'h9 == out_iindex_1 ? 64'h100026237b200073 : _GEN_1774; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1776 = 8'ha == out_iindex_1 ? 64'h100073 : _GEN_1775; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1777 = 8'hb == out_iindex_1 ? 64'h0 : _GEN_1776; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1778 = 8'hc == out_iindex_1 ? 64'h0 : _GEN_1777; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1779 = 8'hd == out_iindex_1 ? 64'h0 : _GEN_1778; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1780 = 8'he == out_iindex_1 ? 64'h0 : _GEN_1779; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1781 = 8'hf == out_iindex_1 ? 64'h0 : _GEN_1780; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1782 = 8'h10 == out_iindex_1 ? 64'h0 : _GEN_1781; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1783 = 8'h11 == out_iindex_1 ? 64'h0 : _GEN_1782; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1784 = 8'h12 == out_iindex_1 ? 64'h0 : _GEN_1783; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1785 = 8'h13 == out_iindex_1 ? 64'h0 : _GEN_1784; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1786 = 8'h14 == out_iindex_1 ? 64'h0 : _GEN_1785; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1787 = 8'h15 == out_iindex_1 ? 64'h0 : _GEN_1786; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1788 = 8'h16 == out_iindex_1 ? 64'h0 : _GEN_1787; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1789 = 8'h17 == out_iindex_1 ? 64'h0 : _GEN_1788; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1790 = 8'h18 == out_iindex_1 ? 64'h0 : _GEN_1789; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1791 = 8'h19 == out_iindex_1 ? 64'h0 : _GEN_1790; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1792 = 8'h1a == out_iindex_1 ? 64'h0 : _GEN_1791; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1793 = 8'h1b == out_iindex_1 ? 64'h0 : _GEN_1792; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1794 = 8'h1c == out_iindex_1 ? 64'h0 : _GEN_1793; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1795 = 8'h1d == out_iindex_1 ? 64'h0 : _GEN_1794; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1796 = 8'h1e == out_iindex_1 ? 64'h0 : _GEN_1795; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1797 = 8'h1f == out_iindex_1 ? 64'h0 : _GEN_1796; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1798 = 8'h20 == out_iindex_1 ? 64'h0 : _GEN_1797; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1799 = 8'h21 == out_iindex_1 ? 64'h0 : _GEN_1798; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1800 = 8'h22 == out_iindex_1 ? 64'h0 : _GEN_1799; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1801 = 8'h23 == out_iindex_1 ? 64'h0 : _GEN_1800; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1802 = 8'h24 == out_iindex_1 ? 64'h0 : _GEN_1801; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1803 = 8'h25 == out_iindex_1 ? 64'h0 : _GEN_1802; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1804 = 8'h26 == out_iindex_1 ? 64'h0 : _GEN_1803; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1805 = 8'h27 == out_iindex_1 ? 64'h0 : _GEN_1804; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1806 = 8'h28 == out_iindex_1 ? 64'h0 : _GEN_1805; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1807 = 8'h29 == out_iindex_1 ? 64'h0 : _GEN_1806; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1808 = 8'h2a == out_iindex_1 ? 64'h0 : _GEN_1807; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1809 = 8'h2b == out_iindex_1 ? 64'h0 : _GEN_1808; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1810 = 8'h2c == out_iindex_1 ? 64'h0 : _GEN_1809; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1811 = 8'h2d == out_iindex_1 ? 64'h0 : _GEN_1810; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1812 = 8'h2e == out_iindex_1 ? 64'h0 : _GEN_1811; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1813 = 8'h2f == out_iindex_1 ? 64'h0 : _GEN_1812; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1814 = 8'h30 == out_iindex_1 ? 64'h0 : _GEN_1813; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1815 = 8'h31 == out_iindex_1 ? 64'h0 : _GEN_1814; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1816 = 8'h32 == out_iindex_1 ? 64'h0 : _GEN_1815; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1817 = 8'h33 == out_iindex_1 ? 64'h0 : _GEN_1816; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1818 = 8'h34 == out_iindex_1 ? 64'h0 : _GEN_1817; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1819 = 8'h35 == out_iindex_1 ? 64'h0 : _GEN_1818; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1820 = 8'h36 == out_iindex_1 ? 64'h0 : _GEN_1819; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1821 = 8'h37 == out_iindex_1 ? 64'h0 : _GEN_1820; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1822 = 8'h38 == out_iindex_1 ? 64'h0 : _GEN_1821; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1823 = 8'h39 == out_iindex_1 ? 64'h0 : _GEN_1822; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1824 = 8'h3a == out_iindex_1 ? 64'h0 : _GEN_1823; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1825 = 8'h3b == out_iindex_1 ? 64'h0 : _GEN_1824; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1826 = 8'h3c == out_iindex_1 ? 64'h0 : _GEN_1825; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1827 = 8'h3d == out_iindex_1 ? 64'h0 : _GEN_1826; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1828 = 8'h3e == out_iindex_1 ? 64'h0 : _GEN_1827; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1829 = 8'h3f == out_iindex_1 ? 64'h0 : _GEN_1828; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1830 = 8'h40 == out_iindex_1 ? 64'h0 : _GEN_1829; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1831 = 8'h41 == out_iindex_1 ? 64'h0 : _GEN_1830; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1832 = 8'h42 == out_iindex_1 ? 64'h0 : _GEN_1831; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1833 = 8'h43 == out_iindex_1 ? 64'h0 : _GEN_1832; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1834 = 8'h44 == out_iindex_1 ? 64'h0 : _GEN_1833; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1835 = 8'h45 == out_iindex_1 ? 64'h0 : _GEN_1834; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1836 = 8'h46 == out_iindex_1 ? 64'h0 : _GEN_1835; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1837 = 8'h47 == out_iindex_1 ? 64'h0 : _GEN_1836; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1838 = 8'h48 == out_iindex_1 ? 64'h0 : _GEN_1837; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1839 = 8'h49 == out_iindex_1 ? 64'h0 : _GEN_1838; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1840 = 8'h4a == out_iindex_1 ? 64'h0 : _GEN_1839; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1841 = 8'h4b == out_iindex_1 ? 64'h0 : _GEN_1840; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1842 = 8'h4c == out_iindex_1 ? 64'h0 : _GEN_1841; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1843 = 8'h4d == out_iindex_1 ? 64'h0 : _GEN_1842; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1844 = 8'h4e == out_iindex_1 ? 64'h0 : _GEN_1843; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1845 = 8'h4f == out_iindex_1 ? 64'h0 : _GEN_1844; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1846 = 8'h50 == out_iindex_1 ? 64'h0 : _GEN_1845; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1847 = 8'h51 == out_iindex_1 ? 64'h0 : _GEN_1846; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1848 = 8'h52 == out_iindex_1 ? 64'h0 : _GEN_1847; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1849 = 8'h53 == out_iindex_1 ? 64'h0 : _GEN_1848; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1850 = 8'h54 == out_iindex_1 ? 64'h0 : _GEN_1849; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1851 = 8'h55 == out_iindex_1 ? 64'h0 : _GEN_1850; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1852 = 8'h56 == out_iindex_1 ? 64'h0 : _GEN_1851; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1853 = 8'h57 == out_iindex_1 ? 64'h0 : _GEN_1852; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1854 = 8'h58 == out_iindex_1 ? 64'h0 : _GEN_1853; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1855 = 8'h59 == out_iindex_1 ? 64'h0 : _GEN_1854; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1856 = 8'h5a == out_iindex_1 ? 64'h0 : _GEN_1855; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1857 = 8'h5b == out_iindex_1 ? 64'h0 : _GEN_1856; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1858 = 8'h5c == out_iindex_1 ? 64'h0 : _GEN_1857; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1859 = 8'h5d == out_iindex_1 ? 64'h0 : _GEN_1858; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1860 = 8'h5e == out_iindex_1 ? 64'h0 : _GEN_1859; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1861 = 8'h5f == out_iindex_1 ? 64'h0 : _GEN_1860; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1862 = 8'h60 == out_iindex_1 ? 64'h380006f : _GEN_1861; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1863 = 8'h61 == out_iindex_1 ? 64'h0 : _GEN_1862; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1864 = 8'h62 == out_iindex_1 ? 64'h0 : _GEN_1863; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1865 = 8'h63 == out_iindex_1 ? 64'h0 : _GEN_1864; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1866 = 8'h64 == out_iindex_1 ? 64'h0 : _GEN_1865; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1867 = 8'h65 == out_iindex_1 ? 64'h0 : _GEN_1866; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1868 = 8'h66 == out_iindex_1 ? 64'h0 : _GEN_1867; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1869 = 8'h67 == out_iindex_1 ? out_prepend_673 : _GEN_1868; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1870 = 8'h68 == out_iindex_1 ? out_prepend_897 : _GEN_1869; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1871 = 8'h69 == out_iindex_1 ? out_prepend_514 : _GEN_1870; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1872 = 8'h6a == out_iindex_1 ? out_prepend_261 : _GEN_1871; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1873 = 8'h6b == out_iindex_1 ? out_prepend_1016 : _GEN_1872; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1874 = 8'h6c == out_iindex_1 ? out_prepend_722 : _GEN_1873; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1875 = 8'h6d == out_iindex_1 ? out_prepend_444 : _GEN_1874; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1876 = 8'h6e == out_iindex_1 ? out_prepend_177 : _GEN_1875; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1877 = 8'h6f == out_iindex_1 ? out_prepend_1079 : _GEN_1876; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1878 = 8'h70 == out_iindex_1 ? out_prepend_792 : _GEN_1877; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1879 = 8'h71 == out_iindex_1 ? 64'h0 : _GEN_1878; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1880 = 8'h72 == out_iindex_1 ? 64'h0 : _GEN_1879; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1881 = 8'h73 == out_iindex_1 ? 64'h0 : _GEN_1880; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1882 = 8'h74 == out_iindex_1 ? 64'h0 : _GEN_1881; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1883 = 8'h75 == out_iindex_1 ? 64'h0 : _GEN_1882; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1884 = 8'h76 == out_iindex_1 ? 64'h0 : _GEN_1883; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1885 = 8'h77 == out_iindex_1 ? 64'h0 : _GEN_1884; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1886 = 8'h78 == out_iindex_1 ? 64'h0 : _GEN_1885; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1887 = 8'h79 == out_iindex_1 ? 64'h0 : _GEN_1886; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1888 = 8'h7a == out_iindex_1 ? 64'h0 : _GEN_1887; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1889 = 8'h7b == out_iindex_1 ? 64'h0 : _GEN_1888; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1890 = 8'h7c == out_iindex_1 ? 64'h0 : _GEN_1889; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1891 = 8'h7d == out_iindex_1 ? 64'h0 : _GEN_1890; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1892 = 8'h7e == out_iindex_1 ? 64'h0 : _GEN_1891; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1893 = 8'h7f == out_iindex_1 ? 64'h0 : _GEN_1892; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1894 = 8'h80 == out_iindex_1 ? out_prepend_86 : _GEN_1893; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1895 = 8'h81 == out_iindex_1 ? out_prepend_86 : _GEN_1894; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1896 = 8'h82 == out_iindex_1 ? out_prepend_86 : _GEN_1895; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1897 = 8'h83 == out_iindex_1 ? out_prepend_86 : _GEN_1896; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1898 = 8'h84 == out_iindex_1 ? out_prepend_86 : _GEN_1897; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1899 = 8'h85 == out_iindex_1 ? out_prepend_86 : _GEN_1898; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1900 = 8'h86 == out_iindex_1 ? out_prepend_86 : _GEN_1899; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1901 = 8'h87 == out_iindex_1 ? out_prepend_86 : _GEN_1900; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1902 = 8'h88 == out_iindex_1 ? out_prepend_86 : _GEN_1901; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1903 = 8'h89 == out_iindex_1 ? out_prepend_86 : _GEN_1902; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1904 = 8'h8a == out_iindex_1 ? out_prepend_86 : _GEN_1903; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1905 = 8'h8b == out_iindex_1 ? out_prepend_86 : _GEN_1904; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1906 = 8'h8c == out_iindex_1 ? out_prepend_86 : _GEN_1905; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1907 = 8'h8d == out_iindex_1 ? out_prepend_86 : _GEN_1906; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1908 = 8'h8e == out_iindex_1 ? out_prepend_86 : _GEN_1907; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1909 = 8'h8f == out_iindex_1 ? out_prepend_86 : _GEN_1908; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1910 = 8'h90 == out_iindex_1 ? out_prepend_86 : _GEN_1909; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1911 = 8'h91 == out_iindex_1 ? out_prepend_86 : _GEN_1910; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1912 = 8'h92 == out_iindex_1 ? out_prepend_86 : _GEN_1911; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1913 = 8'h93 == out_iindex_1 ? out_prepend_86 : _GEN_1912; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1914 = 8'h94 == out_iindex_1 ? out_prepend_86 : _GEN_1913; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1915 = 8'h95 == out_iindex_1 ? out_prepend_86 : _GEN_1914; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1916 = 8'h96 == out_iindex_1 ? out_prepend_86 : _GEN_1915; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1917 = 8'h97 == out_iindex_1 ? out_prepend_86 : _GEN_1916; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1918 = 8'h98 == out_iindex_1 ? out_prepend_86 : _GEN_1917; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1919 = 8'h99 == out_iindex_1 ? out_prepend_86 : _GEN_1918; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1920 = 8'h9a == out_iindex_1 ? out_prepend_86 : _GEN_1919; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1921 = 8'h9b == out_iindex_1 ? out_prepend_86 : _GEN_1920; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1922 = 8'h9c == out_iindex_1 ? out_prepend_86 : _GEN_1921; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1923 = 8'h9d == out_iindex_1 ? out_prepend_86 : _GEN_1922; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1924 = 8'h9e == out_iindex_1 ? out_prepend_86 : _GEN_1923; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1925 = 8'h9f == out_iindex_1 ? out_prepend_86 : _GEN_1924; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1926 = 8'ha0 == out_iindex_1 ? out_prepend_86 : _GEN_1925; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1927 = 8'ha1 == out_iindex_1 ? out_prepend_86 : _GEN_1926; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1928 = 8'ha2 == out_iindex_1 ? out_prepend_86 : _GEN_1927; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1929 = 8'ha3 == out_iindex_1 ? out_prepend_86 : _GEN_1928; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1930 = 8'ha4 == out_iindex_1 ? out_prepend_86 : _GEN_1929; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1931 = 8'ha5 == out_iindex_1 ? out_prepend_86 : _GEN_1930; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1932 = 8'ha6 == out_iindex_1 ? out_prepend_86 : _GEN_1931; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1933 = 8'ha7 == out_iindex_1 ? out_prepend_86 : _GEN_1932; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1934 = 8'ha8 == out_iindex_1 ? out_prepend_86 : _GEN_1933; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1935 = 8'ha9 == out_iindex_1 ? out_prepend_86 : _GEN_1934; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1936 = 8'haa == out_iindex_1 ? out_prepend_86 : _GEN_1935; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1937 = 8'hab == out_iindex_1 ? out_prepend_86 : _GEN_1936; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1938 = 8'hac == out_iindex_1 ? out_prepend_86 : _GEN_1937; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1939 = 8'had == out_iindex_1 ? out_prepend_86 : _GEN_1938; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1940 = 8'hae == out_iindex_1 ? out_prepend_86 : _GEN_1939; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1941 = 8'haf == out_iindex_1 ? out_prepend_86 : _GEN_1940; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1942 = 8'hb0 == out_iindex_1 ? out_prepend_86 : _GEN_1941; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1943 = 8'hb1 == out_iindex_1 ? out_prepend_86 : _GEN_1942; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1944 = 8'hb2 == out_iindex_1 ? out_prepend_86 : _GEN_1943; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1945 = 8'hb3 == out_iindex_1 ? out_prepend_86 : _GEN_1944; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1946 = 8'hb4 == out_iindex_1 ? out_prepend_86 : _GEN_1945; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1947 = 8'hb5 == out_iindex_1 ? out_prepend_86 : _GEN_1946; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1948 = 8'hb6 == out_iindex_1 ? out_prepend_86 : _GEN_1947; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1949 = 8'hb7 == out_iindex_1 ? out_prepend_86 : _GEN_1948; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1950 = 8'hb8 == out_iindex_1 ? out_prepend_86 : _GEN_1949; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1951 = 8'hb9 == out_iindex_1 ? out_prepend_86 : _GEN_1950; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1952 = 8'hba == out_iindex_1 ? out_prepend_86 : _GEN_1951; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1953 = 8'hbb == out_iindex_1 ? out_prepend_86 : _GEN_1952; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1954 = 8'hbc == out_iindex_1 ? out_prepend_86 : _GEN_1953; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1955 = 8'hbd == out_iindex_1 ? out_prepend_86 : _GEN_1954; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1956 = 8'hbe == out_iindex_1 ? out_prepend_86 : _GEN_1955; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1957 = 8'hbf == out_iindex_1 ? out_prepend_86 : _GEN_1956; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1958 = 8'hc0 == out_iindex_1 ? out_prepend_86 : _GEN_1957; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1959 = 8'hc1 == out_iindex_1 ? out_prepend_86 : _GEN_1958; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1960 = 8'hc2 == out_iindex_1 ? out_prepend_86 : _GEN_1959; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1961 = 8'hc3 == out_iindex_1 ? out_prepend_86 : _GEN_1960; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1962 = 8'hc4 == out_iindex_1 ? out_prepend_86 : _GEN_1961; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1963 = 8'hc5 == out_iindex_1 ? out_prepend_86 : _GEN_1962; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1964 = 8'hc6 == out_iindex_1 ? out_prepend_86 : _GEN_1963; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1965 = 8'hc7 == out_iindex_1 ? out_prepend_86 : _GEN_1964; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1966 = 8'hc8 == out_iindex_1 ? out_prepend_86 : _GEN_1965; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1967 = 8'hc9 == out_iindex_1 ? out_prepend_86 : _GEN_1966; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1968 = 8'hca == out_iindex_1 ? out_prepend_86 : _GEN_1967; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1969 = 8'hcb == out_iindex_1 ? out_prepend_86 : _GEN_1968; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1970 = 8'hcc == out_iindex_1 ? out_prepend_86 : _GEN_1969; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1971 = 8'hcd == out_iindex_1 ? out_prepend_86 : _GEN_1970; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1972 = 8'hce == out_iindex_1 ? out_prepend_86 : _GEN_1971; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1973 = 8'hcf == out_iindex_1 ? out_prepend_86 : _GEN_1972; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1974 = 8'hd0 == out_iindex_1 ? out_prepend_86 : _GEN_1973; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1975 = 8'hd1 == out_iindex_1 ? out_prepend_86 : _GEN_1974; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1976 = 8'hd2 == out_iindex_1 ? out_prepend_86 : _GEN_1975; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1977 = 8'hd3 == out_iindex_1 ? out_prepend_86 : _GEN_1976; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1978 = 8'hd4 == out_iindex_1 ? out_prepend_86 : _GEN_1977; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1979 = 8'hd5 == out_iindex_1 ? out_prepend_86 : _GEN_1978; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1980 = 8'hd6 == out_iindex_1 ? out_prepend_86 : _GEN_1979; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1981 = 8'hd7 == out_iindex_1 ? out_prepend_86 : _GEN_1980; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1982 = 8'hd8 == out_iindex_1 ? out_prepend_86 : _GEN_1981; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1983 = 8'hd9 == out_iindex_1 ? out_prepend_86 : _GEN_1982; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1984 = 8'hda == out_iindex_1 ? out_prepend_86 : _GEN_1983; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1985 = 8'hdb == out_iindex_1 ? out_prepend_86 : _GEN_1984; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1986 = 8'hdc == out_iindex_1 ? out_prepend_86 : _GEN_1985; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1987 = 8'hdd == out_iindex_1 ? out_prepend_86 : _GEN_1986; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1988 = 8'hde == out_iindex_1 ? out_prepend_86 : _GEN_1987; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1989 = 8'hdf == out_iindex_1 ? out_prepend_86 : _GEN_1988; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1990 = 8'he0 == out_iindex_1 ? out_prepend_86 : _GEN_1989; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1991 = 8'he1 == out_iindex_1 ? out_prepend_86 : _GEN_1990; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1992 = 8'he2 == out_iindex_1 ? out_prepend_86 : _GEN_1991; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1993 = 8'he3 == out_iindex_1 ? out_prepend_86 : _GEN_1992; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1994 = 8'he4 == out_iindex_1 ? out_prepend_86 : _GEN_1993; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1995 = 8'he5 == out_iindex_1 ? out_prepend_86 : _GEN_1994; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1996 = 8'he6 == out_iindex_1 ? out_prepend_86 : _GEN_1995; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1997 = 8'he7 == out_iindex_1 ? out_prepend_86 : _GEN_1996; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1998 = 8'he8 == out_iindex_1 ? out_prepend_86 : _GEN_1997; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_1999 = 8'he9 == out_iindex_1 ? out_prepend_86 : _GEN_1998; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2000 = 8'hea == out_iindex_1 ? out_prepend_86 : _GEN_1999; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2001 = 8'heb == out_iindex_1 ? out_prepend_86 : _GEN_2000; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2002 = 8'hec == out_iindex_1 ? out_prepend_86 : _GEN_2001; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2003 = 8'hed == out_iindex_1 ? out_prepend_86 : _GEN_2002; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2004 = 8'hee == out_iindex_1 ? out_prepend_86 : _GEN_2003; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2005 = 8'hef == out_iindex_1 ? out_prepend_86 : _GEN_2004; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2006 = 8'hf0 == out_iindex_1 ? out_prepend_86 : _GEN_2005; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2007 = 8'hf1 == out_iindex_1 ? out_prepend_86 : _GEN_2006; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2008 = 8'hf2 == out_iindex_1 ? out_prepend_86 : _GEN_2007; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2009 = 8'hf3 == out_iindex_1 ? out_prepend_86 : _GEN_2008; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2010 = 8'hf4 == out_iindex_1 ? out_prepend_86 : _GEN_2009; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2011 = 8'hf5 == out_iindex_1 ? out_prepend_86 : _GEN_2010; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2012 = 8'hf6 == out_iindex_1 ? out_prepend_86 : _GEN_2011; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2013 = 8'hf7 == out_iindex_1 ? out_prepend_86 : _GEN_2012; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2014 = 8'hf8 == out_iindex_1 ? out_prepend_86 : _GEN_2013; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2015 = 8'hf9 == out_iindex_1 ? out_prepend_86 : _GEN_2014; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2016 = 8'hfa == out_iindex_1 ? out_prepend_86 : _GEN_2015; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2017 = 8'hfb == out_iindex_1 ? out_prepend_86 : _GEN_2016; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2018 = 8'hfc == out_iindex_1 ? out_prepend_86 : _GEN_2017; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2019 = 8'hfd == out_iindex_1 ? out_prepend_86 : _GEN_2018; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2020 = 8'hfe == out_iindex_1 ? out_prepend_86 : _GEN_2019; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_2021 = 8'hff == out_iindex_1 ? out_prepend_86 : _GEN_2020; // @[MuxLiteral.scala 48:{10,10}]
+ wire [1:0] _GEN_2107 = commandRegBadHaltResume ? 2'h0 : 2'h2; // @[Debug.scala 1691:43 1693:22]
+ wire [1:0] _GEN_2113 = ~goReg & out_f_woready_631 ? 2'h0 : ctrlStateReg; // @[Debug.scala 1707:116 1708:22]
+ wire [1:0] _GEN_2114 = out_f_woready_449 ? 2'h0 : _GEN_2113; // @[Debug.scala 1710:31 1712:24]
+ wire _T_1409 = ctrlStateReg == 2'h3; // @[Debug.scala 1715:30]
+ wire _GEN_2266 = _errorBusy_T & ~_T_1399; // @[Debug.scala 1711:15]
+ TLMonitor_50 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ TLMonitor_51 monitor_1 ( // @[Nodes.scala 24:25]
+ .clock(monitor_1_clock),
+ .reset(monitor_1_reset),
+ .io_in_a_ready(monitor_1_io_in_a_ready),
+ .io_in_a_valid(monitor_1_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_1_io_in_d_ready),
+ .io_in_d_valid(monitor_1_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_1_io_in_d_bits_source)
+ );
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 hartIsInResetSync_0_debug_hartReset_0 ( // @[ShiftReg.scala 45:23]
+ .clock(hartIsInResetSync_0_debug_hartReset_0_clock),
+ .reset(hartIsInResetSync_0_debug_hartReset_0_reset),
+ .io_d(hartIsInResetSync_0_debug_hartReset_0_io_d),
+ .io_q(hartIsInResetSync_0_debug_hartReset_0_io_q)
+ );
+ assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign auto_tl_in_d_bits_opcode = {{2'd0}, in_1_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_in_d_bits_data = _GEN_1765 ? _GEN_2021 : 64'h0; // @[RegisterRouter.scala 83:24]
+ assign auto_dmi_in_a_ready = auto_dmi_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign auto_dmi_in_d_valid = auto_dmi_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign auto_dmi_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign auto_dmi_in_d_bits_size = auto_dmi_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_dmi_in_d_bits_source = auto_dmi_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_dmi_in_d_bits_data = _GEN_300 ? _GEN_332 : 32'h0; // @[RegisterRouter.scala 83:24]
+ assign io_innerCtrl_ready = 1'h1; // @[Debug.scala 836:24]
+ assign io_hgDebugInt_0 = hrDebugIntReg_0; // @[package.scala 66:75]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_dmi_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_a_valid = auto_dmi_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_dmi_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_dmi_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_dmi_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_dmi_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_dmi_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_dmi_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_dmi_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_dmi_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_dmi_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = auto_dmi_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_bits_source = auto_dmi_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_clock = clock;
+ assign monitor_1_reset = reset;
+ assign monitor_1_io_in_a_ready = auto_tl_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign monitor_1_io_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_valid = auto_tl_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign monitor_1_io_in_d_bits_opcode = {{2'd0}, in_1_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_1_io_in_d_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_1_io_in_d_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign hartIsInResetSync_0_debug_hartReset_0_clock = clock;
+ assign hartIsInResetSync_0_debug_hartReset_0_reset = reset;
+ assign hartIsInResetSync_0_debug_hartReset_0_io_d = io_hartIsInReset_0; // @[ShiftReg.scala 47:16]
+ always @(posedge clock) begin
+ haltedBitRegs <= _GEN_65[0];
+ resumeReqRegs <= _GEN_66[0];
+ if (_T_1) begin // @[Debug.scala 919:44]
+ haveResetBitRegs <= 1'h0; // @[Debug.scala 920:24]
+ end else if (_T_4 & io_innerCtrl_bits_ackhavereset) begin // @[Debug.scala 922:68]
+ haveResetBitRegs <= haveResetBitRegs & _resumeAcks_T_1 | hartIsInResetSync_0; // @[Debug.scala 923:26]
+ end else begin
+ haveResetBitRegs <= haveResetBitRegs | hartIsInResetSync_0; // @[Debug.scala 925:26]
+ end
+ if (reset) begin // @[Debug.scala 854:29]
+ hrmaskReg_0 <= 1'h0; // @[Debug.scala 854:29]
+ end else if (~io_dmactive) begin // @[Debug.scala 861:45]
+ hrmaskReg_0 <= 1'h0; // @[Debug.scala 862:17]
+ end else if (_T_4) begin // @[Debug.scala 863:37]
+ hrmaskReg_0 <= io_innerCtrl_bits_hrmask_0; // @[Debug.scala 864:17]
+ end
+ if (_T_1) begin // @[Debug.scala 1102:45]
+ ABSTRACTCSReg_cmderr <= 3'h0; // @[Debug.scala 1103:21]
+ end else if (errorBusy) begin // @[Debug.scala 1105:23]
+ ABSTRACTCSReg_cmderr <= 3'h1; // @[Debug.scala 1106:30]
+ end else if (errorException) begin // @[Debug.scala 1107:35]
+ ABSTRACTCSReg_cmderr <= 3'h3; // @[Debug.scala 1108:30]
+ end else if (errorUnsupported) begin // @[Debug.scala 1109:37]
+ ABSTRACTCSReg_cmderr <= 3'h2; // @[Debug.scala 1110:30]
+ end else begin
+ ABSTRACTCSReg_cmderr <= _GEN_38;
+ end
+ if (_T_1) begin // @[Debug.scala 1724:45]
+ ctrlStateReg <= 2'h0; // @[Debug.scala 1725:20]
+ end else if (ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1673:47]
+ if (wrAccessRegisterCommand | regAccessRegisterCommand) begin // @[Debug.scala 1674:66]
+ ctrlStateReg <= 2'h1; // @[Debug.scala 1675:22]
+ end
+ end else if (ctrlStateReg == 2'h1) begin // @[Debug.scala 1681:59]
+ if (commandRegIsUnsupported) begin // @[Debug.scala 1688:38]
+ ctrlStateReg <= 2'h0; // @[Debug.scala 1690:22]
+ end else begin
+ ctrlStateReg <= _GEN_2107;
+ end
+ end else if (ctrlStateReg == 2'h2) begin // @[Debug.scala 1702:51]
+ ctrlStateReg <= _GEN_2114;
+ end
+ if (_T_1) begin // @[Debug.scala 1183:45]
+ COMMANDRdData_cmdtype <= 8'h0; // @[Debug.scala 1184:18]
+ end else if (COMMANDWrEn) begin // @[Debug.scala 1186:26]
+ COMMANDRdData_cmdtype <= COMMANDWrData_cmdtype; // @[Debug.scala 1187:20]
+ end
+ if (_T_1) begin // @[Debug.scala 1183:45]
+ COMMANDRdData_control <= 24'h0; // @[Debug.scala 1184:18]
+ end else if (COMMANDWrEn) begin // @[Debug.scala 1186:26]
+ COMMANDRdData_control <= COMMANDWrData_control; // @[Debug.scala 1187:20]
+ end
+ if (_T_1) begin // @[Debug.scala 1141:45]
+ ABSTRACTAUTOReg_autoexecdata <= 12'h0; // @[Debug.scala 1142:23]
+ end else if (out_f_woready_8 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1147:61]
+ ABSTRACTAUTOReg_autoexecdata <= _ABSTRACTAUTOReg_autoexecdata_T; // @[Debug.scala 1148:38]
+ end
+ if (_T_1) begin // @[Debug.scala 1141:45]
+ ABSTRACTAUTOReg_autoexecprogbuf <= 16'h0; // @[Debug.scala 1142:23]
+ end else if (out_f_woready_10 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1144:64]
+ ABSTRACTAUTOReg_autoexecprogbuf <= ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala 1145:41]
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ abstractDataMem_0 <= 8'h0; // @[Debug.scala 1597:40]
+ end else if (out_f_wivalid_915) begin // @[RegField.scala 74:88]
+ abstractDataMem_0 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_96 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
+ if (out_f_woready_96) begin // @[Debug.scala 265:24]
+ abstractDataMem_0 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ abstractDataMem_1 <= 8'h0; // @[Debug.scala 1597:40]
+ end else if (out_f_wivalid_916) begin // @[RegField.scala 74:88]
+ abstractDataMem_1 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_97 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
+ if (out_f_woready_97) begin // @[Debug.scala 265:24]
+ abstractDataMem_1 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ abstractDataMem_2 <= 8'h0; // @[Debug.scala 1597:40]
+ end else if (out_f_wivalid_917) begin // @[RegField.scala 74:88]
+ abstractDataMem_2 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_98 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
+ if (out_f_woready_98) begin // @[Debug.scala 265:24]
+ abstractDataMem_2 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ abstractDataMem_3 <= 8'h0; // @[Debug.scala 1597:40]
+ end else if (out_f_wivalid_918) begin // @[RegField.scala 74:88]
+ abstractDataMem_3 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_99 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
+ if (out_f_woready_99) begin // @[Debug.scala 265:24]
+ abstractDataMem_3 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ abstractDataMem_4 <= 8'h0; // @[Debug.scala 1597:40]
+ end else if (out_f_wivalid_919) begin // @[RegField.scala 74:88]
+ abstractDataMem_4 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
+ if (out_f_woready) begin // @[Debug.scala 265:24]
+ abstractDataMem_4 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ abstractDataMem_5 <= 8'h0; // @[Debug.scala 1597:40]
+ end else if (out_f_wivalid_920) begin // @[RegField.scala 74:88]
+ abstractDataMem_5 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_1 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
+ if (out_f_woready_1) begin // @[Debug.scala 265:24]
+ abstractDataMem_5 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ abstractDataMem_6 <= 8'h0; // @[Debug.scala 1597:40]
+ end else if (out_f_wivalid_921) begin // @[RegField.scala 74:88]
+ abstractDataMem_6 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_2 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
+ if (out_f_woready_2) begin // @[Debug.scala 265:24]
+ abstractDataMem_6 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ abstractDataMem_7 <= 8'h0; // @[Debug.scala 1597:40]
+ end else if (out_f_wivalid_922) begin // @[RegField.scala 74:88]
+ abstractDataMem_7 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_3 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
+ if (out_f_woready_3) begin // @[Debug.scala 265:24]
+ abstractDataMem_7 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_0 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1035) begin // @[RegField.scala 74:88]
+ programBufferMem_0 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_31 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_31) begin // @[Debug.scala 265:24]
+ programBufferMem_0 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_1 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1036) begin // @[RegField.scala 74:88]
+ programBufferMem_1 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_32 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_32) begin // @[Debug.scala 265:24]
+ programBufferMem_1 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_2 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1037) begin // @[RegField.scala 74:88]
+ programBufferMem_2 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_33 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_33) begin // @[Debug.scala 265:24]
+ programBufferMem_2 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_3 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1038) begin // @[RegField.scala 74:88]
+ programBufferMem_3 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_34 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_34) begin // @[Debug.scala 265:24]
+ programBufferMem_3 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_4 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1039) begin // @[RegField.scala 74:88]
+ programBufferMem_4 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_23 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_23) begin // @[Debug.scala 265:24]
+ programBufferMem_4 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_5 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1040) begin // @[RegField.scala 74:88]
+ programBufferMem_5 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_24 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_24) begin // @[Debug.scala 265:24]
+ programBufferMem_5 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_6 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1041) begin // @[RegField.scala 74:88]
+ programBufferMem_6 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_25 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_25) begin // @[Debug.scala 265:24]
+ programBufferMem_6 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_7 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1042) begin // @[RegField.scala 74:88]
+ programBufferMem_7 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_26 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_26) begin // @[Debug.scala 265:24]
+ programBufferMem_7 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_8 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_595) begin // @[RegField.scala 74:88]
+ programBufferMem_8 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_35 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_35) begin // @[Debug.scala 265:24]
+ programBufferMem_8 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_9 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_596) begin // @[RegField.scala 74:88]
+ programBufferMem_9 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_36 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_36) begin // @[Debug.scala 265:24]
+ programBufferMem_9 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_10 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_597) begin // @[RegField.scala 74:88]
+ programBufferMem_10 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_37 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_37) begin // @[Debug.scala 265:24]
+ programBufferMem_10 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_11 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_598) begin // @[RegField.scala 74:88]
+ programBufferMem_11 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_38 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_38) begin // @[Debug.scala 265:24]
+ programBufferMem_11 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_12 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_599) begin // @[RegField.scala 74:88]
+ programBufferMem_12 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_78 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_78) begin // @[Debug.scala 265:24]
+ programBufferMem_12 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_13 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_600) begin // @[RegField.scala 74:88]
+ programBufferMem_13 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_79 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_79) begin // @[Debug.scala 265:24]
+ programBufferMem_13 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_14 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_601) begin // @[RegField.scala 74:88]
+ programBufferMem_14 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_80 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_80) begin // @[Debug.scala 265:24]
+ programBufferMem_14 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_15 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_602) begin // @[RegField.scala 74:88]
+ programBufferMem_15 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_81 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_81) begin // @[Debug.scala 265:24]
+ programBufferMem_15 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_16 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_304) begin // @[RegField.scala 74:88]
+ programBufferMem_16 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_91 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_91) begin // @[Debug.scala 265:24]
+ programBufferMem_16 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_17 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_305) begin // @[RegField.scala 74:88]
+ programBufferMem_17 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_92 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_92) begin // @[Debug.scala 265:24]
+ programBufferMem_17 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_18 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_306) begin // @[RegField.scala 74:88]
+ programBufferMem_18 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_93 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_93) begin // @[Debug.scala 265:24]
+ programBufferMem_18 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_19 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_307) begin // @[RegField.scala 74:88]
+ programBufferMem_19 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_94 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_94) begin // @[Debug.scala 265:24]
+ programBufferMem_19 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_20 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_308) begin // @[RegField.scala 74:88]
+ programBufferMem_20 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_11 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_11) begin // @[Debug.scala 265:24]
+ programBufferMem_20 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_21 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_309) begin // @[RegField.scala 74:88]
+ programBufferMem_21 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_12 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_12) begin // @[Debug.scala 265:24]
+ programBufferMem_21 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_22 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_310) begin // @[RegField.scala 74:88]
+ programBufferMem_22 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_13 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_13) begin // @[Debug.scala 265:24]
+ programBufferMem_22 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_23 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_311) begin // @[RegField.scala 74:88]
+ programBufferMem_23 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_14 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_14) begin // @[Debug.scala 265:24]
+ programBufferMem_23 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_24 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1171) begin // @[RegField.scala 74:88]
+ programBufferMem_24 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_19 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_19) begin // @[Debug.scala 265:24]
+ programBufferMem_24 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_25 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1172) begin // @[RegField.scala 74:88]
+ programBufferMem_25 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_20 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_20) begin // @[Debug.scala 265:24]
+ programBufferMem_25 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_26 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1173) begin // @[RegField.scala 74:88]
+ programBufferMem_26 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_21 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_21) begin // @[Debug.scala 265:24]
+ programBufferMem_26 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_27 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1174) begin // @[RegField.scala 74:88]
+ programBufferMem_27 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_22 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_22) begin // @[Debug.scala 265:24]
+ programBufferMem_27 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_28 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1175) begin // @[RegField.scala 74:88]
+ programBufferMem_28 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_74 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_74) begin // @[Debug.scala 265:24]
+ programBufferMem_28 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_29 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1176) begin // @[RegField.scala 74:88]
+ programBufferMem_29 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_75 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_75) begin // @[Debug.scala 265:24]
+ programBufferMem_29 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_30 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1177) begin // @[RegField.scala 74:88]
+ programBufferMem_30 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_76 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_76) begin // @[Debug.scala 265:24]
+ programBufferMem_30 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_31 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1178) begin // @[RegField.scala 74:88]
+ programBufferMem_31 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_77 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_77) begin // @[Debug.scala 265:24]
+ programBufferMem_31 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_32 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_835) begin // @[RegField.scala 74:88]
+ programBufferMem_32 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_86 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_86) begin // @[Debug.scala 265:24]
+ programBufferMem_32 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_33 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_836) begin // @[RegField.scala 74:88]
+ programBufferMem_33 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_87 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_87) begin // @[Debug.scala 265:24]
+ programBufferMem_33 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_34 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_837) begin // @[RegField.scala 74:88]
+ programBufferMem_34 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_88 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_88) begin // @[Debug.scala 265:24]
+ programBufferMem_34 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_35 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_838) begin // @[RegField.scala 74:88]
+ programBufferMem_35 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_89 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_89) begin // @[Debug.scala 265:24]
+ programBufferMem_35 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_36 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_839) begin // @[RegField.scala 74:88]
+ programBufferMem_36 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_27 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_27) begin // @[Debug.scala 265:24]
+ programBufferMem_36 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_37 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_840) begin // @[RegField.scala 74:88]
+ programBufferMem_37 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_28 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_28) begin // @[Debug.scala 265:24]
+ programBufferMem_37 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_38 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_841) begin // @[RegField.scala 74:88]
+ programBufferMem_38 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_29 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_29) begin // @[Debug.scala 265:24]
+ programBufferMem_38 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_39 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_842) begin // @[RegField.scala 74:88]
+ programBufferMem_39 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_30 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_30) begin // @[Debug.scala 265:24]
+ programBufferMem_39 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_40 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_514) begin // @[RegField.scala 74:88]
+ programBufferMem_40 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_4 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_4) begin // @[Debug.scala 265:24]
+ programBufferMem_40 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_41 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_515) begin // @[RegField.scala 74:88]
+ programBufferMem_41 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_5 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_5) begin // @[Debug.scala 265:24]
+ programBufferMem_41 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_42 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_516) begin // @[RegField.scala 74:88]
+ programBufferMem_42 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_6 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_6) begin // @[Debug.scala 265:24]
+ programBufferMem_42 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_43 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_517) begin // @[RegField.scala 74:88]
+ programBufferMem_43 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_7 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_7) begin // @[Debug.scala 265:24]
+ programBufferMem_43 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_44 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_518) begin // @[RegField.scala 74:88]
+ programBufferMem_44 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_82 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_82) begin // @[Debug.scala 265:24]
+ programBufferMem_44 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_45 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_519) begin // @[RegField.scala 74:88]
+ programBufferMem_45 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_83 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_83) begin // @[Debug.scala 265:24]
+ programBufferMem_45 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_46 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_520) begin // @[RegField.scala 74:88]
+ programBufferMem_46 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_84 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_84) begin // @[Debug.scala 265:24]
+ programBufferMem_46 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_47 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_521) begin // @[RegField.scala 74:88]
+ programBufferMem_47 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_85 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_85) begin // @[Debug.scala 265:24]
+ programBufferMem_47 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_48 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_208) begin // @[RegField.scala 74:88]
+ programBufferMem_48 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_70 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_70) begin // @[Debug.scala 265:24]
+ programBufferMem_48 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_49 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_209) begin // @[RegField.scala 74:88]
+ programBufferMem_49 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_71 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_71) begin // @[Debug.scala 265:24]
+ programBufferMem_49 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_50 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_210) begin // @[RegField.scala 74:88]
+ programBufferMem_50 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_72 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_72) begin // @[Debug.scala 265:24]
+ programBufferMem_50 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_51 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_211) begin // @[RegField.scala 74:88]
+ programBufferMem_51 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_73 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_73) begin // @[Debug.scala 265:24]
+ programBufferMem_51 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_52 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_212) begin // @[RegField.scala 74:88]
+ programBufferMem_52 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_39 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_39) begin // @[Debug.scala 265:24]
+ programBufferMem_52 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_53 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_213) begin // @[RegField.scala 74:88]
+ programBufferMem_53 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_40 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_40) begin // @[Debug.scala 265:24]
+ programBufferMem_53 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_54 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_214) begin // @[RegField.scala 74:88]
+ programBufferMem_54 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_41 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_41) begin // @[Debug.scala 265:24]
+ programBufferMem_54 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_55 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_215) begin // @[RegField.scala 74:88]
+ programBufferMem_55 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_42 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_42) begin // @[Debug.scala 265:24]
+ programBufferMem_55 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_56 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1243) begin // @[RegField.scala 74:88]
+ programBufferMem_56 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_15 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_15) begin // @[Debug.scala 265:24]
+ programBufferMem_56 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_57 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1244) begin // @[RegField.scala 74:88]
+ programBufferMem_57 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_16 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_16) begin // @[Debug.scala 265:24]
+ programBufferMem_57 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_58 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1245) begin // @[RegField.scala 74:88]
+ programBufferMem_58 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_17 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_17) begin // @[Debug.scala 265:24]
+ programBufferMem_58 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_59 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1246) begin // @[RegField.scala 74:88]
+ programBufferMem_59 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_18 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_18) begin // @[Debug.scala 265:24]
+ programBufferMem_59 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_60 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1247) begin // @[RegField.scala 74:88]
+ programBufferMem_60 <= auto_tl_in_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_100 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_100) begin // @[Debug.scala 265:24]
+ programBufferMem_60 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_61 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1248) begin // @[RegField.scala 74:88]
+ programBufferMem_61 <= auto_tl_in_a_bits_data[47:40]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_101 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_101) begin // @[Debug.scala 265:24]
+ programBufferMem_61 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_62 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1249) begin // @[RegField.scala 74:88]
+ programBufferMem_62 <= auto_tl_in_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_102 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_102) begin // @[Debug.scala 265:24]
+ programBufferMem_62 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1596:24]
+ programBufferMem_63 <= 8'h0; // @[Debug.scala 1598:40]
+ end else if (out_f_wivalid_1250) begin // @[RegField.scala 74:88]
+ programBufferMem_63 <= auto_tl_in_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end else if (out_f_woready_103 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
+ if (out_f_woready_103) begin // @[Debug.scala 265:24]
+ programBufferMem_63 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
+ end
+ end
+ if (_T_1) begin // @[Debug.scala 1385:24]
+ goReg <= 1'h0; // @[Debug.scala 1386:13]
+ end else begin
+ goReg <= _GEN_406;
+ end
+ if (goAbstract) begin // @[Debug.scala 1520:23]
+ if (accessRegisterCommandReg_transfer) begin // @[Debug.scala 1524:39]
+ if (accessRegisterCommandReg_write) begin // @[Debug.scala 1525:14]
+ abstractGeneratedMem_0 <= _abstractGeneratedMem_0_T;
+ end else begin
+ abstractGeneratedMem_0 <= _abstractGeneratedMem_0_T_1;
+ end
+ end else begin
+ abstractGeneratedMem_0 <= 32'h13;
+ end
+ end
+ if (goAbstract) begin // @[Debug.scala 1520:23]
+ if (accessRegisterCommandReg_postexec) begin // @[Debug.scala 1528:39]
+ abstractGeneratedMem_1 <= 32'h13;
+ end else begin
+ abstractGeneratedMem_1 <= 32'h100073;
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(hartGoingId == 10'h0) & (~_T_1 & ~goAbstract & out_f_woready_632 & ~reset)) begin
+ $fatal; // @[Debug.scala 1391:15]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~_T_1 & ~goAbstract & out_f_woready_632 & ~reset & ~(hartGoingId == 10'h0)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: Unexpected 'GOING' hart.\n at Debug.scala:1391 assert(hartGoingId === 0.U, \"Unexpected 'GOING' hart.\")//Chisel3 #540 %%x, expected %%x\", hartGoingId, 0.U)\n"
+ ); // @[Debug.scala 1391:15]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_358 & (_errorBusy_T & ~_T_1399 & _T_1400 & out_f_woready_449 & _T_357)) begin
+ $fatal; // @[Debug.scala 1711:15]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_errorBusy_T & ~_T_1399 & _T_1400 & out_f_woready_449 & _T_357 & _T_358) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: Unexpected 'EXCEPTION' hart\n at Debug.scala:1711 assert(hartExceptionId === 0.U, \"Unexpected 'EXCEPTION' hart\")//Chisel3 #540, %%x, expected %%x\", hartExceptionId, 0.U)\n"
+ ); // @[Debug.scala 1711:15]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_GEN_2266 & ~_T_1400 & _T_1409 & _T_357) begin
+ $fatal; // @[Debug.scala 1716:13]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_GEN_2266 & ~_T_1400 & _T_1409 & _T_357) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: Should not be in custom state unless we need it.\n at Debug.scala:1716 assert(needCustom.B, \"Should not be in custom state unless we need it.\")\n"
+ ); // @[Debug.scala 1716:13]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_T_1 | ~out_f_woready_449 | _T_1400) & _T_357) begin
+ $fatal; // @[Debug.scala 1729:12]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_357 & ~(_T_1 | ~out_f_woready_449 | _T_1400)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: Unexpected EXCEPTION write: should only get it in Debug Module EXEC state\n at Debug.scala:1729 assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),\n"
+ ); // @[Debug.scala 1729:12]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[Debug.scala 869:47]
+ hrDebugIntReg_0 <= 1'h0; // @[Debug.scala 870:23]
+ end else if (_T_1) begin // @[Debug.scala 872:23]
+ hrDebugIntReg_0 <= 1'h0;
+ end else begin
+ hrDebugIntReg_0 <= _T_13;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ haltedBitRegs = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ resumeReqRegs = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ haveResetBitRegs = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ hrmaskReg_0 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ hrDebugIntReg_0 = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ ABSTRACTCSReg_cmderr = _RAND_5[2:0];
+ _RAND_6 = {1{`RANDOM}};
+ ctrlStateReg = _RAND_6[1:0];
+ _RAND_7 = {1{`RANDOM}};
+ COMMANDRdData_cmdtype = _RAND_7[7:0];
+ _RAND_8 = {1{`RANDOM}};
+ COMMANDRdData_control = _RAND_8[23:0];
+ _RAND_9 = {1{`RANDOM}};
+ ABSTRACTAUTOReg_autoexecdata = _RAND_9[11:0];
+ _RAND_10 = {1{`RANDOM}};
+ ABSTRACTAUTOReg_autoexecprogbuf = _RAND_10[15:0];
+ _RAND_11 = {1{`RANDOM}};
+ abstractDataMem_0 = _RAND_11[7:0];
+ _RAND_12 = {1{`RANDOM}};
+ abstractDataMem_1 = _RAND_12[7:0];
+ _RAND_13 = {1{`RANDOM}};
+ abstractDataMem_2 = _RAND_13[7:0];
+ _RAND_14 = {1{`RANDOM}};
+ abstractDataMem_3 = _RAND_14[7:0];
+ _RAND_15 = {1{`RANDOM}};
+ abstractDataMem_4 = _RAND_15[7:0];
+ _RAND_16 = {1{`RANDOM}};
+ abstractDataMem_5 = _RAND_16[7:0];
+ _RAND_17 = {1{`RANDOM}};
+ abstractDataMem_6 = _RAND_17[7:0];
+ _RAND_18 = {1{`RANDOM}};
+ abstractDataMem_7 = _RAND_18[7:0];
+ _RAND_19 = {1{`RANDOM}};
+ programBufferMem_0 = _RAND_19[7:0];
+ _RAND_20 = {1{`RANDOM}};
+ programBufferMem_1 = _RAND_20[7:0];
+ _RAND_21 = {1{`RANDOM}};
+ programBufferMem_2 = _RAND_21[7:0];
+ _RAND_22 = {1{`RANDOM}};
+ programBufferMem_3 = _RAND_22[7:0];
+ _RAND_23 = {1{`RANDOM}};
+ programBufferMem_4 = _RAND_23[7:0];
+ _RAND_24 = {1{`RANDOM}};
+ programBufferMem_5 = _RAND_24[7:0];
+ _RAND_25 = {1{`RANDOM}};
+ programBufferMem_6 = _RAND_25[7:0];
+ _RAND_26 = {1{`RANDOM}};
+ programBufferMem_7 = _RAND_26[7:0];
+ _RAND_27 = {1{`RANDOM}};
+ programBufferMem_8 = _RAND_27[7:0];
+ _RAND_28 = {1{`RANDOM}};
+ programBufferMem_9 = _RAND_28[7:0];
+ _RAND_29 = {1{`RANDOM}};
+ programBufferMem_10 = _RAND_29[7:0];
+ _RAND_30 = {1{`RANDOM}};
+ programBufferMem_11 = _RAND_30[7:0];
+ _RAND_31 = {1{`RANDOM}};
+ programBufferMem_12 = _RAND_31[7:0];
+ _RAND_32 = {1{`RANDOM}};
+ programBufferMem_13 = _RAND_32[7:0];
+ _RAND_33 = {1{`RANDOM}};
+ programBufferMem_14 = _RAND_33[7:0];
+ _RAND_34 = {1{`RANDOM}};
+ programBufferMem_15 = _RAND_34[7:0];
+ _RAND_35 = {1{`RANDOM}};
+ programBufferMem_16 = _RAND_35[7:0];
+ _RAND_36 = {1{`RANDOM}};
+ programBufferMem_17 = _RAND_36[7:0];
+ _RAND_37 = {1{`RANDOM}};
+ programBufferMem_18 = _RAND_37[7:0];
+ _RAND_38 = {1{`RANDOM}};
+ programBufferMem_19 = _RAND_38[7:0];
+ _RAND_39 = {1{`RANDOM}};
+ programBufferMem_20 = _RAND_39[7:0];
+ _RAND_40 = {1{`RANDOM}};
+ programBufferMem_21 = _RAND_40[7:0];
+ _RAND_41 = {1{`RANDOM}};
+ programBufferMem_22 = _RAND_41[7:0];
+ _RAND_42 = {1{`RANDOM}};
+ programBufferMem_23 = _RAND_42[7:0];
+ _RAND_43 = {1{`RANDOM}};
+ programBufferMem_24 = _RAND_43[7:0];
+ _RAND_44 = {1{`RANDOM}};
+ programBufferMem_25 = _RAND_44[7:0];
+ _RAND_45 = {1{`RANDOM}};
+ programBufferMem_26 = _RAND_45[7:0];
+ _RAND_46 = {1{`RANDOM}};
+ programBufferMem_27 = _RAND_46[7:0];
+ _RAND_47 = {1{`RANDOM}};
+ programBufferMem_28 = _RAND_47[7:0];
+ _RAND_48 = {1{`RANDOM}};
+ programBufferMem_29 = _RAND_48[7:0];
+ _RAND_49 = {1{`RANDOM}};
+ programBufferMem_30 = _RAND_49[7:0];
+ _RAND_50 = {1{`RANDOM}};
+ programBufferMem_31 = _RAND_50[7:0];
+ _RAND_51 = {1{`RANDOM}};
+ programBufferMem_32 = _RAND_51[7:0];
+ _RAND_52 = {1{`RANDOM}};
+ programBufferMem_33 = _RAND_52[7:0];
+ _RAND_53 = {1{`RANDOM}};
+ programBufferMem_34 = _RAND_53[7:0];
+ _RAND_54 = {1{`RANDOM}};
+ programBufferMem_35 = _RAND_54[7:0];
+ _RAND_55 = {1{`RANDOM}};
+ programBufferMem_36 = _RAND_55[7:0];
+ _RAND_56 = {1{`RANDOM}};
+ programBufferMem_37 = _RAND_56[7:0];
+ _RAND_57 = {1{`RANDOM}};
+ programBufferMem_38 = _RAND_57[7:0];
+ _RAND_58 = {1{`RANDOM}};
+ programBufferMem_39 = _RAND_58[7:0];
+ _RAND_59 = {1{`RANDOM}};
+ programBufferMem_40 = _RAND_59[7:0];
+ _RAND_60 = {1{`RANDOM}};
+ programBufferMem_41 = _RAND_60[7:0];
+ _RAND_61 = {1{`RANDOM}};
+ programBufferMem_42 = _RAND_61[7:0];
+ _RAND_62 = {1{`RANDOM}};
+ programBufferMem_43 = _RAND_62[7:0];
+ _RAND_63 = {1{`RANDOM}};
+ programBufferMem_44 = _RAND_63[7:0];
+ _RAND_64 = {1{`RANDOM}};
+ programBufferMem_45 = _RAND_64[7:0];
+ _RAND_65 = {1{`RANDOM}};
+ programBufferMem_46 = _RAND_65[7:0];
+ _RAND_66 = {1{`RANDOM}};
+ programBufferMem_47 = _RAND_66[7:0];
+ _RAND_67 = {1{`RANDOM}};
+ programBufferMem_48 = _RAND_67[7:0];
+ _RAND_68 = {1{`RANDOM}};
+ programBufferMem_49 = _RAND_68[7:0];
+ _RAND_69 = {1{`RANDOM}};
+ programBufferMem_50 = _RAND_69[7:0];
+ _RAND_70 = {1{`RANDOM}};
+ programBufferMem_51 = _RAND_70[7:0];
+ _RAND_71 = {1{`RANDOM}};
+ programBufferMem_52 = _RAND_71[7:0];
+ _RAND_72 = {1{`RANDOM}};
+ programBufferMem_53 = _RAND_72[7:0];
+ _RAND_73 = {1{`RANDOM}};
+ programBufferMem_54 = _RAND_73[7:0];
+ _RAND_74 = {1{`RANDOM}};
+ programBufferMem_55 = _RAND_74[7:0];
+ _RAND_75 = {1{`RANDOM}};
+ programBufferMem_56 = _RAND_75[7:0];
+ _RAND_76 = {1{`RANDOM}};
+ programBufferMem_57 = _RAND_76[7:0];
+ _RAND_77 = {1{`RANDOM}};
+ programBufferMem_58 = _RAND_77[7:0];
+ _RAND_78 = {1{`RANDOM}};
+ programBufferMem_59 = _RAND_78[7:0];
+ _RAND_79 = {1{`RANDOM}};
+ programBufferMem_60 = _RAND_79[7:0];
+ _RAND_80 = {1{`RANDOM}};
+ programBufferMem_61 = _RAND_80[7:0];
+ _RAND_81 = {1{`RANDOM}};
+ programBufferMem_62 = _RAND_81[7:0];
+ _RAND_82 = {1{`RANDOM}};
+ programBufferMem_63 = _RAND_82[7:0];
+ _RAND_83 = {1{`RANDOM}};
+ goReg = _RAND_83[0:0];
+ _RAND_84 = {1{`RANDOM}};
+ abstractGeneratedMem_0 = _RAND_84[31:0];
+ _RAND_85 = {1{`RANDOM}};
+ abstractGeneratedMem_1 = _RAND_85[31:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ hrDebugIntReg_0 = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockCrossingReg_w55(
+ input clock,
+ input [54:0] io_d,
+ output [54:0] io_q,
+ input io_en
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [63:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg [54:0] cdc_reg; // @[Reg.scala 16:16]
+ assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
+ always @(posedge clock) begin
+ if (io_en) begin // @[Reg.scala 17:18]
+ cdc_reg <= io_d; // @[Reg.scala 17:22]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {2{`RANDOM}};
+ cdc_reg = _RAND_0[54:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module AsyncQueueSink_1(
+ input clock,
+ input reset,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [1:0] io_deq_bits_size,
+ output io_deq_bits_source,
+ output [8:0] io_deq_bits_address,
+ output [3:0] io_deq_bits_mask,
+ output [31:0] io_deq_bits_data,
+ output io_deq_bits_corrupt,
+ input [2:0] io_async_mem_0_opcode,
+ input [8:0] io_async_mem_0_address,
+ input [31:0] io_async_mem_0_data,
+ output io_async_ridx,
+ input io_async_widx,
+ output io_async_safe_ridx_valid,
+ input io_async_safe_widx_valid,
+ input io_async_safe_source_reset_n,
+ output io_async_safe_sink_reset_n
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+`endif // RANDOMIZE_REG_INIT
+ wire widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
+ wire io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
+ wire [54:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
+ wire [54:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
+ wire io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
+ wire sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
+ wire source_extend_io_in; // @[AsyncQueue.scala 171:31]
+ wire source_extend_io_out; // @[AsyncQueue.scala 171:31]
+ wire source_extend_clock; // @[AsyncQueue.scala 171:31]
+ wire source_extend_reset; // @[AsyncQueue.scala 171:31]
+ wire source_valid_io_in; // @[AsyncQueue.scala 172:31]
+ wire source_valid_io_out; // @[AsyncQueue.scala 172:31]
+ wire source_valid_clock; // @[AsyncQueue.scala 172:31]
+ wire source_valid_reset; // @[AsyncQueue.scala 172:31]
+ wire _ridx_T_1 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ wire source_ready = source_valid_io_out;
+ wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
+ reg ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
+ wire ridx_incremented = _ridx_T_2 ? 1'h0 : ridx_ridx_bin + _ridx_T_1; // @[AsyncQueue.scala 53:23]
+ wire widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire [45:0] io_deq_bits_deq_bits_reg_io_d_lo = {io_async_mem_0_address,4'hf,io_async_mem_0_data,1'h0}; // @[SynchronizerReg.scala 209:24]
+ wire [8:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_async_mem_0_opcode,3'h0,3'h4}; // @[SynchronizerReg.scala 209:24]
+ wire [54:0] _io_deq_bits_WIRE_1 = io_deq_bits_deq_bits_reg_io_q;
+ reg valid_reg; // @[AsyncQueue.scala 161:56]
+ reg ridx_gray; // @[AsyncQueue.scala 164:55]
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
+ .clock(widx_widx_gray_clock),
+ .reset(widx_widx_gray_reset),
+ .io_d(widx_widx_gray_io_d),
+ .io_q(widx_widx_gray_io_q)
+ );
+ ClockCrossingReg_w55 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
+ .clock(io_deq_bits_deq_bits_reg_clock),
+ .io_d(io_deq_bits_deq_bits_reg_io_d),
+ .io_q(io_deq_bits_deq_bits_reg_io_q),
+ .io_en(io_deq_bits_deq_bits_reg_io_en)
+ );
+ AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
+ .io_in(sink_valid_0_io_in),
+ .io_out(sink_valid_0_io_out),
+ .clock(sink_valid_0_clock),
+ .reset(sink_valid_0_reset)
+ );
+ AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
+ .io_in(sink_valid_1_io_in),
+ .io_out(sink_valid_1_io_out),
+ .clock(sink_valid_1_clock),
+ .reset(sink_valid_1_reset)
+ );
+ AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
+ .io_in(source_extend_io_in),
+ .io_out(source_extend_io_out),
+ .clock(source_extend_clock),
+ .reset(source_extend_reset)
+ );
+ AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
+ .io_in(source_valid_io_in),
+ .io_out(source_valid_io_out),
+ .clock(source_valid_clock),
+ .reset(source_valid_reset)
+ );
+ assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
+ assign io_deq_bits_opcode = _io_deq_bits_WIRE_1[54:52]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_param = _io_deq_bits_WIRE_1[51:49]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_size = _io_deq_bits_WIRE_1[48:47]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_source = _io_deq_bits_WIRE_1[46]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_address = _io_deq_bits_WIRE_1[45:37]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_mask = _io_deq_bits_WIRE_1[36:33]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_data = _io_deq_bits_WIRE_1[32:1]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_corrupt = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala 211:26]
+ assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
+ assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
+ assign io_async_safe_sink_reset_n = ~reset; // @[AsyncQueue.scala 189:25]
+ assign widx_widx_gray_clock = clock;
+ assign widx_widx_gray_reset = reset;
+ assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
+ assign io_deq_bits_deq_bits_reg_clock = clock;
+ assign io_deq_bits_deq_bits_reg_io_d = {io_deq_bits_deq_bits_reg_io_d_hi,io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala 209:24]
+ assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx_incremented != widx; // @[AsyncQueue.scala 146:28]
+ assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
+ assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
+ assign sink_valid_0_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 173:66]
+ assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
+ assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
+ assign sink_valid_1_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 174:66]
+ assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
+ assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
+ assign source_extend_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 175:66]
+ assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
+ assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
+ assign source_valid_reset = reset; // @[AsyncQueue.scala 176:34]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ ridx_ridx_bin <= 1'h0;
+ end else if (_ridx_T_2) begin
+ ridx_ridx_bin <= 1'h0;
+ end else begin
+ ridx_ridx_bin <= ridx_ridx_bin + _ridx_T_1;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 146:28]
+ valid_reg <= 1'h0;
+ end else begin
+ valid_reg <= source_ready & ridx_incremented != widx;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ ridx_gray <= 1'h0;
+ end else if (_ridx_T_2) begin
+ ridx_gray <= 1'h0;
+ end else begin
+ ridx_gray <= ridx_ridx_bin + _ridx_T_1;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ ridx_ridx_bin = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ valid_reg = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ ridx_gray = _RAND_2[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ ridx_ridx_bin = 1'h0;
+ end
+ if (reset) begin
+ valid_reg = 1'h0;
+ end
+ if (reset) begin
+ ridx_gray = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module AsyncQueueSource_2(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [1:0] io_enq_bits_size,
+ input io_enq_bits_source,
+ input [31:0] io_enq_bits_data,
+ output [2:0] io_async_mem_0_opcode,
+ output [1:0] io_async_mem_0_size,
+ output io_async_mem_0_source,
+ output [31:0] io_async_mem_0_data,
+ input io_async_ridx,
+ output io_async_widx,
+ input io_async_safe_ridx_valid,
+ output io_async_safe_widx_valid,
+ output io_async_safe_source_reset_n,
+ input io_async_safe_sink_reset_n
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+`endif // RANDOMIZE_REG_INIT
+ wire ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
+ wire ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
+ wire source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_clock; // @[AsyncQueue.scala 100:32]
+ wire source_valid_0_reset; // @[AsyncQueue.scala 100:32]
+ wire source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_clock; // @[AsyncQueue.scala 101:32]
+ wire source_valid_1_reset; // @[AsyncQueue.scala 101:32]
+ wire sink_extend_io_in; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_io_out; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_clock; // @[AsyncQueue.scala 103:30]
+ wire sink_extend_reset; // @[AsyncQueue.scala 103:30]
+ wire sink_valid_io_in; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_io_out; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_clock; // @[AsyncQueue.scala 104:30]
+ wire sink_valid_reset; // @[AsyncQueue.scala 104:30]
+ reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 80:16]
+ reg [1:0] mem_0_size; // @[AsyncQueue.scala 80:16]
+ reg mem_0_source; // @[AsyncQueue.scala 80:16]
+ reg [31:0] mem_0_data; // @[AsyncQueue.scala 80:16]
+ wire _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire sink_ready = sink_valid_io_out;
+ wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
+ reg widx_widx_bin; // @[AsyncQueue.scala 52:25]
+ wire widx_incremented = _widx_T_2 ? 1'h0 : widx_widx_bin + _widx_T_1; // @[AsyncQueue.scala 53:23]
+ wire ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
+ reg ready_reg; // @[AsyncQueue.scala 88:56]
+ reg widx_gray; // @[AsyncQueue.scala 91:55]
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
+ .clock(ridx_ridx_gray_clock),
+ .reset(ridx_ridx_gray_reset),
+ .io_d(ridx_ridx_gray_io_d),
+ .io_q(ridx_ridx_gray_io_q)
+ );
+ AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
+ .io_in(source_valid_0_io_in),
+ .io_out(source_valid_0_io_out),
+ .clock(source_valid_0_clock),
+ .reset(source_valid_0_reset)
+ );
+ AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
+ .io_in(source_valid_1_io_in),
+ .io_out(source_valid_1_io_out),
+ .clock(source_valid_1_clock),
+ .reset(source_valid_1_reset)
+ );
+ AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
+ .io_in(sink_extend_io_in),
+ .io_out(sink_extend_io_out),
+ .clock(sink_extend_clock),
+ .reset(sink_extend_reset)
+ );
+ AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
+ .io_in(sink_valid_io_in),
+ .io_out(sink_valid_io_out),
+ .clock(sink_valid_clock),
+ .reset(sink_valid_reset)
+ );
+ assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
+ assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 96:31]
+ assign io_async_mem_0_size = mem_0_size; // @[AsyncQueue.scala 96:31]
+ assign io_async_mem_0_source = mem_0_source; // @[AsyncQueue.scala 96:31]
+ assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 96:31]
+ assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
+ assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
+ assign io_async_safe_source_reset_n = ~reset; // @[AsyncQueue.scala 121:27]
+ assign ridx_ridx_gray_clock = clock;
+ assign ridx_ridx_gray_reset = reset;
+ assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
+ assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
+ assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
+ assign source_valid_0_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 105:65]
+ assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
+ assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
+ assign source_valid_1_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 106:65]
+ assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
+ assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
+ assign sink_extend_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 107:65]
+ assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
+ assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
+ assign sink_valid_reset = reset; // @[AsyncQueue.scala 108:35]
+ always @(posedge clock) begin
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_opcode <= io_enq_bits_opcode; // @[AsyncQueue.scala 86:37]
+ end
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_size <= io_enq_bits_size; // @[AsyncQueue.scala 86:37]
+ end
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_source <= io_enq_bits_source; // @[AsyncQueue.scala 86:37]
+ end
+ if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
+ mem_0_data <= io_enq_bits_data; // @[AsyncQueue.scala 86:37]
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ widx_widx_bin <= 1'h0;
+ end else if (_widx_T_2) begin
+ widx_widx_bin <= 1'h0;
+ end else begin
+ widx_widx_bin <= widx_widx_bin + _widx_T_1;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 83:26]
+ ready_reg <= 1'h0;
+ end else begin
+ ready_reg <= sink_ready & widx_incremented != (ridx ^ 1'h1);
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ widx_gray <= 1'h0;
+ end else if (_widx_T_2) begin
+ widx_gray <= 1'h0;
+ end else begin
+ widx_gray <= widx_widx_bin + _widx_T_1;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ mem_0_opcode = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ mem_0_size = _RAND_1[1:0];
+ _RAND_2 = {1{`RANDOM}};
+ mem_0_source = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ mem_0_data = _RAND_3[31:0];
+ _RAND_4 = {1{`RANDOM}};
+ widx_widx_bin = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ ready_reg = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ widx_gray = _RAND_6[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ widx_widx_bin = 1'h0;
+ end
+ if (reset) begin
+ ready_reg = 1'h0;
+ end
+ if (reset) begin
+ widx_gray = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLAsyncCrossingSink(
+ input clock,
+ input reset,
+ input [2:0] auto_in_a_mem_0_opcode,
+ input [8:0] auto_in_a_mem_0_address,
+ input [31:0] auto_in_a_mem_0_data,
+ output auto_in_a_ridx,
+ input auto_in_a_widx,
+ output auto_in_a_safe_ridx_valid,
+ input auto_in_a_safe_widx_valid,
+ input auto_in_a_safe_source_reset_n,
+ output auto_in_a_safe_sink_reset_n,
+ output [2:0] auto_in_d_mem_0_opcode,
+ output [1:0] auto_in_d_mem_0_size,
+ output auto_in_d_mem_0_source,
+ output [31:0] auto_in_d_mem_0_data,
+ input auto_in_d_ridx,
+ output auto_in_d_widx,
+ input auto_in_d_safe_ridx_valid,
+ output auto_in_d_safe_widx_valid,
+ output auto_in_d_safe_source_reset_n,
+ input auto_in_d_safe_sink_reset_n,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output auto_out_a_bits_source,
+ output [8:0] auto_out_a_bits_address,
+ output [3:0] auto_out_a_bits_mask,
+ output [31:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input auto_out_d_bits_source,
+ input [31:0] auto_out_d_bits_data
+);
+ wire bundleOut_0_a_sink_clock; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_reset; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_deq_ready; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_deq_valid; // @[AsyncQueue.scala 207:22]
+ wire [2:0] bundleOut_0_a_sink_io_deq_bits_opcode; // @[AsyncQueue.scala 207:22]
+ wire [2:0] bundleOut_0_a_sink_io_deq_bits_param; // @[AsyncQueue.scala 207:22]
+ wire [1:0] bundleOut_0_a_sink_io_deq_bits_size; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_deq_bits_source; // @[AsyncQueue.scala 207:22]
+ wire [8:0] bundleOut_0_a_sink_io_deq_bits_address; // @[AsyncQueue.scala 207:22]
+ wire [3:0] bundleOut_0_a_sink_io_deq_bits_mask; // @[AsyncQueue.scala 207:22]
+ wire [31:0] bundleOut_0_a_sink_io_deq_bits_data; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala 207:22]
+ wire [2:0] bundleOut_0_a_sink_io_async_mem_0_opcode; // @[AsyncQueue.scala 207:22]
+ wire [8:0] bundleOut_0_a_sink_io_async_mem_0_address; // @[AsyncQueue.scala 207:22]
+ wire [31:0] bundleOut_0_a_sink_io_async_mem_0_data; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_async_ridx; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_async_widx; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 207:22]
+ wire bundleOut_0_a_sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 207:22]
+ wire bundleIn_0_d_source_clock; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_reset; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_enq_ready; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_enq_valid; // @[AsyncQueue.scala 216:24]
+ wire [2:0] bundleIn_0_d_source_io_enq_bits_opcode; // @[AsyncQueue.scala 216:24]
+ wire [1:0] bundleIn_0_d_source_io_enq_bits_size; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_enq_bits_source; // @[AsyncQueue.scala 216:24]
+ wire [31:0] bundleIn_0_d_source_io_enq_bits_data; // @[AsyncQueue.scala 216:24]
+ wire [2:0] bundleIn_0_d_source_io_async_mem_0_opcode; // @[AsyncQueue.scala 216:24]
+ wire [1:0] bundleIn_0_d_source_io_async_mem_0_size; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_async_mem_0_source; // @[AsyncQueue.scala 216:24]
+ wire [31:0] bundleIn_0_d_source_io_async_mem_0_data; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_async_ridx; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_async_widx; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_async_safe_widx_valid; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 216:24]
+ wire bundleIn_0_d_source_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 216:24]
+ AsyncQueueSink_1 bundleOut_0_a_sink ( // @[AsyncQueue.scala 207:22]
+ .clock(bundleOut_0_a_sink_clock),
+ .reset(bundleOut_0_a_sink_reset),
+ .io_deq_ready(bundleOut_0_a_sink_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_sink_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_sink_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_sink_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_sink_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_sink_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_sink_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_sink_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_sink_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_sink_io_deq_bits_corrupt),
+ .io_async_mem_0_opcode(bundleOut_0_a_sink_io_async_mem_0_opcode),
+ .io_async_mem_0_address(bundleOut_0_a_sink_io_async_mem_0_address),
+ .io_async_mem_0_data(bundleOut_0_a_sink_io_async_mem_0_data),
+ .io_async_ridx(bundleOut_0_a_sink_io_async_ridx),
+ .io_async_widx(bundleOut_0_a_sink_io_async_widx),
+ .io_async_safe_ridx_valid(bundleOut_0_a_sink_io_async_safe_ridx_valid),
+ .io_async_safe_widx_valid(bundleOut_0_a_sink_io_async_safe_widx_valid),
+ .io_async_safe_source_reset_n(bundleOut_0_a_sink_io_async_safe_source_reset_n),
+ .io_async_safe_sink_reset_n(bundleOut_0_a_sink_io_async_safe_sink_reset_n)
+ );
+ AsyncQueueSource_2 bundleIn_0_d_source ( // @[AsyncQueue.scala 216:24]
+ .clock(bundleIn_0_d_source_clock),
+ .reset(bundleIn_0_d_source_reset),
+ .io_enq_ready(bundleIn_0_d_source_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_source_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_source_io_enq_bits_opcode),
+ .io_enq_bits_size(bundleIn_0_d_source_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_source_io_enq_bits_source),
+ .io_enq_bits_data(bundleIn_0_d_source_io_enq_bits_data),
+ .io_async_mem_0_opcode(bundleIn_0_d_source_io_async_mem_0_opcode),
+ .io_async_mem_0_size(bundleIn_0_d_source_io_async_mem_0_size),
+ .io_async_mem_0_source(bundleIn_0_d_source_io_async_mem_0_source),
+ .io_async_mem_0_data(bundleIn_0_d_source_io_async_mem_0_data),
+ .io_async_ridx(bundleIn_0_d_source_io_async_ridx),
+ .io_async_widx(bundleIn_0_d_source_io_async_widx),
+ .io_async_safe_ridx_valid(bundleIn_0_d_source_io_async_safe_ridx_valid),
+ .io_async_safe_widx_valid(bundleIn_0_d_source_io_async_safe_widx_valid),
+ .io_async_safe_source_reset_n(bundleIn_0_d_source_io_async_safe_source_reset_n),
+ .io_async_safe_sink_reset_n(bundleIn_0_d_source_io_async_safe_sink_reset_n)
+ );
+ assign auto_in_a_ridx = bundleOut_0_a_sink_io_async_ridx; // @[Nodes.scala 1210:84 AsyncQueue.scala 208:19]
+ assign auto_in_a_safe_ridx_valid = bundleOut_0_a_sink_io_async_safe_ridx_valid; // @[Nodes.scala 1210:84 AsyncQueue.scala 208:19]
+ assign auto_in_a_safe_sink_reset_n = bundleOut_0_a_sink_io_async_safe_sink_reset_n; // @[Nodes.scala 1210:84 AsyncQueue.scala 208:19]
+ assign auto_in_d_mem_0_opcode = bundleIn_0_d_source_io_async_mem_0_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
+ assign auto_in_d_mem_0_size = bundleIn_0_d_source_io_async_mem_0_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
+ assign auto_in_d_mem_0_source = bundleIn_0_d_source_io_async_mem_0_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
+ assign auto_in_d_mem_0_data = bundleIn_0_d_source_io_async_mem_0_data; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
+ assign auto_in_d_widx = bundleIn_0_d_source_io_async_widx; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
+ assign auto_in_d_safe_widx_valid = bundleIn_0_d_source_io_async_safe_widx_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
+ assign auto_in_d_safe_source_reset_n = bundleIn_0_d_source_io_async_safe_source_reset_n; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
+ assign auto_out_a_valid = bundleOut_0_a_sink_io_deq_valid; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_sink_io_deq_bits_opcode; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_sink_io_deq_bits_param; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_sink_io_deq_bits_size; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_sink_io_deq_bits_source; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_sink_io_deq_bits_address; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_sink_io_deq_bits_mask; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_sink_io_deq_bits_data; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_sink_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
+ assign auto_out_d_ready = bundleIn_0_d_source_io_enq_ready; // @[Nodes.scala 1207:84 AsyncQueue.scala 217:19]
+ assign bundleOut_0_a_sink_clock = clock;
+ assign bundleOut_0_a_sink_reset = reset;
+ assign bundleOut_0_a_sink_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleOut_0_a_sink_io_async_mem_0_opcode = auto_in_a_mem_0_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_sink_io_async_mem_0_address = auto_in_a_mem_0_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_sink_io_async_mem_0_data = auto_in_a_mem_0_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_sink_io_async_widx = auto_in_a_widx; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_sink_io_async_safe_widx_valid = auto_in_a_safe_widx_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_sink_io_async_safe_source_reset_n = auto_in_a_safe_source_reset_n; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleIn_0_d_source_clock = clock;
+ assign bundleIn_0_d_source_reset = reset;
+ assign bundleIn_0_d_source_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_source_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_source_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_source_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_source_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_source_io_async_ridx = auto_in_d_ridx; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleIn_0_d_source_io_async_safe_ridx_valid = auto_in_d_safe_ridx_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleIn_0_d_source_io_async_safe_sink_reset_n = auto_in_d_safe_sink_reset_n; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockCrossingReg_w15(
+ input clock,
+ input [14:0] io_d,
+ output [14:0] io_q,
+ input io_en
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg [14:0] cdc_reg; // @[Reg.scala 16:16]
+ assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
+ always @(posedge clock) begin
+ if (io_en) begin // @[Reg.scala 17:18]
+ cdc_reg <= io_d; // @[Reg.scala 17:22]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ cdc_reg = _RAND_0[14:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module AsyncQueueSink_2(
+ input clock,
+ input reset,
+ output io_deq_valid,
+ output io_deq_bits_resumereq,
+ output [9:0] io_deq_bits_hartsel,
+ output io_deq_bits_ackhavereset,
+ output io_deq_bits_hrmask_0,
+ input io_async_mem_0_resumereq,
+ input io_async_mem_0_ackhavereset,
+ input io_async_mem_0_hrmask_0,
+ output io_async_ridx,
+ input io_async_widx,
+ output io_async_safe_ridx_valid,
+ input io_async_safe_widx_valid,
+ input io_async_safe_source_reset_n,
+ output io_async_safe_sink_reset_n
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+`endif // RANDOMIZE_REG_INIT
+ wire widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
+ wire widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
+ wire io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
+ wire [14:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
+ wire [14:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
+ wire io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
+ wire sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
+ wire sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
+ wire sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
+ wire source_extend_io_in; // @[AsyncQueue.scala 171:31]
+ wire source_extend_io_out; // @[AsyncQueue.scala 171:31]
+ wire source_extend_clock; // @[AsyncQueue.scala 171:31]
+ wire source_extend_reset; // @[AsyncQueue.scala 171:31]
+ wire source_valid_io_in; // @[AsyncQueue.scala 172:31]
+ wire source_valid_io_out; // @[AsyncQueue.scala 172:31]
+ wire source_valid_clock; // @[AsyncQueue.scala 172:31]
+ wire source_valid_reset; // @[AsyncQueue.scala 172:31]
+ wire source_ready = source_valid_io_out;
+ wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
+ reg ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
+ wire ridx_incremented = _ridx_T_2 ? 1'h0 : ridx_ridx_bin + io_deq_valid; // @[AsyncQueue.scala 53:23]
+ wire widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire [2:0] io_deq_bits_deq_bits_reg_io_d_lo = {2'h0,io_async_mem_0_hrmask_0}; // @[SynchronizerReg.scala 209:24]
+ wire [11:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_async_mem_0_resumereq,10'h0,io_async_mem_0_ackhavereset}; // @[SynchronizerReg.scala 209:24]
+ wire [14:0] _io_deq_bits_WIRE_1 = io_deq_bits_deq_bits_reg_io_q;
+ reg valid_reg; // @[AsyncQueue.scala 161:56]
+ reg ridx_gray; // @[AsyncQueue.scala 164:55]
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
+ .clock(widx_widx_gray_clock),
+ .reset(widx_widx_gray_reset),
+ .io_d(widx_widx_gray_io_d),
+ .io_q(widx_widx_gray_io_q)
+ );
+ ClockCrossingReg_w15 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
+ .clock(io_deq_bits_deq_bits_reg_clock),
+ .io_d(io_deq_bits_deq_bits_reg_io_d),
+ .io_q(io_deq_bits_deq_bits_reg_io_q),
+ .io_en(io_deq_bits_deq_bits_reg_io_en)
+ );
+ AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
+ .io_in(sink_valid_0_io_in),
+ .io_out(sink_valid_0_io_out),
+ .clock(sink_valid_0_clock),
+ .reset(sink_valid_0_reset)
+ );
+ AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
+ .io_in(sink_valid_1_io_in),
+ .io_out(sink_valid_1_io_out),
+ .clock(sink_valid_1_clock),
+ .reset(sink_valid_1_reset)
+ );
+ AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
+ .io_in(source_extend_io_in),
+ .io_out(source_extend_io_out),
+ .clock(source_extend_clock),
+ .reset(source_extend_reset)
+ );
+ AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
+ .io_in(source_valid_io_in),
+ .io_out(source_valid_io_out),
+ .clock(source_valid_clock),
+ .reset(source_valid_reset)
+ );
+ assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
+ assign io_deq_bits_resumereq = _io_deq_bits_WIRE_1[14]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_hartsel = _io_deq_bits_WIRE_1[13:4]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_ackhavereset = _io_deq_bits_WIRE_1[3]; // @[SynchronizerReg.scala 211:26]
+ assign io_deq_bits_hrmask_0 = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala 211:26]
+ assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
+ assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
+ assign io_async_safe_sink_reset_n = ~reset; // @[AsyncQueue.scala 189:25]
+ assign widx_widx_gray_clock = clock;
+ assign widx_widx_gray_reset = reset;
+ assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
+ assign io_deq_bits_deq_bits_reg_clock = clock;
+ assign io_deq_bits_deq_bits_reg_io_d = {io_deq_bits_deq_bits_reg_io_d_hi,io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala 209:24]
+ assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx_incremented != widx; // @[AsyncQueue.scala 146:28]
+ assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
+ assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
+ assign sink_valid_0_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 173:66]
+ assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
+ assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
+ assign sink_valid_1_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 174:66]
+ assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
+ assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
+ assign source_extend_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 175:66]
+ assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
+ assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
+ assign source_valid_reset = reset; // @[AsyncQueue.scala 176:34]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ ridx_ridx_bin <= 1'h0;
+ end else if (_ridx_T_2) begin
+ ridx_ridx_bin <= 1'h0;
+ end else begin
+ ridx_ridx_bin <= ridx_ridx_bin + io_deq_valid;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 146:28]
+ valid_reg <= 1'h0;
+ end else begin
+ valid_reg <= source_ready & ridx_incremented != widx;
+ end
+ end
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncQueue.scala 53:23]
+ ridx_gray <= 1'h0;
+ end else if (_ridx_T_2) begin
+ ridx_gray <= 1'h0;
+ end else begin
+ ridx_gray <= ridx_ridx_bin + io_deq_valid;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ ridx_ridx_bin = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ valid_reg = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ ridx_gray = _RAND_2[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ ridx_ridx_bin = 1'h0;
+ end
+ if (reset) begin
+ valid_reg = 1'h0;
+ end
+ if (reset) begin
+ ridx_gray = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLDebugModuleInnerAsync(
+ input [2:0] auto_dmiXing_in_a_mem_0_opcode,
+ input [8:0] auto_dmiXing_in_a_mem_0_address,
+ input [31:0] auto_dmiXing_in_a_mem_0_data,
+ output auto_dmiXing_in_a_ridx,
+ input auto_dmiXing_in_a_widx,
+ output auto_dmiXing_in_a_safe_ridx_valid,
+ input auto_dmiXing_in_a_safe_widx_valid,
+ input auto_dmiXing_in_a_safe_source_reset_n,
+ output auto_dmiXing_in_a_safe_sink_reset_n,
+ output [2:0] auto_dmiXing_in_d_mem_0_opcode,
+ output [1:0] auto_dmiXing_in_d_mem_0_size,
+ output auto_dmiXing_in_d_mem_0_source,
+ output [31:0] auto_dmiXing_in_d_mem_0_data,
+ input auto_dmiXing_in_d_ridx,
+ output auto_dmiXing_in_d_widx,
+ input auto_dmiXing_in_d_safe_ridx_valid,
+ output auto_dmiXing_in_d_safe_widx_valid,
+ output auto_dmiXing_in_d_safe_source_reset_n,
+ input auto_dmiXing_in_d_safe_sink_reset_n,
+ output auto_dmInner_tl_in_a_ready,
+ input auto_dmInner_tl_in_a_valid,
+ input [2:0] auto_dmInner_tl_in_a_bits_opcode,
+ input [2:0] auto_dmInner_tl_in_a_bits_param,
+ input [1:0] auto_dmInner_tl_in_a_bits_size,
+ input [6:0] auto_dmInner_tl_in_a_bits_source,
+ input [11:0] auto_dmInner_tl_in_a_bits_address,
+ input [7:0] auto_dmInner_tl_in_a_bits_mask,
+ input [63:0] auto_dmInner_tl_in_a_bits_data,
+ input auto_dmInner_tl_in_a_bits_corrupt,
+ input auto_dmInner_tl_in_d_ready,
+ output auto_dmInner_tl_in_d_valid,
+ output [2:0] auto_dmInner_tl_in_d_bits_opcode,
+ output [1:0] auto_dmInner_tl_in_d_bits_size,
+ output [6:0] auto_dmInner_tl_in_d_bits_source,
+ output [63:0] auto_dmInner_tl_in_d_bits_data,
+ input io_debug_clock,
+ input io_debug_reset,
+ input io_dmactive,
+ input io_innerCtrl_mem_0_resumereq,
+ input io_innerCtrl_mem_0_ackhavereset,
+ input io_innerCtrl_mem_0_hrmask_0,
+ output io_innerCtrl_ridx,
+ input io_innerCtrl_widx,
+ output io_innerCtrl_safe_ridx_valid,
+ input io_innerCtrl_safe_widx_valid,
+ input io_innerCtrl_safe_source_reset_n,
+ output io_innerCtrl_safe_sink_reset_n,
+ output io_hgDebugInt_0,
+ input io_hartIsInReset_0
+);
+ wire dmInner_clock; // @[Debug.scala 1741:27]
+ wire dmInner_reset; // @[Debug.scala 1741:27]
+ wire dmInner_auto_tl_in_a_ready; // @[Debug.scala 1741:27]
+ wire dmInner_auto_tl_in_a_valid; // @[Debug.scala 1741:27]
+ wire [2:0] dmInner_auto_tl_in_a_bits_opcode; // @[Debug.scala 1741:27]
+ wire [2:0] dmInner_auto_tl_in_a_bits_param; // @[Debug.scala 1741:27]
+ wire [1:0] dmInner_auto_tl_in_a_bits_size; // @[Debug.scala 1741:27]
+ wire [6:0] dmInner_auto_tl_in_a_bits_source; // @[Debug.scala 1741:27]
+ wire [11:0] dmInner_auto_tl_in_a_bits_address; // @[Debug.scala 1741:27]
+ wire [7:0] dmInner_auto_tl_in_a_bits_mask; // @[Debug.scala 1741:27]
+ wire [63:0] dmInner_auto_tl_in_a_bits_data; // @[Debug.scala 1741:27]
+ wire dmInner_auto_tl_in_a_bits_corrupt; // @[Debug.scala 1741:27]
+ wire dmInner_auto_tl_in_d_ready; // @[Debug.scala 1741:27]
+ wire dmInner_auto_tl_in_d_valid; // @[Debug.scala 1741:27]
+ wire [2:0] dmInner_auto_tl_in_d_bits_opcode; // @[Debug.scala 1741:27]
+ wire [1:0] dmInner_auto_tl_in_d_bits_size; // @[Debug.scala 1741:27]
+ wire [6:0] dmInner_auto_tl_in_d_bits_source; // @[Debug.scala 1741:27]
+ wire [63:0] dmInner_auto_tl_in_d_bits_data; // @[Debug.scala 1741:27]
+ wire dmInner_auto_dmi_in_a_ready; // @[Debug.scala 1741:27]
+ wire dmInner_auto_dmi_in_a_valid; // @[Debug.scala 1741:27]
+ wire [2:0] dmInner_auto_dmi_in_a_bits_opcode; // @[Debug.scala 1741:27]
+ wire [2:0] dmInner_auto_dmi_in_a_bits_param; // @[Debug.scala 1741:27]
+ wire [1:0] dmInner_auto_dmi_in_a_bits_size; // @[Debug.scala 1741:27]
+ wire dmInner_auto_dmi_in_a_bits_source; // @[Debug.scala 1741:27]
+ wire [8:0] dmInner_auto_dmi_in_a_bits_address; // @[Debug.scala 1741:27]
+ wire [3:0] dmInner_auto_dmi_in_a_bits_mask; // @[Debug.scala 1741:27]
+ wire [31:0] dmInner_auto_dmi_in_a_bits_data; // @[Debug.scala 1741:27]
+ wire dmInner_auto_dmi_in_a_bits_corrupt; // @[Debug.scala 1741:27]
+ wire dmInner_auto_dmi_in_d_ready; // @[Debug.scala 1741:27]
+ wire dmInner_auto_dmi_in_d_valid; // @[Debug.scala 1741:27]
+ wire [2:0] dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala 1741:27]
+ wire [1:0] dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala 1741:27]
+ wire dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala 1741:27]
+ wire [31:0] dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala 1741:27]
+ wire dmInner_io_dmactive; // @[Debug.scala 1741:27]
+ wire dmInner_io_innerCtrl_ready; // @[Debug.scala 1741:27]
+ wire dmInner_io_innerCtrl_valid; // @[Debug.scala 1741:27]
+ wire dmInner_io_innerCtrl_bits_resumereq; // @[Debug.scala 1741:27]
+ wire [9:0] dmInner_io_innerCtrl_bits_hartsel; // @[Debug.scala 1741:27]
+ wire dmInner_io_innerCtrl_bits_ackhavereset; // @[Debug.scala 1741:27]
+ wire dmInner_io_innerCtrl_bits_hrmask_0; // @[Debug.scala 1741:27]
+ wire dmInner_io_hgDebugInt_0; // @[Debug.scala 1741:27]
+ wire dmInner_io_hartIsInReset_0; // @[Debug.scala 1741:27]
+ wire dmiXing_clock; // @[Debug.scala 1742:27]
+ wire dmiXing_reset; // @[Debug.scala 1742:27]
+ wire [2:0] dmiXing_auto_in_a_mem_0_opcode; // @[Debug.scala 1742:27]
+ wire [8:0] dmiXing_auto_in_a_mem_0_address; // @[Debug.scala 1742:27]
+ wire [31:0] dmiXing_auto_in_a_mem_0_data; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_a_ridx; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_a_widx; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_a_safe_ridx_valid; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_a_safe_widx_valid; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_a_safe_source_reset_n; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_a_safe_sink_reset_n; // @[Debug.scala 1742:27]
+ wire [2:0] dmiXing_auto_in_d_mem_0_opcode; // @[Debug.scala 1742:27]
+ wire [1:0] dmiXing_auto_in_d_mem_0_size; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_d_mem_0_source; // @[Debug.scala 1742:27]
+ wire [31:0] dmiXing_auto_in_d_mem_0_data; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_d_ridx; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_d_widx; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_d_safe_ridx_valid; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_d_safe_widx_valid; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_d_safe_source_reset_n; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_in_d_safe_sink_reset_n; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_out_a_ready; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_out_a_valid; // @[Debug.scala 1742:27]
+ wire [2:0] dmiXing_auto_out_a_bits_opcode; // @[Debug.scala 1742:27]
+ wire [2:0] dmiXing_auto_out_a_bits_param; // @[Debug.scala 1742:27]
+ wire [1:0] dmiXing_auto_out_a_bits_size; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_out_a_bits_source; // @[Debug.scala 1742:27]
+ wire [8:0] dmiXing_auto_out_a_bits_address; // @[Debug.scala 1742:27]
+ wire [3:0] dmiXing_auto_out_a_bits_mask; // @[Debug.scala 1742:27]
+ wire [31:0] dmiXing_auto_out_a_bits_data; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_out_d_ready; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_out_d_valid; // @[Debug.scala 1742:27]
+ wire [2:0] dmiXing_auto_out_d_bits_opcode; // @[Debug.scala 1742:27]
+ wire [1:0] dmiXing_auto_out_d_bits_size; // @[Debug.scala 1742:27]
+ wire dmiXing_auto_out_d_bits_source; // @[Debug.scala 1742:27]
+ wire [31:0] dmiXing_auto_out_d_bits_data; // @[Debug.scala 1742:27]
+ wire dmactive_synced_dmactive_synced_dmactiveSync_clock; // @[ShiftReg.scala 45:23]
+ wire dmactive_synced_dmactive_synced_dmactiveSync_reset; // @[ShiftReg.scala 45:23]
+ wire dmactive_synced_dmactive_synced_dmactiveSync_io_d; // @[ShiftReg.scala 45:23]
+ wire dmactive_synced_dmactive_synced_dmactiveSync_io_q; // @[ShiftReg.scala 45:23]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_clock; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_reset; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala 207:22]
+ wire [9:0] dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_resumereq; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_ackhavereset; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_hrmask_0; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_ridx; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_widx; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 207:22]
+ wire dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 207:22]
+ TLDebugModuleInner dmInner ( // @[Debug.scala 1741:27]
+ .clock(dmInner_clock),
+ .reset(dmInner_reset),
+ .auto_tl_in_a_ready(dmInner_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(dmInner_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(dmInner_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(dmInner_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(dmInner_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(dmInner_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(dmInner_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(dmInner_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(dmInner_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(dmInner_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(dmInner_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(dmInner_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(dmInner_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(dmInner_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(dmInner_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(dmInner_auto_tl_in_d_bits_data),
+ .auto_dmi_in_a_ready(dmInner_auto_dmi_in_a_ready),
+ .auto_dmi_in_a_valid(dmInner_auto_dmi_in_a_valid),
+ .auto_dmi_in_a_bits_opcode(dmInner_auto_dmi_in_a_bits_opcode),
+ .auto_dmi_in_a_bits_param(dmInner_auto_dmi_in_a_bits_param),
+ .auto_dmi_in_a_bits_size(dmInner_auto_dmi_in_a_bits_size),
+ .auto_dmi_in_a_bits_source(dmInner_auto_dmi_in_a_bits_source),
+ .auto_dmi_in_a_bits_address(dmInner_auto_dmi_in_a_bits_address),
+ .auto_dmi_in_a_bits_mask(dmInner_auto_dmi_in_a_bits_mask),
+ .auto_dmi_in_a_bits_data(dmInner_auto_dmi_in_a_bits_data),
+ .auto_dmi_in_a_bits_corrupt(dmInner_auto_dmi_in_a_bits_corrupt),
+ .auto_dmi_in_d_ready(dmInner_auto_dmi_in_d_ready),
+ .auto_dmi_in_d_valid(dmInner_auto_dmi_in_d_valid),
+ .auto_dmi_in_d_bits_opcode(dmInner_auto_dmi_in_d_bits_opcode),
+ .auto_dmi_in_d_bits_size(dmInner_auto_dmi_in_d_bits_size),
+ .auto_dmi_in_d_bits_source(dmInner_auto_dmi_in_d_bits_source),
+ .auto_dmi_in_d_bits_data(dmInner_auto_dmi_in_d_bits_data),
+ .io_dmactive(dmInner_io_dmactive),
+ .io_innerCtrl_ready(dmInner_io_innerCtrl_ready),
+ .io_innerCtrl_valid(dmInner_io_innerCtrl_valid),
+ .io_innerCtrl_bits_resumereq(dmInner_io_innerCtrl_bits_resumereq),
+ .io_innerCtrl_bits_hartsel(dmInner_io_innerCtrl_bits_hartsel),
+ .io_innerCtrl_bits_ackhavereset(dmInner_io_innerCtrl_bits_ackhavereset),
+ .io_innerCtrl_bits_hrmask_0(dmInner_io_innerCtrl_bits_hrmask_0),
+ .io_hgDebugInt_0(dmInner_io_hgDebugInt_0),
+ .io_hartIsInReset_0(dmInner_io_hartIsInReset_0)
+ );
+ TLAsyncCrossingSink dmiXing ( // @[Debug.scala 1742:27]
+ .clock(dmiXing_clock),
+ .reset(dmiXing_reset),
+ .auto_in_a_mem_0_opcode(dmiXing_auto_in_a_mem_0_opcode),
+ .auto_in_a_mem_0_address(dmiXing_auto_in_a_mem_0_address),
+ .auto_in_a_mem_0_data(dmiXing_auto_in_a_mem_0_data),
+ .auto_in_a_ridx(dmiXing_auto_in_a_ridx),
+ .auto_in_a_widx(dmiXing_auto_in_a_widx),
+ .auto_in_a_safe_ridx_valid(dmiXing_auto_in_a_safe_ridx_valid),
+ .auto_in_a_safe_widx_valid(dmiXing_auto_in_a_safe_widx_valid),
+ .auto_in_a_safe_source_reset_n(dmiXing_auto_in_a_safe_source_reset_n),
+ .auto_in_a_safe_sink_reset_n(dmiXing_auto_in_a_safe_sink_reset_n),
+ .auto_in_d_mem_0_opcode(dmiXing_auto_in_d_mem_0_opcode),
+ .auto_in_d_mem_0_size(dmiXing_auto_in_d_mem_0_size),
+ .auto_in_d_mem_0_source(dmiXing_auto_in_d_mem_0_source),
+ .auto_in_d_mem_0_data(dmiXing_auto_in_d_mem_0_data),
+ .auto_in_d_ridx(dmiXing_auto_in_d_ridx),
+ .auto_in_d_widx(dmiXing_auto_in_d_widx),
+ .auto_in_d_safe_ridx_valid(dmiXing_auto_in_d_safe_ridx_valid),
+ .auto_in_d_safe_widx_valid(dmiXing_auto_in_d_safe_widx_valid),
+ .auto_in_d_safe_source_reset_n(dmiXing_auto_in_d_safe_source_reset_n),
+ .auto_in_d_safe_sink_reset_n(dmiXing_auto_in_d_safe_sink_reset_n),
+ .auto_out_a_ready(dmiXing_auto_out_a_ready),
+ .auto_out_a_valid(dmiXing_auto_out_a_valid),
+ .auto_out_a_bits_opcode(dmiXing_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(dmiXing_auto_out_a_bits_param),
+ .auto_out_a_bits_size(dmiXing_auto_out_a_bits_size),
+ .auto_out_a_bits_source(dmiXing_auto_out_a_bits_source),
+ .auto_out_a_bits_address(dmiXing_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(dmiXing_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(dmiXing_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(dmiXing_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(dmiXing_auto_out_d_ready),
+ .auto_out_d_valid(dmiXing_auto_out_d_valid),
+ .auto_out_d_bits_opcode(dmiXing_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(dmiXing_auto_out_d_bits_size),
+ .auto_out_d_bits_source(dmiXing_auto_out_d_bits_source),
+ .auto_out_d_bits_data(dmiXing_auto_out_d_bits_data)
+ );
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala 45:23]
+ .clock(dmactive_synced_dmactive_synced_dmactiveSync_clock),
+ .reset(dmactive_synced_dmactive_synced_dmactiveSync_reset),
+ .io_d(dmactive_synced_dmactive_synced_dmactiveSync_io_d),
+ .io_q(dmactive_synced_dmactive_synced_dmactiveSync_io_q)
+ );
+ AsyncQueueSink_2 dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala 207:22]
+ .clock(dmactive_synced_dmInner_io_innerCtrl_sink_clock),
+ .reset(dmactive_synced_dmInner_io_innerCtrl_sink_reset),
+ .io_deq_valid(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid),
+ .io_deq_bits_resumereq(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq),
+ .io_deq_bits_hartsel(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel),
+ .io_deq_bits_ackhavereset(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset),
+ .io_deq_bits_hrmask_0(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0),
+ .io_async_mem_0_resumereq(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_resumereq),
+ .io_async_mem_0_ackhavereset(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_ackhavereset),
+ .io_async_mem_0_hrmask_0(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_hrmask_0),
+ .io_async_ridx(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_ridx),
+ .io_async_widx(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_widx),
+ .io_async_safe_ridx_valid(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_ridx_valid),
+ .io_async_safe_widx_valid(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_widx_valid),
+ .io_async_safe_source_reset_n(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_source_reset_n),
+ .io_async_safe_sink_reset_n(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_sink_reset_n)
+ );
+ assign auto_dmiXing_in_a_ridx = dmiXing_auto_in_a_ridx; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_a_safe_ridx_valid = dmiXing_auto_in_a_safe_ridx_valid; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_a_safe_sink_reset_n = dmiXing_auto_in_a_safe_sink_reset_n; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_d_mem_0_opcode = dmiXing_auto_in_d_mem_0_opcode; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_d_mem_0_size = dmiXing_auto_in_d_mem_0_size; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_d_mem_0_source = dmiXing_auto_in_d_mem_0_source; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_d_mem_0_data = dmiXing_auto_in_d_mem_0_data; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_d_widx = dmiXing_auto_in_d_widx; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_d_safe_widx_valid = dmiXing_auto_in_d_safe_widx_valid; // @[LazyModule.scala 309:16]
+ assign auto_dmiXing_in_d_safe_source_reset_n = dmiXing_auto_in_d_safe_source_reset_n; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_tl_in_a_ready = dmInner_auto_tl_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_tl_in_d_valid = dmInner_auto_tl_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_tl_in_d_bits_opcode = dmInner_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_tl_in_d_bits_size = dmInner_auto_tl_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_tl_in_d_bits_source = dmInner_auto_tl_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_tl_in_d_bits_data = dmInner_auto_tl_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign io_innerCtrl_ridx = dmactive_synced_dmInner_io_innerCtrl_sink_io_async_ridx; // @[AsyncQueue.scala 208:19]
+ assign io_innerCtrl_safe_ridx_valid = dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 208:19]
+ assign io_innerCtrl_safe_sink_reset_n = dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 208:19]
+ assign io_hgDebugInt_0 = dmInner_io_hgDebugInt_0; // @[Debug.scala 1789:21]
+ assign dmInner_clock = io_debug_clock; // @[Debug.scala 1782:28]
+ assign dmInner_reset = io_debug_reset; // @[Debug.scala 1783:28]
+ assign dmInner_auto_tl_in_a_valid = auto_dmInner_tl_in_a_valid; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_a_bits_opcode = auto_dmInner_tl_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_a_bits_param = auto_dmInner_tl_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_a_bits_size = auto_dmInner_tl_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_a_bits_source = auto_dmInner_tl_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_a_bits_address = auto_dmInner_tl_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_a_bits_mask = auto_dmInner_tl_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_a_bits_data = auto_dmInner_tl_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_a_bits_corrupt = auto_dmInner_tl_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_tl_in_d_ready = auto_dmInner_tl_in_d_ready; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmi_in_a_valid = dmiXing_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_a_bits_opcode = dmiXing_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_a_bits_param = dmiXing_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_a_bits_size = dmiXing_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_a_bits_source = dmiXing_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_a_bits_address = dmiXing_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_a_bits_mask = dmiXing_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_a_bits_data = dmiXing_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_a_bits_corrupt = dmiXing_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign dmInner_auto_dmi_in_d_ready = dmiXing_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign dmInner_io_dmactive = dmactive_synced_dmactive_synced_dmactiveSync_io_q; // @[ShiftReg.scala 48:{24,24}]
+ assign dmInner_io_innerCtrl_valid = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[Debug.scala 1787:35]
+ assign dmInner_io_innerCtrl_bits_resumereq = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[Debug.scala 1787:35]
+ assign dmInner_io_innerCtrl_bits_hartsel = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[Debug.scala 1787:35]
+ assign dmInner_io_innerCtrl_bits_ackhavereset = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[Debug.scala 1787:35]
+ assign dmInner_io_innerCtrl_bits_hrmask_0 = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[Debug.scala 1787:35]
+ assign dmInner_io_hartIsInReset_0 = io_hartIsInReset_0; // @[Debug.scala 1791:39]
+ assign dmiXing_clock = io_debug_clock; // @[Debug.scala 1777:16 LazyModule.scala 350:31]
+ assign dmiXing_reset = io_debug_reset; // @[Debug.scala 1778:16 LazyModule.scala 352:31]
+ assign dmiXing_auto_in_a_mem_0_opcode = auto_dmiXing_in_a_mem_0_opcode; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_in_a_mem_0_address = auto_dmiXing_in_a_mem_0_address; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_in_a_mem_0_data = auto_dmiXing_in_a_mem_0_data; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_in_a_widx = auto_dmiXing_in_a_widx; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_in_a_safe_widx_valid = auto_dmiXing_in_a_safe_widx_valid; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_in_a_safe_source_reset_n = auto_dmiXing_in_a_safe_source_reset_n; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_in_d_ridx = auto_dmiXing_in_d_ridx; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_in_d_safe_ridx_valid = auto_dmiXing_in_d_safe_ridx_valid; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_in_d_safe_sink_reset_n = auto_dmiXing_in_d_safe_sink_reset_n; // @[LazyModule.scala 309:16]
+ assign dmiXing_auto_out_a_ready = dmInner_auto_dmi_in_a_ready; // @[LazyModule.scala 296:16]
+ assign dmiXing_auto_out_d_valid = dmInner_auto_dmi_in_d_valid; // @[LazyModule.scala 296:16]
+ assign dmiXing_auto_out_d_bits_opcode = dmInner_auto_dmi_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign dmiXing_auto_out_d_bits_size = dmInner_auto_dmi_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign dmiXing_auto_out_d_bits_source = dmInner_auto_dmi_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign dmiXing_auto_out_d_bits_data = dmInner_auto_dmi_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign dmactive_synced_dmactive_synced_dmactiveSync_clock = io_debug_clock; // @[Debug.scala 1777:16 LazyModule.scala 350:31]
+ assign dmactive_synced_dmactive_synced_dmactiveSync_reset = io_debug_reset; // @[Debug.scala 1778:16 LazyModule.scala 352:31]
+ assign dmactive_synced_dmactive_synced_dmactiveSync_io_d = io_dmactive; // @[ShiftReg.scala 47:16]
+ assign dmactive_synced_dmInner_io_innerCtrl_sink_clock = io_debug_clock; // @[Debug.scala 1777:16 LazyModule.scala 350:31]
+ assign dmactive_synced_dmInner_io_innerCtrl_sink_reset = io_debug_reset; // @[Debug.scala 1778:16 LazyModule.scala 352:31]
+ assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_resumereq = io_innerCtrl_mem_0_resumereq; // @[AsyncQueue.scala 208:19]
+ assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_ackhavereset = io_innerCtrl_mem_0_ackhavereset; // @[AsyncQueue.scala 208:19]
+ assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_hrmask_0 = io_innerCtrl_mem_0_hrmask_0; // @[AsyncQueue.scala 208:19]
+ assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_widx = io_innerCtrl_widx; // @[AsyncQueue.scala 208:19]
+ assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_widx_valid = io_innerCtrl_safe_widx_valid; // @[AsyncQueue.scala 208:19]
+ assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_source_reset_n = io_innerCtrl_safe_source_reset_n; // @[AsyncQueue.scala 208:19]
+endmodule
+module TLDebugModule(
+ output auto_dmInner_dmInner_tl_in_a_ready,
+ input auto_dmInner_dmInner_tl_in_a_valid,
+ input [2:0] auto_dmInner_dmInner_tl_in_a_bits_opcode,
+ input [2:0] auto_dmInner_dmInner_tl_in_a_bits_param,
+ input [1:0] auto_dmInner_dmInner_tl_in_a_bits_size,
+ input [6:0] auto_dmInner_dmInner_tl_in_a_bits_source,
+ input [11:0] auto_dmInner_dmInner_tl_in_a_bits_address,
+ input [7:0] auto_dmInner_dmInner_tl_in_a_bits_mask,
+ input [63:0] auto_dmInner_dmInner_tl_in_a_bits_data,
+ input auto_dmInner_dmInner_tl_in_a_bits_corrupt,
+ input auto_dmInner_dmInner_tl_in_d_ready,
+ output auto_dmInner_dmInner_tl_in_d_valid,
+ output [2:0] auto_dmInner_dmInner_tl_in_d_bits_opcode,
+ output [1:0] auto_dmInner_dmInner_tl_in_d_bits_size,
+ output [6:0] auto_dmInner_dmInner_tl_in_d_bits_source,
+ output [63:0] auto_dmInner_dmInner_tl_in_d_bits_data,
+ output auto_dmOuter_intsource_out_sync_0,
+ input io_debug_clock,
+ input io_debug_reset,
+ output io_ctrl_dmactive,
+ input io_ctrl_dmactiveAck,
+ output io_dmi_dmi_req_ready,
+ input io_dmi_dmi_req_valid,
+ input [6:0] io_dmi_dmi_req_bits_addr,
+ input [31:0] io_dmi_dmi_req_bits_data,
+ input [1:0] io_dmi_dmi_req_bits_op,
+ input io_dmi_dmi_resp_ready,
+ output io_dmi_dmi_resp_valid,
+ output [31:0] io_dmi_dmi_resp_bits_data,
+ output [1:0] io_dmi_dmi_resp_bits_resp,
+ input io_dmi_dmiClock,
+ input io_dmi_dmiReset,
+ input io_hartIsInReset_0
+);
+ wire [2:0] dmOuter_auto_asource_out_a_mem_0_opcode; // @[Debug.scala 1819:53]
+ wire [8:0] dmOuter_auto_asource_out_a_mem_0_address; // @[Debug.scala 1819:53]
+ wire [31:0] dmOuter_auto_asource_out_a_mem_0_data; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_a_ridx; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_a_widx; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_a_safe_ridx_valid; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_a_safe_widx_valid; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_a_safe_source_reset_n; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_a_safe_sink_reset_n; // @[Debug.scala 1819:53]
+ wire [2:0] dmOuter_auto_asource_out_d_mem_0_opcode; // @[Debug.scala 1819:53]
+ wire [1:0] dmOuter_auto_asource_out_d_mem_0_size; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_d_mem_0_source; // @[Debug.scala 1819:53]
+ wire [31:0] dmOuter_auto_asource_out_d_mem_0_data; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_d_ridx; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_d_widx; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_d_safe_ridx_valid; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_d_safe_widx_valid; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_d_safe_source_reset_n; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_asource_out_d_safe_sink_reset_n; // @[Debug.scala 1819:53]
+ wire dmOuter_auto_intsource_out_sync_0; // @[Debug.scala 1819:53]
+ wire dmOuter_io_dmi_clock; // @[Debug.scala 1819:53]
+ wire dmOuter_io_dmi_reset; // @[Debug.scala 1819:53]
+ wire dmOuter_io_dmi_req_ready; // @[Debug.scala 1819:53]
+ wire dmOuter_io_dmi_req_valid; // @[Debug.scala 1819:53]
+ wire [6:0] dmOuter_io_dmi_req_bits_addr; // @[Debug.scala 1819:53]
+ wire [31:0] dmOuter_io_dmi_req_bits_data; // @[Debug.scala 1819:53]
+ wire [1:0] dmOuter_io_dmi_req_bits_op; // @[Debug.scala 1819:53]
+ wire dmOuter_io_dmi_resp_ready; // @[Debug.scala 1819:53]
+ wire dmOuter_io_dmi_resp_valid; // @[Debug.scala 1819:53]
+ wire [31:0] dmOuter_io_dmi_resp_bits_data; // @[Debug.scala 1819:53]
+ wire [1:0] dmOuter_io_dmi_resp_bits_resp; // @[Debug.scala 1819:53]
+ wire dmOuter_io_ctrl_dmactive; // @[Debug.scala 1819:53]
+ wire dmOuter_io_ctrl_dmactiveAck; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_ridx; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_widx; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1819:53]
+ wire dmOuter_io_innerCtrl_safe_sink_reset_n; // @[Debug.scala 1819:53]
+ wire dmOuter_io_hgDebugInt_0; // @[Debug.scala 1819:53]
+ wire [2:0] dmInner_auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala 1820:53]
+ wire [8:0] dmInner_auto_dmiXing_in_a_mem_0_address; // @[Debug.scala 1820:53]
+ wire [31:0] dmInner_auto_dmiXing_in_a_mem_0_data; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_a_ridx; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_a_widx; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_a_safe_ridx_valid; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_a_safe_sink_reset_n; // @[Debug.scala 1820:53]
+ wire [2:0] dmInner_auto_dmiXing_in_d_mem_0_opcode; // @[Debug.scala 1820:53]
+ wire [1:0] dmInner_auto_dmiXing_in_d_mem_0_size; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_d_mem_0_source; // @[Debug.scala 1820:53]
+ wire [31:0] dmInner_auto_dmiXing_in_d_mem_0_data; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_d_ridx; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_d_widx; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_d_safe_widx_valid; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_d_safe_source_reset_n; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmInner_tl_in_a_ready; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmInner_tl_in_a_valid; // @[Debug.scala 1820:53]
+ wire [2:0] dmInner_auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala 1820:53]
+ wire [2:0] dmInner_auto_dmInner_tl_in_a_bits_param; // @[Debug.scala 1820:53]
+ wire [1:0] dmInner_auto_dmInner_tl_in_a_bits_size; // @[Debug.scala 1820:53]
+ wire [6:0] dmInner_auto_dmInner_tl_in_a_bits_source; // @[Debug.scala 1820:53]
+ wire [11:0] dmInner_auto_dmInner_tl_in_a_bits_address; // @[Debug.scala 1820:53]
+ wire [7:0] dmInner_auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala 1820:53]
+ wire [63:0] dmInner_auto_dmInner_tl_in_a_bits_data; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmInner_tl_in_d_ready; // @[Debug.scala 1820:53]
+ wire dmInner_auto_dmInner_tl_in_d_valid; // @[Debug.scala 1820:53]
+ wire [2:0] dmInner_auto_dmInner_tl_in_d_bits_opcode; // @[Debug.scala 1820:53]
+ wire [1:0] dmInner_auto_dmInner_tl_in_d_bits_size; // @[Debug.scala 1820:53]
+ wire [6:0] dmInner_auto_dmInner_tl_in_d_bits_source; // @[Debug.scala 1820:53]
+ wire [63:0] dmInner_auto_dmInner_tl_in_d_bits_data; // @[Debug.scala 1820:53]
+ wire dmInner_io_debug_clock; // @[Debug.scala 1820:53]
+ wire dmInner_io_debug_reset; // @[Debug.scala 1820:53]
+ wire dmInner_io_dmactive; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_ridx; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_widx; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1820:53]
+ wire dmInner_io_innerCtrl_safe_sink_reset_n; // @[Debug.scala 1820:53]
+ wire dmInner_io_hgDebugInt_0; // @[Debug.scala 1820:53]
+ wire dmInner_io_hartIsInReset_0; // @[Debug.scala 1820:53]
+ TLDebugModuleOuterAsync dmOuter ( // @[Debug.scala 1819:53]
+ .auto_asource_out_a_mem_0_opcode(dmOuter_auto_asource_out_a_mem_0_opcode),
+ .auto_asource_out_a_mem_0_address(dmOuter_auto_asource_out_a_mem_0_address),
+ .auto_asource_out_a_mem_0_data(dmOuter_auto_asource_out_a_mem_0_data),
+ .auto_asource_out_a_ridx(dmOuter_auto_asource_out_a_ridx),
+ .auto_asource_out_a_widx(dmOuter_auto_asource_out_a_widx),
+ .auto_asource_out_a_safe_ridx_valid(dmOuter_auto_asource_out_a_safe_ridx_valid),
+ .auto_asource_out_a_safe_widx_valid(dmOuter_auto_asource_out_a_safe_widx_valid),
+ .auto_asource_out_a_safe_source_reset_n(dmOuter_auto_asource_out_a_safe_source_reset_n),
+ .auto_asource_out_a_safe_sink_reset_n(dmOuter_auto_asource_out_a_safe_sink_reset_n),
+ .auto_asource_out_d_mem_0_opcode(dmOuter_auto_asource_out_d_mem_0_opcode),
+ .auto_asource_out_d_mem_0_size(dmOuter_auto_asource_out_d_mem_0_size),
+ .auto_asource_out_d_mem_0_source(dmOuter_auto_asource_out_d_mem_0_source),
+ .auto_asource_out_d_mem_0_data(dmOuter_auto_asource_out_d_mem_0_data),
+ .auto_asource_out_d_ridx(dmOuter_auto_asource_out_d_ridx),
+ .auto_asource_out_d_widx(dmOuter_auto_asource_out_d_widx),
+ .auto_asource_out_d_safe_ridx_valid(dmOuter_auto_asource_out_d_safe_ridx_valid),
+ .auto_asource_out_d_safe_widx_valid(dmOuter_auto_asource_out_d_safe_widx_valid),
+ .auto_asource_out_d_safe_source_reset_n(dmOuter_auto_asource_out_d_safe_source_reset_n),
+ .auto_asource_out_d_safe_sink_reset_n(dmOuter_auto_asource_out_d_safe_sink_reset_n),
+ .auto_intsource_out_sync_0(dmOuter_auto_intsource_out_sync_0),
+ .io_dmi_clock(dmOuter_io_dmi_clock),
+ .io_dmi_reset(dmOuter_io_dmi_reset),
+ .io_dmi_req_ready(dmOuter_io_dmi_req_ready),
+ .io_dmi_req_valid(dmOuter_io_dmi_req_valid),
+ .io_dmi_req_bits_addr(dmOuter_io_dmi_req_bits_addr),
+ .io_dmi_req_bits_data(dmOuter_io_dmi_req_bits_data),
+ .io_dmi_req_bits_op(dmOuter_io_dmi_req_bits_op),
+ .io_dmi_resp_ready(dmOuter_io_dmi_resp_ready),
+ .io_dmi_resp_valid(dmOuter_io_dmi_resp_valid),
+ .io_dmi_resp_bits_data(dmOuter_io_dmi_resp_bits_data),
+ .io_dmi_resp_bits_resp(dmOuter_io_dmi_resp_bits_resp),
+ .io_ctrl_dmactive(dmOuter_io_ctrl_dmactive),
+ .io_ctrl_dmactiveAck(dmOuter_io_ctrl_dmactiveAck),
+ .io_innerCtrl_mem_0_resumereq(dmOuter_io_innerCtrl_mem_0_resumereq),
+ .io_innerCtrl_mem_0_ackhavereset(dmOuter_io_innerCtrl_mem_0_ackhavereset),
+ .io_innerCtrl_mem_0_hrmask_0(dmOuter_io_innerCtrl_mem_0_hrmask_0),
+ .io_innerCtrl_ridx(dmOuter_io_innerCtrl_ridx),
+ .io_innerCtrl_widx(dmOuter_io_innerCtrl_widx),
+ .io_innerCtrl_safe_ridx_valid(dmOuter_io_innerCtrl_safe_ridx_valid),
+ .io_innerCtrl_safe_widx_valid(dmOuter_io_innerCtrl_safe_widx_valid),
+ .io_innerCtrl_safe_source_reset_n(dmOuter_io_innerCtrl_safe_source_reset_n),
+ .io_innerCtrl_safe_sink_reset_n(dmOuter_io_innerCtrl_safe_sink_reset_n),
+ .io_hgDebugInt_0(dmOuter_io_hgDebugInt_0)
+ );
+ TLDebugModuleInnerAsync dmInner ( // @[Debug.scala 1820:53]
+ .auto_dmiXing_in_a_mem_0_opcode(dmInner_auto_dmiXing_in_a_mem_0_opcode),
+ .auto_dmiXing_in_a_mem_0_address(dmInner_auto_dmiXing_in_a_mem_0_address),
+ .auto_dmiXing_in_a_mem_0_data(dmInner_auto_dmiXing_in_a_mem_0_data),
+ .auto_dmiXing_in_a_ridx(dmInner_auto_dmiXing_in_a_ridx),
+ .auto_dmiXing_in_a_widx(dmInner_auto_dmiXing_in_a_widx),
+ .auto_dmiXing_in_a_safe_ridx_valid(dmInner_auto_dmiXing_in_a_safe_ridx_valid),
+ .auto_dmiXing_in_a_safe_widx_valid(dmInner_auto_dmiXing_in_a_safe_widx_valid),
+ .auto_dmiXing_in_a_safe_source_reset_n(dmInner_auto_dmiXing_in_a_safe_source_reset_n),
+ .auto_dmiXing_in_a_safe_sink_reset_n(dmInner_auto_dmiXing_in_a_safe_sink_reset_n),
+ .auto_dmiXing_in_d_mem_0_opcode(dmInner_auto_dmiXing_in_d_mem_0_opcode),
+ .auto_dmiXing_in_d_mem_0_size(dmInner_auto_dmiXing_in_d_mem_0_size),
+ .auto_dmiXing_in_d_mem_0_source(dmInner_auto_dmiXing_in_d_mem_0_source),
+ .auto_dmiXing_in_d_mem_0_data(dmInner_auto_dmiXing_in_d_mem_0_data),
+ .auto_dmiXing_in_d_ridx(dmInner_auto_dmiXing_in_d_ridx),
+ .auto_dmiXing_in_d_widx(dmInner_auto_dmiXing_in_d_widx),
+ .auto_dmiXing_in_d_safe_ridx_valid(dmInner_auto_dmiXing_in_d_safe_ridx_valid),
+ .auto_dmiXing_in_d_safe_widx_valid(dmInner_auto_dmiXing_in_d_safe_widx_valid),
+ .auto_dmiXing_in_d_safe_source_reset_n(dmInner_auto_dmiXing_in_d_safe_source_reset_n),
+ .auto_dmiXing_in_d_safe_sink_reset_n(dmInner_auto_dmiXing_in_d_safe_sink_reset_n),
+ .auto_dmInner_tl_in_a_ready(dmInner_auto_dmInner_tl_in_a_ready),
+ .auto_dmInner_tl_in_a_valid(dmInner_auto_dmInner_tl_in_a_valid),
+ .auto_dmInner_tl_in_a_bits_opcode(dmInner_auto_dmInner_tl_in_a_bits_opcode),
+ .auto_dmInner_tl_in_a_bits_param(dmInner_auto_dmInner_tl_in_a_bits_param),
+ .auto_dmInner_tl_in_a_bits_size(dmInner_auto_dmInner_tl_in_a_bits_size),
+ .auto_dmInner_tl_in_a_bits_source(dmInner_auto_dmInner_tl_in_a_bits_source),
+ .auto_dmInner_tl_in_a_bits_address(dmInner_auto_dmInner_tl_in_a_bits_address),
+ .auto_dmInner_tl_in_a_bits_mask(dmInner_auto_dmInner_tl_in_a_bits_mask),
+ .auto_dmInner_tl_in_a_bits_data(dmInner_auto_dmInner_tl_in_a_bits_data),
+ .auto_dmInner_tl_in_a_bits_corrupt(dmInner_auto_dmInner_tl_in_a_bits_corrupt),
+ .auto_dmInner_tl_in_d_ready(dmInner_auto_dmInner_tl_in_d_ready),
+ .auto_dmInner_tl_in_d_valid(dmInner_auto_dmInner_tl_in_d_valid),
+ .auto_dmInner_tl_in_d_bits_opcode(dmInner_auto_dmInner_tl_in_d_bits_opcode),
+ .auto_dmInner_tl_in_d_bits_size(dmInner_auto_dmInner_tl_in_d_bits_size),
+ .auto_dmInner_tl_in_d_bits_source(dmInner_auto_dmInner_tl_in_d_bits_source),
+ .auto_dmInner_tl_in_d_bits_data(dmInner_auto_dmInner_tl_in_d_bits_data),
+ .io_debug_clock(dmInner_io_debug_clock),
+ .io_debug_reset(dmInner_io_debug_reset),
+ .io_dmactive(dmInner_io_dmactive),
+ .io_innerCtrl_mem_0_resumereq(dmInner_io_innerCtrl_mem_0_resumereq),
+ .io_innerCtrl_mem_0_ackhavereset(dmInner_io_innerCtrl_mem_0_ackhavereset),
+ .io_innerCtrl_mem_0_hrmask_0(dmInner_io_innerCtrl_mem_0_hrmask_0),
+ .io_innerCtrl_ridx(dmInner_io_innerCtrl_ridx),
+ .io_innerCtrl_widx(dmInner_io_innerCtrl_widx),
+ .io_innerCtrl_safe_ridx_valid(dmInner_io_innerCtrl_safe_ridx_valid),
+ .io_innerCtrl_safe_widx_valid(dmInner_io_innerCtrl_safe_widx_valid),
+ .io_innerCtrl_safe_source_reset_n(dmInner_io_innerCtrl_safe_source_reset_n),
+ .io_innerCtrl_safe_sink_reset_n(dmInner_io_innerCtrl_safe_sink_reset_n),
+ .io_hgDebugInt_0(dmInner_io_hgDebugInt_0),
+ .io_hartIsInReset_0(dmInner_io_hartIsInReset_0)
+ );
+ assign auto_dmInner_dmInner_tl_in_a_ready = dmInner_auto_dmInner_tl_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_dmInner_tl_in_d_valid = dmInner_auto_dmInner_tl_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_dmInner_tl_in_d_bits_opcode = dmInner_auto_dmInner_tl_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_dmInner_tl_in_d_bits_size = dmInner_auto_dmInner_tl_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_dmInner_tl_in_d_bits_source = dmInner_auto_dmInner_tl_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_dmInner_dmInner_tl_in_d_bits_data = dmInner_auto_dmInner_tl_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_dmOuter_intsource_out_sync_0 = dmOuter_auto_intsource_out_sync_0; // @[LazyModule.scala 311:12]
+ assign io_ctrl_dmactive = dmOuter_io_ctrl_dmactive; // @[Debug.scala 1879:13]
+ assign io_dmi_dmi_req_ready = dmOuter_io_dmi_req_ready; // @[Debug.scala 1857:18]
+ assign io_dmi_dmi_resp_valid = dmOuter_io_dmi_resp_valid; // @[Debug.scala 1857:18]
+ assign io_dmi_dmi_resp_bits_data = dmOuter_io_dmi_resp_bits_data; // @[Debug.scala 1857:18]
+ assign io_dmi_dmi_resp_bits_resp = dmOuter_io_dmi_resp_bits_resp; // @[Debug.scala 1857:18]
+ assign dmOuter_auto_asource_out_a_ridx = dmInner_auto_dmiXing_in_a_ridx; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_a_safe_ridx_valid = dmInner_auto_dmiXing_in_a_safe_ridx_valid; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_a_safe_sink_reset_n = dmInner_auto_dmiXing_in_a_safe_sink_reset_n; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_d_mem_0_opcode = dmInner_auto_dmiXing_in_d_mem_0_opcode; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_d_mem_0_size = dmInner_auto_dmiXing_in_d_mem_0_size; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_d_mem_0_source = dmInner_auto_dmiXing_in_d_mem_0_source; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_d_mem_0_data = dmInner_auto_dmiXing_in_d_mem_0_data; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_d_widx = dmInner_auto_dmiXing_in_d_widx; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_d_safe_widx_valid = dmInner_auto_dmiXing_in_d_safe_widx_valid; // @[LazyModule.scala 298:16]
+ assign dmOuter_auto_asource_out_d_safe_source_reset_n = dmInner_auto_dmiXing_in_d_safe_source_reset_n; // @[LazyModule.scala 298:16]
+ assign dmOuter_io_dmi_clock = io_dmi_dmiClock; // @[Debug.scala 1859:35]
+ assign dmOuter_io_dmi_reset = io_dmi_dmiReset; // @[Debug.scala 1858:35]
+ assign dmOuter_io_dmi_req_valid = io_dmi_dmi_req_valid; // @[Debug.scala 1857:18]
+ assign dmOuter_io_dmi_req_bits_addr = io_dmi_dmi_req_bits_addr; // @[Debug.scala 1857:18]
+ assign dmOuter_io_dmi_req_bits_data = io_dmi_dmi_req_bits_data; // @[Debug.scala 1857:18]
+ assign dmOuter_io_dmi_req_bits_op = io_dmi_dmi_req_bits_op; // @[Debug.scala 1857:18]
+ assign dmOuter_io_dmi_resp_ready = io_dmi_dmi_resp_ready; // @[Debug.scala 1857:18]
+ assign dmOuter_io_ctrl_dmactiveAck = io_ctrl_dmactiveAck; // @[Debug.scala 1879:13]
+ assign dmOuter_io_innerCtrl_ridx = dmInner_io_innerCtrl_ridx; // @[Debug.scala 1874:36]
+ assign dmOuter_io_innerCtrl_safe_ridx_valid = dmInner_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1874:36]
+ assign dmOuter_io_innerCtrl_safe_sink_reset_n = dmInner_io_innerCtrl_safe_sink_reset_n; // @[Debug.scala 1874:36]
+ assign dmOuter_io_hgDebugInt_0 = dmInner_io_hgDebugInt_0; // @[Debug.scala 1877:36]
+ assign dmInner_auto_dmiXing_in_a_mem_0_opcode = dmOuter_auto_asource_out_a_mem_0_opcode; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmiXing_in_a_mem_0_address = dmOuter_auto_asource_out_a_mem_0_address; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmiXing_in_a_mem_0_data = dmOuter_auto_asource_out_a_mem_0_data; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmiXing_in_a_widx = dmOuter_auto_asource_out_a_widx; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmiXing_in_a_safe_widx_valid = dmOuter_auto_asource_out_a_safe_widx_valid; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmiXing_in_a_safe_source_reset_n = dmOuter_auto_asource_out_a_safe_source_reset_n; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmiXing_in_d_ridx = dmOuter_auto_asource_out_d_ridx; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmiXing_in_d_safe_ridx_valid = dmOuter_auto_asource_out_d_safe_ridx_valid; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmiXing_in_d_safe_sink_reset_n = dmOuter_auto_asource_out_d_safe_sink_reset_n; // @[LazyModule.scala 298:16]
+ assign dmInner_auto_dmInner_tl_in_a_valid = auto_dmInner_dmInner_tl_in_a_valid; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_a_bits_opcode = auto_dmInner_dmInner_tl_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_a_bits_param = auto_dmInner_dmInner_tl_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_a_bits_size = auto_dmInner_dmInner_tl_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_a_bits_source = auto_dmInner_dmInner_tl_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_a_bits_address = auto_dmInner_dmInner_tl_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_a_bits_mask = auto_dmInner_dmInner_tl_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_a_bits_data = auto_dmInner_dmInner_tl_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_a_bits_corrupt = auto_dmInner_dmInner_tl_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign dmInner_auto_dmInner_tl_in_d_ready = auto_dmInner_dmInner_tl_in_d_ready; // @[LazyModule.scala 309:16]
+ assign dmInner_io_debug_clock = io_debug_clock; // @[Debug.scala 1870:35]
+ assign dmInner_io_debug_reset = io_debug_reset; // @[Debug.scala 1871:35]
+ assign dmInner_io_dmactive = dmOuter_io_ctrl_dmactive; // @[Debug.scala 1875:36]
+ assign dmInner_io_innerCtrl_mem_0_resumereq = dmOuter_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1874:36]
+ assign dmInner_io_innerCtrl_mem_0_ackhavereset = dmOuter_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1874:36]
+ assign dmInner_io_innerCtrl_mem_0_hrmask_0 = dmOuter_io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala 1874:36]
+ assign dmInner_io_innerCtrl_widx = dmOuter_io_innerCtrl_widx; // @[Debug.scala 1874:36]
+ assign dmInner_io_innerCtrl_safe_widx_valid = dmOuter_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1874:36]
+ assign dmInner_io_innerCtrl_safe_source_reset_n = dmOuter_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1874:36]
+ assign dmInner_io_hartIsInReset_0 = io_hartIsInReset_0; // @[Debug.scala 1881:37]
+endmodule
+module BundleBridgeNexus_13(
+ output auto_out
+);
+ wire outputs_0 = 1'h0; // @[HasTiles.scala 162:32]
+ assign auto_out = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
+endmodule
+module AsyncResetRegVec_w2_i0(
+ input clock,
+ input reset,
+ input [1:0] io_d,
+ output [1:0] io_q
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
+ assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncResetReg.scala 65:16]
+ reg_ <= 2'h0; // @[AsyncResetReg.scala 66:9]
+ end else begin
+ reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ reg_ = _RAND_0[1:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ reg_ = 2'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module IntSyncCrossingSource_5(
+ input clock,
+ input reset,
+ input auto_in_0,
+ input auto_in_1,
+ output auto_out_sync_0,
+ output auto_out_sync_1
+);
+ wire reg__clock; // @[AsyncResetReg.scala 89:21]
+ wire reg__reset; // @[AsyncResetReg.scala 89:21]
+ wire [1:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
+ wire [1:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
+ AsyncResetRegVec_w2_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
+ .clock(reg__clock),
+ .reset(reg__reset),
+ .io_d(reg__io_d),
+ .io_q(reg__io_q)
+ );
+ assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
+ assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
+ assign reg__clock = clock;
+ assign reg__reset = reset;
+ assign reg__io_d = {auto_in_1,auto_in_0}; // @[Cat.scala 31:58]
+endmodule
+module TLMonitor_52(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [16:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [95:0] _RAND_9;
+ reg [319:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [16:0] _GEN_71 = {{14'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [16:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [16:0] _T_33 = io_in_a_bits_address ^ 17'h10000; // @[Parameters.scala 137:31]
+ wire [17:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [17:0] _T_36 = $signed(_T_34) & -18'sh10000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 18'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_233 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_267 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_268 = io_in_a_bits_mask & _T_267; // @[Monitor.scala 127:31]
+ wire _T_269 = _T_268 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_273 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_303 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_311 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_341 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_349 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_379 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [16:0] address; // @[Monitor.scala 388:22]
+ wire _T_537 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_538 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_542 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_546 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_550 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_554 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_561 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_570 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_574 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_588 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_591 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_593 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_595 = ~_T_593[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_599 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_588 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_612 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_614 = _T_612[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_619 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_620 = 3'h1 == _GEN_32 | _T_619; // @[Monitor.scala 685:77]
+ wire _T_624 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_631 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_632 = 3'h1 == _GEN_48 | _T_631; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_636 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_644 = _T_599 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_648 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_657 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_233 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_233 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_233 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_233 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_233 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_233 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_233 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_233 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_269 & (io_in_a_valid & _T_233 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_233 & ~reset & ~_T_269) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_273 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_273 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_273 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_273 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_273 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_273 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_303 & (io_in_a_valid & _T_273 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_273 & ~reset & ~_T_303) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_273 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_273 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_311 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_311 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_311 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_311 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_311 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_311 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_341 & (io_in_a_valid & _T_311 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_311 & ~reset & ~_T_341) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_311 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_311 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_349 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_349 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_349 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_349 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_349 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_349 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_379 & (io_in_a_valid & _T_349 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_349 & ~reset & ~_T_379) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_349 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_349 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_349 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_349 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_538 & (_T_537 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_537 & ~reset & ~_T_538) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_542 & (_T_537 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_537 & ~reset & ~_T_542) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_546 & (_T_537 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_537 & ~reset & ~_T_546) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_550 & (_T_537 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_537 & ~reset & ~_T_550) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_554 & (_T_537 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_537 & ~reset & ~_T_554) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_570 & (_T_561 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_561 & _T_2 & ~_T_570) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at BootROM.scala:84:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_574 & (_T_561 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_561 & _T_2 & ~_T_574) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at BootROM.scala:84:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_595 & (_T_591 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_591 & ~reset & ~_T_595) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_614 & (_T_599 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_599 & _T_2 & ~_T_614) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BootROM.scala:84:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_599 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_599 & same_cycle_resp & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BootROM.scala:84:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_624 & (_T_599 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_599 & same_cycle_resp & _T_2 & ~_T_624) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BootROM.scala:84:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_632 & (_T_599 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_599 & ~same_cycle_resp & _T_2 & ~_T_632) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at BootROM.scala:84:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_636 & (_T_599 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_599 & ~same_cycle_resp & _T_2 & ~_T_636) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at BootROM.scala:84:18)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_648 & (_T_644 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_644 & _T_2 & ~_T_648) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_657 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_657) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at BootROM.scala:84:18)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[16:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[1:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[6:0];
+ _RAND_9 = {3{`RANDOM}};
+ inflight = _RAND_9[79:0];
+ _RAND_10 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_10[319:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_sizes = _RAND_11[319:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLROM(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [1:0] auto_in_a_bits_size,
+ input [6:0] auto_in_a_bits_source,
+ input [16:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [1:0] auto_in_d_bits_size,
+ output [6:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [16:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire [8:0] index = auto_in_a_bits_address[11:3]; // @[BootROM.scala 49:34]
+ wire [3:0] high = auto_in_a_bits_address[15:12]; // @[BootROM.scala 50:68]
+ wire [63:0] _GEN_1 = 9'h1 == index ? 64'h780006f00050463 : 64'hf1402573020005b7; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_2 = 9'h2 == index ? 64'h10069300458613 : _GEN_1; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_3 = 9'h3 == index ? 64'h46061300d62023 : _GEN_2; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_4 = 9'h4 == index ? 64'hfe069ae3ffc62683 : _GEN_3; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_5 = 9'h5 == index ? 64'h6c0006f : _GEN_4; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_6 = 9'h6 == index ? 64'h0 : _GEN_5; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_7 = 9'h7 == index ? 64'h0 : _GEN_6; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_8 = 9'h8 == index ? 64'hfc05051300000517 : _GEN_7; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_9 = 9'h9 == index ? 64'h301022f330551073 : _GEN_8; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_10 = 9'ha == index ? 64'h12f2934122d293 : _GEN_9; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_11 = 9'hb == index ? 64'h3030107300028463 : _GEN_10; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_12 = 9'hc == index ? 64'h3045107300800513 : _GEN_11; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_13 = 9'hd == index ? 64'h1050007330052073 : _GEN_12; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_14 = 9'he == index ? 64'hffdff06f : _GEN_13; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_15 = 9'hf == index ? 64'h0 : _GEN_14; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_16 = 9'h10 == index ? 64'h5a283fc1ff06f : _GEN_15; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_17 = 9'h11 == index ? 64'h251513fe029ee3 : _GEN_16; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_18 = 9'h12 == index ? 64'h5a02300b505b3 : _GEN_17; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_19 = 9'h13 == index ? 64'h5350300004537 : _GEN_18; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_20 = 9'h14 == index ? 64'hf140257334151073 : _GEN_19; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_21 = 9'h15 == index ? 64'h185859300000597 : _GEN_20; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_22 = 9'h16 == index ? 64'h3006307308000613 : _GEN_21; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_23 = 9'h17 == index ? 64'h1330200073 : _GEN_22; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_24 = 9'h18 == index ? 64'h430d0000edfe0dd0 : _GEN_23; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_25 = 9'h19 == index ? 64'h680b000038000000 : _GEN_24; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_26 = 9'h1a == index ? 64'h1100000028000000 : _GEN_25; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_27 = 9'h1b == index ? 64'h10000000 : _GEN_26; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_28 = 9'h1c == index ? 64'h300b0000db010000 : _GEN_27; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_29 = 9'h1d == index ? 64'h0 : _GEN_28; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_30 = 9'h1e == index ? 64'h0 : _GEN_29; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_31 = 9'h1f == index ? 64'h1000000 : _GEN_30; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_32 = 9'h20 == index ? 64'h400000003000000 : _GEN_31; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_33 = 9'h21 == index ? 64'h100000000000000 : _GEN_32; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_34 = 9'h22 == index ? 64'h400000003000000 : _GEN_33; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_35 = 9'h23 == index ? 64'h10000000f000000 : _GEN_34; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_36 = 9'h24 == index ? 64'h2100000003000000 : _GEN_35; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_37 = 9'h25 == index ? 64'h656572661b000000 : _GEN_36; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_38 = 9'h26 == index ? 64'h6f722c7370696863 : _GEN_37; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_39 = 9'h27 == index ? 64'h7069686374656b63 : _GEN_38; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_40 = 9'h28 == index ? 64'h6e776f6e6b6e752d : _GEN_39; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_41 = 9'h29 == index ? 64'h7665642d : _GEN_40; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_42 = 9'h2a == index ? 64'h1d00000003000000 : _GEN_41; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_43 = 9'h2b == index ? 64'h6565726626000000 : _GEN_42; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_44 = 9'h2c == index ? 64'h6f722c7370696863 : _GEN_43; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_45 = 9'h2d == index ? 64'h7069686374656b63 : _GEN_44; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_46 = 9'h2e == index ? 64'h6e776f6e6b6e752d : _GEN_45; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_47 = 9'h2f == index ? 64'h100000000000000 : _GEN_46; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_48 = 9'h30 == index ? 64'h73657361696c61 : _GEN_47; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_49 = 9'h31 == index ? 64'h1500000003000000 : _GEN_48; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_50 = 9'h32 == index ? 64'h636f732f2c000000 : _GEN_49; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_51 = 9'h33 == index ? 64'h406c61697265732f : _GEN_50; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_52 = 9'h34 == index ? 64'h3030303031303031 : _GEN_51; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_53 = 9'h35 == index ? 64'h300000000000000 : _GEN_52; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_54 = 9'h36 == index ? 64'h3400000015000000 : _GEN_53; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_55 = 9'h37 == index ? 64'h7265732f636f732f : _GEN_54; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_56 = 9'h38 == index ? 64'h31303031406c6169 : _GEN_55; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_57 = 9'h39 == index ? 64'h30303031 : _GEN_56; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_58 = 9'h3a == index ? 64'h100000002000000 : _GEN_57; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_59 = 9'h3b == index ? 64'h73757063 : _GEN_58; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_60 = 9'h3c == index ? 64'h400000003000000 : _GEN_59; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_61 = 9'h3d == index ? 64'h100000000000000 : _GEN_60; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_62 = 9'h3e == index ? 64'h400000003000000 : _GEN_61; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_63 = 9'h3f == index ? 64'hf000000 : _GEN_62; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_64 = 9'h40 == index ? 64'h400000003000000 : _GEN_63; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_65 = 9'h41 == index ? 64'h40420f003c000000 : _GEN_64; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_66 = 9'h42 == index ? 64'h4075706301000000 : _GEN_65; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_67 = 9'h43 == index ? 64'h300000000000030 : _GEN_66; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_68 = 9'h44 == index ? 64'h4f00000004000000 : _GEN_67; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_69 = 9'h45 == index ? 64'h300000000000000 : _GEN_68; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_70 = 9'h46 == index ? 64'h1b00000015000000 : _GEN_69; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_71 = 9'h47 == index ? 64'h722c657669666973 : _GEN_70; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_72 = 9'h48 == index ? 64'h72003074656b636f : _GEN_71; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_73 = 9'h49 == index ? 64'h76637369 : _GEN_72; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_74 = 9'h4a == index ? 64'h400000003000000 : _GEN_73; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_75 = 9'h4b == index ? 64'h7570635f000000 : _GEN_74; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_76 = 9'h4c == index ? 64'h400000003000000 : _GEN_75; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_77 = 9'h4d == index ? 64'h10000006b000000 : _GEN_76; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_78 = 9'h4e == index ? 64'h400000003000000 : _GEN_77; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_79 = 9'h4f == index ? 64'h400000008a000000 : _GEN_78; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_80 = 9'h50 == index ? 64'h400000003000000 : _GEN_79; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_81 = 9'h51 == index ? 64'h400000009d000000 : _GEN_80; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_82 = 9'h52 == index ? 64'h400000003000000 : _GEN_81; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_83 = 9'h53 == index ? 64'h100000aa000000 : _GEN_82; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_84 = 9'h54 == index ? 64'h400000003000000 : _GEN_83; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_85 = 9'h55 == index ? 64'hb7000000 : _GEN_84; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_86 = 9'h56 == index ? 64'h900000003000000 : _GEN_85; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_87 = 9'h57 == index ? 64'h34367672bb000000 : _GEN_86; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_88 = 9'h58 == index ? 64'h63616d69 : _GEN_87; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_89 = 9'h59 == index ? 64'h400000003000000 : _GEN_88; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_90 = 9'h5a == index ? 64'h4000000c5000000 : _GEN_89; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_91 = 9'h5b == index ? 64'h400000003000000 : _GEN_90; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_92 = 9'h5c == index ? 64'h8000000da000000 : _GEN_91; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_93 = 9'h5d == index ? 64'h400000003000000 : _GEN_92; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_94 = 9'h5e == index ? 64'h1000000eb000000 : _GEN_93; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_95 = 9'h5f == index ? 64'h500000003000000 : _GEN_94; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_96 = 9'h60 == index ? 64'h79616b6ff7000000 : _GEN_95; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_97 = 9'h61 == index ? 64'h300000000000000 : _GEN_96; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_98 = 9'h62 == index ? 64'h3c00000004000000 : _GEN_97; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_99 = 9'h63 == index ? 64'h100000040420f00 : _GEN_98; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_100 = 9'h64 == index ? 64'h7075727265746e69 : _GEN_99; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_101 = 9'h65 == index ? 64'h6f72746e6f632d74 : _GEN_100; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_102 = 9'h66 == index ? 64'h72656c6c : _GEN_101; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_103 = 9'h67 == index ? 64'h400000003000000 : _GEN_102; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_104 = 9'h68 == index ? 64'h1000000fe000000 : _GEN_103; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_105 = 9'h69 == index ? 64'hf00000003000000 : _GEN_104; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_106 = 9'h6a == index ? 64'h637369721b000000 : _GEN_105; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_107 = 9'h6b == index ? 64'h6e692d7570632c76 : _GEN_106; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_108 = 9'h6c == index ? 64'h300000000006374 : _GEN_107; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_109 = 9'h6d == index ? 64'hf01000000000000 : _GEN_108; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_110 = 9'h6e == index ? 64'h400000003000000 : _GEN_109; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_111 = 9'h6f == index ? 64'h200000024010000 : _GEN_110; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_112 = 9'h70 == index ? 64'h200000002000000 : _GEN_111; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_113 = 9'h71 == index ? 64'h100000002000000 : _GEN_112; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_114 = 9'h72 == index ? 64'h66697468 : _GEN_113; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_115 = 9'h73 == index ? 64'ha00000003000000 : _GEN_114; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_116 = 9'h74 == index ? 64'h2c6263751b000000 : _GEN_115; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_117 = 9'h75 == index ? 64'h3066697468 : _GEN_116; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_118 = 9'h76 == index ? 64'h100000002000000 : _GEN_117; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_119 = 9'h77 == index ? 64'h300000000636f73 : _GEN_118; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_120 = 9'h78 == index ? 64'h4000000 : _GEN_119; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_121 = 9'h79 == index ? 64'h300000001000000 : _GEN_120; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_122 = 9'h7a == index ? 64'hf00000004000000 : _GEN_121; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_123 = 9'h7b == index ? 64'h300000001000000 : _GEN_122; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_124 = 9'h7c == index ? 64'h1b0000002c000000 : _GEN_123; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_125 = 9'h7d == index ? 64'h7069686365657266 : _GEN_124; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_126 = 9'h7e == index ? 64'h74656b636f722c73 : _GEN_125; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_127 = 9'h7f == index ? 64'h6b6e752d70696863 : _GEN_126; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_128 = 9'h80 == index ? 64'h636f732d6e776f6e : _GEN_127; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_129 = 9'h81 == index ? 64'h2d656c706d697300 : _GEN_128; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_130 = 9'h82 == index ? 64'h300000000737562 : _GEN_129; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_131 = 9'h83 == index ? 64'h2c01000000000000 : _GEN_130; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_132 = 9'h84 == index ? 64'h746f6f6201000000 : _GEN_131; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_133 = 9'h85 == index ? 64'h737365726464612d : _GEN_132; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_134 = 9'h86 == index ? 64'h303034406765722d : _GEN_133; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_135 = 9'h87 == index ? 64'h300000000000030 : _GEN_134; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_136 = 9'h88 == index ? 64'hb700000008000000 : _GEN_135; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_137 = 9'h89 == index ? 64'h10000000400000 : _GEN_136; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_138 = 9'h8a == index ? 64'h800000003000000 : _GEN_137; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_139 = 9'h8b == index ? 64'h746e6f6333010000 : _GEN_138; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_140 = 9'h8c == index ? 64'h2000000006c6f72 : _GEN_139; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_141 = 9'h8d == index ? 64'h6e696c6301000000 : _GEN_140; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_142 = 9'h8e == index ? 64'h3030303030324074 : _GEN_141; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_143 = 9'h8f == index ? 64'h300000000000030 : _GEN_142; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_144 = 9'h90 == index ? 64'h1b0000000d000000 : _GEN_143; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_145 = 9'h91 == index ? 64'h6c632c7663736972 : _GEN_144; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_146 = 9'h92 == index ? 64'h30746e69 : _GEN_145; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_147 = 9'h93 == index ? 64'h1000000003000000 : _GEN_146; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_148 = 9'h94 == index ? 64'h20000003d010000 : _GEN_147; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_149 = 9'h95 == index ? 64'h200000003000000 : _GEN_148; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_150 = 9'h96 == index ? 64'h300000007000000 : _GEN_149; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_151 = 9'h97 == index ? 64'hb700000008000000 : _GEN_150; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_152 = 9'h98 == index ? 64'h10000000002 : _GEN_151; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_153 = 9'h99 == index ? 64'h800000003000000 : _GEN_152; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_154 = 9'h9a == index ? 64'h746e6f6333010000 : _GEN_153; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_155 = 9'h9b == index ? 64'h2000000006c6f72 : _GEN_154; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_156 = 9'h9c == index ? 64'h636f6c6301000000 : _GEN_155; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_157 = 9'h9d == index ? 64'h4072657461672d6b : _GEN_156; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_158 = 9'h9e == index ? 64'h303030303031 : _GEN_157; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_159 = 9'h9f == index ? 64'h800000003000000 : _GEN_158; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_160 = 9'ha0 == index ? 64'h1000b7000000 : _GEN_159; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_161 = 9'ha1 == index ? 64'h300000000100000 : _GEN_160; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_162 = 9'ha2 == index ? 64'h3301000008000000 : _GEN_161; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_163 = 9'ha3 == index ? 64'h6c6f72746e6f63 : _GEN_162; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_164 = 9'ha4 == index ? 64'h100000002000000 : _GEN_163; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_165 = 9'ha5 == index ? 64'h6f632d6775626564 : _GEN_164; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_166 = 9'ha6 == index ? 64'h72656c6c6f72746e : _GEN_165; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_167 = 9'ha7 == index ? 64'h300000000003040 : _GEN_166; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_168 = 9'ha8 == index ? 64'h1b00000021000000 : _GEN_167; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_169 = 9'ha9 == index ? 64'h642c657669666973 : _GEN_168; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_170 = 9'haa == index ? 64'h3331302d67756265 : _GEN_169; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_171 = 9'hab == index ? 64'h642c766373697200 : _GEN_170; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_172 = 9'hac == index ? 64'h3331302d67756265 : _GEN_171; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_173 = 9'had == index ? 64'h300000000000000 : _GEN_172; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_174 = 9'hae == index ? 64'h5101000005000000 : _GEN_173; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_175 = 9'haf == index ? 64'h6761746a : _GEN_174; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_176 = 9'hb0 == index ? 64'h800000003000000 : _GEN_175; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_177 = 9'hb1 == index ? 64'h20000003d010000 : _GEN_176; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_178 = 9'hb2 == index ? 64'h3000000ffff0000 : _GEN_177; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_179 = 9'hb3 == index ? 64'hb700000008000000 : _GEN_178; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_180 = 9'hb4 == index ? 64'h10000000000000 : _GEN_179; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_181 = 9'hb5 == index ? 64'h800000003000000 : _GEN_180; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_182 = 9'hb6 == index ? 64'h746e6f6333010000 : _GEN_181; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_183 = 9'hb7 == index ? 64'h2000000006c6f72 : _GEN_182; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_184 = 9'hb8 == index ? 64'h6d69746401000000 : _GEN_183; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_185 = 9'hb9 == index ? 64'h3030303030303840 : _GEN_184; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_186 = 9'hba == index ? 64'h300000000000030 : _GEN_185; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_187 = 9'hbb == index ? 64'h1b0000000d000000 : _GEN_186; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_188 = 9'hbc == index ? 64'h642c657669666973 : _GEN_187; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_189 = 9'hbd == index ? 64'h306d6974 : _GEN_188; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_190 = 9'hbe == index ? 64'h800000003000000 : _GEN_189; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_191 = 9'hbf == index ? 64'h80b7000000 : _GEN_190; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_192 = 9'hc0 == index ? 64'h300000000400000 : _GEN_191; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_193 = 9'hc1 == index ? 64'h3301000004000000 : _GEN_192; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_194 = 9'hc2 == index ? 64'h3000000006d656d : _GEN_193; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_195 = 9'hc3 == index ? 64'h2401000004000000 : _GEN_194; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_196 = 9'hc4 == index ? 64'h200000001000000 : _GEN_195; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_197 = 9'hc5 == index ? 64'h6f72726501000000 : _GEN_196; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_198 = 9'hc6 == index ? 64'h6563697665642d72 : _GEN_197; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_199 = 9'hc7 == index ? 64'h3030303340 : _GEN_198; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_200 = 9'hc8 == index ? 64'he00000003000000 : _GEN_199; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_201 = 9'hc9 == index ? 64'h696669731b000000 : _GEN_200; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_202 = 9'hca == index ? 64'h726f7272652c6576 : _GEN_201; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_203 = 9'hcb == index ? 64'h300000000000030 : _GEN_202; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_204 = 9'hcc == index ? 64'hb700000008000000 : _GEN_203; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_205 = 9'hcd == index ? 64'h10000000300000 : _GEN_204; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_206 = 9'hce == index ? 64'h100000002000000 : _GEN_205; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_207 = 9'hcf == index ? 64'h303031406f697067 : _GEN_206; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_208 = 9'hd0 == index ? 64'h3030303231 : _GEN_207; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_209 = 9'hd1 == index ? 64'h400000003000000 : _GEN_208; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_210 = 9'hd2 == index ? 64'h20000005e010000 : _GEN_209; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_211 = 9'hd3 == index ? 64'h400000003000000 : _GEN_210; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_212 = 9'hd4 == index ? 64'h2000000fe000000 : _GEN_211; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_213 = 9'hd5 == index ? 64'h400000003000000 : _GEN_212; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_214 = 9'hd6 == index ? 64'h30000006a010000 : _GEN_213; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_215 = 9'hd7 == index ? 64'h1a00000003000000 : _GEN_214; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_216 = 9'hd8 == index ? 64'h696669731b000000 : _GEN_215; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_217 = 9'hd9 == index ? 64'h306f6970672c6576 : _GEN_216; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_218 = 9'hda == index ? 64'h2c65766966697300 : _GEN_217; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_219 = 9'hdb == index ? 64'h316f697067 : _GEN_218; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_220 = 9'hdc == index ? 64'h3000000 : _GEN_219; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_221 = 9'hdd == index ? 64'h300000071010000 : _GEN_220; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_222 = 9'hde == index ? 64'hf01000000000000 : _GEN_221; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_223 = 9'hdf == index ? 64'h400000003000000 : _GEN_222; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_224 = 9'he0 == index ? 64'h400000081010000 : _GEN_223; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_225 = 9'he1 == index ? 64'h1000000003000000 : _GEN_224; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_226 = 9'he2 == index ? 64'h300000092010000 : _GEN_225; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_227 = 9'he3 == index ? 64'h500000004000000 : _GEN_226; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_228 = 9'he4 == index ? 64'h300000006000000 : _GEN_227; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_229 = 9'he5 == index ? 64'hb700000008000000 : _GEN_228; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_230 = 9'he6 == index ? 64'h10000000200110 : _GEN_229; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_231 = 9'he7 == index ? 64'h800000003000000 : _GEN_230; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_232 = 9'he8 == index ? 64'h746e6f6333010000 : _GEN_231; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_233 = 9'he9 == index ? 64'h2000000006c6f72 : _GEN_232; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_234 = 9'hea == index ? 64'h65746e6901000000 : _GEN_233; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_235 = 9'heb == index ? 64'h6f632d7470757272 : _GEN_234; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_236 = 9'hec == index ? 64'h72656c6c6f72746e : _GEN_235; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_237 = 9'hed == index ? 64'h3030303030306340 : _GEN_236; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_238 = 9'hee == index ? 64'h300000000000000 : _GEN_237; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_239 = 9'hef == index ? 64'hfe00000004000000 : _GEN_238; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_240 = 9'hf0 == index ? 64'h300000001000000 : _GEN_239; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_241 = 9'hf1 == index ? 64'h1b0000000c000000 : _GEN_240; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_242 = 9'hf2 == index ? 64'h6c702c7663736972 : _GEN_241; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_243 = 9'hf3 == index ? 64'h300000000306369 : _GEN_242; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_244 = 9'hf4 == index ? 64'hf01000000000000 : _GEN_243; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_245 = 9'hf5 == index ? 64'h800000003000000 : _GEN_244; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_246 = 9'hf6 == index ? 64'h20000003d010000 : _GEN_245; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_247 = 9'hf7 == index ? 64'h30000000b000000 : _GEN_246; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_248 = 9'hf8 == index ? 64'hb700000008000000 : _GEN_247; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_249 = 9'hf9 == index ? 64'h40000000c : _GEN_248; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_250 = 9'hfa == index ? 64'h800000003000000 : _GEN_249; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_251 = 9'hfb == index ? 64'h746e6f6333010000 : _GEN_250; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_252 = 9'hfc == index ? 64'h3000000006c6f72 : _GEN_251; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_253 = 9'hfd == index ? 64'h9d01000004000000 : _GEN_252; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_254 = 9'hfe == index ? 64'h300000007000000 : _GEN_253; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_255 = 9'hff == index ? 64'hb001000004000000 : _GEN_254; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_256 = 9'h100 == index ? 64'h300000008000000 : _GEN_255; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_257 = 9'h101 == index ? 64'h2401000004000000 : _GEN_256; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_258 = 9'h102 == index ? 64'h200000004000000 : _GEN_257; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_259 = 9'h103 == index ? 64'h6977626c01000000 : _GEN_258; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_260 = 9'h104 == index ? 64'h3031406d61722d66 : _GEN_259; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_261 = 9'h105 == index ? 64'h303030303030 : _GEN_260; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_262 = 9'h106 == index ? 64'h800000003000000 : _GEN_261; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_263 = 9'h107 == index ? 64'h10b7000000 : _GEN_262; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_264 = 9'h108 == index ? 64'h200000000100000 : _GEN_263; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_265 = 9'h109 == index ? 64'h6977626c01000000 : _GEN_264; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_266 = 9'h10a == index ? 64'h3032406d6f722d66 : _GEN_265; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_267 = 9'h10b == index ? 64'h300000000303030 : _GEN_266; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_268 = 9'h10c == index ? 64'hb700000008000000 : _GEN_267; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_269 = 9'h10d == index ? 64'h10000000200 : _GEN_268; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_270 = 9'h10e == index ? 64'h100000002000000 : _GEN_269; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_271 = 9'h10f == index ? 64'h30303031406d6f72 : _GEN_270; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_272 = 9'h110 == index ? 64'h300000000000030 : _GEN_271; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_273 = 9'h111 == index ? 64'h1b0000000c000000 : _GEN_272; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_274 = 9'h112 == index ? 64'h722c657669666973 : _GEN_273; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_275 = 9'h113 == index ? 64'h300000000306d6f : _GEN_274; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_276 = 9'h114 == index ? 64'hb700000008000000 : _GEN_275; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_277 = 9'h115 == index ? 64'h10000000100 : _GEN_276; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_278 = 9'h116 == index ? 64'h400000003000000 : _GEN_277; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_279 = 9'h117 == index ? 64'h6d656d33010000 : _GEN_278; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_280 = 9'h118 == index ? 64'h100000002000000 : _GEN_279; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_281 = 9'h119 == index ? 64'h31406c6169726573 : _GEN_280; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_282 = 9'h11a == index ? 64'h30303030313030 : _GEN_281; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_283 = 9'h11b == index ? 64'h400000003000000 : _GEN_282; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_284 = 9'h11c == index ? 64'h30000006a010000 : _GEN_283; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_285 = 9'h11d == index ? 64'hd00000003000000 : _GEN_284; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_286 = 9'h11e == index ? 64'h696669731b000000 : _GEN_285; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_287 = 9'h11f == index ? 64'h30747261752c6576 : _GEN_286; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_288 = 9'h120 == index ? 64'h300000000000000 : _GEN_287; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_289 = 9'h121 == index ? 64'h8101000004000000 : _GEN_288; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_290 = 9'h122 == index ? 64'h300000004000000 : _GEN_289; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_291 = 9'h123 == index ? 64'h9201000004000000 : _GEN_290; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_292 = 9'h124 == index ? 64'h300000001000000 : _GEN_291; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_293 = 9'h125 == index ? 64'hb700000008000000 : _GEN_292; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_294 = 9'h126 == index ? 64'h10000000000110 : _GEN_293; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_295 = 9'h127 == index ? 64'h800000003000000 : _GEN_294; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_296 = 9'h128 == index ? 64'h746e6f6333010000 : _GEN_295; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_297 = 9'h129 == index ? 64'h2000000006c6f72 : _GEN_296; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_298 = 9'h12a == index ? 64'h6972657301000000 : _GEN_297; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_299 = 9'h12b == index ? 64'h3131303031406c61 : _GEN_298; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_300 = 9'h12c == index ? 64'h300000000303030 : _GEN_299; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_301 = 9'h12d == index ? 64'h6a01000004000000 : _GEN_300; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_302 = 9'h12e == index ? 64'h300000003000000 : _GEN_301; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_303 = 9'h12f == index ? 64'h1b0000000d000000 : _GEN_302; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_304 = 9'h130 == index ? 64'h752c657669666973 : _GEN_303; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_305 = 9'h131 == index ? 64'h30747261 : _GEN_304; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_306 = 9'h132 == index ? 64'h400000003000000 : _GEN_305; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_307 = 9'h133 == index ? 64'h400000081010000 : _GEN_306; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_308 = 9'h134 == index ? 64'h400000003000000 : _GEN_307; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_309 = 9'h135 == index ? 64'h200000092010000 : _GEN_308; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_310 = 9'h136 == index ? 64'h800000003000000 : _GEN_309; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_311 = 9'h137 == index ? 64'h100110b7000000 : _GEN_310; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_312 = 9'h138 == index ? 64'h300000000100000 : _GEN_311; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_313 = 9'h139 == index ? 64'h3301000008000000 : _GEN_312; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_314 = 9'h13a == index ? 64'h6c6f72746e6f63 : _GEN_313; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_315 = 9'h13b == index ? 64'h100000002000000 : _GEN_314; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_316 = 9'h13c == index ? 64'h3130303140697073 : _GEN_315; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_317 = 9'h13d == index ? 64'h30303033 : _GEN_316; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_318 = 9'h13e == index ? 64'h400000003000000 : _GEN_317; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_319 = 9'h13f == index ? 64'h100000000000000 : _GEN_318; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_320 = 9'h140 == index ? 64'h400000003000000 : _GEN_319; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_321 = 9'h141 == index ? 64'hf000000 : _GEN_320; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_322 = 9'h142 == index ? 64'h400000003000000 : _GEN_321; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_323 = 9'h143 == index ? 64'h30000006a010000 : _GEN_322; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_324 = 9'h144 == index ? 64'hc00000003000000 : _GEN_323; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_325 = 9'h145 == index ? 64'h696669731b000000 : _GEN_324; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_326 = 9'h146 == index ? 64'h306970732c6576 : _GEN_325; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_327 = 9'h147 == index ? 64'h400000003000000 : _GEN_326; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_328 = 9'h148 == index ? 64'h400000081010000 : _GEN_327; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_329 = 9'h149 == index ? 64'h400000003000000 : _GEN_328; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_330 = 9'h14a == index ? 64'h700000092010000 : _GEN_329; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_331 = 9'h14b == index ? 64'h1000000003000000 : _GEN_330; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_332 = 9'h14c == index ? 64'h300110b7000000 : _GEN_331; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_333 = 9'h14d == index ? 64'h2000100000 : _GEN_332; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_334 = 9'h14e == index ? 64'h300000000000010 : _GEN_333; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_335 = 9'h14f == index ? 64'h330100000c000000 : _GEN_334; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_336 = 9'h150 == index ? 64'h6c6f72746e6f63 : _GEN_335; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_337 = 9'h151 == index ? 64'h2000000006d656d : _GEN_336; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_338 = 9'h152 == index ? 64'h4069707301000000 : _GEN_337; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_339 = 9'h153 == index ? 64'h3030303431303031 : _GEN_338; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_340 = 9'h154 == index ? 64'h300000000000000 : _GEN_339; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_341 = 9'h155 == index ? 64'h4000000 : _GEN_340; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_342 = 9'h156 == index ? 64'h300000001000000 : _GEN_341; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_343 = 9'h157 == index ? 64'hf00000004000000 : _GEN_342; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_344 = 9'h158 == index ? 64'h300000000000000 : _GEN_343; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_345 = 9'h159 == index ? 64'h6a01000004000000 : _GEN_344; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_346 = 9'h15a == index ? 64'h300000003000000 : _GEN_345; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_347 = 9'h15b == index ? 64'h1b0000000c000000 : _GEN_346; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_348 = 9'h15c == index ? 64'h732c657669666973 : _GEN_347; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_349 = 9'h15d == index ? 64'h300000000306970 : _GEN_348; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_350 = 9'h15e == index ? 64'h8101000004000000 : _GEN_349; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_351 = 9'h15f == index ? 64'h300000004000000 : _GEN_350; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_352 = 9'h160 == index ? 64'h9201000004000000 : _GEN_351; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_353 = 9'h161 == index ? 64'h300000008000000 : _GEN_352; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_354 = 9'h162 == index ? 64'hb700000010000000 : _GEN_353; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_355 = 9'h163 == index ? 64'h10000000400110 : _GEN_354; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_356 = 9'h164 == index ? 64'h1000000030 : _GEN_355; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_357 = 9'h165 == index ? 64'hc00000003000000 : _GEN_356; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_358 = 9'h166 == index ? 64'h746e6f6333010000 : _GEN_357; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_359 = 9'h167 == index ? 64'h6d656d006c6f72 : _GEN_358; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_360 = 9'h168 == index ? 64'h100000002000000 : _GEN_359; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_361 = 9'h169 == index ? 64'h6574737973627573 : _GEN_360; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_362 = 9'h16a == index ? 64'h635f737562705f6d : _GEN_361; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_363 = 9'h16b == index ? 64'h6b636f6c : _GEN_362; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_364 = 9'h16c == index ? 64'h400000003000000 : _GEN_363; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_365 = 9'h16d == index ? 64'hbb010000 : _GEN_364; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_366 = 9'h16e == index ? 64'h400000003000000 : _GEN_365; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_367 = 9'h16f == index ? 64'he1f5054f000000 : _GEN_366; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_368 = 9'h170 == index ? 64'h1500000003000000 : _GEN_367; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_369 = 9'h171 == index ? 64'h73627573c8010000 : _GEN_368; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_370 = 9'h172 == index ? 64'h62705f6d65747379 : _GEN_369; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_371 = 9'h173 == index ? 64'h6b636f6c635f7375 : _GEN_370; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_372 = 9'h174 == index ? 64'h300000000000000 : _GEN_371; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_373 = 9'h175 == index ? 64'h1b0000000c000000 : _GEN_372; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_374 = 9'h176 == index ? 64'h6c632d6465786966 : _GEN_373; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_375 = 9'h177 == index ? 64'h3000000006b636f : _GEN_374; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_376 = 9'h178 == index ? 64'h2401000004000000 : _GEN_375; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_377 = 9'h179 == index ? 64'h200000003000000 : _GEN_376; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_378 = 9'h17a == index ? 64'h656c697401000000 : _GEN_377; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_379 = 9'h17b == index ? 64'h732d74657365722d : _GEN_378; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_380 = 9'h17c == index ? 64'h3131407265747465 : _GEN_379; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_381 = 9'h17d == index ? 64'h30303030 : _GEN_380; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_382 = 9'h17e == index ? 64'h800000003000000 : _GEN_381; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_383 = 9'h17f == index ? 64'h1100b7000000 : _GEN_382; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_384 = 9'h180 == index ? 64'h300000000100000 : _GEN_383; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_385 = 9'h181 == index ? 64'h3301000008000000 : _GEN_384; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_386 = 9'h182 == index ? 64'h6c6f72746e6f63 : _GEN_385; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_387 = 9'h183 == index ? 64'h200000002000000 : _GEN_386; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_388 = 9'h184 == index ? 64'h900000002000000 : _GEN_387; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_389 = 9'h185 == index ? 64'h7373657264646123 : _GEN_388; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_390 = 9'h186 == index ? 64'h2300736c6c65632d : _GEN_389; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_391 = 9'h187 == index ? 64'h6c65632d657a6973 : _GEN_390; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_392 = 9'h188 == index ? 64'h61706d6f6300736c : _GEN_391; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_393 = 9'h189 == index ? 64'h6f6d00656c626974 : _GEN_392; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_394 = 9'h18a == index ? 64'h69726573006c6564 : _GEN_393; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_395 = 9'h18b == index ? 64'h6972657300306c61 : _GEN_394; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_396 = 9'h18c == index ? 64'h656d697400316c61 : _GEN_395; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_397 = 9'h18d == index ? 64'h6572662d65736162 : _GEN_396; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_398 = 9'h18e == index ? 64'h630079636e657571 : _GEN_397; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_399 = 9'h18f == index ? 64'h6572662d6b636f6c : _GEN_398; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_400 = 9'h190 == index ? 64'h640079636e657571 : _GEN_399; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_401 = 9'h191 == index ? 64'h79745f6563697665 : _GEN_400; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_402 = 9'h192 == index ? 64'h7764726168006570 : _GEN_401; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_403 = 9'h193 == index ? 64'h636578652d657261 : _GEN_402; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_404 = 9'h194 == index ? 64'h6f706b616572622d : _GEN_403; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_405 = 9'h195 == index ? 64'h6e756f632d746e69 : _GEN_404; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_406 = 9'h196 == index ? 64'h686361632d690074 : _GEN_405; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_407 = 9'h197 == index ? 64'h2d6b636f6c622d65 : _GEN_406; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_408 = 9'h198 == index ? 64'h632d6900657a6973 : _GEN_407; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_409 = 9'h199 == index ? 64'h7465732d65686361 : _GEN_408; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_410 = 9'h19a == index ? 64'h686361632d690073 : _GEN_409; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_411 = 9'h19b == index ? 64'h7200657a69732d65 : _GEN_410; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_412 = 9'h19c == index ? 64'h7663736972006765 : _GEN_411; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_413 = 9'h19d == index ? 64'h736972006173692c : _GEN_412; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_414 = 9'h19e == index ? 64'h7267706d702c7663 : _GEN_413; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_415 = 9'h19f == index ? 64'h746972616c756e61 : _GEN_414; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_416 = 9'h1a0 == index ? 64'h2c76637369720079 : _GEN_415; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_417 = 9'h1a1 == index ? 64'h6f69676572706d70 : _GEN_416; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_418 = 9'h1a2 == index ? 64'h766966697300736e : _GEN_417; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_419 = 9'h1a3 == index ? 64'h73006d6974642c65 : _GEN_418; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_420 = 9'h1a4 == index ? 64'h6923007375746174 : _GEN_419; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_421 = 9'h1a5 == index ? 64'h747075727265746e : _GEN_420; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_422 = 9'h1a6 == index ? 64'h6900736c6c65632d : _GEN_421; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_423 = 9'h1a7 == index ? 64'h747075727265746e : _GEN_422; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_424 = 9'h1a8 == index ? 64'h6c6f72746e6f632d : _GEN_423; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_425 = 9'h1a9 == index ? 64'h6e6168700072656c : _GEN_424; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_426 = 9'h1aa == index ? 64'h676e617200656c64 : _GEN_425; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_427 = 9'h1ab == index ? 64'h6e2d676572007365 : _GEN_426; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_428 = 9'h1ac == index ? 64'h746e690073656d61 : _GEN_427; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_429 = 9'h1ad == index ? 64'h2d73747075727265 : _GEN_428; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_430 = 9'h1ae == index ? 64'h6465646e65747865 : _GEN_429; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_431 = 9'h1af == index ? 64'h612d677562656400 : _GEN_430; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_432 = 9'h1b0 == index ? 64'h6723006863617474 : _GEN_431; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_433 = 9'h1b1 == index ? 64'h6c6c65632d6f6970 : _GEN_432; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_434 = 9'h1b2 == index ? 64'h736b636f6c630073 : _GEN_433; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_435 = 9'h1b3 == index ? 64'h6f632d6f69706700 : _GEN_434; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_436 = 9'h1b4 == index ? 64'h72656c6c6f72746e : _GEN_435; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_437 = 9'h1b5 == index ? 64'h75727265746e6900 : _GEN_436; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_438 = 9'h1b6 == index ? 64'h6e657261702d7470 : _GEN_437; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_439 = 9'h1b7 == index ? 64'h727265746e690074 : _GEN_438; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_440 = 9'h1b8 == index ? 64'h7369720073747075 : _GEN_439; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_441 = 9'h1b9 == index ? 64'h702d78616d2c7663 : _GEN_440; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_442 = 9'h1ba == index ? 64'h797469726f6972 : _GEN_441; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_443 = 9'h1bb == index ? 64'h646e2c7663736972 : _GEN_442; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_444 = 9'h1bc == index ? 64'h636f6c6323007665 : _GEN_443; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_445 = 9'h1bd == index ? 64'h736c6c65632d6b : _GEN_444; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_446 = 9'h1be == index ? 64'h756f2d6b636f6c63 : _GEN_445; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_447 = 9'h1bf == index ? 64'h6d616e2d74757074 : _GEN_446; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_448 = 9'h1c0 == index ? 64'h7365 : _GEN_447; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_449 = 9'h1c1 == index ? 64'h0 : _GEN_448; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_450 = 9'h1c2 == index ? 64'h0 : _GEN_449; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_451 = 9'h1c3 == index ? 64'h0 : _GEN_450; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_452 = 9'h1c4 == index ? 64'h0 : _GEN_451; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_453 = 9'h1c5 == index ? 64'h0 : _GEN_452; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_454 = 9'h1c6 == index ? 64'h0 : _GEN_453; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_455 = 9'h1c7 == index ? 64'h0 : _GEN_454; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_456 = 9'h1c8 == index ? 64'h0 : _GEN_455; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_457 = 9'h1c9 == index ? 64'h0 : _GEN_456; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_458 = 9'h1ca == index ? 64'h0 : _GEN_457; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_459 = 9'h1cb == index ? 64'h0 : _GEN_458; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_460 = 9'h1cc == index ? 64'h0 : _GEN_459; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_461 = 9'h1cd == index ? 64'h0 : _GEN_460; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_462 = 9'h1ce == index ? 64'h0 : _GEN_461; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_463 = 9'h1cf == index ? 64'h0 : _GEN_462; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_464 = 9'h1d0 == index ? 64'h0 : _GEN_463; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_465 = 9'h1d1 == index ? 64'h0 : _GEN_464; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_466 = 9'h1d2 == index ? 64'h0 : _GEN_465; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_467 = 9'h1d3 == index ? 64'h0 : _GEN_466; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_468 = 9'h1d4 == index ? 64'h0 : _GEN_467; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_469 = 9'h1d5 == index ? 64'h0 : _GEN_468; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_470 = 9'h1d6 == index ? 64'h0 : _GEN_469; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_471 = 9'h1d7 == index ? 64'h0 : _GEN_470; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_472 = 9'h1d8 == index ? 64'h0 : _GEN_471; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_473 = 9'h1d9 == index ? 64'h0 : _GEN_472; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_474 = 9'h1da == index ? 64'h0 : _GEN_473; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_475 = 9'h1db == index ? 64'h0 : _GEN_474; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_476 = 9'h1dc == index ? 64'h0 : _GEN_475; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_477 = 9'h1dd == index ? 64'h0 : _GEN_476; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_478 = 9'h1de == index ? 64'h0 : _GEN_477; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_479 = 9'h1df == index ? 64'h0 : _GEN_478; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_480 = 9'h1e0 == index ? 64'h0 : _GEN_479; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_481 = 9'h1e1 == index ? 64'h0 : _GEN_480; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_482 = 9'h1e2 == index ? 64'h0 : _GEN_481; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_483 = 9'h1e3 == index ? 64'h0 : _GEN_482; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_484 = 9'h1e4 == index ? 64'h0 : _GEN_483; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_485 = 9'h1e5 == index ? 64'h0 : _GEN_484; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_486 = 9'h1e6 == index ? 64'h0 : _GEN_485; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_487 = 9'h1e7 == index ? 64'h0 : _GEN_486; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_488 = 9'h1e8 == index ? 64'h0 : _GEN_487; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_489 = 9'h1e9 == index ? 64'h0 : _GEN_488; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_490 = 9'h1ea == index ? 64'h0 : _GEN_489; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_491 = 9'h1eb == index ? 64'h0 : _GEN_490; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_492 = 9'h1ec == index ? 64'h0 : _GEN_491; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_493 = 9'h1ed == index ? 64'h0 : _GEN_492; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_494 = 9'h1ee == index ? 64'h0 : _GEN_493; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_495 = 9'h1ef == index ? 64'h0 : _GEN_494; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_496 = 9'h1f0 == index ? 64'h0 : _GEN_495; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_497 = 9'h1f1 == index ? 64'h0 : _GEN_496; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_498 = 9'h1f2 == index ? 64'h0 : _GEN_497; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_499 = 9'h1f3 == index ? 64'h0 : _GEN_498; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_500 = 9'h1f4 == index ? 64'h0 : _GEN_499; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_501 = 9'h1f5 == index ? 64'h0 : _GEN_500; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_502 = 9'h1f6 == index ? 64'h0 : _GEN_501; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_503 = 9'h1f7 == index ? 64'h0 : _GEN_502; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_504 = 9'h1f8 == index ? 64'h0 : _GEN_503; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_505 = 9'h1f9 == index ? 64'h0 : _GEN_504; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_506 = 9'h1fa == index ? 64'h0 : _GEN_505; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_507 = 9'h1fb == index ? 64'h0 : _GEN_506; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_508 = 9'h1fc == index ? 64'h0 : _GEN_507; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_509 = 9'h1fd == index ? 64'h0 : _GEN_508; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_510 = 9'h1fe == index ? 64'h0 : _GEN_509; // @[BootROM.scala 51:{47,47}]
+ wire [63:0] _GEN_511 = 9'h1ff == index ? 64'h0 : _GEN_510; // @[BootROM.scala 51:{47,47}]
+ TLMonitor_52 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ assign auto_in_a_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_in_d_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_in_d_bits_data = |high ? 64'h0 : _GEN_511; // @[BootROM.scala 51:47]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockSinkDomain_1(
+ output auto_bootrom_in_a_ready,
+ input auto_bootrom_in_a_valid,
+ input [2:0] auto_bootrom_in_a_bits_opcode,
+ input [2:0] auto_bootrom_in_a_bits_param,
+ input [1:0] auto_bootrom_in_a_bits_size,
+ input [6:0] auto_bootrom_in_a_bits_source,
+ input [16:0] auto_bootrom_in_a_bits_address,
+ input [7:0] auto_bootrom_in_a_bits_mask,
+ input auto_bootrom_in_a_bits_corrupt,
+ input auto_bootrom_in_d_ready,
+ output auto_bootrom_in_d_valid,
+ output [1:0] auto_bootrom_in_d_bits_size,
+ output [6:0] auto_bootrom_in_d_bits_source,
+ output [63:0] auto_bootrom_in_d_bits_data,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire bootrom_clock; // @[BootROM.scala 81:17]
+ wire bootrom_reset; // @[BootROM.scala 81:17]
+ wire bootrom_auto_in_a_ready; // @[BootROM.scala 81:17]
+ wire bootrom_auto_in_a_valid; // @[BootROM.scala 81:17]
+ wire [2:0] bootrom_auto_in_a_bits_opcode; // @[BootROM.scala 81:17]
+ wire [2:0] bootrom_auto_in_a_bits_param; // @[BootROM.scala 81:17]
+ wire [1:0] bootrom_auto_in_a_bits_size; // @[BootROM.scala 81:17]
+ wire [6:0] bootrom_auto_in_a_bits_source; // @[BootROM.scala 81:17]
+ wire [16:0] bootrom_auto_in_a_bits_address; // @[BootROM.scala 81:17]
+ wire [7:0] bootrom_auto_in_a_bits_mask; // @[BootROM.scala 81:17]
+ wire bootrom_auto_in_a_bits_corrupt; // @[BootROM.scala 81:17]
+ wire bootrom_auto_in_d_ready; // @[BootROM.scala 81:17]
+ wire bootrom_auto_in_d_valid; // @[BootROM.scala 81:17]
+ wire [1:0] bootrom_auto_in_d_bits_size; // @[BootROM.scala 81:17]
+ wire [6:0] bootrom_auto_in_d_bits_source; // @[BootROM.scala 81:17]
+ wire [63:0] bootrom_auto_in_d_bits_data; // @[BootROM.scala 81:17]
+ TLROM bootrom ( // @[BootROM.scala 81:17]
+ .clock(bootrom_clock),
+ .reset(bootrom_reset),
+ .auto_in_a_ready(bootrom_auto_in_a_ready),
+ .auto_in_a_valid(bootrom_auto_in_a_valid),
+ .auto_in_a_bits_opcode(bootrom_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(bootrom_auto_in_a_bits_param),
+ .auto_in_a_bits_size(bootrom_auto_in_a_bits_size),
+ .auto_in_a_bits_source(bootrom_auto_in_a_bits_source),
+ .auto_in_a_bits_address(bootrom_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(bootrom_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(bootrom_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(bootrom_auto_in_d_ready),
+ .auto_in_d_valid(bootrom_auto_in_d_valid),
+ .auto_in_d_bits_size(bootrom_auto_in_d_bits_size),
+ .auto_in_d_bits_source(bootrom_auto_in_d_bits_source),
+ .auto_in_d_bits_data(bootrom_auto_in_d_bits_data)
+ );
+ assign auto_bootrom_in_a_ready = bootrom_auto_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_bootrom_in_d_valid = bootrom_auto_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_bootrom_in_d_bits_size = bootrom_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_bootrom_in_d_bits_source = bootrom_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_bootrom_in_d_bits_data = bootrom_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign bootrom_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bootrom_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bootrom_auto_in_a_valid = auto_bootrom_in_a_valid; // @[LazyModule.scala 309:16]
+ assign bootrom_auto_in_a_bits_opcode = auto_bootrom_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign bootrom_auto_in_a_bits_param = auto_bootrom_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign bootrom_auto_in_a_bits_size = auto_bootrom_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign bootrom_auto_in_a_bits_source = auto_bootrom_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign bootrom_auto_in_a_bits_address = auto_bootrom_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign bootrom_auto_in_a_bits_mask = auto_bootrom_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign bootrom_auto_in_a_bits_corrupt = auto_bootrom_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign bootrom_auto_in_d_ready = auto_bootrom_in_d_ready; // @[LazyModule.scala 309:16]
+endmodule
+module TLMonitor_53(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_56 = io_in_a_bits_address ^ 29'h20000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_59 = $signed(_T_57) & -30'sh10000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 30'sh0; // @[Parameters.scala 137:67]
+ wire [28:0] _T_61 = io_in_a_bits_address ^ 29'h10000000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_64 = $signed(_T_62) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_66 = _T_60 | _T_65; // @[Parameters.scala 671:42]
+ wire _T_104 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_108 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_109 = _T_108 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_113 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_117 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_183 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_196 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_213 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_227 = _T_213 & _T_66; // @[Parameters.scala 670:56]
+ wire _T_238 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_242 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_250 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_272 = _T_213 & _T_65; // @[Parameters.scala 670:56]
+ wire _T_282 = source_ok & _T_272; // @[Monitor.scala 115:71]
+ wire _T_300 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_346 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_347 = io_in_a_bits_mask & _T_346; // @[Monitor.scala 127:31]
+ wire _T_348 = _T_347 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_352 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_389 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_397 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_434 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_442 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_479 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_491 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_495 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_499 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_503 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_507 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_511 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_515 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_526 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_530 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_543 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_563 = _T_511 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_572 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_589 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_607 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_637 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_638 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_642 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_646 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_650 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_654 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_661 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_662 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_666 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_670 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_674 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_678 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_682 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_688 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_691 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_693 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_695 = ~_T_693[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_699 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_701 = ~_T_495; // @[Monitor.scala 671:74]
+ wire _T_702 = io_in_d_valid & d_first_1 & ~_T_495; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_701 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_701 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_688 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_712 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_714 = _T_712[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_719 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_720 = io_in_d_bits_opcode == _GEN_32 | _T_719; // @[Monitor.scala 685:77]
+ wire _T_724 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_731 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_732 = io_in_d_bits_opcode == _GEN_48 | _T_731; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_736 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_746 = _T_699 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_701; // @[Monitor.scala 694:116]
+ wire _T_748 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_757 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_783 = io_in_d_valid & d_first_2 & _T_495; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_495 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_495 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_791 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_801 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_821 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_104 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_104) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_109 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_109) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_113 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_113) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_104 & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_T_104) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_109 & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_T_109) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_113 & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_T_113) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_227 & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~_T_227) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_238 & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~_T_238) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_113 & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~_T_113) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_282 & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~_T_282) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_238 & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~_T_238) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_282 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_282) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_238 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_238) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_348 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_348) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_352 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_352 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_389 & (io_in_a_valid & _T_352 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset & ~_T_389) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_352 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_434 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_434) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_479 & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~_T_479) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_113 & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~_T_113) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_491 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_491) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_507 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_507) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_526 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_526) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_530 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_530) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_507 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_507) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_526 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_526) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_530 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_530) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_563 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_563) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_572 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_572 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_d_valid & _T_572 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_572 & _T_2 & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_507 & (io_in_d_valid & _T_572 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_572 & _T_2 & ~_T_507) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_572 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_572 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_589 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_589 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_d_valid & _T_589 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_589 & _T_2 & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_563 & (io_in_d_valid & _T_589 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_589 & _T_2 & ~_T_563) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_589 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_589 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_607 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_607 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_d_valid & _T_607 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_607 & _T_2 & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_507 & (io_in_d_valid & _T_607 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_607 & _T_2 & ~_T_507) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_607 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_607 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_670 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_670) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_674 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_674) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_682 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_682) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_695 & (_T_691 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_691 & ~reset & ~_T_695) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_714 & (_T_702 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & _T_2 & ~_T_714) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_720 & (_T_702 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & same_cycle_resp & _T_2 & ~_T_720) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_724 & (_T_702 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & same_cycle_resp & _T_2 & ~_T_724) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_732 & (_T_702 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & ~same_cycle_resp & _T_2 & ~_T_732) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_736 & (_T_702 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & ~same_cycle_resp & _T_2 & ~_T_736) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_748 & (_T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_746 & _T_2 & ~_T_748) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_757 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_757) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_791[0] & (_T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_783 & _T_2 & ~_T_791[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_801 & (_T_783 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_783 & _T_2 & ~_T_801) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_821 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_821) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module HellaPeekingArbiter(
+ input clock,
+ input reset,
+ output io_in_1_ready,
+ input io_in_1_valid,
+ input [2:0] io_in_1_bits_opcode,
+ input [2:0] io_in_1_bits_param,
+ input [3:0] io_in_1_bits_size,
+ input [2:0] io_in_1_bits_source,
+ input [63:0] io_in_1_bits_data,
+ input io_in_1_bits_corrupt,
+ input [7:0] io_in_1_bits_union,
+ input io_in_1_bits_last,
+ output io_in_4_ready,
+ input io_in_4_valid,
+ input [2:0] io_in_4_bits_opcode,
+ input [2:0] io_in_4_bits_param,
+ input [3:0] io_in_4_bits_size,
+ input [2:0] io_in_4_bits_source,
+ input [31:0] io_in_4_bits_address,
+ input [63:0] io_in_4_bits_data,
+ input io_in_4_bits_corrupt,
+ input [7:0] io_in_4_bits_union,
+ input io_in_4_bits_last,
+ input io_out_ready,
+ output io_out_valid,
+ output [2:0] io_out_bits_chanId,
+ output [2:0] io_out_bits_opcode,
+ output [2:0] io_out_bits_param,
+ output [3:0] io_out_bits_size,
+ output [2:0] io_out_bits_source,
+ output [31:0] io_out_bits_address,
+ output [63:0] io_out_bits_data,
+ output io_out_bits_corrupt,
+ output [7:0] io_out_bits_union,
+ output io_out_bits_last
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] lockIdx; // @[Arbiters.scala 25:20]
+ reg locked; // @[Arbiters.scala 26:19]
+ wire [2:0] choice = io_in_1_valid ? 3'h1 : 3'h4; // @[Mux.scala 47:70]
+ wire [2:0] chosen = locked ? lockIdx : choice; // @[Arbiters.scala 36:19]
+ wire _GEN_60 = 3'h1 == chosen; // @[Arbiters.scala 42:{16,16}]
+ wire _GEN_2 = 3'h2 == chosen ? 1'h0 : 3'h1 == chosen & io_in_1_valid; // @[Arbiters.scala 42:{16,16}]
+ wire _GEN_3 = 3'h3 == chosen ? 1'h0 : _GEN_2; // @[Arbiters.scala 42:{16,16}]
+ wire [2:0] _GEN_6 = 3'h1 == chosen ? 3'h3 : 3'h4; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_7 = 3'h2 == chosen ? 3'h2 : _GEN_6; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_8 = 3'h3 == chosen ? 3'h1 : _GEN_7; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_11 = 3'h1 == chosen ? io_in_1_bits_opcode : 3'h0; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_12 = 3'h2 == chosen ? 3'h0 : _GEN_11; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_13 = 3'h3 == chosen ? 3'h0 : _GEN_12; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_16 = 3'h1 == chosen ? io_in_1_bits_param : 3'h0; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_17 = 3'h2 == chosen ? 3'h0 : _GEN_16; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_18 = 3'h3 == chosen ? 3'h0 : _GEN_17; // @[Arbiters.scala 43:{15,15}]
+ wire [3:0] _GEN_21 = 3'h1 == chosen ? io_in_1_bits_size : 4'h0; // @[Arbiters.scala 43:{15,15}]
+ wire [3:0] _GEN_22 = 3'h2 == chosen ? 4'h0 : _GEN_21; // @[Arbiters.scala 43:{15,15}]
+ wire [3:0] _GEN_23 = 3'h3 == chosen ? 4'h0 : _GEN_22; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_26 = 3'h1 == chosen ? io_in_1_bits_source : 3'h0; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_27 = 3'h2 == chosen ? 3'h0 : _GEN_26; // @[Arbiters.scala 43:{15,15}]
+ wire [2:0] _GEN_28 = 3'h3 == chosen ? 3'h0 : _GEN_27; // @[Arbiters.scala 43:{15,15}]
+ wire [63:0] _GEN_36 = 3'h1 == chosen ? io_in_1_bits_data : 64'h0; // @[Arbiters.scala 43:{15,15}]
+ wire [63:0] _GEN_37 = 3'h2 == chosen ? 64'h0 : _GEN_36; // @[Arbiters.scala 43:{15,15}]
+ wire [63:0] _GEN_38 = 3'h3 == chosen ? 64'h0 : _GEN_37; // @[Arbiters.scala 43:{15,15}]
+ wire _GEN_42 = 3'h2 == chosen ? 1'h0 : _GEN_60 & io_in_1_bits_corrupt; // @[Arbiters.scala 43:{15,15}]
+ wire _GEN_43 = 3'h3 == chosen ? 1'h0 : _GEN_42; // @[Arbiters.scala 43:{15,15}]
+ wire [7:0] _GEN_46 = 3'h1 == chosen ? io_in_1_bits_union : 8'h0; // @[Arbiters.scala 43:{15,15}]
+ wire [7:0] _GEN_47 = 3'h2 == chosen ? 8'h0 : _GEN_46; // @[Arbiters.scala 43:{15,15}]
+ wire [7:0] _GEN_48 = 3'h3 == chosen ? 8'h0 : _GEN_47; // @[Arbiters.scala 43:{15,15}]
+ wire _GEN_51 = 3'h1 == chosen ? io_in_1_bits_last : 1'h1; // @[Arbiters.scala 43:{15,15}]
+ wire _T = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_56 = ~locked | locked; // @[Arbiters.scala 59:50 61:14 26:19]
+ assign io_in_1_ready = io_out_ready & chosen == 3'h1; // @[Arbiters.scala 39:36]
+ assign io_in_4_ready = io_out_ready & chosen == 3'h4; // @[Arbiters.scala 39:36]
+ assign io_out_valid = 3'h4 == chosen ? io_in_4_valid : _GEN_3; // @[Arbiters.scala 42:{16,16}]
+ assign io_out_bits_chanId = 3'h4 == chosen ? 3'h0 : _GEN_8; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_opcode = 3'h4 == chosen ? io_in_4_bits_opcode : _GEN_13; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_param = 3'h4 == chosen ? io_in_4_bits_param : _GEN_18; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_size = 3'h4 == chosen ? io_in_4_bits_size : _GEN_23; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_source = 3'h4 == chosen ? io_in_4_bits_source : _GEN_28; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_address = 3'h4 == chosen ? io_in_4_bits_address : 32'h0; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_data = 3'h4 == chosen ? io_in_4_bits_data : _GEN_38; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_corrupt = 3'h4 == chosen ? io_in_4_bits_corrupt : _GEN_43; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_union = 3'h4 == chosen ? io_in_4_bits_union : _GEN_48; // @[Arbiters.scala 43:{15,15}]
+ assign io_out_bits_last = 3'h4 == chosen ? io_in_4_bits_last : 3'h3 == chosen | (3'h2 == chosen | _GEN_51); // @[Arbiters.scala 43:{15,15}]
+ always @(posedge clock) begin
+ if (reset) begin // @[Arbiters.scala 25:20]
+ lockIdx <= 3'h0; // @[Arbiters.scala 25:20]
+ end else if (_T) begin // @[Arbiters.scala 58:24]
+ if (~locked) begin // @[Arbiters.scala 59:50]
+ if (io_in_1_valid) begin // @[Mux.scala 47:70]
+ lockIdx <= 3'h1;
+ end else begin
+ lockIdx <= 3'h4;
+ end
+ end
+ end
+ if (reset) begin // @[Arbiters.scala 26:19]
+ locked <= 1'h0; // @[Arbiters.scala 26:19]
+ end else if (_T) begin // @[Arbiters.scala 58:24]
+ if (io_out_bits_last) begin // @[Arbiters.scala 64:35]
+ locked <= 1'h0; // @[Arbiters.scala 65:14]
+ end else begin
+ locked <= _GEN_56;
+ end
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ lockIdx = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ locked = _RAND_1[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module GenericSerializer(
+ input clock,
+ input reset,
+ output io_in_ready,
+ input io_in_valid,
+ input [2:0] io_in_bits_chanId,
+ input [2:0] io_in_bits_opcode,
+ input [2:0] io_in_bits_param,
+ input [3:0] io_in_bits_size,
+ input [2:0] io_in_bits_source,
+ input [31:0] io_in_bits_address,
+ input [63:0] io_in_bits_data,
+ input io_in_bits_corrupt,
+ input [7:0] io_in_bits_union,
+ input io_in_bits_last,
+ input io_out_ready,
+ output io_out_valid,
+ output [31:0] io_out_bits
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [127:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+`endif // RANDOMIZE_REG_INIT
+ reg [121:0] data; // @[Serdes.scala 173:17]
+ reg sending; // @[Serdes.scala 175:24]
+ wire _T = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
+ reg [1:0] sendCount; // @[Counter.scala 62:40]
+ wire wrap_wrap = sendCount == 2'h3; // @[Counter.scala 74:24]
+ wire [1:0] _wrap_value_T_1 = sendCount + 2'h1; // @[Counter.scala 78:24]
+ wire sendDone = _T & wrap_wrap; // @[Counter.scala 120:{16,23}]
+ wire _T_1 = io_in_ready & io_in_valid; // @[Decoupled.scala 50:35]
+ wire [121:0] _data_T = {io_in_bits_chanId,io_in_bits_opcode,io_in_bits_param,io_in_bits_size,io_in_bits_source,
+ io_in_bits_address,io_in_bits_data,io_in_bits_corrupt,io_in_bits_union,io_in_bits_last}; // @[Serdes.scala 183:24]
+ wire _GEN_3 = _T_1 | sending; // @[Serdes.scala 182:21 184:13 175:24]
+ wire [121:0] _data_T_1 = {{32'd0}, data[121:32]}; // @[Serdes.scala 187:37]
+ assign io_in_ready = ~sending; // @[Serdes.scala 178:18]
+ assign io_out_valid = sending; // @[Serdes.scala 179:16]
+ assign io_out_bits = data[31:0]; // @[Serdes.scala 180:22]
+ always @(posedge clock) begin
+ if (_T) begin // @[Serdes.scala 187:22]
+ data <= _data_T_1; // @[Serdes.scala 187:29]
+ end else if (_T_1) begin // @[Serdes.scala 182:21]
+ data <= _data_T; // @[Serdes.scala 183:10]
+ end
+ if (reset) begin // @[Serdes.scala 175:24]
+ sending <= 1'h0; // @[Serdes.scala 175:24]
+ end else if (sendDone) begin // @[Serdes.scala 189:19]
+ sending <= 1'h0; // @[Serdes.scala 189:29]
+ end else begin
+ sending <= _GEN_3;
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ sendCount <= 2'h0; // @[Counter.scala 62:40]
+ end else if (_T) begin // @[Counter.scala 120:16]
+ sendCount <= _wrap_value_T_1; // @[Counter.scala 78:15]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {4{`RANDOM}};
+ data = _RAND_0[121:0];
+ _RAND_1 = {1{`RANDOM}};
+ sending = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ sendCount = _RAND_2[1:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module GenericDeserializer(
+ input clock,
+ input reset,
+ output io_in_ready,
+ input io_in_valid,
+ input [31:0] io_in_bits,
+ input io_out_ready,
+ output io_out_valid,
+ output [2:0] io_out_bits_chanId,
+ output [2:0] io_out_bits_opcode,
+ output [2:0] io_out_bits_param,
+ output [3:0] io_out_bits_size,
+ output [2:0] io_out_bits_source,
+ output [31:0] io_out_bits_address,
+ output [63:0] io_out_bits_data,
+ output io_out_bits_corrupt,
+ output [7:0] io_out_bits_union
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+`endif // RANDOMIZE_REG_INIT
+ reg [31:0] data_0; // @[Serdes.scala 200:17]
+ reg [31:0] data_1; // @[Serdes.scala 200:17]
+ reg [31:0] data_2; // @[Serdes.scala 200:17]
+ reg [31:0] data_3; // @[Serdes.scala 200:17]
+ reg receiving; // @[Serdes.scala 202:26]
+ wire _T = io_in_ready & io_in_valid; // @[Decoupled.scala 50:35]
+ reg [1:0] recvCount; // @[Counter.scala 62:40]
+ wire wrap_wrap = recvCount == 2'h3; // @[Counter.scala 74:24]
+ wire [1:0] _wrap_value_T_1 = recvCount + 2'h1; // @[Counter.scala 78:24]
+ wire recvDone = _T & wrap_wrap; // @[Counter.scala 120:{16,23}]
+ wire [127:0] _io_out_bits_T = {data_3,data_2,data_1,data_0}; // @[Serdes.scala 207:23]
+ wire _GEN_10 = recvDone ? 1'h0 : receiving; // @[Serdes.scala 213:19 202:26 213:31]
+ wire _T_2 = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_11 = _T_2 | _GEN_10; // @[Serdes.scala 215:{22,34}]
+ assign io_in_ready = receiving; // @[Serdes.scala 205:15]
+ assign io_out_valid = ~receiving; // @[Serdes.scala 206:19]
+ assign io_out_bits_chanId = _io_out_bits_T[121:119]; // @[Serdes.scala 207:38]
+ assign io_out_bits_opcode = _io_out_bits_T[118:116]; // @[Serdes.scala 207:38]
+ assign io_out_bits_param = _io_out_bits_T[115:113]; // @[Serdes.scala 207:38]
+ assign io_out_bits_size = _io_out_bits_T[112:109]; // @[Serdes.scala 207:38]
+ assign io_out_bits_source = _io_out_bits_T[108:106]; // @[Serdes.scala 207:38]
+ assign io_out_bits_address = _io_out_bits_T[105:74]; // @[Serdes.scala 207:38]
+ assign io_out_bits_data = _io_out_bits_T[73:10]; // @[Serdes.scala 207:38]
+ assign io_out_bits_corrupt = _io_out_bits_T[9]; // @[Serdes.scala 207:38]
+ assign io_out_bits_union = _io_out_bits_T[8:1]; // @[Serdes.scala 207:38]
+ always @(posedge clock) begin
+ if (_T) begin // @[Serdes.scala 209:21]
+ if (2'h0 == recvCount) begin // @[Serdes.scala 210:21]
+ data_0 <= io_in_bits; // @[Serdes.scala 210:21]
+ end
+ end
+ if (_T) begin // @[Serdes.scala 209:21]
+ if (2'h1 == recvCount) begin // @[Serdes.scala 210:21]
+ data_1 <= io_in_bits; // @[Serdes.scala 210:21]
+ end
+ end
+ if (_T) begin // @[Serdes.scala 209:21]
+ if (2'h2 == recvCount) begin // @[Serdes.scala 210:21]
+ data_2 <= io_in_bits; // @[Serdes.scala 210:21]
+ end
+ end
+ if (_T) begin // @[Serdes.scala 209:21]
+ if (2'h3 == recvCount) begin // @[Serdes.scala 210:21]
+ data_3 <= io_in_bits; // @[Serdes.scala 210:21]
+ end
+ end
+ receiving <= reset | _GEN_11; // @[Serdes.scala 202:{26,26}]
+ if (reset) begin // @[Counter.scala 62:40]
+ recvCount <= 2'h0; // @[Counter.scala 62:40]
+ end else if (_T) begin // @[Counter.scala 120:16]
+ recvCount <= _wrap_value_T_1; // @[Counter.scala 78:15]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ data_0 = _RAND_0[31:0];
+ _RAND_1 = {1{`RANDOM}};
+ data_1 = _RAND_1[31:0];
+ _RAND_2 = {1{`RANDOM}};
+ data_2 = _RAND_2[31:0];
+ _RAND_3 = {1{`RANDOM}};
+ data_3 = _RAND_3[31:0];
+ _RAND_4 = {1{`RANDOM}};
+ receiving = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ recvCount = _RAND_5[1:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLSerdesser(
+ input clock,
+ input reset,
+ output auto_manager_in_a_ready,
+ input auto_manager_in_a_valid,
+ input [2:0] auto_manager_in_a_bits_opcode,
+ input [2:0] auto_manager_in_a_bits_param,
+ input [2:0] auto_manager_in_a_bits_size,
+ input [2:0] auto_manager_in_a_bits_source,
+ input [28:0] auto_manager_in_a_bits_address,
+ input [7:0] auto_manager_in_a_bits_mask,
+ input [63:0] auto_manager_in_a_bits_data,
+ input auto_manager_in_a_bits_corrupt,
+ input auto_manager_in_d_ready,
+ output auto_manager_in_d_valid,
+ output [2:0] auto_manager_in_d_bits_opcode,
+ output [1:0] auto_manager_in_d_bits_param,
+ output [2:0] auto_manager_in_d_bits_size,
+ output [2:0] auto_manager_in_d_bits_source,
+ output auto_manager_in_d_bits_sink,
+ output auto_manager_in_d_bits_denied,
+ output [63:0] auto_manager_in_d_bits_data,
+ output auto_manager_in_d_bits_corrupt,
+ input auto_client_out_a_ready,
+ output auto_client_out_a_valid,
+ output [2:0] auto_client_out_a_bits_opcode,
+ output [2:0] auto_client_out_a_bits_param,
+ output [3:0] auto_client_out_a_bits_size,
+ output auto_client_out_a_bits_source,
+ output [31:0] auto_client_out_a_bits_address,
+ output [7:0] auto_client_out_a_bits_mask,
+ output [63:0] auto_client_out_a_bits_data,
+ output auto_client_out_a_bits_corrupt,
+ output auto_client_out_d_ready,
+ input auto_client_out_d_valid,
+ input [2:0] auto_client_out_d_bits_opcode,
+ input [1:0] auto_client_out_d_bits_param,
+ input [3:0] auto_client_out_d_bits_size,
+ input auto_client_out_d_bits_source,
+ input auto_client_out_d_bits_sink,
+ input auto_client_out_d_bits_denied,
+ input [63:0] auto_client_out_d_bits_data,
+ input auto_client_out_d_bits_corrupt,
+ output io_ser_in_ready,
+ input io_ser_in_valid,
+ input [31:0] io_ser_in_bits,
+ input io_ser_out_ready,
+ output io_ser_out_valid,
+ output [31:0] io_ser_out_bits
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire outArb_clock; // @[Serdes.scala 619:24]
+ wire outArb_reset; // @[Serdes.scala 619:24]
+ wire outArb_io_in_1_ready; // @[Serdes.scala 619:24]
+ wire outArb_io_in_1_valid; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_in_1_bits_opcode; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_in_1_bits_param; // @[Serdes.scala 619:24]
+ wire [3:0] outArb_io_in_1_bits_size; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_in_1_bits_source; // @[Serdes.scala 619:24]
+ wire [63:0] outArb_io_in_1_bits_data; // @[Serdes.scala 619:24]
+ wire outArb_io_in_1_bits_corrupt; // @[Serdes.scala 619:24]
+ wire [7:0] outArb_io_in_1_bits_union; // @[Serdes.scala 619:24]
+ wire outArb_io_in_1_bits_last; // @[Serdes.scala 619:24]
+ wire outArb_io_in_4_ready; // @[Serdes.scala 619:24]
+ wire outArb_io_in_4_valid; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_in_4_bits_opcode; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_in_4_bits_param; // @[Serdes.scala 619:24]
+ wire [3:0] outArb_io_in_4_bits_size; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_in_4_bits_source; // @[Serdes.scala 619:24]
+ wire [31:0] outArb_io_in_4_bits_address; // @[Serdes.scala 619:24]
+ wire [63:0] outArb_io_in_4_bits_data; // @[Serdes.scala 619:24]
+ wire outArb_io_in_4_bits_corrupt; // @[Serdes.scala 619:24]
+ wire [7:0] outArb_io_in_4_bits_union; // @[Serdes.scala 619:24]
+ wire outArb_io_in_4_bits_last; // @[Serdes.scala 619:24]
+ wire outArb_io_out_ready; // @[Serdes.scala 619:24]
+ wire outArb_io_out_valid; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_out_bits_chanId; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_out_bits_opcode; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_out_bits_param; // @[Serdes.scala 619:24]
+ wire [3:0] outArb_io_out_bits_size; // @[Serdes.scala 619:24]
+ wire [2:0] outArb_io_out_bits_source; // @[Serdes.scala 619:24]
+ wire [31:0] outArb_io_out_bits_address; // @[Serdes.scala 619:24]
+ wire [63:0] outArb_io_out_bits_data; // @[Serdes.scala 619:24]
+ wire outArb_io_out_bits_corrupt; // @[Serdes.scala 619:24]
+ wire [7:0] outArb_io_out_bits_union; // @[Serdes.scala 619:24]
+ wire outArb_io_out_bits_last; // @[Serdes.scala 619:24]
+ wire outSer_clock; // @[Serdes.scala 621:24]
+ wire outSer_reset; // @[Serdes.scala 621:24]
+ wire outSer_io_in_ready; // @[Serdes.scala 621:24]
+ wire outSer_io_in_valid; // @[Serdes.scala 621:24]
+ wire [2:0] outSer_io_in_bits_chanId; // @[Serdes.scala 621:24]
+ wire [2:0] outSer_io_in_bits_opcode; // @[Serdes.scala 621:24]
+ wire [2:0] outSer_io_in_bits_param; // @[Serdes.scala 621:24]
+ wire [3:0] outSer_io_in_bits_size; // @[Serdes.scala 621:24]
+ wire [2:0] outSer_io_in_bits_source; // @[Serdes.scala 621:24]
+ wire [31:0] outSer_io_in_bits_address; // @[Serdes.scala 621:24]
+ wire [63:0] outSer_io_in_bits_data; // @[Serdes.scala 621:24]
+ wire outSer_io_in_bits_corrupt; // @[Serdes.scala 621:24]
+ wire [7:0] outSer_io_in_bits_union; // @[Serdes.scala 621:24]
+ wire outSer_io_in_bits_last; // @[Serdes.scala 621:24]
+ wire outSer_io_out_ready; // @[Serdes.scala 621:24]
+ wire outSer_io_out_valid; // @[Serdes.scala 621:24]
+ wire [31:0] outSer_io_out_bits; // @[Serdes.scala 621:24]
+ wire inDes_clock; // @[Serdes.scala 626:23]
+ wire inDes_reset; // @[Serdes.scala 626:23]
+ wire inDes_io_in_ready; // @[Serdes.scala 626:23]
+ wire inDes_io_in_valid; // @[Serdes.scala 626:23]
+ wire [31:0] inDes_io_in_bits; // @[Serdes.scala 626:23]
+ wire inDes_io_out_ready; // @[Serdes.scala 626:23]
+ wire inDes_io_out_valid; // @[Serdes.scala 626:23]
+ wire [2:0] inDes_io_out_bits_chanId; // @[Serdes.scala 626:23]
+ wire [2:0] inDes_io_out_bits_opcode; // @[Serdes.scala 626:23]
+ wire [2:0] inDes_io_out_bits_param; // @[Serdes.scala 626:23]
+ wire [3:0] inDes_io_out_bits_size; // @[Serdes.scala 626:23]
+ wire [2:0] inDes_io_out_bits_source; // @[Serdes.scala 626:23]
+ wire [31:0] inDes_io_out_bits_address; // @[Serdes.scala 626:23]
+ wire [63:0] inDes_io_out_bits_data; // @[Serdes.scala 626:23]
+ wire inDes_io_out_bits_corrupt; // @[Serdes.scala 626:23]
+ wire [7:0] inDes_io_out_bits_union; // @[Serdes.scala 626:23]
+ wire [1:0] _merged_bits_merged_union_T_1 = {auto_client_out_d_bits_sink,auto_client_out_d_bits_denied}; // @[Cat.scala 31:58]
+ wire merged_1_ready = outArb_io_in_1_ready; // @[Serdes.scala 354:22 622:18]
+ wire _merged_bits_last_T_1 = merged_1_ready & auto_client_out_d_valid; // @[Decoupled.scala 50:35]
+ wire [26:0] _merged_bits_last_beats1_decode_T_1 = 27'hfff << auto_client_out_d_bits_size; // @[package.scala 234:77]
+ wire [11:0] _merged_bits_last_beats1_decode_T_3 = ~_merged_bits_last_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
+ wire [8:0] merged_bits_last_beats1_decode = _merged_bits_last_beats1_decode_T_3[11:3]; // @[Edges.scala 219:59]
+ wire merged_bits_last_beats1_opdata = auto_client_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ wire [8:0] merged_bits_last_beats1 = merged_bits_last_beats1_opdata ? merged_bits_last_beats1_decode : 9'h0; // @[Edges.scala 220:14]
+ reg [8:0] merged_bits_last_counter_1; // @[Edges.scala 228:27]
+ wire [8:0] merged_bits_last_counter1_1 = merged_bits_last_counter_1 - 9'h1; // @[Edges.scala 229:28]
+ wire merged_bits_last_first_1 = merged_bits_last_counter_1 == 9'h0; // @[Edges.scala 230:25]
+ wire merged_4_ready = outArb_io_in_4_ready; // @[Serdes.scala 354:22 622:18]
+ wire _merged_bits_last_T_4 = merged_4_ready & auto_manager_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [18:0] _merged_bits_last_beats1_decode_T_13 = 19'hfff << auto_manager_in_a_bits_size; // @[package.scala 234:77]
+ wire [11:0] _merged_bits_last_beats1_decode_T_15 = ~_merged_bits_last_beats1_decode_T_13[11:0]; // @[package.scala 234:46]
+ wire [8:0] merged_bits_last_beats1_decode_3 = _merged_bits_last_beats1_decode_T_15[11:3]; // @[Edges.scala 219:59]
+ wire merged_bits_last_beats1_opdata_3 = ~auto_manager_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ wire [8:0] merged_bits_last_beats1_3 = merged_bits_last_beats1_opdata_3 ? merged_bits_last_beats1_decode_3 : 9'h0; // @[Edges.scala 220:14]
+ reg [8:0] merged_bits_last_counter_4; // @[Edges.scala 228:27]
+ wire [8:0] merged_bits_last_counter1_4 = merged_bits_last_counter_4 - 9'h1; // @[Edges.scala 229:28]
+ wire merged_bits_last_first_4 = merged_bits_last_counter_4 == 9'h0; // @[Edges.scala 230:25]
+ wire _bundleOut_0_a_valid_T = inDes_io_out_bits_chanId == 3'h0; // @[Serdes.scala 234:37]
+ wire _bundleIn_0_d_valid_T = inDes_io_out_bits_chanId == 3'h3; // @[Serdes.scala 237:37]
+ wire [7:0] _bundleIn_0_d_bits_d_sink_T = {{1'd0}, inDes_io_out_bits_union[7:1]}; // @[Serdes.scala 465:31]
+ wire _inDes_io_out_ready_T_3 = 3'h1 == inDes_io_out_bits_chanId ? 1'h0 : 3'h0 == inDes_io_out_bits_chanId &
+ auto_client_out_a_ready; // @[Mux.scala 81:58]
+ wire _inDes_io_out_ready_T_5 = 3'h2 == inDes_io_out_bits_chanId ? 1'h0 : _inDes_io_out_ready_T_3; // @[Mux.scala 81:58]
+ wire _inDes_io_out_ready_T_7 = 3'h3 == inDes_io_out_bits_chanId ? auto_manager_in_d_ready : _inDes_io_out_ready_T_5; // @[Mux.scala 81:58]
+ TLMonitor_53 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ HellaPeekingArbiter outArb ( // @[Serdes.scala 619:24]
+ .clock(outArb_clock),
+ .reset(outArb_reset),
+ .io_in_1_ready(outArb_io_in_1_ready),
+ .io_in_1_valid(outArb_io_in_1_valid),
+ .io_in_1_bits_opcode(outArb_io_in_1_bits_opcode),
+ .io_in_1_bits_param(outArb_io_in_1_bits_param),
+ .io_in_1_bits_size(outArb_io_in_1_bits_size),
+ .io_in_1_bits_source(outArb_io_in_1_bits_source),
+ .io_in_1_bits_data(outArb_io_in_1_bits_data),
+ .io_in_1_bits_corrupt(outArb_io_in_1_bits_corrupt),
+ .io_in_1_bits_union(outArb_io_in_1_bits_union),
+ .io_in_1_bits_last(outArb_io_in_1_bits_last),
+ .io_in_4_ready(outArb_io_in_4_ready),
+ .io_in_4_valid(outArb_io_in_4_valid),
+ .io_in_4_bits_opcode(outArb_io_in_4_bits_opcode),
+ .io_in_4_bits_param(outArb_io_in_4_bits_param),
+ .io_in_4_bits_size(outArb_io_in_4_bits_size),
+ .io_in_4_bits_source(outArb_io_in_4_bits_source),
+ .io_in_4_bits_address(outArb_io_in_4_bits_address),
+ .io_in_4_bits_data(outArb_io_in_4_bits_data),
+ .io_in_4_bits_corrupt(outArb_io_in_4_bits_corrupt),
+ .io_in_4_bits_union(outArb_io_in_4_bits_union),
+ .io_in_4_bits_last(outArb_io_in_4_bits_last),
+ .io_out_ready(outArb_io_out_ready),
+ .io_out_valid(outArb_io_out_valid),
+ .io_out_bits_chanId(outArb_io_out_bits_chanId),
+ .io_out_bits_opcode(outArb_io_out_bits_opcode),
+ .io_out_bits_param(outArb_io_out_bits_param),
+ .io_out_bits_size(outArb_io_out_bits_size),
+ .io_out_bits_source(outArb_io_out_bits_source),
+ .io_out_bits_address(outArb_io_out_bits_address),
+ .io_out_bits_data(outArb_io_out_bits_data),
+ .io_out_bits_corrupt(outArb_io_out_bits_corrupt),
+ .io_out_bits_union(outArb_io_out_bits_union),
+ .io_out_bits_last(outArb_io_out_bits_last)
+ );
+ GenericSerializer outSer ( // @[Serdes.scala 621:24]
+ .clock(outSer_clock),
+ .reset(outSer_reset),
+ .io_in_ready(outSer_io_in_ready),
+ .io_in_valid(outSer_io_in_valid),
+ .io_in_bits_chanId(outSer_io_in_bits_chanId),
+ .io_in_bits_opcode(outSer_io_in_bits_opcode),
+ .io_in_bits_param(outSer_io_in_bits_param),
+ .io_in_bits_size(outSer_io_in_bits_size),
+ .io_in_bits_source(outSer_io_in_bits_source),
+ .io_in_bits_address(outSer_io_in_bits_address),
+ .io_in_bits_data(outSer_io_in_bits_data),
+ .io_in_bits_corrupt(outSer_io_in_bits_corrupt),
+ .io_in_bits_union(outSer_io_in_bits_union),
+ .io_in_bits_last(outSer_io_in_bits_last),
+ .io_out_ready(outSer_io_out_ready),
+ .io_out_valid(outSer_io_out_valid),
+ .io_out_bits(outSer_io_out_bits)
+ );
+ GenericDeserializer inDes ( // @[Serdes.scala 626:23]
+ .clock(inDes_clock),
+ .reset(inDes_reset),
+ .io_in_ready(inDes_io_in_ready),
+ .io_in_valid(inDes_io_in_valid),
+ .io_in_bits(inDes_io_in_bits),
+ .io_out_ready(inDes_io_out_ready),
+ .io_out_valid(inDes_io_out_valid),
+ .io_out_bits_chanId(inDes_io_out_bits_chanId),
+ .io_out_bits_opcode(inDes_io_out_bits_opcode),
+ .io_out_bits_param(inDes_io_out_bits_param),
+ .io_out_bits_size(inDes_io_out_bits_size),
+ .io_out_bits_source(inDes_io_out_bits_source),
+ .io_out_bits_address(inDes_io_out_bits_address),
+ .io_out_bits_data(inDes_io_out_bits_data),
+ .io_out_bits_corrupt(inDes_io_out_bits_corrupt),
+ .io_out_bits_union(inDes_io_out_bits_union)
+ );
+ assign auto_manager_in_a_ready = outArb_io_in_4_ready; // @[Serdes.scala 354:22 622:18]
+ assign auto_manager_in_d_valid = inDes_io_out_valid & _bundleIn_0_d_valid_T; // @[Serdes.scala 634:46]
+ assign auto_manager_in_d_bits_opcode = inDes_io_out_bits_opcode; // @[Serdes.scala 457:17 458:15]
+ assign auto_manager_in_d_bits_param = inDes_io_out_bits_param[1:0]; // @[Serdes.scala 457:17 459:15]
+ assign auto_manager_in_d_bits_size = inDes_io_out_bits_size[2:0]; // @[Serdes.scala 457:17 460:15]
+ assign auto_manager_in_d_bits_source = inDes_io_out_bits_source; // @[Serdes.scala 457:17 461:15]
+ assign auto_manager_in_d_bits_sink = _bundleIn_0_d_bits_d_sink_T[0]; // @[Serdes.scala 457:17 465:17]
+ assign auto_manager_in_d_bits_denied = inDes_io_out_bits_union[0]; // @[Serdes.scala 466:30]
+ assign auto_manager_in_d_bits_data = inDes_io_out_bits_data; // @[Serdes.scala 457:17 462:15]
+ assign auto_manager_in_d_bits_corrupt = inDes_io_out_bits_corrupt; // @[Serdes.scala 457:17 464:17]
+ assign auto_client_out_a_valid = inDes_io_out_valid & _bundleOut_0_a_valid_T; // @[Serdes.scala 628:45]
+ assign auto_client_out_a_bits_opcode = inDes_io_out_bits_opcode; // @[Serdes.scala 371:17 372:15]
+ assign auto_client_out_a_bits_param = inDes_io_out_bits_param; // @[Serdes.scala 371:17 373:15]
+ assign auto_client_out_a_bits_size = inDes_io_out_bits_size; // @[Serdes.scala 371:17 374:15]
+ assign auto_client_out_a_bits_source = inDes_io_out_bits_source[0]; // @[Serdes.scala 371:17 375:15]
+ assign auto_client_out_a_bits_address = inDes_io_out_bits_address; // @[Serdes.scala 371:17 376:15]
+ assign auto_client_out_a_bits_mask = inDes_io_out_bits_union; // @[Serdes.scala 371:17 382:15]
+ assign auto_client_out_a_bits_data = inDes_io_out_bits_data; // @[Serdes.scala 371:17 377:15]
+ assign auto_client_out_a_bits_corrupt = inDes_io_out_bits_corrupt; // @[Serdes.scala 371:17 379:17]
+ assign auto_client_out_d_ready = outArb_io_in_1_ready; // @[Serdes.scala 354:22 622:18]
+ assign io_ser_in_ready = inDes_io_in_ready; // @[Serdes.scala 627:17]
+ assign io_ser_out_valid = outSer_io_out_valid; // @[Serdes.scala 624:16]
+ assign io_ser_out_bits = outSer_io_out_bits; // @[Serdes.scala 624:16]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = outArb_io_in_4_ready; // @[Serdes.scala 354:22 622:18]
+ assign monitor_io_in_a_valid = auto_manager_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_manager_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_manager_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_manager_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_manager_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_manager_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_manager_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_manager_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_manager_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = inDes_io_out_valid & _bundleIn_0_d_valid_T; // @[Serdes.scala 634:46]
+ assign monitor_io_in_d_bits_opcode = inDes_io_out_bits_opcode; // @[Serdes.scala 457:17 458:15]
+ assign monitor_io_in_d_bits_param = inDes_io_out_bits_param[1:0]; // @[Serdes.scala 457:17 459:15]
+ assign monitor_io_in_d_bits_size = inDes_io_out_bits_size[2:0]; // @[Serdes.scala 457:17 460:15]
+ assign monitor_io_in_d_bits_source = inDes_io_out_bits_source; // @[Serdes.scala 457:17 461:15]
+ assign monitor_io_in_d_bits_sink = _bundleIn_0_d_bits_d_sink_T[0]; // @[Serdes.scala 457:17 465:17]
+ assign monitor_io_in_d_bits_denied = inDes_io_out_bits_union[0]; // @[Serdes.scala 466:30]
+ assign monitor_io_in_d_bits_corrupt = inDes_io_out_bits_corrupt; // @[Serdes.scala 457:17 464:17]
+ assign outArb_clock = clock;
+ assign outArb_reset = reset;
+ assign outArb_io_in_1_valid = auto_client_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign outArb_io_in_1_bits_opcode = auto_client_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign outArb_io_in_1_bits_param = {{1'd0}, auto_client_out_d_bits_param}; // @[Serdes.scala 309:22 312:20]
+ assign outArb_io_in_1_bits_size = auto_client_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign outArb_io_in_1_bits_source = {{2'd0}, auto_client_out_d_bits_source}; // @[Serdes.scala 309:22 314:20]
+ assign outArb_io_in_1_bits_data = auto_client_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign outArb_io_in_1_bits_corrupt = auto_client_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign outArb_io_in_1_bits_union = {{6'd0}, _merged_bits_merged_union_T_1}; // @[Serdes.scala 309:22 319:22]
+ assign outArb_io_in_1_bits_last = merged_bits_last_counter_1 == 9'h1 | merged_bits_last_beats1 == 9'h0; // @[Edges.scala 231:37]
+ assign outArb_io_in_4_valid = auto_manager_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign outArb_io_in_4_bits_opcode = auto_manager_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign outArb_io_in_4_bits_param = auto_manager_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign outArb_io_in_4_bits_size = {{1'd0}, auto_manager_in_a_bits_size}; // @[Serdes.scala 252:22 256:20]
+ assign outArb_io_in_4_bits_source = auto_manager_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign outArb_io_in_4_bits_address = {{3'd0}, auto_manager_in_a_bits_address}; // @[Serdes.scala 252:22 258:20]
+ assign outArb_io_in_4_bits_data = auto_manager_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign outArb_io_in_4_bits_corrupt = auto_manager_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign outArb_io_in_4_bits_union = auto_manager_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign outArb_io_in_4_bits_last = merged_bits_last_counter_4 == 9'h1 | merged_bits_last_beats1_3 == 9'h0; // @[Edges.scala 231:37]
+ assign outArb_io_out_ready = outSer_io_in_ready; // @[Serdes.scala 623:18]
+ assign outSer_clock = clock;
+ assign outSer_reset = reset;
+ assign outSer_io_in_valid = outArb_io_out_valid; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_chanId = outArb_io_out_bits_chanId; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_opcode = outArb_io_out_bits_opcode; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_param = outArb_io_out_bits_param; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_size = outArb_io_out_bits_size; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_source = outArb_io_out_bits_source; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_address = outArb_io_out_bits_address; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_data = outArb_io_out_bits_data; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_corrupt = outArb_io_out_bits_corrupt; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_union = outArb_io_out_bits_union; // @[Serdes.scala 623:18]
+ assign outSer_io_in_bits_last = outArb_io_out_bits_last; // @[Serdes.scala 623:18]
+ assign outSer_io_out_ready = io_ser_out_ready; // @[Serdes.scala 624:16]
+ assign inDes_clock = clock;
+ assign inDes_reset = reset;
+ assign inDes_io_in_valid = io_ser_in_valid; // @[Serdes.scala 627:17]
+ assign inDes_io_in_bits = io_ser_in_bits; // @[Serdes.scala 627:17]
+ assign inDes_io_out_ready = 3'h4 == inDes_io_out_bits_chanId ? 1'h0 : _inDes_io_out_ready_T_7; // @[Mux.scala 81:58]
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ merged_bits_last_counter_1 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_merged_bits_last_T_1) begin // @[Edges.scala 234:17]
+ if (merged_bits_last_first_1) begin // @[Edges.scala 235:21]
+ if (merged_bits_last_beats1_opdata) begin // @[Edges.scala 220:14]
+ merged_bits_last_counter_1 <= merged_bits_last_beats1_decode;
+ end else begin
+ merged_bits_last_counter_1 <= 9'h0;
+ end
+ end else begin
+ merged_bits_last_counter_1 <= merged_bits_last_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ merged_bits_last_counter_4 <= 9'h0; // @[Edges.scala 228:27]
+ end else if (_merged_bits_last_T_4) begin // @[Edges.scala 234:17]
+ if (merged_bits_last_first_4) begin // @[Edges.scala 235:21]
+ if (merged_bits_last_beats1_opdata_3) begin // @[Edges.scala 220:14]
+ merged_bits_last_counter_4 <= merged_bits_last_beats1_decode_3;
+ end else begin
+ merged_bits_last_counter_4 <= 9'h0;
+ end
+ end else begin
+ merged_bits_last_counter_4 <= merged_bits_last_counter1_4;
+ end
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ merged_bits_last_counter_1 = _RAND_0[8:0];
+ _RAND_1 = {1{`RANDOM}};
+ merged_bits_last_counter_4 = _RAND_1[8:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_54(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [2:0] io_in_a_bits_size,
+ input [2:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_param,
+ input [2:0] io_in_d_bits_size,
+ input [2:0] io_in_d_bits_source,
+ input io_in_d_bits_sink,
+ input io_in_d_bits_denied,
+ input io_in_d_bits_corrupt
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T = io_in_a_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_1 = io_in_a_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_2 = io_in_a_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_3 = io_in_a_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2 | _source_ok_T_3; // @[Parameters.scala 1125:46]
+ wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [1:0] mask_sizeOH_shiftAmount = io_in_a_bits_size[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 3'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_42 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_56 = io_in_a_bits_address ^ 29'h20000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_57 = {1'b0,$signed(_T_56)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_59 = $signed(_T_57) & -30'sh10000; // @[Parameters.scala 137:52]
+ wire _T_60 = $signed(_T_59) == 30'sh0; // @[Parameters.scala 137:67]
+ wire [28:0] _T_61 = io_in_a_bits_address ^ 29'h10000000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_62 = {1'b0,$signed(_T_61)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_64 = $signed(_T_62) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_65 = $signed(_T_64) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_66 = _T_60 | _T_65; // @[Parameters.scala 671:42]
+ wire _T_104 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_108 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_109 = _T_108 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_113 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_117 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_183 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_196 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_213 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
+ wire _T_227 = _T_213 & _T_66; // @[Parameters.scala 670:56]
+ wire _T_238 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_242 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_250 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_272 = _T_213 & _T_65; // @[Parameters.scala 670:56]
+ wire _T_282 = source_ok & _T_272; // @[Monitor.scala 115:71]
+ wire _T_300 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_346 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_347 = io_in_a_bits_mask & _T_346; // @[Monitor.scala 127:31]
+ wire _T_348 = _T_347 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_352 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_389 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_397 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_434 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_442 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_479 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_491 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_6 = io_in_d_bits_source == 3'h2; // @[Parameters.scala 46:9]
+ wire _source_ok_T_7 = io_in_d_bits_source == 3'h1; // @[Parameters.scala 46:9]
+ wire _source_ok_T_8 = io_in_d_bits_source == 3'h0; // @[Parameters.scala 46:9]
+ wire _source_ok_T_9 = io_in_d_bits_source == 3'h4; // @[Parameters.scala 46:9]
+ wire source_ok_1 = _source_ok_T_6 | _source_ok_T_7 | _source_ok_T_8 | _source_ok_T_9; // @[Parameters.scala 1125:46]
+ wire _T_495 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_499 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 312:27]
+ wire _T_503 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
+ wire _T_507 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
+ wire _T_511 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
+ wire _T_515 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_526 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
+ wire _T_530 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
+ wire _T_543 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_563 = _T_511 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
+ wire _T_572 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_589 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_607 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] a_first_beats1_decode = is_aligned_mask[5:3]; // @[Edges.scala 219:59]
+ wire a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
+ reg [2:0] a_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1 = a_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire a_first = a_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [2:0] size; // @[Monitor.scala 386:22]
+ reg [2:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_637 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_638 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_642 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_646 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_650 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_654 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
+ wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
+ wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:3]; // @[Edges.scala 219:59]
+ wire d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
+ reg [2:0] d_first_counter; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1 = d_first_counter - 3'h1; // @[Edges.scala 229:28]
+ wire d_first = d_first_counter == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] param_1; // @[Monitor.scala 536:22]
+ reg [2:0] size_1; // @[Monitor.scala 537:22]
+ reg [2:0] source_1; // @[Monitor.scala 538:22]
+ reg sink; // @[Monitor.scala 539:22]
+ reg denied; // @[Monitor.scala 540:22]
+ wire _T_661 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_662 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_666 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
+ wire _T_670 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_674 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ wire _T_678 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
+ wire _T_682 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
+ reg [4:0] inflight; // @[Monitor.scala 611:27]
+ reg [19:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [19:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg [2:0] a_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] a_first_counter1_1 = a_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ reg [2:0] d_first_counter_1; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_1 = d_first_counter_1 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala 230:25]
+ wire [4:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [5:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [19:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [19:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala 634:152]
+ wire [19:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [19:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [19:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[19:1]}; // @[Monitor.scala 638:144]
+ wire _T_688 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [7:0] _a_set_wo_ready_T = 8'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 648:71 649:22]
+ wire _T_691 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
+ wire [4:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [5:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [66:0] _GEN_1 = {{63'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [66:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
+ wire [66:0] _GEN_2 = {{63'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [66:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [4:0] _T_693 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_695 = ~_T_693[0]; // @[Monitor.scala 658:17]
+ wire [7:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 8'h0; // @[Monitor.scala 652:72 653:28]
+ wire [66:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 656:28]
+ wire [66:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 67'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_699 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_701 = ~_T_495; // @[Monitor.scala 671:74]
+ wire _T_702 = io_in_d_valid & d_first_1 & ~_T_495; // @[Monitor.scala 671:71]
+ wire [7:0] _d_clr_wo_ready_T = 8'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [7:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_495 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 671:90 672:22]
+ wire [78:0] _GEN_3 = {{63'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [78:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [7:0] _GEN_22 = _d_first_T & d_first_1 & _T_701 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 675:91 676:21]
+ wire [78:0] _GEN_23 = _d_first_T & d_first_1 & _T_701 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_688 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [4:0] _T_712 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_714 = _T_712[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_719 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_720 = io_in_d_bits_opcode == _GEN_32 | _T_719; // @[Monitor.scala 685:77]
+ wire _T_724 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_731 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_732 = io_in_d_bits_opcode == _GEN_48 | _T_731; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_736 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_746 = _T_699 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_701; // @[Monitor.scala 694:116]
+ wire _T_748 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [4:0] a_set_wo_ready = _GEN_15[4:0];
+ wire [4:0] d_clr_wo_ready = _GEN_21[4:0];
+ wire _T_755 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
+ wire [4:0] a_set = _GEN_16[4:0];
+ wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [4:0] d_clr = _GEN_22[4:0];
+ wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [19:0] a_opcodes_set = _GEN_19[19:0];
+ wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [19:0] d_opcodes_clr = _GEN_23[19:0];
+ wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [19:0] a_sizes_set = _GEN_20[19:0];
+ wire [19:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [19:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_764 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [4:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [19:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg [2:0] d_first_counter_2; // @[Edges.scala 228:27]
+ wire [2:0] d_first_counter1_2 = d_first_counter_2 - 3'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala 230:25]
+ wire [19:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [19:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [19:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[19:1]}; // @[Monitor.scala 747:146]
+ wire _T_790 = io_in_d_valid & d_first_2 & _T_495; // @[Monitor.scala 779:71]
+ wire [7:0] _GEN_67 = _d_first_T & d_first_2 & _T_495 ? _d_clr_wo_ready_T : 8'h0; // @[Monitor.scala 783:90 784:21]
+ wire [78:0] _GEN_68 = _d_first_T & d_first_2 & _T_495 ? _d_opcodes_clr_T_5 : 79'h0; // @[Monitor.scala 783:90 785:21]
+ wire [4:0] _T_798 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_808 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [4:0] d_clr_1 = _GEN_67[4:0];
+ wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [4:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [19:0] d_opcodes_clr_1 = _GEN_68[19:0];
+ wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [19:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_833 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter <= a_first_beats1_decode;
+ end else begin
+ a_first_counter <= 3'h0;
+ end
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter <= d_first_beats1_decode;
+ end else begin
+ d_first_counter <= 3'h0;
+ end
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
+ end
+ if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
+ denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 5'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 20'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 20'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_a_first_T) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ a_first_counter_1 <= a_first_beats1_decode;
+ end else begin
+ a_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_1 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_1 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 5'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 20'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 3'h0; // @[Edges.scala 228:27]
+ end else if (_d_first_T) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
+ d_first_counter_2 <= d_first_beats1_decode;
+ end else begin
+ d_first_counter_2 <= 3'h0;
+ end
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (_d_first_T) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_104 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_104) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_109 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_109) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_113 & (io_in_a_valid & _T_42 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_42 & ~reset & ~_T_113) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_104 & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_T_104) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_109 & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_T_109) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_113 & (io_in_a_valid & _T_117 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_117 & ~reset & ~_T_113) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_227 & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~_T_227) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_238 & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~_T_238) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_113 & (io_in_a_valid & _T_196 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_196 & ~reset & ~_T_113) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_282 & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~_T_282) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_238 & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~_T_238) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_250 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_250 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_282 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_282) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_238 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_238) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_348 & (io_in_a_valid & _T_300 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_300 & ~reset & ~_T_348) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_352 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_352 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_389 & (io_in_a_valid & _T_352 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset & ~_T_389) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_352 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_352 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_434 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_434) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_397 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_397 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~source_ok) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_479 & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~_T_479) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_242 & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~_T_242) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_113 & (io_in_a_valid & _T_442 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_442 & ~reset & ~_T_113) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_491 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_491) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_507 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_507) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_526 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_526) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_530 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_530) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_507 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_507) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_515 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_515 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_499 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_499) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_526 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_526) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_530 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_530) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_563 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_563) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_543 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_543 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_572 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_572 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_d_valid & _T_572 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_572 & _T_2 & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_507 & (io_in_d_valid & _T_572 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_572 & _T_2 & ~_T_507) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_572 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_572 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_589 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_589 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_d_valid & _T_589 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_589 & _T_2 & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_563 & (io_in_d_valid & _T_589 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_589 & _T_2 & ~_T_563) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_589 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_589 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~source_ok_1 & (io_in_d_valid & _T_607 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_607 & _T_2 & ~source_ok_1) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_503 & (io_in_d_valid & _T_607 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_607 & _T_2 & ~_T_503) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_507 & (io_in_d_valid & _T_607 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_607 & _T_2 & ~_T_507) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_511 & (io_in_d_valid & _T_607 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_607 & _T_2 & ~_T_511) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck is denied (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_646) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_650 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_650) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_637 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_637 & ~reset & ~_T_654) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_662 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_662) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_666 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_666) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_670 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_670) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_674 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_674) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_678 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_678) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_682 & (_T_661 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_661 & _T_2 & ~_T_682) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_695 & (_T_691 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_691 & ~reset & ~_T_695) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_714 & (_T_702 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & _T_2 & ~_T_714) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_720 & (_T_702 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & same_cycle_resp & _T_2 & ~_T_720) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_724 & (_T_702 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & same_cycle_resp & _T_2 & ~_T_724) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_732 & (_T_702 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & ~same_cycle_resp & _T_2 & ~_T_732) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_736 & (_T_702 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_702 & ~same_cycle_resp & _T_2 & ~_T_736) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_748 & (_T_746 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_746 & _T_2 & ~_T_748) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_755 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_2 & ~_T_755) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_764 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_764) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_798[0] & (_T_790 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_790 & _T_2 & ~_T_798[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_808 & (_T_790 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_790 & _T_2 & ~_T_808) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_833 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_833) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:44)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[2:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[2:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ param_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ size_1 = _RAND_9[2:0];
+ _RAND_10 = {1{`RANDOM}};
+ source_1 = _RAND_10[2:0];
+ _RAND_11 = {1{`RANDOM}};
+ sink = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ denied = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ inflight = _RAND_13[4:0];
+ _RAND_14 = {1{`RANDOM}};
+ inflight_opcodes = _RAND_14[19:0];
+ _RAND_15 = {1{`RANDOM}};
+ inflight_sizes = _RAND_15[19:0];
+ _RAND_16 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_16[2:0];
+ _RAND_17 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_17[2:0];
+ _RAND_18 = {1{`RANDOM}};
+ watchdog = _RAND_18[31:0];
+ _RAND_19 = {1{`RANDOM}};
+ inflight_1 = _RAND_19[4:0];
+ _RAND_20 = {1{`RANDOM}};
+ inflight_sizes_1 = _RAND_20[19:0];
+ _RAND_21 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_21[2:0];
+ _RAND_22 = {1{`RANDOM}};
+ watchdog_1 = _RAND_22[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module Queue_24(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [2:0] io_enq_bits_opcode,
+ input [2:0] io_enq_bits_param,
+ input [2:0] io_enq_bits_size,
+ input [2:0] io_enq_bits_source,
+ input [28:0] io_enq_bits_address,
+ input [7:0] io_enq_bits_mask,
+ input [63:0] io_enq_bits_data,
+ input io_enq_bits_corrupt,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [2:0] io_deq_bits_opcode,
+ output [2:0] io_deq_bits_param,
+ output [2:0] io_deq_bits_size,
+ output [2:0] io_deq_bits_source,
+ output [28:0] io_deq_bits_address,
+ output [7:0] io_deq_bits_mask,
+ output [63:0] io_deq_bits_data,
+ output io_deq_bits_corrupt
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [63:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+ reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_param_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_size_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_source_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [28:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [28:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [28:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_address_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [63:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [63:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_data_MPORT_en; // @[Decoupled.scala 259:95]
+ reg ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
+ reg value; // @[Counter.scala 62:40]
+ reg value_1; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = value == value_1; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
+ assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_opcode_MPORT_data = io_enq_bits_opcode;
+ assign ram_opcode_MPORT_addr = value;
+ assign ram_opcode_MPORT_mask = 1'h1;
+ assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_param_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_param_io_deq_bits_MPORT_addr = value_1;
+ assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_param_MPORT_data = io_enq_bits_param;
+ assign ram_param_MPORT_addr = value;
+ assign ram_param_MPORT_mask = 1'h1;
+ assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_size_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_size_io_deq_bits_MPORT_addr = value_1;
+ assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_size_MPORT_data = io_enq_bits_size;
+ assign ram_size_MPORT_addr = value;
+ assign ram_size_MPORT_mask = 1'h1;
+ assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_source_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_source_io_deq_bits_MPORT_addr = value_1;
+ assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_source_MPORT_data = io_enq_bits_source;
+ assign ram_source_MPORT_addr = value;
+ assign ram_source_MPORT_mask = 1'h1;
+ assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_address_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_address_io_deq_bits_MPORT_addr = value_1;
+ assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_address_MPORT_data = io_enq_bits_address;
+ assign ram_address_MPORT_addr = value;
+ assign ram_address_MPORT_mask = 1'h1;
+ assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_mask_io_deq_bits_MPORT_addr = value_1;
+ assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_mask_MPORT_data = io_enq_bits_mask;
+ assign ram_mask_MPORT_addr = value;
+ assign ram_mask_MPORT_mask = 1'h1;
+ assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_data_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_data_io_deq_bits_MPORT_addr = value_1;
+ assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_data_MPORT_data = io_enq_bits_data;
+ assign ram_data_MPORT_addr = value;
+ assign ram_data_MPORT_mask = 1'h1;
+ assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
+ assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
+ assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
+ assign ram_corrupt_MPORT_addr = value;
+ assign ram_corrupt_MPORT_mask = 1'h1;
+ assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ always @(posedge clock) begin
+ if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
+ ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
+ ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
+ ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
+ ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
+ ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
+ ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
+ ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
+ ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ value <= value + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ value_1 <= 1'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_opcode[initvar] = _RAND_0[2:0];
+ _RAND_1 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_param[initvar] = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_size[initvar] = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_source[initvar] = _RAND_3[2:0];
+ _RAND_4 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_address[initvar] = _RAND_4[28:0];
+ _RAND_5 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_mask[initvar] = _RAND_5[7:0];
+ _RAND_6 = {2{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_data[initvar] = _RAND_6[63:0];
+ _RAND_7 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 2; initvar = initvar+1)
+ ram_corrupt[initvar] = _RAND_7[0:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_8 = {1{`RANDOM}};
+ value = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ value_1 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ maybe_full = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLBuffer_19(
+ input clock,
+ input reset,
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [2:0] auto_in_a_bits_size,
+ input [2:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_param,
+ output [2:0] auto_in_d_bits_size,
+ output [2:0] auto_in_d_bits_source,
+ output auto_in_d_bits_sink,
+ output auto_in_d_bits_denied,
+ output [63:0] auto_in_d_bits_data,
+ output auto_in_d_bits_corrupt,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [2:0] auto_out_a_bits_size,
+ output [2:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_param,
+ input [2:0] auto_out_d_bits_size,
+ input [2:0] auto_out_d_bits_source,
+ input auto_out_d_bits_sink,
+ input auto_out_d_bits_denied,
+ input [63:0] auto_out_d_bits_data,
+ input auto_out_d_bits_corrupt
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
+ wire bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire [28:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire [28:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
+ wire [7:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
+ wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
+ wire [2:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
+ wire [63:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
+ wire bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
+ TLMonitor_54 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_param(monitor_io_in_d_bits_param),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source),
+ .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
+ .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
+ .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
+ );
+ Queue_24 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleOut_0_a_q_clock),
+ .reset(bundleOut_0_a_q_reset),
+ .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
+ .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
+ .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
+ .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
+ .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
+ .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
+ .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
+ .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
+ .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
+ );
+ Queue_1 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
+ .clock(bundleIn_0_d_q_clock),
+ .reset(bundleIn_0_d_q_reset),
+ .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
+ .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
+ .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
+ .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
+ .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
+ .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
+ .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
+ .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
+ .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
+ .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
+ .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
+ .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
+ .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
+ .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
+ .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
+ .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
+ .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
+ .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
+ .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
+ .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
+ );
+ assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
+ assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
+ assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
+ assign bundleOut_0_a_q_clock = clock;
+ assign bundleOut_0_a_q_reset = reset;
+ assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_clock = clock;
+ assign bundleIn_0_d_q_reset = reset;
+ assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockSinkDomain_2(
+ input auto_serdesser_client_out_a_ready,
+ output auto_serdesser_client_out_a_valid,
+ output [2:0] auto_serdesser_client_out_a_bits_opcode,
+ output [2:0] auto_serdesser_client_out_a_bits_param,
+ output [3:0] auto_serdesser_client_out_a_bits_size,
+ output auto_serdesser_client_out_a_bits_source,
+ output [31:0] auto_serdesser_client_out_a_bits_address,
+ output [7:0] auto_serdesser_client_out_a_bits_mask,
+ output [63:0] auto_serdesser_client_out_a_bits_data,
+ output auto_serdesser_client_out_a_bits_corrupt,
+ output auto_serdesser_client_out_d_ready,
+ input auto_serdesser_client_out_d_valid,
+ input [2:0] auto_serdesser_client_out_d_bits_opcode,
+ input [1:0] auto_serdesser_client_out_d_bits_param,
+ input [3:0] auto_serdesser_client_out_d_bits_size,
+ input auto_serdesser_client_out_d_bits_source,
+ input auto_serdesser_client_out_d_bits_sink,
+ input auto_serdesser_client_out_d_bits_denied,
+ input [63:0] auto_serdesser_client_out_d_bits_data,
+ input auto_serdesser_client_out_d_bits_corrupt,
+ output auto_tlserial_manager_crossing_in_a_ready,
+ input auto_tlserial_manager_crossing_in_a_valid,
+ input [2:0] auto_tlserial_manager_crossing_in_a_bits_opcode,
+ input [2:0] auto_tlserial_manager_crossing_in_a_bits_param,
+ input [2:0] auto_tlserial_manager_crossing_in_a_bits_size,
+ input [2:0] auto_tlserial_manager_crossing_in_a_bits_source,
+ input [28:0] auto_tlserial_manager_crossing_in_a_bits_address,
+ input [7:0] auto_tlserial_manager_crossing_in_a_bits_mask,
+ input [63:0] auto_tlserial_manager_crossing_in_a_bits_data,
+ input auto_tlserial_manager_crossing_in_a_bits_corrupt,
+ input auto_tlserial_manager_crossing_in_d_ready,
+ output auto_tlserial_manager_crossing_in_d_valid,
+ output [2:0] auto_tlserial_manager_crossing_in_d_bits_opcode,
+ output [1:0] auto_tlserial_manager_crossing_in_d_bits_param,
+ output [2:0] auto_tlserial_manager_crossing_in_d_bits_size,
+ output [2:0] auto_tlserial_manager_crossing_in_d_bits_source,
+ output auto_tlserial_manager_crossing_in_d_bits_sink,
+ output auto_tlserial_manager_crossing_in_d_bits_denied,
+ output [63:0] auto_tlserial_manager_crossing_in_d_bits_data,
+ output auto_tlserial_manager_crossing_in_d_bits_corrupt,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset,
+ output serial_tl_in_ready,
+ input serial_tl_in_valid,
+ input [31:0] serial_tl_in_bits,
+ input serial_tl_out_ready,
+ output serial_tl_out_valid,
+ output [31:0] serial_tl_out_bits,
+ output clock
+);
+ wire serdesser_clock; // @[SerialAdapter.scala 376:40]
+ wire serdesser_reset; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_manager_in_a_ready; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_manager_in_a_valid; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_manager_in_a_bits_opcode; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_manager_in_a_bits_param; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_manager_in_a_bits_size; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_manager_in_a_bits_source; // @[SerialAdapter.scala 376:40]
+ wire [28:0] serdesser_auto_manager_in_a_bits_address; // @[SerialAdapter.scala 376:40]
+ wire [7:0] serdesser_auto_manager_in_a_bits_mask; // @[SerialAdapter.scala 376:40]
+ wire [63:0] serdesser_auto_manager_in_a_bits_data; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_manager_in_a_bits_corrupt; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_manager_in_d_ready; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_manager_in_d_valid; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_manager_in_d_bits_opcode; // @[SerialAdapter.scala 376:40]
+ wire [1:0] serdesser_auto_manager_in_d_bits_param; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_manager_in_d_bits_size; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_manager_in_d_bits_source; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_manager_in_d_bits_sink; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_manager_in_d_bits_denied; // @[SerialAdapter.scala 376:40]
+ wire [63:0] serdesser_auto_manager_in_d_bits_data; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_manager_in_d_bits_corrupt; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_a_ready; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_a_valid; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_client_out_a_bits_opcode; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_client_out_a_bits_param; // @[SerialAdapter.scala 376:40]
+ wire [3:0] serdesser_auto_client_out_a_bits_size; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_a_bits_source; // @[SerialAdapter.scala 376:40]
+ wire [31:0] serdesser_auto_client_out_a_bits_address; // @[SerialAdapter.scala 376:40]
+ wire [7:0] serdesser_auto_client_out_a_bits_mask; // @[SerialAdapter.scala 376:40]
+ wire [63:0] serdesser_auto_client_out_a_bits_data; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_a_bits_corrupt; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_d_ready; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_d_valid; // @[SerialAdapter.scala 376:40]
+ wire [2:0] serdesser_auto_client_out_d_bits_opcode; // @[SerialAdapter.scala 376:40]
+ wire [1:0] serdesser_auto_client_out_d_bits_param; // @[SerialAdapter.scala 376:40]
+ wire [3:0] serdesser_auto_client_out_d_bits_size; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_d_bits_source; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_d_bits_sink; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_d_bits_denied; // @[SerialAdapter.scala 376:40]
+ wire [63:0] serdesser_auto_client_out_d_bits_data; // @[SerialAdapter.scala 376:40]
+ wire serdesser_auto_client_out_d_bits_corrupt; // @[SerialAdapter.scala 376:40]
+ wire serdesser_io_ser_in_ready; // @[SerialAdapter.scala 376:40]
+ wire serdesser_io_ser_in_valid; // @[SerialAdapter.scala 376:40]
+ wire [31:0] serdesser_io_ser_in_bits; // @[SerialAdapter.scala 376:40]
+ wire serdesser_io_ser_out_ready; // @[SerialAdapter.scala 376:40]
+ wire serdesser_io_ser_out_valid; // @[SerialAdapter.scala 376:40]
+ wire [31:0] serdesser_io_ser_out_bits; // @[SerialAdapter.scala 376:40]
+ wire buffer_clock; // @[Buffer.scala 68:28]
+ wire buffer_reset; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
+ TLSerdesser serdesser ( // @[SerialAdapter.scala 376:40]
+ .clock(serdesser_clock),
+ .reset(serdesser_reset),
+ .auto_manager_in_a_ready(serdesser_auto_manager_in_a_ready),
+ .auto_manager_in_a_valid(serdesser_auto_manager_in_a_valid),
+ .auto_manager_in_a_bits_opcode(serdesser_auto_manager_in_a_bits_opcode),
+ .auto_manager_in_a_bits_param(serdesser_auto_manager_in_a_bits_param),
+ .auto_manager_in_a_bits_size(serdesser_auto_manager_in_a_bits_size),
+ .auto_manager_in_a_bits_source(serdesser_auto_manager_in_a_bits_source),
+ .auto_manager_in_a_bits_address(serdesser_auto_manager_in_a_bits_address),
+ .auto_manager_in_a_bits_mask(serdesser_auto_manager_in_a_bits_mask),
+ .auto_manager_in_a_bits_data(serdesser_auto_manager_in_a_bits_data),
+ .auto_manager_in_a_bits_corrupt(serdesser_auto_manager_in_a_bits_corrupt),
+ .auto_manager_in_d_ready(serdesser_auto_manager_in_d_ready),
+ .auto_manager_in_d_valid(serdesser_auto_manager_in_d_valid),
+ .auto_manager_in_d_bits_opcode(serdesser_auto_manager_in_d_bits_opcode),
+ .auto_manager_in_d_bits_param(serdesser_auto_manager_in_d_bits_param),
+ .auto_manager_in_d_bits_size(serdesser_auto_manager_in_d_bits_size),
+ .auto_manager_in_d_bits_source(serdesser_auto_manager_in_d_bits_source),
+ .auto_manager_in_d_bits_sink(serdesser_auto_manager_in_d_bits_sink),
+ .auto_manager_in_d_bits_denied(serdesser_auto_manager_in_d_bits_denied),
+ .auto_manager_in_d_bits_data(serdesser_auto_manager_in_d_bits_data),
+ .auto_manager_in_d_bits_corrupt(serdesser_auto_manager_in_d_bits_corrupt),
+ .auto_client_out_a_ready(serdesser_auto_client_out_a_ready),
+ .auto_client_out_a_valid(serdesser_auto_client_out_a_valid),
+ .auto_client_out_a_bits_opcode(serdesser_auto_client_out_a_bits_opcode),
+ .auto_client_out_a_bits_param(serdesser_auto_client_out_a_bits_param),
+ .auto_client_out_a_bits_size(serdesser_auto_client_out_a_bits_size),
+ .auto_client_out_a_bits_source(serdesser_auto_client_out_a_bits_source),
+ .auto_client_out_a_bits_address(serdesser_auto_client_out_a_bits_address),
+ .auto_client_out_a_bits_mask(serdesser_auto_client_out_a_bits_mask),
+ .auto_client_out_a_bits_data(serdesser_auto_client_out_a_bits_data),
+ .auto_client_out_a_bits_corrupt(serdesser_auto_client_out_a_bits_corrupt),
+ .auto_client_out_d_ready(serdesser_auto_client_out_d_ready),
+ .auto_client_out_d_valid(serdesser_auto_client_out_d_valid),
+ .auto_client_out_d_bits_opcode(serdesser_auto_client_out_d_bits_opcode),
+ .auto_client_out_d_bits_param(serdesser_auto_client_out_d_bits_param),
+ .auto_client_out_d_bits_size(serdesser_auto_client_out_d_bits_size),
+ .auto_client_out_d_bits_source(serdesser_auto_client_out_d_bits_source),
+ .auto_client_out_d_bits_sink(serdesser_auto_client_out_d_bits_sink),
+ .auto_client_out_d_bits_denied(serdesser_auto_client_out_d_bits_denied),
+ .auto_client_out_d_bits_data(serdesser_auto_client_out_d_bits_data),
+ .auto_client_out_d_bits_corrupt(serdesser_auto_client_out_d_bits_corrupt),
+ .io_ser_in_ready(serdesser_io_ser_in_ready),
+ .io_ser_in_valid(serdesser_io_ser_in_valid),
+ .io_ser_in_bits(serdesser_io_ser_in_bits),
+ .io_ser_out_ready(serdesser_io_ser_out_ready),
+ .io_ser_out_valid(serdesser_io_ser_out_valid),
+ .io_ser_out_bits(serdesser_io_ser_out_bits)
+ );
+ TLBuffer_19 buffer ( // @[Buffer.scala 68:28]
+ .clock(buffer_clock),
+ .reset(buffer_reset),
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
+ .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
+ .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
+ .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
+ );
+ assign auto_serdesser_client_out_a_valid = serdesser_auto_client_out_a_valid; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_a_bits_opcode = serdesser_auto_client_out_a_bits_opcode; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_a_bits_param = serdesser_auto_client_out_a_bits_param; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_a_bits_size = serdesser_auto_client_out_a_bits_size; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_a_bits_source = serdesser_auto_client_out_a_bits_source; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_a_bits_address = serdesser_auto_client_out_a_bits_address; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_a_bits_mask = serdesser_auto_client_out_a_bits_mask; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_a_bits_data = serdesser_auto_client_out_a_bits_data; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_a_bits_corrupt = serdesser_auto_client_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign auto_serdesser_client_out_d_ready = serdesser_auto_client_out_d_ready; // @[LazyModule.scala 311:12]
+ assign auto_tlserial_manager_crossing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_bits_param = buffer_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_tlserial_manager_crossing_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign serial_tl_in_ready = serdesser_io_ser_in_ready; // @[SerialAdapter.scala 397:34]
+ assign serial_tl_out_valid = serdesser_io_ser_out_valid; // @[SerialAdapter.scala 396:20]
+ assign serial_tl_out_bits = serdesser_io_ser_out_bits; // @[SerialAdapter.scala 396:20]
+ assign clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign serdesser_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign serdesser_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign serdesser_auto_manager_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_manager_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
+ assign serdesser_auto_client_out_a_ready = auto_serdesser_client_out_a_ready; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_valid = auto_serdesser_client_out_d_valid; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_bits_opcode = auto_serdesser_client_out_d_bits_opcode; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_bits_param = auto_serdesser_client_out_d_bits_param; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_bits_size = auto_serdesser_client_out_d_bits_size; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_bits_source = auto_serdesser_client_out_d_bits_source; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_bits_sink = auto_serdesser_client_out_d_bits_sink; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_bits_denied = auto_serdesser_client_out_d_bits_denied; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_bits_data = auto_serdesser_client_out_d_bits_data; // @[LazyModule.scala 311:12]
+ assign serdesser_auto_client_out_d_bits_corrupt = auto_serdesser_client_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
+ assign serdesser_io_ser_in_valid = serial_tl_in_valid; // @[SerialAdapter.scala 397:34]
+ assign serdesser_io_ser_in_bits = serial_tl_in_bits; // @[SerialAdapter.scala 397:34]
+ assign serdesser_io_ser_out_ready = serial_tl_out_ready; // @[SerialAdapter.scala 396:20]
+ assign buffer_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_valid = auto_tlserial_manager_crossing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_tlserial_manager_crossing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_tlserial_manager_crossing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_tlserial_manager_crossing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_tlserial_manager_crossing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_tlserial_manager_crossing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_tlserial_manager_crossing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_data = auto_tlserial_manager_crossing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_tlserial_manager_crossing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_tlserial_manager_crossing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = serdesser_auto_manager_in_a_ready; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = serdesser_auto_manager_in_d_valid; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = serdesser_auto_manager_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_param = serdesser_auto_manager_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_size = serdesser_auto_manager_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = serdesser_auto_manager_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_sink = serdesser_auto_manager_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_denied = serdesser_auto_manager_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = serdesser_auto_manager_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_corrupt = serdesser_auto_manager_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+endmodule
+module TLBuffer_20(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input [1:0] auto_in_a_bits_size,
+ input [6:0] auto_in_a_bits_source,
+ input [28:0] auto_in_a_bits_address,
+ input [7:0] auto_in_a_bits_mask,
+ input [63:0] auto_in_a_bits_data,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output [2:0] auto_in_d_bits_opcode,
+ output [1:0] auto_in_d_bits_size,
+ output [6:0] auto_in_d_bits_source,
+ output [63:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output [1:0] auto_out_a_bits_size,
+ output [6:0] auto_out_a_bits_source,
+ output [28:0] auto_out_a_bits_address,
+ output [7:0] auto_out_a_bits_mask,
+ output [63:0] auto_out_a_bits_data,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input [2:0] auto_out_d_bits_opcode,
+ input [1:0] auto_out_d_bits_size,
+ input [6:0] auto_out_d_bits_source,
+ input [63:0] auto_out_d_bits_data
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_55(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{26'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10010000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module UARTTx(
+ input clock,
+ input reset,
+ input io_en,
+ output io_in_ready,
+ input io_in_valid,
+ input [7:0] io_in_bits,
+ output io_out,
+ input [15:0] io_div,
+ input io_nstop
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ reg [15:0] prescaler; // @[UARTTx.scala 23:22]
+ wire pulse = prescaler == 16'h0; // @[UARTTx.scala 24:26]
+ reg [3:0] counter; // @[UARTTx.scala 27:20]
+ reg [8:0] shifter; // @[UARTTx.scala 28:20]
+ reg out; // @[UARTTx.scala 29:16]
+ wire plusarg_tx = |plusarg_reader_out; // @[UARTTx.scala 32:90]
+ wire busy = counter != 4'h0; // @[UARTTx.scala 34:23]
+ wire _T = io_in_ready & io_in_valid; // @[Decoupled.scala 50:35]
+ wire [9:0] _shifter_T_1 = {1'h1,io_in_bits,1'h0}; // @[Cat.scala 31:58]
+ wire _counter_T = ~io_nstop; // @[UARTTx.scala 57:19]
+ wire [3:0] _counter_T_2 = _counter_T ? 4'ha : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _counter_T_3 = io_nstop ? 4'hb : 4'h0; // @[Mux.scala 27:73]
+ wire [3:0] _counter_T_4 = _counter_T_2 | _counter_T_3; // @[Mux.scala 27:73]
+ wire [3:0] _counter_T_6 = _counter_T_4 - 4'h0; // @[UARTTx.scala 57:53]
+ wire [9:0] _GEN_0 = _T & plusarg_tx ? _shifter_T_1 : {{1'd0}, shifter}; // @[UARTTx.scala 40:37 55:15 28:20]
+ wire [15:0] _prescaler_T_2 = prescaler - 16'h1; // @[UARTTx.scala 61:78]
+ wire [3:0] _counter_T_8 = counter - 4'h1; // @[UARTTx.scala 64:24]
+ wire [8:0] _shifter_T_3 = {1'h1,shifter[8:1]}; // @[Cat.scala 31:58]
+ wire [9:0] _GEN_4 = pulse & busy ? {{1'd0}, _shifter_T_3} : _GEN_0; // @[UARTTx.scala 63:24 65:13]
+ wire _GEN_5 = pulse & busy ? shifter[0] : out; // @[UARTTx.scala 29:16 63:24 66:9]
+ plusarg_reader #(.FORMAT("uart_tx=%d"), .DEFAULT(1), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ assign io_in_ready = io_en & ~busy; // @[UARTTx.scala 35:24]
+ assign io_out = out; // @[UARTTx.scala 30:10]
+ always @(posedge clock) begin
+ if (reset) begin // @[UARTTx.scala 23:22]
+ prescaler <= 16'h0; // @[UARTTx.scala 23:22]
+ end else if (busy) begin // @[UARTTx.scala 60:15]
+ if (pulse) begin // @[UARTTx.scala 61:21]
+ prescaler <= io_div;
+ end else begin
+ prescaler <= _prescaler_T_2;
+ end
+ end
+ if (reset) begin // @[UARTTx.scala 27:20]
+ counter <= 4'h0; // @[UARTTx.scala 27:20]
+ end else if (pulse & busy) begin // @[UARTTx.scala 63:24]
+ counter <= _counter_T_8; // @[UARTTx.scala 64:13]
+ end else if (_T & plusarg_tx) begin // @[UARTTx.scala 40:37]
+ counter <= _counter_T_6; // @[UARTTx.scala 56:15]
+ end
+ shifter <= _GEN_4[8:0];
+ out <= reset | _GEN_5; // @[UARTTx.scala 29:{16,16}]
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T & ~reset) begin
+ $fwrite(32'h80000002,"UART TX (%x): %c\n",io_in_bits,io_in_bits); // @[UARTTx.scala 38:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ prescaler = _RAND_0[15:0];
+ _RAND_1 = {1{`RANDOM}};
+ counter = _RAND_1[3:0];
+ _RAND_2 = {1{`RANDOM}};
+ shifter = _RAND_2[8:0];
+ _RAND_3 = {1{`RANDOM}};
+ out = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module QueueCompatibility(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [7:0] io_enq_bits,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [7:0] io_deq_bits,
+ output [8:0] io_count
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ reg [7:0] ram [0:255]; // @[Decoupled.scala 259:95]
+ wire ram_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [7:0] enq_ptr_value; // @[Counter.scala 62:40]
+ reg [7:0] deq_ptr_value; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ wire [7:0] _value_T_1 = enq_ptr_value + 8'h1; // @[Counter.scala 78:24]
+ wire [7:0] _value_T_3 = deq_ptr_value + 8'h1; // @[Counter.scala 78:24]
+ wire [7:0] ptr_diff = enq_ptr_value - deq_ptr_value; // @[Decoupled.scala 312:32]
+ wire [8:0] _io_count_T_1 = maybe_full & ptr_match ? 9'h100 : 9'h0; // @[Decoupled.scala 315:20]
+ wire [8:0] _GEN_11 = {{1'd0}, ptr_diff}; // @[Decoupled.scala 315:62]
+ assign ram_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_io_deq_bits_MPORT_addr = deq_ptr_value;
+ assign ram_io_deq_bits_MPORT_data = ram[ram_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_MPORT_data = io_enq_bits;
+ assign ram_MPORT_addr = enq_ptr_value;
+ assign ram_MPORT_mask = 1'h1;
+ assign ram_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits = ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_count = _io_count_T_1 | _GEN_11; // @[Decoupled.scala 315:62]
+ always @(posedge clock) begin
+ if (ram_MPORT_en & ram_MPORT_mask) begin
+ ram[ram_MPORT_addr] <= ram_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ enq_ptr_value <= 8'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ enq_ptr_value <= _value_T_1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ deq_ptr_value <= 8'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ deq_ptr_value <= _value_T_3; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 256; initvar = initvar+1)
+ ram[initvar] = _RAND_0[7:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_1 = {1{`RANDOM}};
+ enq_ptr_value = _RAND_1[7:0];
+ _RAND_2 = {1{`RANDOM}};
+ deq_ptr_value = _RAND_2[7:0];
+ _RAND_3 = {1{`RANDOM}};
+ maybe_full = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module UARTRx(
+ input clock,
+ input reset,
+ input io_en,
+ input io_in,
+ output io_out_valid,
+ output [7:0] io_out_bits,
+ input [15:0] io_div
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ reg [1:0] debounce; // @[UARTRx.scala 24:21]
+ wire debounce_max = debounce == 2'h3; // @[UARTRx.scala 25:32]
+ wire debounce_min = debounce == 2'h0; // @[UARTRx.scala 26:32]
+ reg [12:0] prescaler; // @[UARTRx.scala 28:22]
+ wire pulse = prescaler == 13'h0; // @[UARTRx.scala 30:26]
+ reg [3:0] data_count; // @[UARTRx.scala 34:23]
+ wire data_last = data_count == 4'h0; // @[UARTRx.scala 35:31]
+ reg [3:0] sample_count; // @[UARTRx.scala 37:25]
+ wire sample_mid = sample_count == 4'h7; // @[UARTRx.scala 38:34]
+ wire [7:0] _countdown_T = {data_count,sample_count}; // @[Cat.scala 31:58]
+ wire [7:0] countdown = _countdown_T - 8'h1; // @[UARTRx.scala 40:49]
+ wire [3:0] remainder = io_div[3:0]; // @[UARTRx.scala 45:25]
+ wire extend = sample_count < remainder; // @[UARTRx.scala 46:30]
+ reg state; // @[UARTRx.scala 61:18]
+ wire _T_5 = ~io_in; // @[UARTRx.scala 68:13]
+ wire _GEN_8 = ~io_in & debounce_max; // @[UARTRx.scala 68:21]
+ wire start = ~state & _GEN_8; // @[UARTRx.scala 63:18]
+ wire restore = start | pulse; // @[UARTRx.scala 47:23]
+ wire [12:0] prescaler_in = restore ? {{1'd0}, io_div[15:4]} : prescaler; // @[UARTRx.scala 48:25]
+ wire _prescaler_next_T_1 = restore & extend ? 1'h0 : 1'h1; // @[UARTRx.scala 49:42]
+ wire [12:0] _GEN_41 = {{12'd0}, _prescaler_next_T_1}; // @[UARTRx.scala 49:37]
+ wire [12:0] prescaler_next = prescaler_in - _GEN_41; // @[UARTRx.scala 49:37]
+ reg [2:0] sample; // @[UARTRx.scala 51:19]
+ wire _voter_T_3 = sample[0] & sample[1]; // @[Misc.scala 166:48]
+ wire _voter_T_4 = sample[0] & sample[2]; // @[Misc.scala 166:48]
+ wire _voter_T_6 = sample[1] & sample[2]; // @[Misc.scala 166:48]
+ wire voter = _voter_T_3 | _voter_T_4 | _voter_T_6; // @[Misc.scala 167:22]
+ reg [7:0] shifter; // @[UARTRx.scala 53:20]
+ reg valid; // @[UARTRx.scala 55:18]
+ wire [1:0] _debounce_T_1 = debounce - 2'h1; // @[UARTRx.scala 66:30]
+ wire [1:0] _GEN_0 = ~_T_5 & ~debounce_min ? _debounce_T_1 : debounce; // @[UARTRx.scala 65:41 66:18 24:21]
+ wire [1:0] _debounce_T_3 = debounce + 2'h1; // @[UARTRx.scala 69:30]
+ wire [3:0] _data_count_T_3 = 4'h9 - 4'h0; // @[UARTRx.scala 74:94]
+ wire _GEN_1 = debounce_max | state; // @[UARTRx.scala 70:29 71:17 61:18]
+ wire [3:0] _sample_T = {sample,io_in}; // @[Cat.scala 31:58]
+ wire [7:0] _shifter_T_1 = {voter,shifter[7:1]}; // @[Cat.scala 31:58]
+ wire _GEN_12 = data_last ? 1'h0 : state; // @[UARTRx.scala 102:30 103:21 61:18]
+ wire [7:0] _GEN_14 = data_last ? shifter : _shifter_T_1; // @[UARTRx.scala 102:30 53:20 106:23]
+ wire _GEN_15 = sample_mid ? _GEN_12 : state; // @[UARTRx.scala 61:18 87:27]
+ wire _GEN_16 = sample_mid & data_last; // @[UARTRx.scala 87:27 56:9]
+ wire [3:0] _GEN_18 = pulse ? _sample_T : {{1'd0}, sample}; // @[UARTRx.scala 82:20 83:16 51:19]
+ wire _GEN_22 = pulse & _GEN_16; // @[UARTRx.scala 82:20 56:9]
+ wire [3:0] _GEN_25 = state ? _GEN_18 : {{1'd0}, sample}; // @[UARTRx.scala 63:18 51:19]
+ wire [3:0] _GEN_37 = ~state ? {{1'd0}, sample} : _GEN_25; // @[UARTRx.scala 63:18 51:19]
+ assign io_out_valid = valid; // @[UARTRx.scala 57:16]
+ assign io_out_bits = shifter; // @[UARTRx.scala 58:15]
+ always @(posedge clock) begin
+ if (reset) begin // @[UARTRx.scala 24:21]
+ debounce <= 2'h0; // @[UARTRx.scala 24:21]
+ end else if (~io_en) begin // @[UARTRx.scala 114:17]
+ debounce <= 2'h0; // @[UARTRx.scala 115:14]
+ end else if (~state) begin // @[UARTRx.scala 63:18]
+ if (~io_in) begin // @[UARTRx.scala 68:21]
+ debounce <= _debounce_T_3; // @[UARTRx.scala 69:18]
+ end else begin
+ debounce <= _GEN_0;
+ end
+ end
+ if (~state) begin // @[UARTRx.scala 63:18]
+ if (~io_in) begin // @[UARTRx.scala 68:21]
+ if (debounce_max) begin // @[UARTRx.scala 70:29]
+ prescaler <= prescaler_next; // @[UARTRx.scala 73:21]
+ end
+ end
+ end else if (state) begin // @[UARTRx.scala 63:18]
+ prescaler <= prescaler_next; // @[UARTRx.scala 81:17]
+ end
+ if (~state) begin // @[UARTRx.scala 63:18]
+ if (~io_in) begin // @[UARTRx.scala 68:21]
+ if (debounce_max) begin // @[UARTRx.scala 70:29]
+ data_count <= _data_count_T_3; // @[UARTRx.scala 74:22]
+ end
+ end
+ end else if (state) begin // @[UARTRx.scala 63:18]
+ if (pulse) begin // @[UARTRx.scala 82:20]
+ data_count <= countdown[7:4]; // @[UARTRx.scala 84:20]
+ end
+ end
+ if (~state) begin // @[UARTRx.scala 63:18]
+ if (~io_in) begin // @[UARTRx.scala 68:21]
+ if (debounce_max) begin // @[UARTRx.scala 70:29]
+ sample_count <= 4'hf; // @[UARTRx.scala 75:24]
+ end
+ end
+ end else if (state) begin // @[UARTRx.scala 63:18]
+ if (pulse) begin // @[UARTRx.scala 82:20]
+ sample_count <= countdown[3:0]; // @[UARTRx.scala 85:22]
+ end
+ end
+ if (reset) begin // @[UARTRx.scala 61:18]
+ state <= 1'h0; // @[UARTRx.scala 61:18]
+ end else if (~state) begin // @[UARTRx.scala 63:18]
+ if (~io_in) begin // @[UARTRx.scala 68:21]
+ state <= _GEN_1;
+ end
+ end else if (state) begin // @[UARTRx.scala 63:18]
+ if (pulse) begin // @[UARTRx.scala 82:20]
+ state <= _GEN_15;
+ end
+ end
+ sample <= _GEN_37[2:0];
+ if (!(~state)) begin // @[UARTRx.scala 63:18]
+ if (state) begin // @[UARTRx.scala 63:18]
+ if (pulse) begin // @[UARTRx.scala 82:20]
+ if (sample_mid) begin // @[UARTRx.scala 87:27]
+ shifter <= _GEN_14;
+ end
+ end
+ end
+ end
+ if (reset) begin // @[UARTRx.scala 55:18]
+ valid <= 1'h0; // @[UARTRx.scala 55:18]
+ end else if (~state) begin // @[UARTRx.scala 63:18]
+ valid <= 1'h0; // @[UARTRx.scala 56:9]
+ end else begin
+ valid <= state & _GEN_22;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ debounce = _RAND_0[1:0];
+ _RAND_1 = {1{`RANDOM}};
+ prescaler = _RAND_1[12:0];
+ _RAND_2 = {1{`RANDOM}};
+ data_count = _RAND_2[3:0];
+ _RAND_3 = {1{`RANDOM}};
+ sample_count = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ state = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ sample = _RAND_5[2:0];
+ _RAND_6 = {1{`RANDOM}};
+ shifter = _RAND_6[7:0];
+ _RAND_7 = {1{`RANDOM}};
+ valid = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLUART(
+ input clock,
+ input reset,
+ output auto_int_xing_out_sync_0,
+ output auto_control_xing_in_a_ready,
+ input auto_control_xing_in_a_valid,
+ input [2:0] auto_control_xing_in_a_bits_opcode,
+ input [2:0] auto_control_xing_in_a_bits_param,
+ input [1:0] auto_control_xing_in_a_bits_size,
+ input [6:0] auto_control_xing_in_a_bits_source,
+ input [28:0] auto_control_xing_in_a_bits_address,
+ input [7:0] auto_control_xing_in_a_bits_mask,
+ input [63:0] auto_control_xing_in_a_bits_data,
+ input auto_control_xing_in_a_bits_corrupt,
+ input auto_control_xing_in_d_ready,
+ output auto_control_xing_in_d_valid,
+ output [2:0] auto_control_xing_in_d_bits_opcode,
+ output [1:0] auto_control_xing_in_d_bits_size,
+ output [6:0] auto_control_xing_in_d_bits_source,
+ output [63:0] auto_control_xing_in_d_bits_data,
+ output auto_io_out_txd,
+ input auto_io_out_rxd
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire intsource_clock; // @[Crossing.scala 26:31]
+ wire intsource_reset; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire txm_clock; // @[UART.scala 79:19]
+ wire txm_reset; // @[UART.scala 79:19]
+ wire txm_io_en; // @[UART.scala 79:19]
+ wire txm_io_in_ready; // @[UART.scala 79:19]
+ wire txm_io_in_valid; // @[UART.scala 79:19]
+ wire [7:0] txm_io_in_bits; // @[UART.scala 79:19]
+ wire txm_io_out; // @[UART.scala 79:19]
+ wire [15:0] txm_io_div; // @[UART.scala 79:19]
+ wire txm_io_nstop; // @[UART.scala 79:19]
+ wire txq_clock; // @[UART.scala 80:19]
+ wire txq_reset; // @[UART.scala 80:19]
+ wire txq_io_enq_ready; // @[UART.scala 80:19]
+ wire txq_io_enq_valid; // @[UART.scala 80:19]
+ wire [7:0] txq_io_enq_bits; // @[UART.scala 80:19]
+ wire txq_io_deq_ready; // @[UART.scala 80:19]
+ wire txq_io_deq_valid; // @[UART.scala 80:19]
+ wire [7:0] txq_io_deq_bits; // @[UART.scala 80:19]
+ wire [8:0] txq_io_count; // @[UART.scala 80:19]
+ wire rxm_clock; // @[UART.scala 82:19]
+ wire rxm_reset; // @[UART.scala 82:19]
+ wire rxm_io_en; // @[UART.scala 82:19]
+ wire rxm_io_in; // @[UART.scala 82:19]
+ wire rxm_io_out_valid; // @[UART.scala 82:19]
+ wire [7:0] rxm_io_out_bits; // @[UART.scala 82:19]
+ wire [15:0] rxm_io_div; // @[UART.scala 82:19]
+ wire rxq_clock; // @[UART.scala 83:19]
+ wire rxq_reset; // @[UART.scala 83:19]
+ wire rxq_io_enq_ready; // @[UART.scala 83:19]
+ wire rxq_io_enq_valid; // @[UART.scala 83:19]
+ wire [7:0] rxq_io_enq_bits; // @[UART.scala 83:19]
+ wire rxq_io_deq_ready; // @[UART.scala 83:19]
+ wire rxq_io_deq_valid; // @[UART.scala 83:19]
+ wire [7:0] rxq_io_deq_bits; // @[UART.scala 83:19]
+ wire [8:0] rxq_io_count; // @[UART.scala 83:19]
+ reg [15:0] div; // @[UART.scala 85:16]
+ reg txen; // @[UART.scala 91:17]
+ reg rxen; // @[UART.scala 92:17]
+ reg [8:0] txwm; // @[UART.scala 99:17]
+ reg [8:0] rxwm; // @[UART.scala 100:17]
+ reg nstop; // @[UART.scala 101:18]
+ reg ie_rxwm; // @[UART.scala 135:15]
+ reg ie_txwm; // @[UART.scala 135:15]
+ wire ip_txwm = txq_io_count < txwm; // @[UART.scala 138:28]
+ wire ip_rxwm = rxq_io_count > rxwm; // @[UART.scala 139:28]
+ wire _T = ~txq_io_enq_ready; // @[RegMapFIFO.scala 25:9]
+ wire _T_1 = ~rxq_io_deq_valid; // @[RegMapFIFO.scala 46:21]
+ wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [8:0] in_bits_index = bundleIn_0_a_bits_address[11:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire [8:0] out_findex = in_bits_index & 9'h1fc; // @[RegisterRouter.scala 83:24]
+ wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_13 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_15 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_17 = bundleIn_0_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_19 = bundleIn_0_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_21 = bundleIn_0_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_23 = bundleIn_0_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_frontMask = {_out_frontMask_T_23,_out_frontMask_T_21,_out_frontMask_T_19,_out_frontMask_T_17,
+ _out_frontMask_T_15,_out_frontMask_T_13,_out_frontMask_T_11,_out_frontMask_T_9}; // @[Cat.scala 31:58]
+ wire out_wimask = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
+ wire bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [1:0] out_oindex = {in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [3:0] _out_frontSel_T = 4'h1 << out_oindex; // @[OneHot.scala 57:35]
+ wire out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire [63:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire out_wimask_1 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1 = out_wivalid_0 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [1:0] out_prepend = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
+ wire out_wimask_2 = &out_frontMask[32]; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_1 = {{30'd0}, out_prepend}; // @[RegisterRouter.scala 83:24]
+ wire [33:0] out_prepend_2 = {ip_rxwm,ip_txwm,_out_prepend_T_1}; // @[Cat.scala 31:58]
+ wire out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_4 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_4 = out_wivalid_4 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_5 = out_wivalid_4 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [1:0] out_prepend_3 = {nstop,txen}; // @[Cat.scala 31:58]
+ wire out_wimask_6 = &out_frontMask[24:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_6 = out_wivalid_4 & out_wimask_6; // @[RegisterRouter.scala 83:24]
+ wire [15:0] _out_prepend_T_4 = {{14'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
+ wire [24:0] out_prepend_4 = {txwm,_out_prepend_T_4}; // @[Cat.scala 31:58]
+ wire out_f_wivalid_7 = out_wivalid_4 & out_wimask_2; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_5 = {{7'd0}, out_prepend_4}; // @[RegisterRouter.scala 83:24]
+ wire [32:0] out_prepend_5 = {rxen,_out_prepend_T_5}; // @[Cat.scala 31:58]
+ wire out_wimask_8 = &out_frontMask[56:48]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_8 = out_wivalid_4 & out_wimask_8; // @[RegisterRouter.scala 83:24]
+ wire [47:0] _out_prepend_T_6 = {{15'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
+ wire [56:0] out_prepend_6 = {rxwm,_out_prepend_T_6}; // @[Cat.scala 31:58]
+ wire out_wimask_9 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_10 = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_rivalid_10 = bundleIn_0_a_valid & bundleIn_0_d_ready & in_bits_read & out_frontSel_0 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_10 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala 83:24]
+ wire out_womask_12 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_12 = out_wivalid_10 & out_womask_12; // @[RegisterRouter.scala 83:24]
+ wire quash = out_f_woready_12 & bundleIn_0_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
+ wire out_rimask_13 = |out_frontMask[39:32]; // @[RegisterRouter.scala 83:24]
+ wire [40:0] out_prepend_10 = {1'h0,rxq_io_deq_bits,_T,31'h0}; // @[Cat.scala 31:58]
+ wire [62:0] _out_T_157 = {{22'd0}, out_prepend_10}; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_11 = {_T_1,_out_T_157}; // @[Cat.scala 31:58]
+ wire _GEN_25 = 2'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_26 = 2'h2 == out_oindex ? _out_T : _GEN_25; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_27 = 2'h3 == out_oindex ? _out_T : _GEN_26; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_1 = {{7'd0}, out_prepend_6}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_29 = 2'h1 == out_oindex ? _out_out_bits_data_WIRE_1_1 : out_prepend_11; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_2 = {{30'd0}, out_prepend_2}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_30 = 2'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_29; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_3 = {{48'd0}, div}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_31 = 2'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_30; // @[MuxLiteral.scala 48:{10,10}]
+ TLBuffer_20 buffer ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
+ .clock(intsource_clock),
+ .reset(intsource_reset),
+ .auto_in_0(intsource_auto_in_0),
+ .auto_out_sync_0(intsource_auto_out_sync_0)
+ );
+ TLMonitor_55 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ UARTTx txm ( // @[UART.scala 79:19]
+ .clock(txm_clock),
+ .reset(txm_reset),
+ .io_en(txm_io_en),
+ .io_in_ready(txm_io_in_ready),
+ .io_in_valid(txm_io_in_valid),
+ .io_in_bits(txm_io_in_bits),
+ .io_out(txm_io_out),
+ .io_div(txm_io_div),
+ .io_nstop(txm_io_nstop)
+ );
+ QueueCompatibility txq ( // @[UART.scala 80:19]
+ .clock(txq_clock),
+ .reset(txq_reset),
+ .io_enq_ready(txq_io_enq_ready),
+ .io_enq_valid(txq_io_enq_valid),
+ .io_enq_bits(txq_io_enq_bits),
+ .io_deq_ready(txq_io_deq_ready),
+ .io_deq_valid(txq_io_deq_valid),
+ .io_deq_bits(txq_io_deq_bits),
+ .io_count(txq_io_count)
+ );
+ UARTRx rxm ( // @[UART.scala 82:19]
+ .clock(rxm_clock),
+ .reset(rxm_reset),
+ .io_en(rxm_io_en),
+ .io_in(rxm_io_in),
+ .io_out_valid(rxm_io_out_valid),
+ .io_out_bits(rxm_io_out_bits),
+ .io_div(rxm_io_div)
+ );
+ QueueCompatibility rxq ( // @[UART.scala 83:19]
+ .clock(rxq_clock),
+ .reset(rxq_reset),
+ .io_enq_ready(rxq_io_enq_ready),
+ .io_enq_valid(rxq_io_enq_valid),
+ .io_enq_bits(rxq_io_enq_bits),
+ .io_deq_ready(rxq_io_deq_ready),
+ .io_deq_valid(rxq_io_deq_valid),
+ .io_deq_bits(rxq_io_deq_bits),
+ .io_count(rxq_io_count)
+ );
+ assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_io_out_txd = txm_io_out; // @[Nodes.scala 1207:84 UART.scala 113:12]
+ assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = _GEN_27 ? _GEN_31 : 64'h0; // @[RegisterRouter.scala 83:24]
+ assign intsource_clock = clock;
+ assign intsource_reset = reset;
+ assign intsource_auto_in_0 = ip_txwm & ie_txwm | ip_rxwm & ie_rxwm; // @[UART.scala 140:41]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign txm_clock = clock;
+ assign txm_reset = reset;
+ assign txm_io_en = txen; // @[UART.scala 109:15]
+ assign txm_io_in_valid = txq_io_deq_valid; // @[UART.scala 110:13]
+ assign txm_io_in_bits = txq_io_deq_bits; // @[UART.scala 110:13]
+ assign txm_io_div = div; // @[UART.scala 111:14]
+ assign txm_io_nstop = nstop; // @[UART.scala 112:16]
+ assign txq_clock = clock;
+ assign txq_reset = reset;
+ assign txq_io_enq_valid = out_f_wivalid_10 & ~quash; // @[RegMapFIFO.scala 19:30]
+ assign txq_io_enq_bits = bundleIn_0_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
+ assign txq_io_deq_ready = txm_io_in_ready; // @[UART.scala 110:13]
+ assign rxm_clock = clock;
+ assign rxm_reset = reset;
+ assign rxm_io_en = rxen; // @[UART.scala 120:13]
+ assign rxm_io_in = auto_io_out_rxd; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign rxm_io_div = div; // @[UART.scala 123:14]
+ assign rxq_clock = clock;
+ assign rxq_reset = reset;
+ assign rxq_io_enq_valid = rxm_io_out_valid; // @[UART.scala 122:14]
+ assign rxq_io_enq_bits = rxm_io_out_bits; // @[UART.scala 122:14]
+ assign rxq_io_deq_ready = out_rivalid_10 & out_rimask_13; // @[RegisterRouter.scala 83:24]
+ always @(posedge clock) begin
+ if (reset) begin // @[UART.scala 85:16]
+ div <= 16'h364; // @[UART.scala 85:16]
+ end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
+ div <= bundleIn_0_a_bits_data[15:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 91:17]
+ txen <= 1'h0; // @[UART.scala 91:17]
+ end else if (out_f_wivalid_4) begin // @[RegField.scala 74:88]
+ txen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 92:17]
+ rxen <= 1'h0; // @[UART.scala 92:17]
+ end else if (out_f_wivalid_7) begin // @[RegField.scala 74:88]
+ rxen <= bundleIn_0_a_bits_data[32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 99:17]
+ txwm <= 9'h0; // @[UART.scala 99:17]
+ end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
+ txwm <= bundleIn_0_a_bits_data[24:16]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 100:17]
+ rxwm <= 9'h0; // @[UART.scala 100:17]
+ end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
+ rxwm <= bundleIn_0_a_bits_data[56:48]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 101:18]
+ nstop <= 1'h0; // @[UART.scala 101:18]
+ end else if (out_f_wivalid_5) begin // @[RegField.scala 74:88]
+ nstop <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 135:15]
+ ie_rxwm <= 1'h0; // @[UART.scala 135:15]
+ end else if (out_f_wivalid_1) begin // @[RegField.scala 74:88]
+ ie_rxwm <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 135:15]
+ ie_txwm <= 1'h0; // @[UART.scala 135:15]
+ end else if (out_f_wivalid) begin // @[RegField.scala 74:88]
+ ie_txwm <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ div = _RAND_0[15:0];
+ _RAND_1 = {1{`RANDOM}};
+ txen = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ rxen = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ txwm = _RAND_3[8:0];
+ _RAND_4 = {1{`RANDOM}};
+ rxwm = _RAND_4[8:0];
+ _RAND_5 = {1{`RANDOM}};
+ nstop = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ ie_rxwm = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ ie_txwm = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockSinkDomain_3(
+ output auto_uart_0_int_xing_out_sync_0,
+ output auto_uart_0_control_xing_in_a_ready,
+ input auto_uart_0_control_xing_in_a_valid,
+ input [2:0] auto_uart_0_control_xing_in_a_bits_opcode,
+ input [2:0] auto_uart_0_control_xing_in_a_bits_param,
+ input [1:0] auto_uart_0_control_xing_in_a_bits_size,
+ input [6:0] auto_uart_0_control_xing_in_a_bits_source,
+ input [28:0] auto_uart_0_control_xing_in_a_bits_address,
+ input [7:0] auto_uart_0_control_xing_in_a_bits_mask,
+ input [63:0] auto_uart_0_control_xing_in_a_bits_data,
+ input auto_uart_0_control_xing_in_a_bits_corrupt,
+ input auto_uart_0_control_xing_in_d_ready,
+ output auto_uart_0_control_xing_in_d_valid,
+ output [2:0] auto_uart_0_control_xing_in_d_bits_opcode,
+ output [1:0] auto_uart_0_control_xing_in_d_bits_size,
+ output [6:0] auto_uart_0_control_xing_in_d_bits_source,
+ output [63:0] auto_uart_0_control_xing_in_d_bits_data,
+ output auto_uart_0_io_out_txd,
+ input auto_uart_0_io_out_rxd,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire uart_0_clock; // @[UART.scala 243:51]
+ wire uart_0_reset; // @[UART.scala 243:51]
+ wire uart_0_auto_int_xing_out_sync_0; // @[UART.scala 243:51]
+ wire uart_0_auto_control_xing_in_a_ready; // @[UART.scala 243:51]
+ wire uart_0_auto_control_xing_in_a_valid; // @[UART.scala 243:51]
+ wire [2:0] uart_0_auto_control_xing_in_a_bits_opcode; // @[UART.scala 243:51]
+ wire [2:0] uart_0_auto_control_xing_in_a_bits_param; // @[UART.scala 243:51]
+ wire [1:0] uart_0_auto_control_xing_in_a_bits_size; // @[UART.scala 243:51]
+ wire [6:0] uart_0_auto_control_xing_in_a_bits_source; // @[UART.scala 243:51]
+ wire [28:0] uart_0_auto_control_xing_in_a_bits_address; // @[UART.scala 243:51]
+ wire [7:0] uart_0_auto_control_xing_in_a_bits_mask; // @[UART.scala 243:51]
+ wire [63:0] uart_0_auto_control_xing_in_a_bits_data; // @[UART.scala 243:51]
+ wire uart_0_auto_control_xing_in_a_bits_corrupt; // @[UART.scala 243:51]
+ wire uart_0_auto_control_xing_in_d_ready; // @[UART.scala 243:51]
+ wire uart_0_auto_control_xing_in_d_valid; // @[UART.scala 243:51]
+ wire [2:0] uart_0_auto_control_xing_in_d_bits_opcode; // @[UART.scala 243:51]
+ wire [1:0] uart_0_auto_control_xing_in_d_bits_size; // @[UART.scala 243:51]
+ wire [6:0] uart_0_auto_control_xing_in_d_bits_source; // @[UART.scala 243:51]
+ wire [63:0] uart_0_auto_control_xing_in_d_bits_data; // @[UART.scala 243:51]
+ wire uart_0_auto_io_out_txd; // @[UART.scala 243:51]
+ wire uart_0_auto_io_out_rxd; // @[UART.scala 243:51]
+ TLUART uart_0 ( // @[UART.scala 243:51]
+ .clock(uart_0_clock),
+ .reset(uart_0_reset),
+ .auto_int_xing_out_sync_0(uart_0_auto_int_xing_out_sync_0),
+ .auto_control_xing_in_a_ready(uart_0_auto_control_xing_in_a_ready),
+ .auto_control_xing_in_a_valid(uart_0_auto_control_xing_in_a_valid),
+ .auto_control_xing_in_a_bits_opcode(uart_0_auto_control_xing_in_a_bits_opcode),
+ .auto_control_xing_in_a_bits_param(uart_0_auto_control_xing_in_a_bits_param),
+ .auto_control_xing_in_a_bits_size(uart_0_auto_control_xing_in_a_bits_size),
+ .auto_control_xing_in_a_bits_source(uart_0_auto_control_xing_in_a_bits_source),
+ .auto_control_xing_in_a_bits_address(uart_0_auto_control_xing_in_a_bits_address),
+ .auto_control_xing_in_a_bits_mask(uart_0_auto_control_xing_in_a_bits_mask),
+ .auto_control_xing_in_a_bits_data(uart_0_auto_control_xing_in_a_bits_data),
+ .auto_control_xing_in_a_bits_corrupt(uart_0_auto_control_xing_in_a_bits_corrupt),
+ .auto_control_xing_in_d_ready(uart_0_auto_control_xing_in_d_ready),
+ .auto_control_xing_in_d_valid(uart_0_auto_control_xing_in_d_valid),
+ .auto_control_xing_in_d_bits_opcode(uart_0_auto_control_xing_in_d_bits_opcode),
+ .auto_control_xing_in_d_bits_size(uart_0_auto_control_xing_in_d_bits_size),
+ .auto_control_xing_in_d_bits_source(uart_0_auto_control_xing_in_d_bits_source),
+ .auto_control_xing_in_d_bits_data(uart_0_auto_control_xing_in_d_bits_data),
+ .auto_io_out_txd(uart_0_auto_io_out_txd),
+ .auto_io_out_rxd(uart_0_auto_io_out_rxd)
+ );
+ assign auto_uart_0_int_xing_out_sync_0 = uart_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
+ assign auto_uart_0_control_xing_in_a_ready = uart_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_uart_0_control_xing_in_d_valid = uart_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_uart_0_control_xing_in_d_bits_opcode = uart_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_uart_0_control_xing_in_d_bits_size = uart_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_uart_0_control_xing_in_d_bits_source = uart_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_uart_0_control_xing_in_d_bits_data = uart_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_uart_0_io_out_txd = uart_0_auto_io_out_txd; // @[LazyModule.scala 311:12]
+ assign uart_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign uart_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_valid = auto_uart_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_bits_opcode = auto_uart_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_bits_param = auto_uart_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_bits_size = auto_uart_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_bits_source = auto_uart_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_bits_address = auto_uart_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_bits_mask = auto_uart_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_bits_data = auto_uart_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_a_bits_corrupt = auto_uart_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_control_xing_in_d_ready = auto_uart_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
+ assign uart_0_auto_io_out_rxd = auto_uart_0_io_out_rxd; // @[LazyModule.scala 311:12]
+endmodule
+module TLMonitor_56(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{26'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10011000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLUART_1(
+ input clock,
+ input reset,
+ output auto_int_xing_out_sync_0,
+ output auto_control_xing_in_a_ready,
+ input auto_control_xing_in_a_valid,
+ input [2:0] auto_control_xing_in_a_bits_opcode,
+ input [2:0] auto_control_xing_in_a_bits_param,
+ input [1:0] auto_control_xing_in_a_bits_size,
+ input [6:0] auto_control_xing_in_a_bits_source,
+ input [28:0] auto_control_xing_in_a_bits_address,
+ input [7:0] auto_control_xing_in_a_bits_mask,
+ input [63:0] auto_control_xing_in_a_bits_data,
+ input auto_control_xing_in_a_bits_corrupt,
+ input auto_control_xing_in_d_ready,
+ output auto_control_xing_in_d_valid,
+ output [2:0] auto_control_xing_in_d_bits_opcode,
+ output [1:0] auto_control_xing_in_d_bits_size,
+ output [6:0] auto_control_xing_in_d_bits_source,
+ output [63:0] auto_control_xing_in_d_bits_data,
+ output auto_io_out_txd,
+ input auto_io_out_rxd
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire intsource_clock; // @[Crossing.scala 26:31]
+ wire intsource_reset; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire txm_clock; // @[UART.scala 79:19]
+ wire txm_reset; // @[UART.scala 79:19]
+ wire txm_io_en; // @[UART.scala 79:19]
+ wire txm_io_in_ready; // @[UART.scala 79:19]
+ wire txm_io_in_valid; // @[UART.scala 79:19]
+ wire [7:0] txm_io_in_bits; // @[UART.scala 79:19]
+ wire txm_io_out; // @[UART.scala 79:19]
+ wire [15:0] txm_io_div; // @[UART.scala 79:19]
+ wire txm_io_nstop; // @[UART.scala 79:19]
+ wire txq_clock; // @[UART.scala 80:19]
+ wire txq_reset; // @[UART.scala 80:19]
+ wire txq_io_enq_ready; // @[UART.scala 80:19]
+ wire txq_io_enq_valid; // @[UART.scala 80:19]
+ wire [7:0] txq_io_enq_bits; // @[UART.scala 80:19]
+ wire txq_io_deq_ready; // @[UART.scala 80:19]
+ wire txq_io_deq_valid; // @[UART.scala 80:19]
+ wire [7:0] txq_io_deq_bits; // @[UART.scala 80:19]
+ wire [8:0] txq_io_count; // @[UART.scala 80:19]
+ wire rxm_clock; // @[UART.scala 82:19]
+ wire rxm_reset; // @[UART.scala 82:19]
+ wire rxm_io_en; // @[UART.scala 82:19]
+ wire rxm_io_in; // @[UART.scala 82:19]
+ wire rxm_io_out_valid; // @[UART.scala 82:19]
+ wire [7:0] rxm_io_out_bits; // @[UART.scala 82:19]
+ wire [15:0] rxm_io_div; // @[UART.scala 82:19]
+ wire rxq_clock; // @[UART.scala 83:19]
+ wire rxq_reset; // @[UART.scala 83:19]
+ wire rxq_io_enq_ready; // @[UART.scala 83:19]
+ wire rxq_io_enq_valid; // @[UART.scala 83:19]
+ wire [7:0] rxq_io_enq_bits; // @[UART.scala 83:19]
+ wire rxq_io_deq_ready; // @[UART.scala 83:19]
+ wire rxq_io_deq_valid; // @[UART.scala 83:19]
+ wire [7:0] rxq_io_deq_bits; // @[UART.scala 83:19]
+ wire [8:0] rxq_io_count; // @[UART.scala 83:19]
+ reg [15:0] div; // @[UART.scala 85:16]
+ reg txen; // @[UART.scala 91:17]
+ reg rxen; // @[UART.scala 92:17]
+ reg [8:0] txwm; // @[UART.scala 99:17]
+ reg [8:0] rxwm; // @[UART.scala 100:17]
+ reg nstop; // @[UART.scala 101:18]
+ reg ie_rxwm; // @[UART.scala 135:15]
+ reg ie_txwm; // @[UART.scala 135:15]
+ wire ip_txwm = txq_io_count < txwm; // @[UART.scala 138:28]
+ wire ip_rxwm = rxq_io_count > rxwm; // @[UART.scala 139:28]
+ wire _T = ~txq_io_enq_ready; // @[RegMapFIFO.scala 25:9]
+ wire _T_1 = ~rxq_io_deq_valid; // @[RegMapFIFO.scala 46:21]
+ wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [8:0] in_bits_index = bundleIn_0_a_bits_address[11:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire [8:0] out_findex = in_bits_index & 9'h1fc; // @[RegisterRouter.scala 83:24]
+ wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_13 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_15 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_17 = bundleIn_0_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_19 = bundleIn_0_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_21 = bundleIn_0_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_23 = bundleIn_0_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_frontMask = {_out_frontMask_T_23,_out_frontMask_T_21,_out_frontMask_T_19,_out_frontMask_T_17,
+ _out_frontMask_T_15,_out_frontMask_T_13,_out_frontMask_T_11,_out_frontMask_T_9}; // @[Cat.scala 31:58]
+ wire out_wimask = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
+ wire bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [1:0] out_oindex = {in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [3:0] _out_frontSel_T = 4'h1 << out_oindex; // @[OneHot.scala 57:35]
+ wire out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire [63:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire out_wimask_1 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1 = out_wivalid_0 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [1:0] out_prepend = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
+ wire out_wimask_2 = &out_frontMask[32]; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_1 = {{30'd0}, out_prepend}; // @[RegisterRouter.scala 83:24]
+ wire [33:0] out_prepend_2 = {ip_rxwm,ip_txwm,_out_prepend_T_1}; // @[Cat.scala 31:58]
+ wire out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_4 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_4 = out_wivalid_4 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_5 = out_wivalid_4 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [1:0] out_prepend_3 = {nstop,txen}; // @[Cat.scala 31:58]
+ wire out_wimask_6 = &out_frontMask[24:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_6 = out_wivalid_4 & out_wimask_6; // @[RegisterRouter.scala 83:24]
+ wire [15:0] _out_prepend_T_4 = {{14'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
+ wire [24:0] out_prepend_4 = {txwm,_out_prepend_T_4}; // @[Cat.scala 31:58]
+ wire out_f_wivalid_7 = out_wivalid_4 & out_wimask_2; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_5 = {{7'd0}, out_prepend_4}; // @[RegisterRouter.scala 83:24]
+ wire [32:0] out_prepend_5 = {rxen,_out_prepend_T_5}; // @[Cat.scala 31:58]
+ wire out_wimask_8 = &out_frontMask[56:48]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_8 = out_wivalid_4 & out_wimask_8; // @[RegisterRouter.scala 83:24]
+ wire [47:0] _out_prepend_T_6 = {{15'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
+ wire [56:0] out_prepend_6 = {rxwm,_out_prepend_T_6}; // @[Cat.scala 31:58]
+ wire out_wimask_9 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_10 = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_rivalid_10 = bundleIn_0_a_valid & bundleIn_0_d_ready & in_bits_read & out_frontSel_0 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_10 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala 83:24]
+ wire out_womask_12 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_12 = out_wivalid_10 & out_womask_12; // @[RegisterRouter.scala 83:24]
+ wire quash = out_f_woready_12 & bundleIn_0_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
+ wire out_rimask_13 = |out_frontMask[39:32]; // @[RegisterRouter.scala 83:24]
+ wire [40:0] out_prepend_10 = {1'h0,rxq_io_deq_bits,_T,31'h0}; // @[Cat.scala 31:58]
+ wire [62:0] _out_T_157 = {{22'd0}, out_prepend_10}; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_11 = {_T_1,_out_T_157}; // @[Cat.scala 31:58]
+ wire _GEN_25 = 2'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_26 = 2'h2 == out_oindex ? _out_T : _GEN_25; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_27 = 2'h3 == out_oindex ? _out_T : _GEN_26; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_1 = {{7'd0}, out_prepend_6}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_29 = 2'h1 == out_oindex ? _out_out_bits_data_WIRE_1_1 : out_prepend_11; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_2 = {{30'd0}, out_prepend_2}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_30 = 2'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_29; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_3 = {{48'd0}, div}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_31 = 2'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_30; // @[MuxLiteral.scala 48:{10,10}]
+ TLBuffer_20 buffer ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
+ .clock(intsource_clock),
+ .reset(intsource_reset),
+ .auto_in_0(intsource_auto_in_0),
+ .auto_out_sync_0(intsource_auto_out_sync_0)
+ );
+ TLMonitor_56 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ UARTTx txm ( // @[UART.scala 79:19]
+ .clock(txm_clock),
+ .reset(txm_reset),
+ .io_en(txm_io_en),
+ .io_in_ready(txm_io_in_ready),
+ .io_in_valid(txm_io_in_valid),
+ .io_in_bits(txm_io_in_bits),
+ .io_out(txm_io_out),
+ .io_div(txm_io_div),
+ .io_nstop(txm_io_nstop)
+ );
+ QueueCompatibility txq ( // @[UART.scala 80:19]
+ .clock(txq_clock),
+ .reset(txq_reset),
+ .io_enq_ready(txq_io_enq_ready),
+ .io_enq_valid(txq_io_enq_valid),
+ .io_enq_bits(txq_io_enq_bits),
+ .io_deq_ready(txq_io_deq_ready),
+ .io_deq_valid(txq_io_deq_valid),
+ .io_deq_bits(txq_io_deq_bits),
+ .io_count(txq_io_count)
+ );
+ UARTRx rxm ( // @[UART.scala 82:19]
+ .clock(rxm_clock),
+ .reset(rxm_reset),
+ .io_en(rxm_io_en),
+ .io_in(rxm_io_in),
+ .io_out_valid(rxm_io_out_valid),
+ .io_out_bits(rxm_io_out_bits),
+ .io_div(rxm_io_div)
+ );
+ QueueCompatibility rxq ( // @[UART.scala 83:19]
+ .clock(rxq_clock),
+ .reset(rxq_reset),
+ .io_enq_ready(rxq_io_enq_ready),
+ .io_enq_valid(rxq_io_enq_valid),
+ .io_enq_bits(rxq_io_enq_bits),
+ .io_deq_ready(rxq_io_deq_ready),
+ .io_deq_valid(rxq_io_deq_valid),
+ .io_deq_bits(rxq_io_deq_bits),
+ .io_count(rxq_io_count)
+ );
+ assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_io_out_txd = txm_io_out; // @[Nodes.scala 1207:84 UART.scala 113:12]
+ assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = _GEN_27 ? _GEN_31 : 64'h0; // @[RegisterRouter.scala 83:24]
+ assign intsource_clock = clock;
+ assign intsource_reset = reset;
+ assign intsource_auto_in_0 = ip_txwm & ie_txwm | ip_rxwm & ie_rxwm; // @[UART.scala 140:41]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign txm_clock = clock;
+ assign txm_reset = reset;
+ assign txm_io_en = txen; // @[UART.scala 109:15]
+ assign txm_io_in_valid = txq_io_deq_valid; // @[UART.scala 110:13]
+ assign txm_io_in_bits = txq_io_deq_bits; // @[UART.scala 110:13]
+ assign txm_io_div = div; // @[UART.scala 111:14]
+ assign txm_io_nstop = nstop; // @[UART.scala 112:16]
+ assign txq_clock = clock;
+ assign txq_reset = reset;
+ assign txq_io_enq_valid = out_f_wivalid_10 & ~quash; // @[RegMapFIFO.scala 19:30]
+ assign txq_io_enq_bits = bundleIn_0_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
+ assign txq_io_deq_ready = txm_io_in_ready; // @[UART.scala 110:13]
+ assign rxm_clock = clock;
+ assign rxm_reset = reset;
+ assign rxm_io_en = rxen; // @[UART.scala 120:13]
+ assign rxm_io_in = auto_io_out_rxd; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign rxm_io_div = div; // @[UART.scala 123:14]
+ assign rxq_clock = clock;
+ assign rxq_reset = reset;
+ assign rxq_io_enq_valid = rxm_io_out_valid; // @[UART.scala 122:14]
+ assign rxq_io_enq_bits = rxm_io_out_bits; // @[UART.scala 122:14]
+ assign rxq_io_deq_ready = out_rivalid_10 & out_rimask_13; // @[RegisterRouter.scala 83:24]
+ always @(posedge clock) begin
+ if (reset) begin // @[UART.scala 85:16]
+ div <= 16'h364; // @[UART.scala 85:16]
+ end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
+ div <= bundleIn_0_a_bits_data[15:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 91:17]
+ txen <= 1'h0; // @[UART.scala 91:17]
+ end else if (out_f_wivalid_4) begin // @[RegField.scala 74:88]
+ txen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 92:17]
+ rxen <= 1'h0; // @[UART.scala 92:17]
+ end else if (out_f_wivalid_7) begin // @[RegField.scala 74:88]
+ rxen <= bundleIn_0_a_bits_data[32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 99:17]
+ txwm <= 9'h0; // @[UART.scala 99:17]
+ end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
+ txwm <= bundleIn_0_a_bits_data[24:16]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 100:17]
+ rxwm <= 9'h0; // @[UART.scala 100:17]
+ end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
+ rxwm <= bundleIn_0_a_bits_data[56:48]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 101:18]
+ nstop <= 1'h0; // @[UART.scala 101:18]
+ end else if (out_f_wivalid_5) begin // @[RegField.scala 74:88]
+ nstop <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 135:15]
+ ie_rxwm <= 1'h0; // @[UART.scala 135:15]
+ end else if (out_f_wivalid_1) begin // @[RegField.scala 74:88]
+ ie_rxwm <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[UART.scala 135:15]
+ ie_txwm <= 1'h0; // @[UART.scala 135:15]
+ end else if (out_f_wivalid) begin // @[RegField.scala 74:88]
+ ie_txwm <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ div = _RAND_0[15:0];
+ _RAND_1 = {1{`RANDOM}};
+ txen = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ rxen = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ txwm = _RAND_3[8:0];
+ _RAND_4 = {1{`RANDOM}};
+ rxwm = _RAND_4[8:0];
+ _RAND_5 = {1{`RANDOM}};
+ nstop = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ ie_rxwm = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ ie_txwm = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockSinkDomain_4(
+ output auto_uart_1_int_xing_out_sync_0,
+ output auto_uart_1_control_xing_in_a_ready,
+ input auto_uart_1_control_xing_in_a_valid,
+ input [2:0] auto_uart_1_control_xing_in_a_bits_opcode,
+ input [2:0] auto_uart_1_control_xing_in_a_bits_param,
+ input [1:0] auto_uart_1_control_xing_in_a_bits_size,
+ input [6:0] auto_uart_1_control_xing_in_a_bits_source,
+ input [28:0] auto_uart_1_control_xing_in_a_bits_address,
+ input [7:0] auto_uart_1_control_xing_in_a_bits_mask,
+ input [63:0] auto_uart_1_control_xing_in_a_bits_data,
+ input auto_uart_1_control_xing_in_a_bits_corrupt,
+ input auto_uart_1_control_xing_in_d_ready,
+ output auto_uart_1_control_xing_in_d_valid,
+ output [2:0] auto_uart_1_control_xing_in_d_bits_opcode,
+ output [1:0] auto_uart_1_control_xing_in_d_bits_size,
+ output [6:0] auto_uart_1_control_xing_in_d_bits_source,
+ output [63:0] auto_uart_1_control_xing_in_d_bits_data,
+ output auto_uart_1_io_out_txd,
+ input auto_uart_1_io_out_rxd,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire uart_1_clock; // @[UART.scala 243:51]
+ wire uart_1_reset; // @[UART.scala 243:51]
+ wire uart_1_auto_int_xing_out_sync_0; // @[UART.scala 243:51]
+ wire uart_1_auto_control_xing_in_a_ready; // @[UART.scala 243:51]
+ wire uart_1_auto_control_xing_in_a_valid; // @[UART.scala 243:51]
+ wire [2:0] uart_1_auto_control_xing_in_a_bits_opcode; // @[UART.scala 243:51]
+ wire [2:0] uart_1_auto_control_xing_in_a_bits_param; // @[UART.scala 243:51]
+ wire [1:0] uart_1_auto_control_xing_in_a_bits_size; // @[UART.scala 243:51]
+ wire [6:0] uart_1_auto_control_xing_in_a_bits_source; // @[UART.scala 243:51]
+ wire [28:0] uart_1_auto_control_xing_in_a_bits_address; // @[UART.scala 243:51]
+ wire [7:0] uart_1_auto_control_xing_in_a_bits_mask; // @[UART.scala 243:51]
+ wire [63:0] uart_1_auto_control_xing_in_a_bits_data; // @[UART.scala 243:51]
+ wire uart_1_auto_control_xing_in_a_bits_corrupt; // @[UART.scala 243:51]
+ wire uart_1_auto_control_xing_in_d_ready; // @[UART.scala 243:51]
+ wire uart_1_auto_control_xing_in_d_valid; // @[UART.scala 243:51]
+ wire [2:0] uart_1_auto_control_xing_in_d_bits_opcode; // @[UART.scala 243:51]
+ wire [1:0] uart_1_auto_control_xing_in_d_bits_size; // @[UART.scala 243:51]
+ wire [6:0] uart_1_auto_control_xing_in_d_bits_source; // @[UART.scala 243:51]
+ wire [63:0] uart_1_auto_control_xing_in_d_bits_data; // @[UART.scala 243:51]
+ wire uart_1_auto_io_out_txd; // @[UART.scala 243:51]
+ wire uart_1_auto_io_out_rxd; // @[UART.scala 243:51]
+ TLUART_1 uart_1 ( // @[UART.scala 243:51]
+ .clock(uart_1_clock),
+ .reset(uart_1_reset),
+ .auto_int_xing_out_sync_0(uart_1_auto_int_xing_out_sync_0),
+ .auto_control_xing_in_a_ready(uart_1_auto_control_xing_in_a_ready),
+ .auto_control_xing_in_a_valid(uart_1_auto_control_xing_in_a_valid),
+ .auto_control_xing_in_a_bits_opcode(uart_1_auto_control_xing_in_a_bits_opcode),
+ .auto_control_xing_in_a_bits_param(uart_1_auto_control_xing_in_a_bits_param),
+ .auto_control_xing_in_a_bits_size(uart_1_auto_control_xing_in_a_bits_size),
+ .auto_control_xing_in_a_bits_source(uart_1_auto_control_xing_in_a_bits_source),
+ .auto_control_xing_in_a_bits_address(uart_1_auto_control_xing_in_a_bits_address),
+ .auto_control_xing_in_a_bits_mask(uart_1_auto_control_xing_in_a_bits_mask),
+ .auto_control_xing_in_a_bits_data(uart_1_auto_control_xing_in_a_bits_data),
+ .auto_control_xing_in_a_bits_corrupt(uart_1_auto_control_xing_in_a_bits_corrupt),
+ .auto_control_xing_in_d_ready(uart_1_auto_control_xing_in_d_ready),
+ .auto_control_xing_in_d_valid(uart_1_auto_control_xing_in_d_valid),
+ .auto_control_xing_in_d_bits_opcode(uart_1_auto_control_xing_in_d_bits_opcode),
+ .auto_control_xing_in_d_bits_size(uart_1_auto_control_xing_in_d_bits_size),
+ .auto_control_xing_in_d_bits_source(uart_1_auto_control_xing_in_d_bits_source),
+ .auto_control_xing_in_d_bits_data(uart_1_auto_control_xing_in_d_bits_data),
+ .auto_io_out_txd(uart_1_auto_io_out_txd),
+ .auto_io_out_rxd(uart_1_auto_io_out_rxd)
+ );
+ assign auto_uart_1_int_xing_out_sync_0 = uart_1_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
+ assign auto_uart_1_control_xing_in_a_ready = uart_1_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_uart_1_control_xing_in_d_valid = uart_1_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_uart_1_control_xing_in_d_bits_opcode = uart_1_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_uart_1_control_xing_in_d_bits_size = uart_1_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_uart_1_control_xing_in_d_bits_source = uart_1_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_uart_1_control_xing_in_d_bits_data = uart_1_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_uart_1_io_out_txd = uart_1_auto_io_out_txd; // @[LazyModule.scala 311:12]
+ assign uart_1_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign uart_1_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_valid = auto_uart_1_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_bits_opcode = auto_uart_1_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_bits_param = auto_uart_1_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_bits_size = auto_uart_1_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_bits_source = auto_uart_1_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_bits_address = auto_uart_1_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_bits_mask = auto_uart_1_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_bits_data = auto_uart_1_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_a_bits_corrupt = auto_uart_1_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_control_xing_in_d_ready = auto_uart_1_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
+ assign uart_1_auto_io_out_rxd = auto_uart_1_io_out_rxd; // @[LazyModule.scala 311:12]
+endmodule
+module AsyncResetRegVec_w4_i0(
+ input clock,
+ input reset,
+ input [3:0] io_d,
+ output [3:0] io_q,
+ input io_en
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg [3:0] reg_; // @[AsyncResetReg.scala 64:50]
+ assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncResetReg.scala 65:16]
+ reg_ <= 4'h0; // @[AsyncResetReg.scala 66:9]
+ end else if (io_en) begin // @[AsyncResetReg.scala 64:50]
+ reg_ <= io_d;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ reg_ = _RAND_0[3:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ reg_ = 4'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module IntSyncCrossingSource_9(
+ input clock,
+ input reset,
+ input auto_in_0,
+ input auto_in_1,
+ input auto_in_2,
+ input auto_in_3,
+ output auto_out_sync_0,
+ output auto_out_sync_1,
+ output auto_out_sync_2,
+ output auto_out_sync_3
+);
+ wire reg__clock; // @[AsyncResetReg.scala 89:21]
+ wire reg__reset; // @[AsyncResetReg.scala 89:21]
+ wire [3:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
+ wire [3:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
+ wire reg__io_en; // @[AsyncResetReg.scala 89:21]
+ wire [1:0] lo = {auto_in_1,auto_in_0}; // @[Cat.scala 31:58]
+ wire [1:0] hi = {auto_in_3,auto_in_2}; // @[Cat.scala 31:58]
+ AsyncResetRegVec_w4_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
+ .clock(reg__clock),
+ .reset(reg__reset),
+ .io_d(reg__io_d),
+ .io_q(reg__io_q),
+ .io_en(reg__io_en)
+ );
+ assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
+ assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
+ assign auto_out_sync_2 = reg__io_q[2]; // @[Crossing.scala 41:52]
+ assign auto_out_sync_3 = reg__io_q[3]; // @[Crossing.scala 41:52]
+ assign reg__clock = clock;
+ assign reg__reset = reset;
+ assign reg__io_d = {hi,lo}; // @[Cat.scala 31:58]
+ assign reg__io_en = 1'h1; // @[AsyncResetReg.scala 92:15]
+endmodule
+module TLMonitor_57(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{26'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10012000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module SynchronizerShiftReg_w4_d3(
+ input clock,
+ input [3:0] io_d,
+ output [3:0] io_q
+);
+ wire output_chain_clock; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_d; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_q; // @[ShiftReg.scala 45:23]
+ wire output_chain_1_clock; // @[ShiftReg.scala 45:23]
+ wire output_chain_1_io_d; // @[ShiftReg.scala 45:23]
+ wire output_chain_1_io_q; // @[ShiftReg.scala 45:23]
+ wire output_chain_2_clock; // @[ShiftReg.scala 45:23]
+ wire output_chain_2_io_d; // @[ShiftReg.scala 45:23]
+ wire output_chain_2_io_q; // @[ShiftReg.scala 45:23]
+ wire output_chain_3_clock; // @[ShiftReg.scala 45:23]
+ wire output_chain_3_io_d; // @[ShiftReg.scala 45:23]
+ wire output_chain_3_io_q; // @[ShiftReg.scala 45:23]
+ wire output_1 = output_chain_1_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire output_0 = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire [1:0] io_q_lo = {output_1,output_0}; // @[Cat.scala 31:58]
+ wire output_3 = output_chain_3_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire output_2 = output_chain_2_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire [1:0] io_q_hi = {output_3,output_2}; // @[Cat.scala 31:58]
+ NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala 45:23]
+ .clock(output_chain_clock),
+ .io_d(output_chain_io_d),
+ .io_q(output_chain_io_q)
+ );
+ NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_1 ( // @[ShiftReg.scala 45:23]
+ .clock(output_chain_1_clock),
+ .io_d(output_chain_1_io_d),
+ .io_q(output_chain_1_io_q)
+ );
+ NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_2 ( // @[ShiftReg.scala 45:23]
+ .clock(output_chain_2_clock),
+ .io_d(output_chain_2_io_d),
+ .io_q(output_chain_2_io_q)
+ );
+ NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_3 ( // @[ShiftReg.scala 45:23]
+ .clock(output_chain_3_clock),
+ .io_d(output_chain_3_io_d),
+ .io_q(output_chain_3_io_q)
+ );
+ assign io_q = {io_q_hi,io_q_lo}; // @[Cat.scala 31:58]
+ assign output_chain_clock = clock;
+ assign output_chain_io_d = io_d[0]; // @[SynchronizerReg.scala 173:39]
+ assign output_chain_1_clock = clock;
+ assign output_chain_1_io_d = io_d[1]; // @[SynchronizerReg.scala 173:39]
+ assign output_chain_2_clock = clock;
+ assign output_chain_2_io_d = io_d[2]; // @[SynchronizerReg.scala 173:39]
+ assign output_chain_3_clock = clock;
+ assign output_chain_3_io_d = io_d[3]; // @[SynchronizerReg.scala 173:39]
+endmodule
+module TLGPIO(
+ input clock,
+ input reset,
+ output auto_int_xing_out_sync_0,
+ output auto_int_xing_out_sync_1,
+ output auto_int_xing_out_sync_2,
+ output auto_int_xing_out_sync_3,
+ output auto_control_xing_in_a_ready,
+ input auto_control_xing_in_a_valid,
+ input [2:0] auto_control_xing_in_a_bits_opcode,
+ input [2:0] auto_control_xing_in_a_bits_param,
+ input [1:0] auto_control_xing_in_a_bits_size,
+ input [6:0] auto_control_xing_in_a_bits_source,
+ input [28:0] auto_control_xing_in_a_bits_address,
+ input [7:0] auto_control_xing_in_a_bits_mask,
+ input [63:0] auto_control_xing_in_a_bits_data,
+ input auto_control_xing_in_a_bits_corrupt,
+ input auto_control_xing_in_d_ready,
+ output auto_control_xing_in_d_valid,
+ output [2:0] auto_control_xing_in_d_bits_opcode,
+ output [1:0] auto_control_xing_in_d_bits_size,
+ output [6:0] auto_control_xing_in_d_bits_source,
+ output [63:0] auto_control_xing_in_d_bits_data,
+ input auto_io_out_pins_0_i_ival,
+ output auto_io_out_pins_0_o_oval,
+ output auto_io_out_pins_0_o_oe,
+ output auto_io_out_pins_0_o_ie,
+ input auto_io_out_pins_1_i_ival,
+ output auto_io_out_pins_1_o_oval,
+ output auto_io_out_pins_1_o_oe,
+ output auto_io_out_pins_1_o_ie,
+ input auto_io_out_pins_2_i_ival,
+ output auto_io_out_pins_2_o_oval,
+ output auto_io_out_pins_2_o_oe,
+ output auto_io_out_pins_2_o_ie,
+ input auto_io_out_pins_3_i_ival,
+ output auto_io_out_pins_3_o_oval,
+ output auto_io_out_pins_3_o_oe,
+ output auto_io_out_pins_3_o_ie
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+`endif // RANDOMIZE_REG_INIT
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire intsource_clock; // @[Crossing.scala 26:31]
+ wire intsource_reset; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_1; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_2; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_3; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_1; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_2; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_3; // @[Crossing.scala 26:31]
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire oeReg_clock; // @[GPIO.scala 79:22]
+ wire oeReg_reset; // @[GPIO.scala 79:22]
+ wire [3:0] oeReg_io_d; // @[GPIO.scala 79:22]
+ wire [3:0] oeReg_io_q; // @[GPIO.scala 79:22]
+ wire oeReg_io_en; // @[GPIO.scala 79:22]
+ wire pueReg_clock; // @[GPIO.scala 80:22]
+ wire pueReg_reset; // @[GPIO.scala 80:22]
+ wire [3:0] pueReg_io_d; // @[GPIO.scala 80:22]
+ wire [3:0] pueReg_io_q; // @[GPIO.scala 80:22]
+ wire pueReg_io_en; // @[GPIO.scala 80:22]
+ wire ieReg_clock; // @[GPIO.scala 82:22]
+ wire ieReg_reset; // @[GPIO.scala 82:22]
+ wire [3:0] ieReg_io_d; // @[GPIO.scala 82:22]
+ wire [3:0] ieReg_io_q; // @[GPIO.scala 82:22]
+ wire ieReg_io_en; // @[GPIO.scala 82:22]
+ wire poeReg_clock; // @[GPIO.scala 84:22]
+ wire poeReg_reset; // @[GPIO.scala 84:22]
+ wire [3:0] poeReg_io_d; // @[GPIO.scala 84:22]
+ wire [3:0] poeReg_io_q; // @[GPIO.scala 84:22]
+ wire poeReg_io_en; // @[GPIO.scala 84:22]
+ wire inSyncReg_inSyncReg_clock; // @[ShiftReg.scala 45:23]
+ wire [3:0] inSyncReg_inSyncReg_io_d; // @[ShiftReg.scala 45:23]
+ wire [3:0] inSyncReg_inSyncReg_io_q; // @[ShiftReg.scala 45:23]
+ wire iofEnReg_clock; // @[GPIO.scala 105:25]
+ wire iofEnReg_reset; // @[GPIO.scala 105:25]
+ wire [3:0] iofEnReg_io_d; // @[GPIO.scala 105:25]
+ wire [3:0] iofEnReg_io_q; // @[GPIO.scala 105:25]
+ wire iofEnReg_io_en; // @[GPIO.scala 105:25]
+ reg [3:0] portReg; // @[GPIO.scala 77:20]
+ reg [3:0] dsReg_0; // @[GPIO.scala 81:23]
+ wire [1:0] inVal_lo = {auto_io_out_pins_1_i_ival,auto_io_out_pins_0_i_ival}; // @[GPIO.scala 88:41]
+ wire [1:0] inVal_hi = {auto_io_out_pins_3_i_ival,auto_io_out_pins_2_i_ival}; // @[GPIO.scala 88:41]
+ reg [3:0] valueReg; // @[GPIO.scala 90:23]
+ reg [3:0] highIeReg; // @[GPIO.scala 93:22]
+ reg [3:0] lowIeReg; // @[GPIO.scala 94:22]
+ reg [3:0] riseIeReg; // @[GPIO.scala 95:22]
+ reg [3:0] fallIeReg; // @[GPIO.scala 96:22]
+ reg [3:0] highIpReg; // @[GPIO.scala 97:22]
+ reg [3:0] lowIpReg; // @[GPIO.scala 98:22]
+ reg [3:0] riseIpReg; // @[GPIO.scala 99:22]
+ reg [3:0] fallIpReg; // @[GPIO.scala 100:22]
+ reg [3:0] passthruHighIeReg; // @[GPIO.scala 101:30]
+ reg [3:0] passthruLowIeReg; // @[GPIO.scala 102:30]
+ reg [3:0] xorReg; // @[GPIO.scala 109:22]
+ wire [3:0] _rise_T = ~valueReg; // @[GPIO.scala 115:14]
+ wire [3:0] inSyncReg = inSyncReg_inSyncReg_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire [3:0] rise = _rise_T & inSyncReg; // @[GPIO.scala 115:24]
+ wire [3:0] _fall_T = ~inSyncReg; // @[GPIO.scala 116:25]
+ wire [3:0] fall = valueReg & _fall_T; // @[GPIO.scala 116:23]
+ wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [8:0] in_bits_index = bundleIn_0_a_bits_address[11:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire [8:0] out_findex = in_bits_index & 9'h1f0; // @[RegisterRouter.scala 83:24]
+ wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_13 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_15 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_17 = bundleIn_0_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_19 = bundleIn_0_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_21 = bundleIn_0_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_23 = bundleIn_0_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_frontMask = {_out_frontMask_T_23,_out_frontMask_T_21,_out_frontMask_T_19,_out_frontMask_T_17,
+ _out_frontMask_T_15,_out_frontMask_T_13,_out_frontMask_T_11,_out_frontMask_T_9}; // @[Cat.scala 31:58]
+ wire out_wimask = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
+ wire bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [3:0] out_oindex = {in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [15:0] _out_frontSel_T = 16'h1 << out_oindex; // @[OneHot.scala 57:35]
+ wire out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [63:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire out_wimask_1 = &out_frontMask[35:32]; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T = {{28'd0}, valueReg}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend = {ieReg_io_q,_out_prepend_T}; // @[Cat.scala 31:58]
+ wire out_frontSel_5 = _out_frontSel_T[5]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_2 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_5 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_2 = out_wivalid_2 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_3 = out_wivalid_2 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [3:0] _out_highIpReg_T = ~highIpReg; // @[RegField.scala 128:61]
+ wire [3:0] _out_highIpReg_T_1 = out_f_wivalid_3 ? bundleIn_0_a_bits_data[35:32] : 4'h0; // @[RegField.scala 128:71]
+ wire [3:0] _out_highIpReg_T_2 = _out_highIpReg_T | _out_highIpReg_T_1; // @[RegField.scala 128:66]
+ wire [3:0] _out_highIpReg_T_3 = ~_out_highIpReg_T_2; // @[RegField.scala 128:59]
+ wire [3:0] _out_highIpReg_T_4 = _out_highIpReg_T_3 | valueReg; // @[RegField.scala 128:95]
+ wire [31:0] _out_prepend_T_1 = {{28'd0}, highIeReg}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_1 = {highIpReg,_out_prepend_T_1}; // @[Cat.scala 31:58]
+ wire out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [3:0] _out_T_82 = oeReg_io_q; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_6 = out_wivalid_5 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_2 = {{28'd0}, _out_T_82}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_2 = {portReg,_out_prepend_T_2}; // @[Cat.scala 31:58]
+ wire out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_7 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_7 = out_wivalid_7 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_8 = out_wivalid_7 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [3:0] _out_lowIpReg_T = ~lowIpReg; // @[RegField.scala 128:61]
+ wire [3:0] _out_lowIpReg_T_1 = out_f_wivalid_8 ? bundleIn_0_a_bits_data[35:32] : 4'h0; // @[RegField.scala 128:71]
+ wire [3:0] _out_lowIpReg_T_2 = _out_lowIpReg_T | _out_lowIpReg_T_1; // @[RegField.scala 128:66]
+ wire [3:0] _out_lowIpReg_T_3 = ~_out_lowIpReg_T_2; // @[RegField.scala 128:59]
+ wire [3:0] _out_lowIpReg_T_4 = _out_lowIpReg_T_3 | _rise_T; // @[RegField.scala 128:95]
+ wire [31:0] _out_prepend_T_3 = {{28'd0}, lowIeReg}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_3 = {lowIpReg,_out_prepend_T_3}; // @[Cat.scala 31:58]
+ wire out_frontSel_9 = _out_frontSel_T[9]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_9 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_9 = out_wivalid_9 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_4 = {{28'd0}, passthruLowIeReg}; // @[RegisterRouter.scala 83:24]
+ wire [32:0] out_prepend_4 = {1'h0,_out_prepend_T_4}; // @[Cat.scala 31:58]
+ wire [35:0] _out_T_135 = {{3'd0}, out_prepend_4}; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_11 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [3:0] _out_T_146 = pueReg_io_q; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_12 = out_wivalid_11 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_5 = {{28'd0}, _out_T_146}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_5 = {dsReg_0,_out_prepend_T_5}; // @[Cat.scala 31:58]
+ wire out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_15 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_15 = out_wivalid_15 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_16 = out_wivalid_15 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [3:0] _out_riseIpReg_T = ~riseIpReg; // @[RegField.scala 128:61]
+ wire [3:0] _out_riseIpReg_T_1 = out_f_wivalid_16 ? bundleIn_0_a_bits_data[35:32] : 4'h0; // @[RegField.scala 128:71]
+ wire [3:0] _out_riseIpReg_T_2 = _out_riseIpReg_T | _out_riseIpReg_T_1; // @[RegField.scala 128:66]
+ wire [3:0] _out_riseIpReg_T_3 = ~_out_riseIpReg_T_2; // @[RegField.scala 128:59]
+ wire [3:0] _out_riseIpReg_T_4 = _out_riseIpReg_T_3 | rise; // @[RegField.scala 128:95]
+ wire [31:0] _out_prepend_T_7 = {{28'd0}, riseIeReg}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_7 = {riseIpReg,_out_prepend_T_7}; // @[Cat.scala 31:58]
+ wire out_frontSel_8 = _out_frontSel_T[8]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_17 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_8 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_17 = out_wivalid_17 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_18 = out_wivalid_17 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_8 = {{28'd0}, xorReg}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_8 = {passthruHighIeReg,_out_prepend_T_8}; // @[Cat.scala 31:58]
+ wire out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_19 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_19 = out_wivalid_19 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_20 = out_wivalid_19 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [3:0] _out_fallIpReg_T = ~fallIpReg; // @[RegField.scala 128:61]
+ wire [3:0] _out_fallIpReg_T_1 = out_f_wivalid_20 ? bundleIn_0_a_bits_data[35:32] : 4'h0; // @[RegField.scala 128:71]
+ wire [3:0] _out_fallIpReg_T_2 = _out_fallIpReg_T | _out_fallIpReg_T_1; // @[RegField.scala 128:66]
+ wire [3:0] _out_fallIpReg_T_3 = ~_out_fallIpReg_T_2; // @[RegField.scala 128:59]
+ wire [3:0] _out_fallIpReg_T_4 = _out_fallIpReg_T_3 | fall; // @[RegField.scala 128:95]
+ wire [31:0] _out_prepend_T_9 = {{28'd0}, fallIeReg}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_9 = {fallIpReg,_out_prepend_T_9}; // @[Cat.scala 31:58]
+ wire _GEN_74 = 4'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_75 = 4'h2 == out_oindex ? _out_T : _GEN_74; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_76 = 4'h3 == out_oindex ? _out_T : _GEN_75; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_77 = 4'h4 == out_oindex ? _out_T : _GEN_76; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_78 = 4'h5 == out_oindex ? _out_T : _GEN_77; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_79 = 4'h6 == out_oindex ? _out_T : _GEN_78; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_80 = 4'h7 == out_oindex ? _out_T : _GEN_79; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_81 = 4'h8 == out_oindex ? _out_T : _GEN_80; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_82 = 4'h9 == out_oindex ? _out_T : _GEN_81; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_83 = 4'ha == out_oindex ? _out_T : _GEN_82; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_88 = 4'hf == out_oindex | (4'he == out_oindex | (4'hd == out_oindex | (4'hc == out_oindex | (4'hb ==
+ out_oindex | _GEN_83)))); // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_90 = 4'h1 == out_oindex ? out_prepend_2 : out_prepend; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_91 = 4'h2 == out_oindex ? out_prepend_5 : _GEN_90; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_92 = 4'h3 == out_oindex ? out_prepend_7 : _GEN_91; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_93 = 4'h4 == out_oindex ? out_prepend_9 : _GEN_92; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_94 = 4'h5 == out_oindex ? out_prepend_1 : _GEN_93; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_95 = 4'h6 == out_oindex ? out_prepend_3 : _GEN_94; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_96 = 4'h7 == out_oindex ? 36'h0 : _GEN_95; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_97 = 4'h8 == out_oindex ? out_prepend_8 : _GEN_96; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_98 = 4'h9 == out_oindex ? _out_T_135 : _GEN_97; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_99 = 4'ha == out_oindex ? 36'h0 : _GEN_98; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_100 = 4'hb == out_oindex ? 36'h0 : _GEN_99; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_101 = 4'hc == out_oindex ? 36'h0 : _GEN_100; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_102 = 4'hd == out_oindex ? 36'h0 : _GEN_101; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_103 = 4'he == out_oindex ? 36'h0 : _GEN_102; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _GEN_104 = 4'hf == out_oindex ? 36'h0 : _GEN_103; // @[MuxLiteral.scala 48:{10,10}]
+ wire [35:0] _out_out_bits_data_T_4 = _GEN_88 ? _GEN_104 : 36'h0; // @[RegisterRouter.scala 83:24]
+ wire swPinCtrl_0_oval = portReg[0]; // @[GPIO.scala 199:37]
+ wire _bundleOut_0_0_T_5 = fallIpReg[0] & fallIeReg[0]; // @[GPIO.scala 239:42]
+ wire _bundleOut_0_0_T_6 = riseIpReg[0] & riseIeReg[0] | _bundleOut_0_0_T_5; // @[GPIO.scala 238:58]
+ wire _bundleOut_0_0_T_9 = highIpReg[0] & highIeReg[0]; // @[GPIO.scala 240:42]
+ wire _bundleOut_0_0_T_10 = _bundleOut_0_0_T_6 | _bundleOut_0_0_T_9; // @[GPIO.scala 239:60]
+ wire _bundleOut_0_0_T_13 = lowIpReg[0] & lowIeReg[0]; // @[GPIO.scala 241:41]
+ wire _bundleOut_0_0_T_14 = _bundleOut_0_0_T_10 | _bundleOut_0_0_T_13; // @[GPIO.scala 240:60]
+ wire _bundleOut_0_0_T_17 = valueReg[0] & passthruHighIeReg[0]; // @[GPIO.scala 242:41]
+ wire _bundleOut_0_0_T_18 = _bundleOut_0_0_T_14 | _bundleOut_0_0_T_17; // @[GPIO.scala 241:58]
+ wire _bundleOut_0_0_T_22 = ~valueReg[0] & passthruLowIeReg[0]; // @[GPIO.scala 243:42]
+ wire swPinCtrl_1_oval = portReg[1]; // @[GPIO.scala 199:37]
+ wire _bundleOut_0_1_T_5 = fallIpReg[1] & fallIeReg[1]; // @[GPIO.scala 239:42]
+ wire _bundleOut_0_1_T_6 = riseIpReg[1] & riseIeReg[1] | _bundleOut_0_1_T_5; // @[GPIO.scala 238:58]
+ wire _bundleOut_0_1_T_9 = highIpReg[1] & highIeReg[1]; // @[GPIO.scala 240:42]
+ wire _bundleOut_0_1_T_10 = _bundleOut_0_1_T_6 | _bundleOut_0_1_T_9; // @[GPIO.scala 239:60]
+ wire _bundleOut_0_1_T_13 = lowIpReg[1] & lowIeReg[1]; // @[GPIO.scala 241:41]
+ wire _bundleOut_0_1_T_14 = _bundleOut_0_1_T_10 | _bundleOut_0_1_T_13; // @[GPIO.scala 240:60]
+ wire _bundleOut_0_1_T_17 = valueReg[1] & passthruHighIeReg[1]; // @[GPIO.scala 242:41]
+ wire _bundleOut_0_1_T_18 = _bundleOut_0_1_T_14 | _bundleOut_0_1_T_17; // @[GPIO.scala 241:58]
+ wire _bundleOut_0_1_T_22 = ~valueReg[1] & passthruLowIeReg[1]; // @[GPIO.scala 243:42]
+ wire swPinCtrl_2_oval = portReg[2]; // @[GPIO.scala 199:37]
+ wire _bundleOut_0_2_T_5 = fallIpReg[2] & fallIeReg[2]; // @[GPIO.scala 239:42]
+ wire _bundleOut_0_2_T_6 = riseIpReg[2] & riseIeReg[2] | _bundleOut_0_2_T_5; // @[GPIO.scala 238:58]
+ wire _bundleOut_0_2_T_9 = highIpReg[2] & highIeReg[2]; // @[GPIO.scala 240:42]
+ wire _bundleOut_0_2_T_10 = _bundleOut_0_2_T_6 | _bundleOut_0_2_T_9; // @[GPIO.scala 239:60]
+ wire _bundleOut_0_2_T_13 = lowIpReg[2] & lowIeReg[2]; // @[GPIO.scala 241:41]
+ wire _bundleOut_0_2_T_14 = _bundleOut_0_2_T_10 | _bundleOut_0_2_T_13; // @[GPIO.scala 240:60]
+ wire _bundleOut_0_2_T_17 = valueReg[2] & passthruHighIeReg[2]; // @[GPIO.scala 242:41]
+ wire _bundleOut_0_2_T_18 = _bundleOut_0_2_T_14 | _bundleOut_0_2_T_17; // @[GPIO.scala 241:58]
+ wire _bundleOut_0_2_T_22 = ~valueReg[2] & passthruLowIeReg[2]; // @[GPIO.scala 243:42]
+ wire swPinCtrl_3_oval = portReg[3]; // @[GPIO.scala 199:37]
+ wire _bundleOut_0_3_T_5 = fallIpReg[3] & fallIeReg[3]; // @[GPIO.scala 239:42]
+ wire _bundleOut_0_3_T_6 = riseIpReg[3] & riseIeReg[3] | _bundleOut_0_3_T_5; // @[GPIO.scala 238:58]
+ wire _bundleOut_0_3_T_9 = highIpReg[3] & highIeReg[3]; // @[GPIO.scala 240:42]
+ wire _bundleOut_0_3_T_10 = _bundleOut_0_3_T_6 | _bundleOut_0_3_T_9; // @[GPIO.scala 239:60]
+ wire _bundleOut_0_3_T_13 = lowIpReg[3] & lowIeReg[3]; // @[GPIO.scala 241:41]
+ wire _bundleOut_0_3_T_14 = _bundleOut_0_3_T_10 | _bundleOut_0_3_T_13; // @[GPIO.scala 240:60]
+ wire _bundleOut_0_3_T_17 = valueReg[3] & passthruHighIeReg[3]; // @[GPIO.scala 242:41]
+ wire _bundleOut_0_3_T_18 = _bundleOut_0_3_T_14 | _bundleOut_0_3_T_17; // @[GPIO.scala 241:58]
+ wire _bundleOut_0_3_T_22 = ~valueReg[3] & passthruLowIeReg[3]; // @[GPIO.scala 243:42]
+ TLBuffer_20 buffer ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ IntSyncCrossingSource_9 intsource ( // @[Crossing.scala 26:31]
+ .clock(intsource_clock),
+ .reset(intsource_reset),
+ .auto_in_0(intsource_auto_in_0),
+ .auto_in_1(intsource_auto_in_1),
+ .auto_in_2(intsource_auto_in_2),
+ .auto_in_3(intsource_auto_in_3),
+ .auto_out_sync_0(intsource_auto_out_sync_0),
+ .auto_out_sync_1(intsource_auto_out_sync_1),
+ .auto_out_sync_2(intsource_auto_out_sync_2),
+ .auto_out_sync_3(intsource_auto_out_sync_3)
+ );
+ TLMonitor_57 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ AsyncResetRegVec_w4_i0 oeReg ( // @[GPIO.scala 79:22]
+ .clock(oeReg_clock),
+ .reset(oeReg_reset),
+ .io_d(oeReg_io_d),
+ .io_q(oeReg_io_q),
+ .io_en(oeReg_io_en)
+ );
+ AsyncResetRegVec_w4_i0 pueReg ( // @[GPIO.scala 80:22]
+ .clock(pueReg_clock),
+ .reset(pueReg_reset),
+ .io_d(pueReg_io_d),
+ .io_q(pueReg_io_q),
+ .io_en(pueReg_io_en)
+ );
+ AsyncResetRegVec_w4_i0 ieReg ( // @[GPIO.scala 82:22]
+ .clock(ieReg_clock),
+ .reset(ieReg_reset),
+ .io_d(ieReg_io_d),
+ .io_q(ieReg_io_q),
+ .io_en(ieReg_io_en)
+ );
+ AsyncResetRegVec_w4_i0 poeReg ( // @[GPIO.scala 84:22]
+ .clock(poeReg_clock),
+ .reset(poeReg_reset),
+ .io_d(poeReg_io_d),
+ .io_q(poeReg_io_q),
+ .io_en(poeReg_io_en)
+ );
+ SynchronizerShiftReg_w4_d3 inSyncReg_inSyncReg ( // @[ShiftReg.scala 45:23]
+ .clock(inSyncReg_inSyncReg_clock),
+ .io_d(inSyncReg_inSyncReg_io_d),
+ .io_q(inSyncReg_inSyncReg_io_q)
+ );
+ AsyncResetRegVec_w4_i0 iofEnReg ( // @[GPIO.scala 105:25]
+ .clock(iofEnReg_clock),
+ .reset(iofEnReg_reset),
+ .io_d(iofEnReg_io_d),
+ .io_q(iofEnReg_io_q),
+ .io_en(iofEnReg_io_en)
+ );
+ assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_int_xing_out_sync_1 = intsource_auto_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_int_xing_out_sync_2 = intsource_auto_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_int_xing_out_sync_3 = intsource_auto_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_io_out_pins_0_o_oval = swPinCtrl_0_oval ^ xorReg[0]; // @[GPIO.scala 235:43]
+ assign auto_io_out_pins_0_o_oe = oeReg_io_q[0]; // @[GPIO.scala 200:40]
+ assign auto_io_out_pins_0_o_ie = ieReg_io_q[0]; // @[GPIO.scala 202:40]
+ assign auto_io_out_pins_1_o_oval = swPinCtrl_1_oval ^ xorReg[1]; // @[GPIO.scala 235:43]
+ assign auto_io_out_pins_1_o_oe = oeReg_io_q[1]; // @[GPIO.scala 200:40]
+ assign auto_io_out_pins_1_o_ie = ieReg_io_q[1]; // @[GPIO.scala 202:40]
+ assign auto_io_out_pins_2_o_oval = swPinCtrl_2_oval ^ xorReg[2]; // @[GPIO.scala 235:43]
+ assign auto_io_out_pins_2_o_oe = oeReg_io_q[2]; // @[GPIO.scala 200:40]
+ assign auto_io_out_pins_2_o_ie = ieReg_io_q[2]; // @[GPIO.scala 202:40]
+ assign auto_io_out_pins_3_o_oval = swPinCtrl_3_oval ^ xorReg[3]; // @[GPIO.scala 235:43]
+ assign auto_io_out_pins_3_o_oe = oeReg_io_q[3]; // @[GPIO.scala 200:40]
+ assign auto_io_out_pins_3_o_ie = ieReg_io_q[3]; // @[GPIO.scala 202:40]
+ assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = {{28'd0}, _out_out_bits_data_T_4}; // @[RegisterRouter.scala 83:{24,24}]
+ assign intsource_clock = clock;
+ assign intsource_reset = reset;
+ assign intsource_auto_in_0 = _bundleOut_0_0_T_18 | _bundleOut_0_0_T_22; // @[GPIO.scala 242:67]
+ assign intsource_auto_in_1 = _bundleOut_0_1_T_18 | _bundleOut_0_1_T_22; // @[GPIO.scala 242:67]
+ assign intsource_auto_in_2 = _bundleOut_0_2_T_18 | _bundleOut_0_2_T_22; // @[GPIO.scala 242:67]
+ assign intsource_auto_in_3 = _bundleOut_0_3_T_18 | _bundleOut_0_3_T_22; // @[GPIO.scala 242:67]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign oeReg_clock = clock;
+ assign oeReg_reset = reset;
+ assign oeReg_io_d = bundleIn_0_a_bits_data[3:0]; // @[RegisterRouter.scala 83:24]
+ assign oeReg_io_en = out_wivalid_5 & out_wimask; // @[RegisterRouter.scala 83:24]
+ assign pueReg_clock = clock;
+ assign pueReg_reset = reset;
+ assign pueReg_io_d = bundleIn_0_a_bits_data[3:0]; // @[RegisterRouter.scala 83:24]
+ assign pueReg_io_en = out_wivalid_11 & out_wimask; // @[RegisterRouter.scala 83:24]
+ assign ieReg_clock = clock;
+ assign ieReg_reset = reset;
+ assign ieReg_io_d = bundleIn_0_a_bits_data[35:32]; // @[RegisterRouter.scala 83:24]
+ assign ieReg_io_en = out_wivalid_0 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ assign poeReg_clock = clock;
+ assign poeReg_reset = reset;
+ assign poeReg_io_d = 4'h0;
+ assign poeReg_io_en = 1'h0;
+ assign inSyncReg_inSyncReg_clock = clock;
+ assign inSyncReg_inSyncReg_io_d = {inVal_hi,inVal_lo}; // @[GPIO.scala 88:41]
+ assign iofEnReg_clock = clock;
+ assign iofEnReg_reset = reset;
+ assign iofEnReg_io_d = 4'h0;
+ assign iofEnReg_io_en = 1'h0;
+ always @(posedge clock) begin
+ if (reset) begin // @[GPIO.scala 77:20]
+ portReg <= 4'h0; // @[GPIO.scala 77:20]
+ end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
+ portReg <= bundleIn_0_a_bits_data[35:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[GPIO.scala 81:23]
+ dsReg_0 <= 4'h0; // @[GPIO.scala 81:23]
+ end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
+ dsReg_0 <= bundleIn_0_a_bits_data[35:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[GPIO.scala 90:23]
+ valueReg <= 4'h0; // @[GPIO.scala 90:23]
+ end else begin
+ valueReg <= inSyncReg; // @[GPIO.scala 90:23]
+ end
+ if (reset) begin // @[GPIO.scala 93:22]
+ highIeReg <= 4'h0; // @[GPIO.scala 93:22]
+ end else if (out_f_wivalid_2) begin // @[RegField.scala 74:88]
+ highIeReg <= bundleIn_0_a_bits_data[3:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[GPIO.scala 94:22]
+ lowIeReg <= 4'h0; // @[GPIO.scala 94:22]
+ end else if (out_f_wivalid_7) begin // @[RegField.scala 74:88]
+ lowIeReg <= bundleIn_0_a_bits_data[3:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[GPIO.scala 95:22]
+ riseIeReg <= 4'h0; // @[GPIO.scala 95:22]
+ end else if (out_f_wivalid_15) begin // @[RegField.scala 74:88]
+ riseIeReg <= bundleIn_0_a_bits_data[3:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[GPIO.scala 96:22]
+ fallIeReg <= 4'h0; // @[GPIO.scala 96:22]
+ end else if (out_f_wivalid_19) begin // @[RegField.scala 74:88]
+ fallIeReg <= bundleIn_0_a_bits_data[3:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[GPIO.scala 97:22]
+ highIpReg <= 4'h0; // @[GPIO.scala 97:22]
+ end else begin
+ highIpReg <= _out_highIpReg_T_4; // @[RegField.scala 128:56]
+ end
+ if (reset) begin // @[GPIO.scala 98:22]
+ lowIpReg <= 4'h0; // @[GPIO.scala 98:22]
+ end else begin
+ lowIpReg <= _out_lowIpReg_T_4; // @[RegField.scala 128:56]
+ end
+ if (reset) begin // @[GPIO.scala 99:22]
+ riseIpReg <= 4'h0; // @[GPIO.scala 99:22]
+ end else begin
+ riseIpReg <= _out_riseIpReg_T_4; // @[RegField.scala 128:56]
+ end
+ if (reset) begin // @[GPIO.scala 100:22]
+ fallIpReg <= 4'h0; // @[GPIO.scala 100:22]
+ end else begin
+ fallIpReg <= _out_fallIpReg_T_4; // @[RegField.scala 128:56]
+ end
+ if (reset) begin // @[GPIO.scala 101:30]
+ passthruHighIeReg <= 4'h0; // @[GPIO.scala 101:30]
+ end else if (out_f_wivalid_18) begin // @[RegField.scala 74:88]
+ passthruHighIeReg <= bundleIn_0_a_bits_data[35:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[GPIO.scala 102:30]
+ passthruLowIeReg <= 4'h0; // @[GPIO.scala 102:30]
+ end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
+ passthruLowIeReg <= bundleIn_0_a_bits_data[3:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[GPIO.scala 109:22]
+ xorReg <= 4'h0; // @[GPIO.scala 109:22]
+ end else if (out_f_wivalid_17) begin // @[RegField.scala 74:88]
+ xorReg <= bundleIn_0_a_bits_data[3:0]; // @[RegField.scala 74:92]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ portReg = _RAND_0[3:0];
+ _RAND_1 = {1{`RANDOM}};
+ dsReg_0 = _RAND_1[3:0];
+ _RAND_2 = {1{`RANDOM}};
+ valueReg = _RAND_2[3:0];
+ _RAND_3 = {1{`RANDOM}};
+ highIeReg = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ lowIeReg = _RAND_4[3:0];
+ _RAND_5 = {1{`RANDOM}};
+ riseIeReg = _RAND_5[3:0];
+ _RAND_6 = {1{`RANDOM}};
+ fallIeReg = _RAND_6[3:0];
+ _RAND_7 = {1{`RANDOM}};
+ highIpReg = _RAND_7[3:0];
+ _RAND_8 = {1{`RANDOM}};
+ lowIpReg = _RAND_8[3:0];
+ _RAND_9 = {1{`RANDOM}};
+ riseIpReg = _RAND_9[3:0];
+ _RAND_10 = {1{`RANDOM}};
+ fallIpReg = _RAND_10[3:0];
+ _RAND_11 = {1{`RANDOM}};
+ passthruHighIeReg = _RAND_11[3:0];
+ _RAND_12 = {1{`RANDOM}};
+ passthruLowIeReg = _RAND_12[3:0];
+ _RAND_13 = {1{`RANDOM}};
+ xorReg = _RAND_13[3:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockSinkDomain_5(
+ output auto_gpio_0_int_xing_out_sync_0,
+ output auto_gpio_0_int_xing_out_sync_1,
+ output auto_gpio_0_int_xing_out_sync_2,
+ output auto_gpio_0_int_xing_out_sync_3,
+ output auto_gpio_0_control_xing_in_a_ready,
+ input auto_gpio_0_control_xing_in_a_valid,
+ input [2:0] auto_gpio_0_control_xing_in_a_bits_opcode,
+ input [2:0] auto_gpio_0_control_xing_in_a_bits_param,
+ input [1:0] auto_gpio_0_control_xing_in_a_bits_size,
+ input [6:0] auto_gpio_0_control_xing_in_a_bits_source,
+ input [28:0] auto_gpio_0_control_xing_in_a_bits_address,
+ input [7:0] auto_gpio_0_control_xing_in_a_bits_mask,
+ input [63:0] auto_gpio_0_control_xing_in_a_bits_data,
+ input auto_gpio_0_control_xing_in_a_bits_corrupt,
+ input auto_gpio_0_control_xing_in_d_ready,
+ output auto_gpio_0_control_xing_in_d_valid,
+ output [2:0] auto_gpio_0_control_xing_in_d_bits_opcode,
+ output [1:0] auto_gpio_0_control_xing_in_d_bits_size,
+ output [6:0] auto_gpio_0_control_xing_in_d_bits_source,
+ output [63:0] auto_gpio_0_control_xing_in_d_bits_data,
+ input auto_gpio_0_io_out_pins_0_i_ival,
+ output auto_gpio_0_io_out_pins_0_o_oval,
+ output auto_gpio_0_io_out_pins_0_o_oe,
+ output auto_gpio_0_io_out_pins_0_o_ie,
+ input auto_gpio_0_io_out_pins_1_i_ival,
+ output auto_gpio_0_io_out_pins_1_o_oval,
+ output auto_gpio_0_io_out_pins_1_o_oe,
+ output auto_gpio_0_io_out_pins_1_o_ie,
+ input auto_gpio_0_io_out_pins_2_i_ival,
+ output auto_gpio_0_io_out_pins_2_o_oval,
+ output auto_gpio_0_io_out_pins_2_o_oe,
+ output auto_gpio_0_io_out_pins_2_o_ie,
+ input auto_gpio_0_io_out_pins_3_i_ival,
+ output auto_gpio_0_io_out_pins_3_o_oval,
+ output auto_gpio_0_io_out_pins_3_o_oe,
+ output auto_gpio_0_io_out_pins_3_o_ie,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire gpio_0_clock; // @[GPIO.scala 282:51]
+ wire gpio_0_reset; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_int_xing_out_sync_0; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_int_xing_out_sync_1; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_int_xing_out_sync_2; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_int_xing_out_sync_3; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_control_xing_in_a_ready; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_control_xing_in_a_valid; // @[GPIO.scala 282:51]
+ wire [2:0] gpio_0_auto_control_xing_in_a_bits_opcode; // @[GPIO.scala 282:51]
+ wire [2:0] gpio_0_auto_control_xing_in_a_bits_param; // @[GPIO.scala 282:51]
+ wire [1:0] gpio_0_auto_control_xing_in_a_bits_size; // @[GPIO.scala 282:51]
+ wire [6:0] gpio_0_auto_control_xing_in_a_bits_source; // @[GPIO.scala 282:51]
+ wire [28:0] gpio_0_auto_control_xing_in_a_bits_address; // @[GPIO.scala 282:51]
+ wire [7:0] gpio_0_auto_control_xing_in_a_bits_mask; // @[GPIO.scala 282:51]
+ wire [63:0] gpio_0_auto_control_xing_in_a_bits_data; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_control_xing_in_a_bits_corrupt; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_control_xing_in_d_ready; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_control_xing_in_d_valid; // @[GPIO.scala 282:51]
+ wire [2:0] gpio_0_auto_control_xing_in_d_bits_opcode; // @[GPIO.scala 282:51]
+ wire [1:0] gpio_0_auto_control_xing_in_d_bits_size; // @[GPIO.scala 282:51]
+ wire [6:0] gpio_0_auto_control_xing_in_d_bits_source; // @[GPIO.scala 282:51]
+ wire [63:0] gpio_0_auto_control_xing_in_d_bits_data; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_0_i_ival; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_0_o_oval; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_0_o_oe; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_0_o_ie; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_1_i_ival; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_1_o_oval; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_1_o_oe; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_1_o_ie; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_2_i_ival; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_2_o_oval; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_2_o_oe; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_2_o_ie; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_3_i_ival; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_3_o_oval; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_3_o_oe; // @[GPIO.scala 282:51]
+ wire gpio_0_auto_io_out_pins_3_o_ie; // @[GPIO.scala 282:51]
+ TLGPIO gpio_0 ( // @[GPIO.scala 282:51]
+ .clock(gpio_0_clock),
+ .reset(gpio_0_reset),
+ .auto_int_xing_out_sync_0(gpio_0_auto_int_xing_out_sync_0),
+ .auto_int_xing_out_sync_1(gpio_0_auto_int_xing_out_sync_1),
+ .auto_int_xing_out_sync_2(gpio_0_auto_int_xing_out_sync_2),
+ .auto_int_xing_out_sync_3(gpio_0_auto_int_xing_out_sync_3),
+ .auto_control_xing_in_a_ready(gpio_0_auto_control_xing_in_a_ready),
+ .auto_control_xing_in_a_valid(gpio_0_auto_control_xing_in_a_valid),
+ .auto_control_xing_in_a_bits_opcode(gpio_0_auto_control_xing_in_a_bits_opcode),
+ .auto_control_xing_in_a_bits_param(gpio_0_auto_control_xing_in_a_bits_param),
+ .auto_control_xing_in_a_bits_size(gpio_0_auto_control_xing_in_a_bits_size),
+ .auto_control_xing_in_a_bits_source(gpio_0_auto_control_xing_in_a_bits_source),
+ .auto_control_xing_in_a_bits_address(gpio_0_auto_control_xing_in_a_bits_address),
+ .auto_control_xing_in_a_bits_mask(gpio_0_auto_control_xing_in_a_bits_mask),
+ .auto_control_xing_in_a_bits_data(gpio_0_auto_control_xing_in_a_bits_data),
+ .auto_control_xing_in_a_bits_corrupt(gpio_0_auto_control_xing_in_a_bits_corrupt),
+ .auto_control_xing_in_d_ready(gpio_0_auto_control_xing_in_d_ready),
+ .auto_control_xing_in_d_valid(gpio_0_auto_control_xing_in_d_valid),
+ .auto_control_xing_in_d_bits_opcode(gpio_0_auto_control_xing_in_d_bits_opcode),
+ .auto_control_xing_in_d_bits_size(gpio_0_auto_control_xing_in_d_bits_size),
+ .auto_control_xing_in_d_bits_source(gpio_0_auto_control_xing_in_d_bits_source),
+ .auto_control_xing_in_d_bits_data(gpio_0_auto_control_xing_in_d_bits_data),
+ .auto_io_out_pins_0_i_ival(gpio_0_auto_io_out_pins_0_i_ival),
+ .auto_io_out_pins_0_o_oval(gpio_0_auto_io_out_pins_0_o_oval),
+ .auto_io_out_pins_0_o_oe(gpio_0_auto_io_out_pins_0_o_oe),
+ .auto_io_out_pins_0_o_ie(gpio_0_auto_io_out_pins_0_o_ie),
+ .auto_io_out_pins_1_i_ival(gpio_0_auto_io_out_pins_1_i_ival),
+ .auto_io_out_pins_1_o_oval(gpio_0_auto_io_out_pins_1_o_oval),
+ .auto_io_out_pins_1_o_oe(gpio_0_auto_io_out_pins_1_o_oe),
+ .auto_io_out_pins_1_o_ie(gpio_0_auto_io_out_pins_1_o_ie),
+ .auto_io_out_pins_2_i_ival(gpio_0_auto_io_out_pins_2_i_ival),
+ .auto_io_out_pins_2_o_oval(gpio_0_auto_io_out_pins_2_o_oval),
+ .auto_io_out_pins_2_o_oe(gpio_0_auto_io_out_pins_2_o_oe),
+ .auto_io_out_pins_2_o_ie(gpio_0_auto_io_out_pins_2_o_ie),
+ .auto_io_out_pins_3_i_ival(gpio_0_auto_io_out_pins_3_i_ival),
+ .auto_io_out_pins_3_o_oval(gpio_0_auto_io_out_pins_3_o_oval),
+ .auto_io_out_pins_3_o_oe(gpio_0_auto_io_out_pins_3_o_oe),
+ .auto_io_out_pins_3_o_ie(gpio_0_auto_io_out_pins_3_o_ie)
+ );
+ assign auto_gpio_0_int_xing_out_sync_0 = gpio_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_int_xing_out_sync_1 = gpio_0_auto_int_xing_out_sync_1; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_int_xing_out_sync_2 = gpio_0_auto_int_xing_out_sync_2; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_int_xing_out_sync_3 = gpio_0_auto_int_xing_out_sync_3; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_control_xing_in_a_ready = gpio_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_gpio_0_control_xing_in_d_valid = gpio_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_gpio_0_control_xing_in_d_bits_opcode = gpio_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_gpio_0_control_xing_in_d_bits_size = gpio_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_gpio_0_control_xing_in_d_bits_source = gpio_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_gpio_0_control_xing_in_d_bits_data = gpio_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_gpio_0_io_out_pins_0_o_oval = gpio_0_auto_io_out_pins_0_o_oval; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_0_o_oe = gpio_0_auto_io_out_pins_0_o_oe; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_0_o_ie = gpio_0_auto_io_out_pins_0_o_ie; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_1_o_oval = gpio_0_auto_io_out_pins_1_o_oval; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_1_o_oe = gpio_0_auto_io_out_pins_1_o_oe; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_1_o_ie = gpio_0_auto_io_out_pins_1_o_ie; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_2_o_oval = gpio_0_auto_io_out_pins_2_o_oval; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_2_o_oe = gpio_0_auto_io_out_pins_2_o_oe; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_2_o_ie = gpio_0_auto_io_out_pins_2_o_ie; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_3_o_oval = gpio_0_auto_io_out_pins_3_o_oval; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_3_o_oe = gpio_0_auto_io_out_pins_3_o_oe; // @[LazyModule.scala 311:12]
+ assign auto_gpio_0_io_out_pins_3_o_ie = gpio_0_auto_io_out_pins_3_o_ie; // @[LazyModule.scala 311:12]
+ assign gpio_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gpio_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_valid = auto_gpio_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_bits_opcode = auto_gpio_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_bits_param = auto_gpio_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_bits_size = auto_gpio_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_bits_source = auto_gpio_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_bits_address = auto_gpio_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_bits_mask = auto_gpio_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_bits_data = auto_gpio_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_a_bits_corrupt = auto_gpio_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_control_xing_in_d_ready = auto_gpio_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
+ assign gpio_0_auto_io_out_pins_0_i_ival = auto_gpio_0_io_out_pins_0_i_ival; // @[LazyModule.scala 311:12]
+ assign gpio_0_auto_io_out_pins_1_i_ival = auto_gpio_0_io_out_pins_1_i_ival; // @[LazyModule.scala 311:12]
+ assign gpio_0_auto_io_out_pins_2_i_ival = auto_gpio_0_io_out_pins_2_i_ival; // @[LazyModule.scala 311:12]
+ assign gpio_0_auto_io_out_pins_3_i_ival = auto_gpio_0_io_out_pins_3_i_ival; // @[LazyModule.scala 311:12]
+endmodule
+module IntSyncSyncCrossingSink_8(
+ input auto_in_sync_0,
+ input auto_in_sync_1,
+ input auto_in_sync_2,
+ input auto_in_sync_3,
+ output auto_out_0,
+ output auto_out_1,
+ output auto_out_2,
+ output auto_out_3
+);
+ assign auto_out_0 = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1 = auto_in_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2 = auto_in_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3 = auto_in_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLBuffer_24(
+ output auto_in_a_ready,
+ input auto_in_a_valid,
+ input [2:0] auto_in_a_bits_opcode,
+ input [2:0] auto_in_a_bits_param,
+ input auto_in_a_bits_size,
+ input [9:0] auto_in_a_bits_source,
+ input [29:0] auto_in_a_bits_address,
+ input auto_in_a_bits_mask,
+ input auto_in_a_bits_corrupt,
+ input auto_in_d_ready,
+ output auto_in_d_valid,
+ output auto_in_d_bits_size,
+ output [9:0] auto_in_d_bits_source,
+ output [7:0] auto_in_d_bits_data,
+ input auto_out_a_ready,
+ output auto_out_a_valid,
+ output [2:0] auto_out_a_bits_opcode,
+ output [2:0] auto_out_a_bits_param,
+ output auto_out_a_bits_size,
+ output [9:0] auto_out_a_bits_source,
+ output [29:0] auto_out_a_bits_address,
+ output auto_out_a_bits_mask,
+ output auto_out_a_bits_corrupt,
+ output auto_out_d_ready,
+ input auto_out_d_valid,
+ input auto_out_d_bits_size,
+ input [9:0] auto_out_d_bits_source,
+ input [7:0] auto_out_d_bits_data
+);
+ assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module TLMonitor_58(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input io_in_a_bits_size,
+ input [9:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input io_in_d_bits_size,
+ input [9:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [639:0] _RAND_9;
+ reg [2559:0] _RAND_10;
+ reg [1279:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 10'h27f; // @[Parameters.scala 57:20]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_33 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_36 = $signed(_T_34) & -31'sh10000000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_163 = ~io_in_a_bits_size; // @[Parameters.scala 91:48]
+ wire _T_170 = _T_163 & _T_37; // @[Parameters.scala 670:56]
+ wire _T_181 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_193 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_231 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_271 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_301 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_309 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_339 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_347 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_377 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 10'h27f; // @[Parameters.scala 57:20]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg size; // @[Monitor.scala 386:22]
+ reg [9:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_535 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_536 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_540 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_544 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_548 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_552 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg size_1; // @[Monitor.scala 537:22]
+ reg [9:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_559 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_572 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [639:0] inflight; // @[Monitor.scala 611:27]
+ reg [2559:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [1279:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [11:0] _GEN_71 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [12:0] _a_opcode_lookup_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 634:69]
+ wire [2559:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [2559:0] _GEN_72 = {{2544'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [2559:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_72; // @[Monitor.scala 634:97]
+ wire [2559:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[2559:1]}; // @[Monitor.scala 634:152]
+ wire [10:0] _a_size_lookup_T = {io_in_d_bits_source, 1'h0}; // @[Monitor.scala 638:65]
+ wire [1279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [3:0] _a_size_lookup_T_5 = 4'h4 - 4'h1; // @[Monitor.scala 609:57]
+ wire [1279:0] _GEN_74 = {{1276'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [1279:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_74; // @[Monitor.scala 638:91]
+ wire [1279:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[1279:1]}; // @[Monitor.scala 638:144]
+ wire _T_586 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1023:0] _a_set_wo_ready_T = 1024'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_589 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [1:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [1:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 2'h1; // @[Monitor.scala 655:59]
+ wire [11:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [12:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [8194:0] _GEN_1 = {{8191'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [8194:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [10:0] _a_sizes_set_T = {io_in_a_bits_source, 1'h0}; // @[Monitor.scala 657:77]
+ wire [1:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 2'h0; // @[Monitor.scala 652:72 655:28]
+ wire [2048:0] _GEN_2 = {{2047'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [2048:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [639:0] _T_591 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_593 = ~_T_591[0]; // @[Monitor.scala 658:17]
+ wire [1023:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 1024'h0; // @[Monitor.scala 652:72 653:28]
+ wire [8194:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 8195'h0; // @[Monitor.scala 652:72 656:28]
+ wire [2048:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 2049'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_597 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [1023:0] _d_clr_wo_ready_T = 1024'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [8206:0] _GEN_3 = {{8191'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [8206:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [2050:0] _GEN_4 = {{2047'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [2050:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [1023:0] _GEN_22 = d_first_done & d_first_1 ? _d_clr_wo_ready_T : 1024'h0; // @[Monitor.scala 675:91 676:21]
+ wire [8206:0] _GEN_23 = d_first_done & d_first_1 ? _d_opcodes_clr_T_5 : 8207'h0; // @[Monitor.scala 675:91 677:21]
+ wire [2050:0] _GEN_24 = d_first_done & d_first_1 ? _d_sizes_clr_T_5 : 2051'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_586 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [639:0] _T_610 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_612 = _T_610[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_617 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_618 = 3'h1 == _GEN_32 | _T_617; // @[Monitor.scala 685:77]
+ wire _T_622 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_629 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_630 = 3'h1 == _GEN_48 | _T_629; // @[Monitor.scala 689:72]
+ wire [1:0] a_size_lookup = _a_size_lookup_T_7[1:0];
+ wire [1:0] _GEN_78 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_634 = _GEN_78 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_642 = _T_597 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_646 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [639:0] a_set = _GEN_16[639:0];
+ wire [639:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [639:0] d_clr = _GEN_22[639:0];
+ wire [639:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [639:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [2559:0] a_opcodes_set = _GEN_19[2559:0];
+ wire [2559:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [2559:0] d_opcodes_clr = _GEN_23[2559:0];
+ wire [2559:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [2559:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [1279:0] a_sizes_set = _GEN_20[1279:0];
+ wire [1279:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [1279:0] d_sizes_clr = _GEN_24[1279:0];
+ wire [1279:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [1279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_655 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 640'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 2560'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 1280'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_170 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_170) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_181 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_181) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_193 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_181 & (io_in_a_valid & _T_193 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset & ~_T_181) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_193 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_231 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_231 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_231 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_231 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_181 & (io_in_a_valid & _T_231 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_231 & ~reset & ~_T_181) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_301 & (io_in_a_valid & _T_271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset & ~_T_301) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_309 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_339 & (io_in_a_valid & _T_309 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset & ~_T_339) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_309 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_347 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_377 & (io_in_a_valid & _T_347 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset & ~_T_377) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_347 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_347 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_536 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_536) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_540 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_540) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_559 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_559 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_559 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_559 & _T_2 & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_593 & (_T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_589 & ~reset & ~_T_593) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_612 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_612) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (_T_597 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & same_cycle_resp & _T_2 & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_622 & (_T_597 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & same_cycle_resp & _T_2 & ~_T_622) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_597 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_634 & (_T_597 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~same_cycle_resp & _T_2 & ~_T_634) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (_T_642 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_642 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_655 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_655) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[9:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[9:0];
+ _RAND_9 = {20{`RANDOM}};
+ inflight = _RAND_9[639:0];
+ _RAND_10 = {80{`RANDOM}};
+ inflight_opcodes = _RAND_10[2559:0];
+ _RAND_11 = {40{`RANDOM}};
+ inflight_sizes = _RAND_11[1279:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_59(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{26'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10013000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module QueueCompatibility_4(
+ input clock,
+ input reset,
+ output io_enq_ready,
+ input io_enq_valid,
+ input [7:0] io_enq_bits,
+ input io_deq_ready,
+ output io_deq_valid,
+ output [7:0] io_deq_bits,
+ output [3:0] io_count
+);
+`ifdef RANDOMIZE_MEM_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+`endif // RANDOMIZE_REG_INIT
+ reg [7:0] ram [0:7]; // @[Decoupled.scala 259:95]
+ wire ram_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [7:0] ram_MPORT_data; // @[Decoupled.scala 259:95]
+ wire [2:0] ram_MPORT_addr; // @[Decoupled.scala 259:95]
+ wire ram_MPORT_mask; // @[Decoupled.scala 259:95]
+ wire ram_MPORT_en; // @[Decoupled.scala 259:95]
+ reg [2:0] enq_ptr_value; // @[Counter.scala 62:40]
+ reg [2:0] deq_ptr_value; // @[Counter.scala 62:40]
+ reg maybe_full; // @[Decoupled.scala 262:27]
+ wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 263:33]
+ wire empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
+ wire full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
+ wire do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
+ wire do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _value_T_1 = enq_ptr_value + 3'h1; // @[Counter.scala 78:24]
+ wire [2:0] _value_T_3 = deq_ptr_value + 3'h1; // @[Counter.scala 78:24]
+ wire [2:0] ptr_diff = enq_ptr_value - deq_ptr_value; // @[Decoupled.scala 312:32]
+ wire [3:0] _io_count_T_1 = maybe_full & ptr_match ? 4'h8 : 4'h0; // @[Decoupled.scala 315:20]
+ wire [3:0] _GEN_11 = {{1'd0}, ptr_diff}; // @[Decoupled.scala 315:62]
+ assign ram_io_deq_bits_MPORT_en = 1'h1;
+ assign ram_io_deq_bits_MPORT_addr = deq_ptr_value;
+ assign ram_io_deq_bits_MPORT_data = ram[ram_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
+ assign ram_MPORT_data = io_enq_bits;
+ assign ram_MPORT_addr = enq_ptr_value;
+ assign ram_MPORT_mask = 1'h1;
+ assign ram_MPORT_en = io_enq_ready & io_enq_valid;
+ assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
+ assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
+ assign io_deq_bits = ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
+ assign io_count = _io_count_T_1 | _GEN_11; // @[Decoupled.scala 315:62]
+ always @(posedge clock) begin
+ if (ram_MPORT_en & ram_MPORT_mask) begin
+ ram[ram_MPORT_addr] <= ram_MPORT_data; // @[Decoupled.scala 259:95]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ enq_ptr_value <= 3'h0; // @[Counter.scala 62:40]
+ end else if (do_enq) begin // @[Decoupled.scala 272:16]
+ enq_ptr_value <= _value_T_1; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Counter.scala 62:40]
+ deq_ptr_value <= 3'h0; // @[Counter.scala 62:40]
+ end else if (do_deq) begin // @[Decoupled.scala 276:16]
+ deq_ptr_value <= _value_T_3; // @[Counter.scala 78:15]
+ end
+ if (reset) begin // @[Decoupled.scala 262:27]
+ maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
+ end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
+ maybe_full <= do_enq; // @[Decoupled.scala 280:16]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_MEM_INIT
+ _RAND_0 = {1{`RANDOM}};
+ for (initvar = 0; initvar < 8; initvar = initvar+1)
+ ram[initvar] = _RAND_0[7:0];
+`endif // RANDOMIZE_MEM_INIT
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_1 = {1{`RANDOM}};
+ enq_ptr_value = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ deq_ptr_value = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ maybe_full = _RAND_3[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module SPIFIFO(
+ input clock,
+ input reset,
+ input [1:0] io_ctrl_fmt_proto,
+ input io_ctrl_fmt_endian,
+ input io_ctrl_fmt_iodir,
+ input [3:0] io_ctrl_fmt_len,
+ input [1:0] io_ctrl_cs_mode,
+ input [3:0] io_ctrl_wm_tx,
+ input [3:0] io_ctrl_wm_rx,
+ input io_link_tx_ready,
+ output io_link_tx_valid,
+ output [7:0] io_link_tx_bits,
+ input io_link_rx_valid,
+ input [7:0] io_link_rx_bits,
+ output [7:0] io_link_cnt,
+ output [1:0] io_link_fmt_proto,
+ output io_link_fmt_endian,
+ output io_link_fmt_iodir,
+ output io_link_cs_set,
+ output io_link_cs_clear,
+ output io_link_lock,
+ output io_tx_ready,
+ input io_tx_valid,
+ input [7:0] io_tx_bits,
+ input io_rx_ready,
+ output io_rx_valid,
+ output [7:0] io_rx_bits,
+ output io_ip_txwm,
+ output io_ip_rxwm
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+ wire txq_clock; // @[SPIFIFO.scala 22:19]
+ wire txq_reset; // @[SPIFIFO.scala 22:19]
+ wire txq_io_enq_ready; // @[SPIFIFO.scala 22:19]
+ wire txq_io_enq_valid; // @[SPIFIFO.scala 22:19]
+ wire [7:0] txq_io_enq_bits; // @[SPIFIFO.scala 22:19]
+ wire txq_io_deq_ready; // @[SPIFIFO.scala 22:19]
+ wire txq_io_deq_valid; // @[SPIFIFO.scala 22:19]
+ wire [7:0] txq_io_deq_bits; // @[SPIFIFO.scala 22:19]
+ wire [3:0] txq_io_count; // @[SPIFIFO.scala 22:19]
+ wire rxq_clock; // @[SPIFIFO.scala 23:19]
+ wire rxq_reset; // @[SPIFIFO.scala 23:19]
+ wire rxq_io_enq_ready; // @[SPIFIFO.scala 23:19]
+ wire rxq_io_enq_valid; // @[SPIFIFO.scala 23:19]
+ wire [7:0] rxq_io_enq_bits; // @[SPIFIFO.scala 23:19]
+ wire rxq_io_deq_ready; // @[SPIFIFO.scala 23:19]
+ wire rxq_io_deq_valid; // @[SPIFIFO.scala 23:19]
+ wire [7:0] rxq_io_deq_bits; // @[SPIFIFO.scala 23:19]
+ wire [3:0] rxq_io_count; // @[SPIFIFO.scala 23:19]
+ wire fire_tx = io_link_tx_ready & io_link_tx_valid; // @[Decoupled.scala 50:35]
+ reg rxen; // @[SPIFIFO.scala 30:17]
+ wire _T = 2'h0 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
+ wire _T_1 = 2'h1 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
+ wire _T_2 = 2'h2 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
+ wire [3:0] _cnt_quot_T_3 = _T ? io_ctrl_fmt_len : 4'h0; // @[Mux.scala 27:73]
+ wire [2:0] _cnt_quot_T_4 = _T_1 ? io_ctrl_fmt_len[3:1] : 3'h0; // @[Mux.scala 27:73]
+ wire [1:0] _cnt_quot_T_5 = _T_2 ? io_ctrl_fmt_len[3:2] : 2'h0; // @[Mux.scala 27:73]
+ wire [3:0] _GEN_2 = {{1'd0}, _cnt_quot_T_4}; // @[Mux.scala 27:73]
+ wire [3:0] _cnt_quot_T_6 = _cnt_quot_T_3 | _GEN_2; // @[Mux.scala 27:73]
+ wire [3:0] _GEN_3 = {{2'd0}, _cnt_quot_T_5}; // @[Mux.scala 27:73]
+ wire [3:0] cnt_quot = _cnt_quot_T_6 | _GEN_3; // @[Mux.scala 27:73]
+ wire _cnt_rmdr_T_1 = |io_ctrl_fmt_len[0]; // @[SPIFIFO.scala 45:92]
+ wire _cnt_rmdr_T_3 = |io_ctrl_fmt_len[1:0]; // @[SPIFIFO.scala 45:92]
+ wire cnt_rmdr = _T_1 & _cnt_rmdr_T_1 | _T_2 & _cnt_rmdr_T_3; // @[Mux.scala 27:73]
+ wire [3:0] _GEN_4 = {{3'd0}, cnt_rmdr}; // @[SPIFIFO.scala 47:27]
+ wire [3:0] _io_link_cnt_T_1 = cnt_quot + _GEN_4; // @[SPIFIFO.scala 47:27]
+ reg [1:0] cs_mode; // @[SPIFIFO.scala 49:24]
+ wire cs_mode_hold = cs_mode == 2'h2; // @[SPIFIFO.scala 50:31]
+ wire cs_mode_off = cs_mode == 2'h3; // @[SPIFIFO.scala 51:30]
+ wire cs_update = cs_mode != io_ctrl_cs_mode; // @[SPIFIFO.scala 52:28]
+ wire cs_clear = ~(cs_mode_hold | cs_mode_off); // @[SPIFIFO.scala 53:18]
+ QueueCompatibility_4 txq ( // @[SPIFIFO.scala 22:19]
+ .clock(txq_clock),
+ .reset(txq_reset),
+ .io_enq_ready(txq_io_enq_ready),
+ .io_enq_valid(txq_io_enq_valid),
+ .io_enq_bits(txq_io_enq_bits),
+ .io_deq_ready(txq_io_deq_ready),
+ .io_deq_valid(txq_io_deq_valid),
+ .io_deq_bits(txq_io_deq_bits),
+ .io_count(txq_io_count)
+ );
+ QueueCompatibility_4 rxq ( // @[SPIFIFO.scala 23:19]
+ .clock(rxq_clock),
+ .reset(rxq_reset),
+ .io_enq_ready(rxq_io_enq_ready),
+ .io_enq_valid(rxq_io_enq_valid),
+ .io_enq_bits(rxq_io_enq_bits),
+ .io_deq_ready(rxq_io_deq_ready),
+ .io_deq_valid(rxq_io_deq_valid),
+ .io_deq_bits(rxq_io_deq_bits),
+ .io_count(rxq_io_count)
+ );
+ assign io_link_tx_valid = txq_io_deq_valid; // @[SPIFIFO.scala 26:14]
+ assign io_link_tx_bits = txq_io_deq_bits; // @[SPIFIFO.scala 26:14]
+ assign io_link_cnt = {{4'd0}, _io_link_cnt_T_1}; // @[SPIFIFO.scala 47:15]
+ assign io_link_fmt_proto = io_ctrl_fmt_proto; // @[SPIFIFO.scala 46:15]
+ assign io_link_fmt_endian = io_ctrl_fmt_endian; // @[SPIFIFO.scala 46:15]
+ assign io_link_fmt_iodir = io_ctrl_fmt_iodir; // @[SPIFIFO.scala 46:15]
+ assign io_link_cs_set = ~cs_mode_off; // @[SPIFIFO.scala 55:21]
+ assign io_link_cs_clear = cs_update | fire_tx & cs_clear; // @[SPIFIFO.scala 56:33]
+ assign io_link_lock = io_link_tx_valid | rxen; // @[SPIFIFO.scala 59:36]
+ assign io_tx_ready = txq_io_enq_ready; // @[SPIFIFO.scala 25:14]
+ assign io_rx_valid = rxq_io_deq_valid; // @[SPIFIFO.scala 34:9]
+ assign io_rx_bits = rxq_io_deq_bits; // @[SPIFIFO.scala 34:9]
+ assign io_ip_txwm = txq_io_count < io_ctrl_wm_tx; // @[SPIFIFO.scala 61:31]
+ assign io_ip_rxwm = rxq_io_count > io_ctrl_wm_rx; // @[SPIFIFO.scala 62:31]
+ assign txq_clock = clock;
+ assign txq_reset = reset;
+ assign txq_io_enq_valid = io_tx_valid; // @[SPIFIFO.scala 25:14]
+ assign txq_io_enq_bits = io_tx_bits; // @[SPIFIFO.scala 25:14]
+ assign txq_io_deq_ready = io_link_tx_ready; // @[SPIFIFO.scala 26:14]
+ assign rxq_clock = clock;
+ assign rxq_reset = reset;
+ assign rxq_io_enq_valid = io_link_rx_valid & rxen; // @[SPIFIFO.scala 32:40]
+ assign rxq_io_enq_bits = io_link_rx_bits; // @[SPIFIFO.scala 33:19]
+ assign rxq_io_deq_ready = io_rx_ready; // @[SPIFIFO.scala 34:9]
+ always @(posedge clock) begin
+ if (reset) begin // @[SPIFIFO.scala 30:17]
+ rxen <= 1'h0; // @[SPIFIFO.scala 30:17]
+ end else if (fire_tx) begin // @[SPIFIFO.scala 39:18]
+ rxen <= ~io_link_fmt_iodir; // @[SPIFIFO.scala 40:10]
+ end else if (io_link_rx_valid) begin // @[SPIFIFO.scala 36:18]
+ rxen <= 1'h0; // @[SPIFIFO.scala 37:10]
+ end
+ if (reset) begin // @[SPIFIFO.scala 49:24]
+ cs_mode <= 2'h0; // @[SPIFIFO.scala 49:24]
+ end else begin
+ cs_mode <= io_ctrl_cs_mode; // @[SPIFIFO.scala 49:24]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ rxen = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ cs_mode = _RAND_1[1:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module SPIPhysical(
+ input clock,
+ input reset,
+ output io_port_sck,
+ input io_port_dq_0_i,
+ output io_port_dq_0_o,
+ output io_port_dq_0_oe,
+ input io_port_dq_1_i,
+ output io_port_dq_1_o,
+ output io_port_dq_1_oe,
+ input io_port_dq_2_i,
+ output io_port_dq_2_o,
+ output io_port_dq_2_oe,
+ input io_port_dq_3_i,
+ output io_port_dq_3_o,
+ output io_port_dq_3_oe,
+ input [11:0] io_ctrl_sck_div,
+ input io_ctrl_sck_pol,
+ input io_ctrl_sck_pha,
+ input [1:0] io_ctrl_fmt_proto,
+ input io_ctrl_fmt_endian,
+ input io_ctrl_fmt_iodir,
+ input [11:0] io_ctrl_extradel_coarse,
+ input [4:0] io_ctrl_sampledel_sd,
+ output io_op_ready,
+ input io_op_valid,
+ input io_op_bits_fn,
+ input io_op_bits_stb,
+ input [7:0] io_op_bits_cnt,
+ input [7:0] io_op_bits_data,
+ output io_rx_valid,
+ output [7:0] io_rx_bits
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+`endif // RANDOMIZE_REG_INIT
+ reg [11:0] ctrl_sck_div; // @[SPIPhysical.scala 52:17]
+ reg ctrl_sck_pol; // @[SPIPhysical.scala 52:17]
+ reg ctrl_sck_pha; // @[SPIPhysical.scala 52:17]
+ reg [1:0] ctrl_fmt_proto; // @[SPIPhysical.scala 52:17]
+ reg ctrl_fmt_endian; // @[SPIPhysical.scala 52:17]
+ reg ctrl_fmt_iodir; // @[SPIPhysical.scala 52:17]
+ wire proto_0 = 2'h0 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
+ wire proto_1 = 2'h1 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
+ wire proto_2 = 2'h2 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
+ reg setup_d; // @[SPIPhysical.scala 60:20]
+ reg [7:0] scnt; // @[SPIPhysical.scala 62:17]
+ reg [11:0] tcnt; // @[SPIPhysical.scala 63:17]
+ wire stop = scnt == 8'h0; // @[SPIPhysical.scala 65:20]
+ wire beat = tcnt == 12'h0; // @[SPIPhysical.scala 66:20]
+ wire [11:0] _GEN_78 = {{7'd0}, io_ctrl_sampledel_sd}; // @[SPIPhysical.scala 69:49]
+ wire [11:0] totalCoarseDel = io_ctrl_extradel_coarse + _GEN_78; // @[SPIPhysical.scala 69:49]
+ reg sample_d; // @[SPIPhysical.scala 70:25]
+ reg [11:0] del_cntr; // @[SPIPhysical.scala 71:25]
+ reg xfr; // @[SPIPhysical.scala 182:16]
+ reg cref; // @[SPIPhysical.scala 117:17]
+ wire _GEN_10 = xfr & cref; // @[SPIPhysical.scala 190:18 192:16]
+ wire _GEN_15 = beat & _GEN_10; // @[SPIPhysical.scala 188:17]
+ wire sample = stop ? 1'h0 : _GEN_15; // @[SPIPhysical.scala 184:15]
+ wire [11:0] _del_cntr_T_1 = totalCoarseDel - 12'h1; // @[SPIPhysical.scala 75:34]
+ wire [11:0] _del_cntr_T_3 = del_cntr - 12'h1; // @[SPIPhysical.scala 82:28]
+ wire _T_3 = del_cntr == 12'h1; // @[SPIPhysical.scala 86:18]
+ reg last_d; // @[SPIPhysical.scala 92:23]
+ reg [11:0] del_cntr_last; // @[SPIPhysical.scala 93:30]
+ wire last = scnt == 8'h1 & (beat & cref & xfr); // @[SPIPhysical.scala 201:27 202:10]
+ wire [11:0] _del_cntr_last_T_3 = del_cntr_last - 12'h1; // @[SPIPhysical.scala 103:38]
+ wire _T_7 = del_cntr_last == 12'h1; // @[SPIPhysical.scala 107:23]
+ wire [11:0] _decr_T = beat ? {{4'd0}, scnt} : tcnt; // @[SPIPhysical.scala 112:17]
+ wire [11:0] decr = _decr_T - 12'h1; // @[SPIPhysical.scala 112:36]
+ wire sched = stop | beat; // @[SPIPhysical.scala 184:15 185:11]
+ reg sck; // @[SPIPhysical.scala 116:16]
+ wire cinv = ctrl_sck_pha ^ ctrl_sck_pol; // @[SPIPhysical.scala 118:27]
+ wire [3:0] rxd = {io_port_dq_3_i,io_port_dq_2_i,io_port_dq_1_i,io_port_dq_0_i}; // @[Cat.scala 31:58]
+ wire rxd_delayed_0 = rxd[0]; // @[SPIPhysical.scala 135:24]
+ wire rxd_delayed_1 = rxd[1]; // @[SPIPhysical.scala 135:24]
+ wire rxd_delayed_2 = rxd[2]; // @[SPIPhysical.scala 135:24]
+ wire rxd_delayed_3 = rxd[3]; // @[SPIPhysical.scala 135:24]
+ wire [3:0] rxd_fin = {rxd_delayed_3,rxd_delayed_2,rxd_delayed_1,rxd_delayed_0}; // @[SPIPhysical.scala 138:29]
+ wire samples_0 = rxd_fin[1]; // @[SPIPhysical.scala 139:28]
+ wire [1:0] samples_1 = rxd_fin[1:0]; // @[SPIPhysical.scala 139:40]
+ reg [7:0] buffer; // @[SPIPhysical.scala 141:19]
+ wire [7:0] _buffer_in_T_9 = {io_op_bits_data[0],io_op_bits_data[1],io_op_bits_data[2],io_op_bits_data[3],
+ io_op_bits_data[4],io_op_bits_data[5],io_op_bits_data[6],io_op_bits_data[7]}; // @[Cat.scala 31:58]
+ wire [7:0] buffer_in = ~io_ctrl_fmt_endian ? io_op_bits_data : _buffer_in_T_9; // @[SPIPhysical.scala 121:8]
+ wire shift = totalCoarseDel > 12'h0 ? setup_d | sample_d & stop : sample_d; // @[SPIPhysical.scala 143:19]
+ wire [6:0] _buffer_T_2 = shift ? buffer[6:0] : buffer[7:1]; // @[SPIPhysical.scala 147:12]
+ wire _buffer_T_4 = sample_d ? samples_0 : buffer[0]; // @[SPIPhysical.scala 148:12]
+ wire [7:0] _buffer_T_5 = {_buffer_T_2,_buffer_T_4}; // @[Cat.scala 31:58]
+ wire [5:0] _buffer_T_8 = shift ? buffer[5:0] : buffer[7:2]; // @[SPIPhysical.scala 147:12]
+ wire [1:0] _buffer_T_10 = sample_d ? samples_1 : buffer[1:0]; // @[SPIPhysical.scala 148:12]
+ wire [7:0] _buffer_T_11 = {_buffer_T_8,_buffer_T_10}; // @[Cat.scala 31:58]
+ wire [3:0] _buffer_T_14 = shift ? buffer[3:0] : buffer[7:4]; // @[SPIPhysical.scala 147:12]
+ wire [3:0] _buffer_T_16 = sample_d ? rxd_fin : buffer[3:0]; // @[SPIPhysical.scala 148:12]
+ wire [7:0] _buffer_T_17 = {_buffer_T_14,_buffer_T_16}; // @[Cat.scala 31:58]
+ wire [7:0] _buffer_T_18 = proto_0 ? _buffer_T_5 : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _buffer_T_19 = proto_1 ? _buffer_T_11 : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _buffer_T_20 = proto_2 ? _buffer_T_17 : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _buffer_T_21 = _buffer_T_18 | _buffer_T_19; // @[Mux.scala 27:73]
+ wire [7:0] _buffer_T_22 = _buffer_T_21 | _buffer_T_20; // @[Mux.scala 27:73]
+ reg [3:0] txd; // @[SPIPhysical.scala 153:16]
+ wire _T_18 = ~cref; // @[SPIPhysical.scala 203:19]
+ wire _GEN_25 = beat & ~cref | stop; // @[SPIPhysical.scala 203:26 204:14]
+ wire accept = scnt == 8'h1 ? _GEN_25 : stop; // @[SPIPhysical.scala 201:27]
+ wire [3:0] txd_in = accept ? buffer_in[7:4] : buffer[7:4]; // @[SPIPhysical.scala 154:19]
+ wire [1:0] _txd_sel_T = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto; // @[SPIPhysical.scala 155:39]
+ wire txd_sel_0 = 2'h0 == _txd_sel_T; // @[SPIConsts.scala 13:48]
+ wire txd_sel_1 = 2'h1 == _txd_sel_T; // @[SPIConsts.scala 13:48]
+ wire txd_sel_2 = 2'h2 == _txd_sel_T; // @[SPIConsts.scala 13:48]
+ wire txd_shf_0 = txd_in[3]; // @[SPIPhysical.scala 156:55]
+ wire [1:0] txd_shf_1 = txd_in[3:2]; // @[SPIPhysical.scala 156:55]
+ wire _txd_T = txd_sel_0 & txd_shf_0; // @[Mux.scala 27:73]
+ wire [1:0] _txd_T_1 = txd_sel_1 ? txd_shf_1 : 2'h0; // @[Mux.scala 27:73]
+ wire [3:0] _txd_T_2 = txd_sel_2 ? txd_in : 4'h0; // @[Mux.scala 27:73]
+ wire [1:0] _GEN_79 = {{1'd0}, _txd_T}; // @[Mux.scala 27:73]
+ wire [1:0] _txd_T_3 = _GEN_79 | _txd_T_1; // @[Mux.scala 27:73]
+ wire [3:0] _GEN_80 = {{2'd0}, _txd_T_3}; // @[Mux.scala 27:73]
+ wire [3:0] _txd_T_4 = _GEN_80 | _txd_T_2; // @[Mux.scala 27:73]
+ reg done; // @[SPIPhysical.scala 176:17]
+ wire _T_21 = ~io_op_bits_fn; // @[SPIPhysical.scala 220:22]
+ wire _GEN_11 = xfr & _T_18; // @[SPIPhysical.scala 190:18 193:15]
+ wire _GEN_16 = beat & _GEN_11; // @[SPIPhysical.scala 188:17]
+ wire _GEN_23 = stop ? 1'h0 : _GEN_16; // @[SPIPhysical.scala 184:15]
+ wire _GEN_26 = beat & ~cref ? 1'h0 : _GEN_23; // @[SPIPhysical.scala 203:26 205:13]
+ wire _GEN_30 = scnt == 8'h1 ? _GEN_26 : _GEN_23; // @[SPIPhysical.scala 201:27]
+ wire _GEN_45 = ~io_op_bits_fn | _GEN_30; // @[SPIPhysical.scala 220:22 224:17]
+ wire _GEN_59 = io_op_valid ? _GEN_45 : _GEN_30; // @[SPIPhysical.scala 212:24]
+ wire setup = accept & done ? _GEN_59 : _GEN_30; // @[SPIPhysical.scala 210:25]
+ wire txen_2 = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
+ wire txen_1 = proto_1 & ctrl_fmt_iodir | txen_2; // @[SPIPhysical.scala 162:82]
+ wire [7:0] _io_rx_bits_T_9 = {buffer[0],buffer[1],buffer[2],buffer[3],buffer[4],buffer[5],buffer[6],buffer[7]}; // @[Cat.scala 31:58]
+ wire _GEN_9 = xfr ? cref ^ cinv : sck; // @[SPIPhysical.scala 190:18 191:13 116:16]
+ wire [11:0] _GEN_12 = _T_18 ? decr : {{4'd0}, scnt}; // @[SPIPhysical.scala 195:20 196:14 62:17]
+ wire _GEN_13 = beat ? _T_18 : cref; // @[SPIPhysical.scala 188:17 189:12 117:17]
+ wire _GEN_14 = beat ? _GEN_9 : sck; // @[SPIPhysical.scala 116:16 188:17]
+ wire [11:0] _GEN_17 = beat ? _GEN_12 : {{4'd0}, scnt}; // @[SPIPhysical.scala 188:17 62:17]
+ wire _GEN_20 = stop ? cref : _GEN_13; // @[SPIPhysical.scala 184:15 117:17]
+ wire _GEN_21 = stop ? sck : _GEN_14; // @[SPIPhysical.scala 184:15 116:16]
+ wire [11:0] _GEN_24 = stop ? {{4'd0}, scnt} : _GEN_17; // @[SPIPhysical.scala 184:15 62:17]
+ wire _GEN_27 = beat & ~cref ? ctrl_sck_pol : _GEN_21; // @[SPIPhysical.scala 203:26 206:11]
+ wire _GEN_31 = scnt == 8'h1 ? _GEN_27 : _GEN_21; // @[SPIPhysical.scala 201:27]
+ wire _GEN_35 = io_op_bits_stb ? io_ctrl_sck_pol : _GEN_31; // @[SPIPhysical.scala 229:25 230:17]
+ wire [11:0] _GEN_36 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div; // @[SPIPhysical.scala 229:25 231:22 52:17]
+ wire _GEN_37 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol; // @[SPIPhysical.scala 229:25 231:22 52:17]
+ wire _GEN_38 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha; // @[SPIPhysical.scala 229:25 231:22 52:17]
+ wire _GEN_46 = ~io_op_bits_fn ? io_op_bits_cnt == 8'h0 : done | last_d; // @[SPIPhysical.scala 220:22 225:16 177:8]
+ wire [11:0] _GEN_51 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : _GEN_24; // @[SPIPhysical.scala 212:24 213:12]
+ wire _GEN_60 = io_op_valid ? _GEN_46 : done | last_d; // @[SPIPhysical.scala 212:24 177:8]
+ wire [11:0] _GEN_65 = accept & done ? _GEN_51 : _GEN_24; // @[SPIPhysical.scala 210:25]
+ wire _GEN_74 = accept & done ? _GEN_60 : done | last_d; // @[SPIPhysical.scala 210:25 177:8]
+ assign io_port_sck = sck; // @[SPIPhysical.scala 166:15]
+ assign io_port_dq_0_o = txd[0]; // @[SPIPhysical.scala 168:24]
+ assign io_port_dq_0_oe = proto_0 | txen_1; // @[SPIPhysical.scala 162:82]
+ assign io_port_dq_1_o = txd[1]; // @[SPIPhysical.scala 168:24]
+ assign io_port_dq_1_oe = proto_1 & ctrl_fmt_iodir | txen_2; // @[SPIPhysical.scala 162:82]
+ assign io_port_dq_2_o = txd[2]; // @[SPIPhysical.scala 168:24]
+ assign io_port_dq_2_oe = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
+ assign io_port_dq_3_o = txd[3]; // @[SPIPhysical.scala 168:24]
+ assign io_port_dq_3_oe = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
+ assign io_op_ready = accept & done; // @[SPIPhysical.scala 210:16]
+ assign io_rx_valid = done; // @[SPIPhysical.scala 179:15]
+ assign io_rx_bits = ~ctrl_fmt_endian ? buffer : _io_rx_bits_T_9; // @[SPIPhysical.scala 121:8]
+ always @(posedge clock) begin
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
+ if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
+ ctrl_sck_div <= _GEN_36;
+ end
+ end
+ end
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
+ if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
+ ctrl_sck_pol <= _GEN_37;
+ end
+ end
+ end
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
+ if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
+ ctrl_sck_pha <= _GEN_38;
+ end
+ end
+ end
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
+ ctrl_fmt_proto <= io_ctrl_fmt_proto; // @[SPIPhysical.scala 216:18]
+ end
+ end
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
+ ctrl_fmt_endian <= io_ctrl_fmt_endian; // @[SPIPhysical.scala 216:18]
+ end
+ end
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
+ ctrl_fmt_iodir <= io_ctrl_fmt_iodir; // @[SPIPhysical.scala 216:18]
+ end
+ end
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ setup_d <= _GEN_45;
+ end else begin
+ setup_d <= _GEN_30;
+ end
+ end else begin
+ setup_d <= _GEN_30;
+ end
+ if (reset) begin // @[SPIPhysical.scala 62:17]
+ scnt <= 8'h0; // @[SPIPhysical.scala 62:17]
+ end else begin
+ scnt <= _GEN_65[7:0];
+ end
+ if (sched) begin // @[SPIPhysical.scala 114:14]
+ tcnt <= ctrl_sck_div;
+ end else begin
+ tcnt <= decr;
+ end
+ if (reset) begin // @[SPIPhysical.scala 70:25]
+ sample_d <= 1'h0; // @[SPIPhysical.scala 70:25]
+ end else begin
+ sample_d <= _T_3;
+ end
+ if (reset) begin // @[SPIPhysical.scala 71:25]
+ del_cntr <= 12'h3; // @[SPIPhysical.scala 71:25]
+ end else if (beat & sample) begin // @[SPIPhysical.scala 73:25]
+ if (totalCoarseDel > 12'h1) begin // @[SPIPhysical.scala 74:32]
+ del_cntr <= _del_cntr_T_1; // @[SPIPhysical.scala 75:16]
+ end else begin
+ del_cntr <= 12'h1; // @[SPIPhysical.scala 78:16]
+ end
+ end else if (del_cntr != 12'h0) begin // @[SPIPhysical.scala 81:27]
+ del_cntr <= _del_cntr_T_3; // @[SPIPhysical.scala 82:16]
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ xfr <= _T_21;
+ end
+ end
+ cref <= reset | _GEN_20; // @[SPIPhysical.scala 117:{17,17}]
+ if (reset) begin // @[SPIPhysical.scala 92:23]
+ last_d <= 1'h0; // @[SPIPhysical.scala 92:23]
+ end else begin
+ last_d <= _T_7;
+ end
+ if (reset) begin // @[SPIPhysical.scala 93:30]
+ del_cntr_last <= 12'h3; // @[SPIPhysical.scala 93:30]
+ end else if (beat & last) begin // @[SPIPhysical.scala 94:23]
+ if (totalCoarseDel > 12'h1) begin // @[SPIPhysical.scala 74:32]
+ del_cntr_last <= _del_cntr_T_1; // @[SPIPhysical.scala 75:16]
+ end else begin
+ del_cntr_last <= 12'h1; // @[SPIPhysical.scala 78:16]
+ end
+ end else if (del_cntr_last != 12'h0) begin // @[SPIPhysical.scala 102:33]
+ del_cntr_last <= _del_cntr_last_T_3; // @[SPIPhysical.scala 103:21]
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ if (~io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
+ sck <= cinv; // @[SPIPhysical.scala 223:15]
+ end else if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
+ sck <= _GEN_35;
+ end else begin
+ sck <= _GEN_31;
+ end
+ end else begin
+ sck <= _GEN_31;
+ end
+ end else begin
+ sck <= _GEN_31;
+ end
+ if (accept & done) begin // @[SPIPhysical.scala 210:25]
+ if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
+ if (~io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
+ if (~io_ctrl_fmt_endian) begin // @[SPIPhysical.scala 121:8]
+ buffer <= io_op_bits_data;
+ end else begin
+ buffer <= _buffer_in_T_9;
+ end
+ end else begin
+ buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
+ end
+ end else begin
+ buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
+ end
+ end else begin
+ buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
+ end
+ if (reset) begin // @[SPIPhysical.scala 153:16]
+ txd <= 4'h0; // @[SPIPhysical.scala 153:16]
+ end else if (setup) begin // @[SPIPhysical.scala 157:16]
+ txd <= _txd_T_4; // @[SPIPhysical.scala 158:9]
+ end
+ done <= reset | _GEN_74; // @[SPIPhysical.scala 176:{17,17}]
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ ctrl_sck_div = _RAND_0[11:0];
+ _RAND_1 = {1{`RANDOM}};
+ ctrl_sck_pol = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ ctrl_sck_pha = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ ctrl_fmt_proto = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ ctrl_fmt_endian = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ ctrl_fmt_iodir = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ setup_d = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ scnt = _RAND_7[7:0];
+ _RAND_8 = {1{`RANDOM}};
+ tcnt = _RAND_8[11:0];
+ _RAND_9 = {1{`RANDOM}};
+ sample_d = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ del_cntr = _RAND_10[11:0];
+ _RAND_11 = {1{`RANDOM}};
+ xfr = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ cref = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ last_d = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ del_cntr_last = _RAND_14[11:0];
+ _RAND_15 = {1{`RANDOM}};
+ sck = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ buffer = _RAND_16[7:0];
+ _RAND_17 = {1{`RANDOM}};
+ txd = _RAND_17[3:0];
+ _RAND_18 = {1{`RANDOM}};
+ done = _RAND_18[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module SPIMedia(
+ input clock,
+ input reset,
+ output io_port_sck,
+ input io_port_dq_0_i,
+ output io_port_dq_0_o,
+ output io_port_dq_0_oe,
+ input io_port_dq_1_i,
+ output io_port_dq_1_o,
+ output io_port_dq_1_oe,
+ input io_port_dq_2_i,
+ output io_port_dq_2_o,
+ output io_port_dq_2_oe,
+ input io_port_dq_3_i,
+ output io_port_dq_3_o,
+ output io_port_dq_3_oe,
+ output io_port_cs_0,
+ input [11:0] io_ctrl_sck_div,
+ input io_ctrl_sck_pol,
+ input io_ctrl_sck_pha,
+ input [7:0] io_ctrl_dla_cssck,
+ input [7:0] io_ctrl_dla_sckcs,
+ input [7:0] io_ctrl_dla_intercs,
+ input [7:0] io_ctrl_dla_interxfr,
+ input io_ctrl_cs_id,
+ input io_ctrl_cs_dflt_0,
+ input [11:0] io_ctrl_extradel_coarse,
+ input [4:0] io_ctrl_sampledel_sd,
+ output io_link_tx_ready,
+ input io_link_tx_valid,
+ input [7:0] io_link_tx_bits,
+ output io_link_rx_valid,
+ output [7:0] io_link_rx_bits,
+ input [7:0] io_link_cnt,
+ input [1:0] io_link_fmt_proto,
+ input io_link_fmt_endian,
+ input io_link_fmt_iodir,
+ input io_link_cs_set,
+ input io_link_cs_clear,
+ input io_link_cs_hold,
+ output io_link_active
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+`endif // RANDOMIZE_REG_INIT
+ wire phy_clock; // @[SPIMedia.scala 36:19]
+ wire phy_reset; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_sck; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_0_i; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_0_o; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_0_oe; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_1_i; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_1_o; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_1_oe; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_2_i; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_2_o; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_2_oe; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_3_i; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_3_o; // @[SPIMedia.scala 36:19]
+ wire phy_io_port_dq_3_oe; // @[SPIMedia.scala 36:19]
+ wire [11:0] phy_io_ctrl_sck_div; // @[SPIMedia.scala 36:19]
+ wire phy_io_ctrl_sck_pol; // @[SPIMedia.scala 36:19]
+ wire phy_io_ctrl_sck_pha; // @[SPIMedia.scala 36:19]
+ wire [1:0] phy_io_ctrl_fmt_proto; // @[SPIMedia.scala 36:19]
+ wire phy_io_ctrl_fmt_endian; // @[SPIMedia.scala 36:19]
+ wire phy_io_ctrl_fmt_iodir; // @[SPIMedia.scala 36:19]
+ wire [11:0] phy_io_ctrl_extradel_coarse; // @[SPIMedia.scala 36:19]
+ wire [4:0] phy_io_ctrl_sampledel_sd; // @[SPIMedia.scala 36:19]
+ wire phy_io_op_ready; // @[SPIMedia.scala 36:19]
+ wire phy_io_op_valid; // @[SPIMedia.scala 36:19]
+ wire phy_io_op_bits_fn; // @[SPIMedia.scala 36:19]
+ wire phy_io_op_bits_stb; // @[SPIMedia.scala 36:19]
+ wire [7:0] phy_io_op_bits_cnt; // @[SPIMedia.scala 36:19]
+ wire [7:0] phy_io_op_bits_data; // @[SPIMedia.scala 36:19]
+ wire phy_io_rx_valid; // @[SPIMedia.scala 36:19]
+ wire [7:0] phy_io_rx_bits; // @[SPIMedia.scala 36:19]
+ reg cs_id; // @[SPIMedia.scala 50:15]
+ reg cs_dflt_0; // @[SPIMedia.scala 50:15]
+ reg cs_set; // @[SPIMedia.scala 51:19]
+ wire [1:0] _GEN_4 = {{1'd0}, io_link_cs_set}; // @[SPIBundle.scala 49:19]
+ wire [1:0] cs_active_mask = _GEN_4 << io_ctrl_cs_id; // @[SPIBundle.scala 49:19]
+ wire [1:0] _GEN_54 = {{1'd0}, io_ctrl_cs_dflt_0}; // @[SPIBundle.scala 50:33]
+ wire [1:0] cs_active_out = _GEN_54 ^ cs_active_mask; // @[SPIBundle.scala 50:33]
+ wire cs_active_0 = cs_active_out[0]; // @[SPIBundle.scala 51:32]
+ wire cs_update = cs_active_0 != cs_dflt_0; // @[SPIMedia.scala 53:37]
+ reg clear; // @[SPIMedia.scala 55:18]
+ reg cs_assert; // @[SPIMedia.scala 56:22]
+ wire cs_deassert = clear | cs_update & ~io_link_cs_hold; // @[SPIMedia.scala 57:27]
+ wire continuous = io_ctrl_dla_interxfr == 8'h0; // @[SPIMedia.scala 61:42]
+ reg [1:0] state; // @[SPIMedia.scala 72:18]
+ wire [1:0] _GEN_0 = phy_io_op_ready ? 2'h2 : state; // @[SPIMedia.scala 72:18 79:27 80:19]
+ wire _T_1 = phy_io_op_ready & phy_io_op_valid; // @[Decoupled.scala 50:35]
+ wire [1:0] _GEN_1 = _T_1 ? 2'h1 : state; // @[SPIMedia.scala 72:18 88:28 89:19]
+ wire [7:0] _GEN_2 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt; // @[SPIMedia.scala 46:15 77:28 78:23]
+ wire _GEN_5 = cs_deassert ? 1'h0 : 1'h1; // @[SPIMedia.scala 45:15 77:28 84:23]
+ wire _GEN_6 = cs_deassert | io_link_tx_valid; // @[SPIMedia.scala 43:12 77:28 86:20]
+ wire _GEN_7 = cs_deassert ? 1'h0 : phy_io_op_ready; // @[SPIMedia.scala 68:20 77:28 87:28]
+ wire _GEN_8 = phy_io_op_ready | cs_assert; // @[SPIMedia.scala 95:25 96:21 56:22]
+ wire [7:0] _GEN_11 = io_link_tx_valid ? io_ctrl_dla_cssck : 8'h0; // @[SPIMedia.scala 102:21 92:38 94:21]
+ wire _GEN_15 = io_link_tx_valid ? 1'h0 : 1'h1; // @[SPIMedia.scala 45:15 103:21 92:38]
+ wire [7:0] _GEN_17 = cs_assert ? _GEN_2 : _GEN_11; // @[SPIMedia.scala 76:24]
+ wire _GEN_19 = cs_assert ? cs_deassert : 1'h1; // @[SPIMedia.scala 44:14 76:24]
+ wire _GEN_20 = cs_assert ? _GEN_5 : _GEN_15; // @[SPIMedia.scala 76:24]
+ wire _GEN_21 = cs_assert ? _GEN_6 : 1'h1; // @[SPIMedia.scala 43:12 76:24]
+ wire _GEN_22 = cs_assert & _GEN_7; // @[SPIMedia.scala 68:20 76:24]
+ wire [1:0] _GEN_31 = {{1'd0}, cs_set}; // @[SPIBundle.scala 49:19]
+ wire [1:0] mask = _GEN_31 << cs_id; // @[SPIBundle.scala 49:19]
+ wire [1:0] _GEN_55 = {{1'd0}, cs_dflt_0}; // @[SPIBundle.scala 50:33]
+ wire [1:0] out = _GEN_55 ^ mask; // @[SPIBundle.scala 50:33]
+ wire [1:0] _GEN_29 = phy_io_op_ready ? 2'h0 : state; // @[SPIMedia.scala 123:23 125:15 72:18]
+ wire [7:0] _GEN_30 = 2'h2 == state ? io_ctrl_dla_intercs : io_link_cnt; // @[SPIMedia.scala 74:18 119:19 46:15]
+ wire _GEN_36 = 2'h1 == state ? ~continuous : 1'h1; // @[SPIMedia.scala 110:16 43:12 74:18]
+ wire [7:0] _GEN_37 = 2'h1 == state ? io_ctrl_dla_interxfr : _GEN_30; // @[SPIMedia.scala 74:18 111:19]
+ wire _GEN_39 = 2'h1 == state ? 1'h0 : 2'h2 == state; // @[SPIMedia.scala 45:15 74:18]
+ SPIPhysical phy ( // @[SPIMedia.scala 36:19]
+ .clock(phy_clock),
+ .reset(phy_reset),
+ .io_port_sck(phy_io_port_sck),
+ .io_port_dq_0_i(phy_io_port_dq_0_i),
+ .io_port_dq_0_o(phy_io_port_dq_0_o),
+ .io_port_dq_0_oe(phy_io_port_dq_0_oe),
+ .io_port_dq_1_i(phy_io_port_dq_1_i),
+ .io_port_dq_1_o(phy_io_port_dq_1_o),
+ .io_port_dq_1_oe(phy_io_port_dq_1_oe),
+ .io_port_dq_2_i(phy_io_port_dq_2_i),
+ .io_port_dq_2_o(phy_io_port_dq_2_o),
+ .io_port_dq_2_oe(phy_io_port_dq_2_oe),
+ .io_port_dq_3_i(phy_io_port_dq_3_i),
+ .io_port_dq_3_o(phy_io_port_dq_3_o),
+ .io_port_dq_3_oe(phy_io_port_dq_3_oe),
+ .io_ctrl_sck_div(phy_io_ctrl_sck_div),
+ .io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
+ .io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
+ .io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
+ .io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
+ .io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
+ .io_ctrl_extradel_coarse(phy_io_ctrl_extradel_coarse),
+ .io_ctrl_sampledel_sd(phy_io_ctrl_sampledel_sd),
+ .io_op_ready(phy_io_op_ready),
+ .io_op_valid(phy_io_op_valid),
+ .io_op_bits_fn(phy_io_op_bits_fn),
+ .io_op_bits_stb(phy_io_op_bits_stb),
+ .io_op_bits_cnt(phy_io_op_bits_cnt),
+ .io_op_bits_data(phy_io_op_bits_data),
+ .io_rx_valid(phy_io_rx_valid),
+ .io_rx_bits(phy_io_rx_bits)
+ );
+ assign io_port_sck = phy_io_port_sck; // @[SPIMedia.scala 63:15]
+ assign io_port_dq_0_o = phy_io_port_dq_0_o; // @[SPIMedia.scala 64:14]
+ assign io_port_dq_0_oe = phy_io_port_dq_0_oe; // @[SPIMedia.scala 64:14]
+ assign io_port_dq_1_o = phy_io_port_dq_1_o; // @[SPIMedia.scala 64:14]
+ assign io_port_dq_1_oe = phy_io_port_dq_1_oe; // @[SPIMedia.scala 64:14]
+ assign io_port_dq_2_o = phy_io_port_dq_2_o; // @[SPIMedia.scala 64:14]
+ assign io_port_dq_2_oe = phy_io_port_dq_2_oe; // @[SPIMedia.scala 64:14]
+ assign io_port_dq_3_o = phy_io_port_dq_3_o; // @[SPIMedia.scala 64:14]
+ assign io_port_dq_3_oe = phy_io_port_dq_3_oe; // @[SPIMedia.scala 64:14]
+ assign io_port_cs_0 = cs_dflt_0; // @[SPIMedia.scala 65:14]
+ assign io_link_tx_ready = 2'h0 == state & _GEN_22; // @[SPIMedia.scala 74:18 68:20]
+ assign io_link_rx_valid = phy_io_rx_valid; // @[SPIMedia.scala 67:14]
+ assign io_link_rx_bits = phy_io_rx_bits; // @[SPIMedia.scala 67:14]
+ assign io_link_active = cs_assert; // @[SPIMedia.scala 69:18]
+ assign phy_clock = clock;
+ assign phy_reset = reset;
+ assign phy_io_port_dq_0_i = io_port_dq_0_i; // @[SPIMedia.scala 64:14]
+ assign phy_io_port_dq_1_i = io_port_dq_1_i; // @[SPIMedia.scala 64:14]
+ assign phy_io_port_dq_2_i = io_port_dq_2_i; // @[SPIMedia.scala 64:14]
+ assign phy_io_port_dq_3_i = io_port_dq_3_i; // @[SPIMedia.scala 64:14]
+ assign phy_io_ctrl_sck_div = io_ctrl_sck_div; // @[SPIMedia.scala 37:19]
+ assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol; // @[SPIMedia.scala 37:19]
+ assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha; // @[SPIMedia.scala 37:19]
+ assign phy_io_ctrl_fmt_proto = io_link_fmt_proto; // @[SPIMedia.scala 38:19]
+ assign phy_io_ctrl_fmt_endian = io_link_fmt_endian; // @[SPIMedia.scala 38:19]
+ assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir; // @[SPIMedia.scala 38:19]
+ assign phy_io_ctrl_extradel_coarse = io_ctrl_extradel_coarse; // @[SPIMedia.scala 39:24]
+ assign phy_io_ctrl_sampledel_sd = io_ctrl_sampledel_sd; // @[SPIMedia.scala 40:25]
+ assign phy_io_op_valid = 2'h0 == state ? _GEN_21 : _GEN_36; // @[SPIMedia.scala 74:18]
+ assign phy_io_op_bits_fn = 2'h0 == state ? _GEN_19 : 1'h1; // @[SPIMedia.scala 44:14 74:18]
+ assign phy_io_op_bits_stb = 2'h0 == state ? _GEN_20 : _GEN_39; // @[SPIMedia.scala 74:18]
+ assign phy_io_op_bits_cnt = 2'h0 == state ? _GEN_17 : _GEN_37; // @[SPIMedia.scala 74:18]
+ assign phy_io_op_bits_data = io_link_tx_bits; // @[SPIMedia.scala 47:16]
+ always @(posedge clock) begin
+ if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
+ if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
+ if (!(io_link_tx_valid)) begin // @[SPIMedia.scala 92:38]
+ cs_id <= io_ctrl_cs_id; // @[SPIMedia.scala 104:12]
+ end
+ end
+ end
+ if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
+ if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
+ if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
+ if (phy_io_op_ready) begin // @[SPIMedia.scala 95:25]
+ cs_dflt_0 <= cs_active_0; // @[SPIMedia.scala 98:19]
+ end
+ end else begin
+ cs_dflt_0 <= io_ctrl_cs_dflt_0; // @[SPIMedia.scala 104:12]
+ end
+ end
+ end else if (!(2'h1 == state)) begin // @[SPIMedia.scala 74:18]
+ if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
+ if (phy_io_op_ready) begin // @[SPIMedia.scala 123:23]
+ cs_dflt_0 <= out[0]; // @[SPIMedia.scala 124:17]
+ end
+ end
+ end
+ if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
+ if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
+ if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
+ if (phy_io_op_ready) begin // @[SPIMedia.scala 95:25]
+ cs_set <= io_link_cs_set; // @[SPIMedia.scala 97:18]
+ end
+ end
+ end
+ end
+ if (reset) begin // @[SPIMedia.scala 55:18]
+ clear <= 1'h0; // @[SPIMedia.scala 55:18]
+ end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
+ clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
+ end else if (2'h1 == state) begin // @[SPIMedia.scala 74:18]
+ clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
+ end else if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
+ clear <= 1'h0; // @[SPIMedia.scala 122:13]
+ end else begin
+ clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
+ end
+ if (reset) begin // @[SPIMedia.scala 56:22]
+ cs_assert <= 1'h0; // @[SPIMedia.scala 56:22]
+ end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
+ if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
+ if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
+ cs_assert <= _GEN_8;
+ end
+ end
+ end else if (!(2'h1 == state)) begin // @[SPIMedia.scala 74:18]
+ if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
+ cs_assert <= 1'h0; // @[SPIMedia.scala 121:17]
+ end
+ end
+ if (reset) begin // @[SPIMedia.scala 72:18]
+ state <= 2'h0; // @[SPIMedia.scala 72:18]
+ end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
+ if (cs_assert) begin // @[SPIMedia.scala 76:24]
+ if (cs_deassert) begin // @[SPIMedia.scala 77:28]
+ state <= _GEN_0;
+ end else begin
+ state <= _GEN_1;
+ end
+ end
+ end else if (2'h1 == state) begin // @[SPIMedia.scala 74:18]
+ if (phy_io_op_ready | continuous) begin // @[SPIMedia.scala 112:37]
+ state <= 2'h0; // @[SPIMedia.scala 113:15]
+ end
+ end else if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
+ state <= _GEN_29;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ cs_id = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ cs_dflt_0 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ cs_set = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ clear = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ cs_assert = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ state = _RAND_5[1:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module SPIFlashMap(
+ input clock,
+ input reset,
+ input io_en,
+ input [1:0] io_ctrl_insn_cmd_proto,
+ input [7:0] io_ctrl_insn_cmd_code,
+ input io_ctrl_insn_cmd_en,
+ input [1:0] io_ctrl_insn_addr_proto,
+ input [2:0] io_ctrl_insn_addr_len,
+ input [7:0] io_ctrl_insn_pad_code,
+ input [3:0] io_ctrl_insn_pad_cnt,
+ input [1:0] io_ctrl_insn_data_proto,
+ input io_ctrl_fmt_endian,
+ output io_addr_ready,
+ input io_addr_valid,
+ input [31:0] io_addr_bits_next,
+ input [31:0] io_addr_bits_hold,
+ input io_data_ready,
+ output io_data_valid,
+ output [7:0] io_data_bits,
+ input io_link_tx_ready,
+ output io_link_tx_valid,
+ output [7:0] io_link_tx_bits,
+ input io_link_rx_valid,
+ input [7:0] io_link_rx_bits,
+ output [7:0] io_link_cnt,
+ output [1:0] io_link_fmt_proto,
+ output io_link_fmt_endian,
+ output io_link_fmt_iodir,
+ output io_link_cs_clear,
+ input io_link_active,
+ output io_link_lock
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] addr = io_addr_bits_hold + 32'h1; // @[SPIFlash.scala 59:32]
+ wire merge = io_link_active & io_addr_bits_next == addr; // @[SPIFlash.scala 60:30]
+ wire _io_link_cnt_T = 2'h0 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
+ wire _io_link_cnt_T_1 = 2'h1 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
+ wire _io_link_cnt_T_2 = 2'h2 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
+ wire [3:0] _io_link_cnt_T_3 = _io_link_cnt_T ? 4'h8 : 4'h0; // @[Mux.scala 27:73]
+ wire [2:0] _io_link_cnt_T_4 = _io_link_cnt_T_1 ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_link_cnt_T_5 = _io_link_cnt_T_2 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
+ wire [3:0] _GEN_73 = {{1'd0}, _io_link_cnt_T_4}; // @[Mux.scala 27:73]
+ wire [3:0] _io_link_cnt_T_6 = _io_link_cnt_T_3 | _GEN_73; // @[Mux.scala 27:73]
+ wire [3:0] _GEN_74 = {{2'd0}, _io_link_cnt_T_5}; // @[Mux.scala 27:73]
+ wire [3:0] _io_link_cnt_T_7 = _io_link_cnt_T_6 | _GEN_74; // @[Mux.scala 27:73]
+ reg [3:0] cnt; // @[SPIFlash.scala 81:16]
+ wire cnt_cmp_0 = cnt == 4'h0; // @[SPIFlash.scala 83:48]
+ wire cnt_cmp_1 = cnt == 4'h1; // @[SPIFlash.scala 83:48]
+ wire cnt_cmp_2 = cnt == 4'h2; // @[SPIFlash.scala 83:48]
+ wire cnt_cmp_3 = cnt == 4'h3; // @[SPIFlash.scala 83:48]
+ wire cnt_cmp_4 = cnt == 4'h4; // @[SPIFlash.scala 83:48]
+ wire cnt_last = cnt_cmp_1 & io_link_tx_ready; // @[SPIFlash.scala 85:29]
+ wire cnt_done = cnt_last | cnt_cmp_0; // @[SPIFlash.scala 86:27]
+ wire _T = io_link_tx_ready & io_link_tx_valid; // @[Decoupled.scala 50:35]
+ wire [3:0] _cnt_T_1 = cnt - 4'h1; // @[SPIFlash.scala 90:18]
+ wire [3:0] _GEN_0 = _T ? _cnt_T_1 : cnt; // @[SPIFlash.scala 89:30 90:11 81:16]
+ reg [2:0] state; // @[SPIFlash.scala 95:18]
+ wire _GEN_54 = 3'h1 == state ? 1'h0 : 3'h2 == state; // @[SPIFlash.scala 97:18]
+ wire cnt_en = 3'h0 == state ? 1'h0 : _GEN_54; // @[SPIFlash.scala 97:18]
+ wire _GEN_1 = cnt_en ? ~cnt_cmp_0 : 1'h1; // @[SPIFlash.scala 87:17 63:20 88:22]
+ wire [3:0] _GEN_2 = cnt_en ? _GEN_0 : cnt; // @[SPIFlash.scala 81:16 87:17]
+ wire [2:0] _state_T = io_ctrl_insn_cmd_en ? 3'h1 : 3'h2; // @[SPIFlash.scala 106:25]
+ wire [2:0] _GEN_3 = merge ? 3'h4 : _state_T; // @[SPIFlash.scala 103:24 104:19 106:19]
+ wire _GEN_4 = merge ? 1'h0 : 1'h1; // @[SPIFlash.scala 103:24 72:20 107:30]
+ wire _GEN_6 = io_addr_valid & _GEN_4; // @[SPIFlash.scala 102:30 72:20]
+ wire _GEN_11 = io_en & _GEN_6; // @[SPIFlash.scala 100:20 72:20]
+ wire _GEN_12 = io_en & io_addr_valid; // @[SPIFlash.scala 100:20 114:22]
+ wire [7:0] _io_link_tx_bits_T_4 = cnt_cmp_1 ? io_addr_bits_hold[7:0] : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _io_link_tx_bits_T_5 = cnt_cmp_2 ? io_addr_bits_hold[15:8] : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _io_link_tx_bits_T_6 = cnt_cmp_3 ? io_addr_bits_hold[23:16] : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _io_link_tx_bits_T_7 = cnt_cmp_4 ? io_addr_bits_hold[31:24] : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _io_link_tx_bits_T_8 = _io_link_tx_bits_T_4 | _io_link_tx_bits_T_5; // @[Mux.scala 27:73]
+ wire [7:0] _io_link_tx_bits_T_9 = _io_link_tx_bits_T_8 | _io_link_tx_bits_T_6; // @[Mux.scala 27:73]
+ wire [7:0] _io_link_tx_bits_T_10 = _io_link_tx_bits_T_9 | _io_link_tx_bits_T_7; // @[Mux.scala 27:73]
+ wire [2:0] _GEN_15 = cnt_done ? 3'h3 : state; // @[SPIFlash.scala 139:23 140:15 95:18]
+ wire [2:0] _GEN_16 = io_link_tx_ready ? 3'h4 : state; // @[SPIFlash.scala 148:31 149:15 95:18]
+ wire [2:0] _GEN_17 = io_link_tx_ready ? 3'h5 : state; // @[SPIFlash.scala 156:31 157:15 95:18]
+ wire _T_7 = io_data_ready & io_data_valid; // @[Decoupled.scala 50:35]
+ wire [2:0] _GEN_18 = _T_7 ? 3'h0 : state; // @[SPIFlash.scala 164:29 165:15 95:18]
+ wire [2:0] _GEN_19 = io_data_ready ? 3'h0 : state; // @[SPIFlash.scala 172:28 173:15 95:18]
+ wire [7:0] _GEN_21 = 3'h6 == state ? 8'h0 : io_link_rx_bits; // @[SPIFlash.scala 97:18 171:20 79:16]
+ wire [2:0] _GEN_22 = 3'h6 == state ? _GEN_19 : state; // @[SPIFlash.scala 95:18 97:18]
+ wire _GEN_23 = 3'h5 == state ? 1'h0 : _GEN_1; // @[SPIFlash.scala 97:18 162:24]
+ wire _GEN_24 = 3'h5 == state ? io_link_rx_valid : 3'h6 == state; // @[SPIFlash.scala 97:18 163:21]
+ wire [2:0] _GEN_25 = 3'h5 == state ? _GEN_18 : _GEN_22; // @[SPIFlash.scala 97:18]
+ wire [7:0] _GEN_26 = 3'h5 == state ? io_link_rx_bits : _GEN_21; // @[SPIFlash.scala 79:16 97:18]
+ wire [1:0] _GEN_27 = 3'h4 == state ? io_ctrl_insn_data_proto : io_ctrl_insn_addr_proto; // @[SPIFlash.scala 97:18 154:25 64:21]
+ wire _GEN_28 = 3'h4 == state ? 1'h0 : 1'h1; // @[SPIFlash.scala 97:18 155:25 65:21]
+ wire [2:0] _GEN_29 = 3'h4 == state ? _GEN_17 : _GEN_25; // @[SPIFlash.scala 97:18]
+ wire _GEN_30 = 3'h4 == state ? _GEN_1 : _GEN_23; // @[SPIFlash.scala 97:18]
+ wire _GEN_31 = 3'h4 == state ? 1'h0 : _GEN_24; // @[SPIFlash.scala 78:17 97:18]
+ wire [7:0] _GEN_32 = 3'h4 == state ? io_link_rx_bits : _GEN_26; // @[SPIFlash.scala 79:16 97:18]
+ wire [3:0] _GEN_33 = 3'h3 == state ? io_ctrl_insn_pad_cnt : _io_link_cnt_T_7; // @[SPIFlash.scala 97:18 145:19 67:15]
+ wire [2:0] _GEN_35 = 3'h3 == state ? _GEN_16 : _GEN_29; // @[SPIFlash.scala 97:18]
+ wire [1:0] _GEN_36 = 3'h3 == state ? io_ctrl_insn_addr_proto : _GEN_27; // @[SPIFlash.scala 97:18 64:21]
+ wire _GEN_38 = 3'h3 == state ? _GEN_1 : _GEN_30; // @[SPIFlash.scala 97:18]
+ wire _GEN_39 = 3'h3 == state ? 1'h0 : _GEN_31; // @[SPIFlash.scala 78:17 97:18]
+ wire [7:0] _GEN_40 = 3'h3 == state ? io_link_rx_bits : _GEN_32; // @[SPIFlash.scala 79:16 97:18]
+ wire [7:0] _GEN_41 = 3'h2 == state ? _io_link_tx_bits_T_10 : io_ctrl_insn_pad_code; // @[SPIFlash.scala 97:18 131:23]
+ wire [3:0] _GEN_44 = 3'h2 == state ? _io_link_cnt_T_7 : _GEN_33; // @[SPIFlash.scala 67:15 97:18]
+ wire [1:0] _GEN_45 = 3'h2 == state ? io_ctrl_insn_addr_proto : _GEN_36; // @[SPIFlash.scala 97:18 64:21]
+ wire _GEN_47 = 3'h2 == state ? _GEN_1 : _GEN_38; // @[SPIFlash.scala 97:18]
+ wire _GEN_48 = 3'h2 == state ? 1'h0 : _GEN_39; // @[SPIFlash.scala 78:17 97:18]
+ wire [7:0] _GEN_49 = 3'h2 == state ? io_link_rx_bits : _GEN_40; // @[SPIFlash.scala 79:16 97:18]
+ wire [1:0] _GEN_50 = 3'h1 == state ? io_ctrl_insn_cmd_proto : _GEN_45; // @[SPIFlash.scala 97:18 122:25]
+ wire [3:0] _GEN_55 = 3'h1 == state ? _io_link_cnt_T_7 : _GEN_44; // @[SPIFlash.scala 67:15 97:18]
+ wire _GEN_57 = 3'h1 == state ? _GEN_1 : _GEN_47; // @[SPIFlash.scala 97:18]
+ wire _GEN_58 = 3'h1 == state ? 1'h0 : _GEN_48; // @[SPIFlash.scala 78:17 97:18]
+ wire [7:0] _GEN_59 = 3'h1 == state ? io_link_rx_bits : _GEN_49; // @[SPIFlash.scala 79:16 97:18]
+ wire [3:0] _GEN_69 = 3'h0 == state ? _io_link_cnt_T_7 : _GEN_55; // @[SPIFlash.scala 67:15 97:18]
+ assign io_addr_ready = 3'h0 == state; // @[SPIFlash.scala 97:18]
+ assign io_data_valid = 3'h0 == state ? 1'h0 : _GEN_58; // @[SPIFlash.scala 78:17 97:18]
+ assign io_data_bits = 3'h0 == state ? io_link_rx_bits : _GEN_59; // @[SPIFlash.scala 79:16 97:18]
+ assign io_link_tx_valid = 3'h0 == state ? 1'h0 : _GEN_57; // @[SPIFlash.scala 97:18 99:24]
+ assign io_link_tx_bits = 3'h1 == state ? io_ctrl_insn_cmd_code : _GEN_41; // @[SPIFlash.scala 97:18 123:23]
+ assign io_link_cnt = {{4'd0}, _GEN_69};
+ assign io_link_fmt_proto = 3'h0 == state ? io_ctrl_insn_addr_proto : _GEN_50; // @[SPIFlash.scala 97:18 64:21]
+ assign io_link_fmt_endian = io_ctrl_fmt_endian; // @[SPIFlash.scala 66:22]
+ assign io_link_fmt_iodir = 3'h0 == state | (3'h1 == state | (3'h2 == state | (3'h3 == state | _GEN_28))); // @[SPIFlash.scala 97:18 65:21]
+ assign io_link_cs_clear = 3'h0 == state & _GEN_11; // @[SPIFlash.scala 97:18 72:20]
+ assign io_link_lock = 3'h0 == state ? _GEN_12 : 1'h1; // @[SPIFlash.scala 74:16 97:18]
+ always @(posedge clock) begin
+ if (3'h0 == state) begin // @[SPIFlash.scala 97:18]
+ cnt <= _GEN_2;
+ end else if (3'h1 == state) begin // @[SPIFlash.scala 97:18]
+ if (io_link_tx_ready) begin // @[SPIFlash.scala 124:31]
+ cnt <= {{1'd0}, io_ctrl_insn_addr_len}; // @[SPIFlash.scala 126:13]
+ end else begin
+ cnt <= _GEN_2;
+ end
+ end else begin
+ cnt <= _GEN_2;
+ end
+ if (reset) begin // @[SPIFlash.scala 95:18]
+ state <= 3'h0; // @[SPIFlash.scala 95:18]
+ end else if (3'h0 == state) begin // @[SPIFlash.scala 97:18]
+ if (io_en) begin // @[SPIFlash.scala 100:20]
+ if (io_addr_valid) begin // @[SPIFlash.scala 102:30]
+ state <= _GEN_3;
+ end
+ end else if (io_addr_valid) begin // @[SPIFlash.scala 115:30]
+ state <= 3'h6; // @[SPIFlash.scala 116:17]
+ end
+ end else if (3'h1 == state) begin // @[SPIFlash.scala 97:18]
+ if (io_link_tx_ready) begin // @[SPIFlash.scala 124:31]
+ state <= 3'h2; // @[SPIFlash.scala 125:15]
+ end
+ end else if (3'h2 == state) begin // @[SPIFlash.scala 97:18]
+ state <= _GEN_15;
+ end else begin
+ state <= _GEN_35;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ cnt = _RAND_0[3:0];
+ _RAND_1 = {1{`RANDOM}};
+ state = _RAND_1[2:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module SPIArbiter(
+ input clock,
+ input reset,
+ output io_inner_0_tx_ready,
+ input io_inner_0_tx_valid,
+ input [7:0] io_inner_0_tx_bits,
+ output io_inner_0_rx_valid,
+ output [7:0] io_inner_0_rx_bits,
+ input [7:0] io_inner_0_cnt,
+ input [1:0] io_inner_0_fmt_proto,
+ input io_inner_0_fmt_endian,
+ input io_inner_0_fmt_iodir,
+ input io_inner_0_cs_clear,
+ output io_inner_0_active,
+ input io_inner_0_lock,
+ output io_inner_1_tx_ready,
+ input io_inner_1_tx_valid,
+ input [7:0] io_inner_1_tx_bits,
+ output io_inner_1_rx_valid,
+ output [7:0] io_inner_1_rx_bits,
+ input [7:0] io_inner_1_cnt,
+ input [1:0] io_inner_1_fmt_proto,
+ input io_inner_1_fmt_endian,
+ input io_inner_1_fmt_iodir,
+ input io_inner_1_cs_set,
+ input io_inner_1_cs_clear,
+ input io_inner_1_lock,
+ input io_outer_tx_ready,
+ output io_outer_tx_valid,
+ output [7:0] io_outer_tx_bits,
+ input io_outer_rx_valid,
+ input [7:0] io_outer_rx_bits,
+ output [7:0] io_outer_cnt,
+ output [1:0] io_outer_fmt_proto,
+ output io_outer_fmt_endian,
+ output io_outer_fmt_iodir,
+ output io_outer_cs_set,
+ output io_outer_cs_clear,
+ output io_outer_cs_hold,
+ input io_outer_active,
+ input io_sel
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+ reg sel_0; // @[SPIArbiter.scala 18:16]
+ reg sel_1; // @[SPIArbiter.scala 18:16]
+ wire [7:0] _io_outer_tx_bits_T = sel_0 ? io_inner_0_tx_bits : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _io_outer_tx_bits_T_1 = sel_1 ? io_inner_1_tx_bits : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _io_outer_cnt_T = sel_0 ? io_inner_0_cnt : 8'h0; // @[Mux.scala 27:73]
+ wire [7:0] _io_outer_cnt_T_1 = sel_1 ? io_inner_1_cnt : 8'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_outer_fmt_T_6 = sel_0 ? io_inner_0_fmt_proto : 2'h0; // @[Mux.scala 27:73]
+ wire [1:0] _io_outer_fmt_T_7 = sel_1 ? io_inner_1_fmt_proto : 2'h0; // @[Mux.scala 27:73]
+ wire _io_outer_cs_T_clear = sel_0 ? io_inner_0_cs_clear : io_inner_1_cs_clear; // @[SPIArbiter.scala 25:21]
+ wire nsel_0 = ~io_sel; // @[SPIArbiter.scala 36:37]
+ wire lock = sel_0 & io_inner_0_lock | sel_1 & io_inner_1_lock; // @[Mux.scala 27:73]
+ wire [1:0] _T_1 = {sel_1,sel_0}; // @[SPIArbiter.scala 40:15]
+ wire [1:0] _T_2 = {io_sel,nsel_0}; // @[SPIArbiter.scala 40:31]
+ wire _GEN_0 = _T_1 != _T_2 | _io_outer_cs_T_clear; // @[SPIArbiter.scala 25:15 40:39 41:25]
+ wire _GEN_1 = ~lock ? nsel_0 : sel_0; // @[SPIArbiter.scala 18:16 38:16 39:9]
+ assign io_inner_0_tx_ready = io_outer_tx_ready & sel_0; // @[SPIArbiter.scala 30:41]
+ assign io_inner_0_rx_valid = io_outer_rx_valid & sel_0; // @[SPIArbiter.scala 31:41]
+ assign io_inner_0_rx_bits = io_outer_rx_bits; // @[SPIArbiter.scala 32:19]
+ assign io_inner_0_active = io_outer_active & sel_0; // @[SPIArbiter.scala 33:37]
+ assign io_inner_1_tx_ready = io_outer_tx_ready & sel_1; // @[SPIArbiter.scala 30:41]
+ assign io_inner_1_rx_valid = io_outer_rx_valid & sel_1; // @[SPIArbiter.scala 31:41]
+ assign io_inner_1_rx_bits = io_outer_rx_bits; // @[SPIArbiter.scala 32:19]
+ assign io_outer_tx_valid = sel_0 & io_inner_0_tx_valid | sel_1 & io_inner_1_tx_valid; // @[Mux.scala 27:73]
+ assign io_outer_tx_bits = _io_outer_tx_bits_T | _io_outer_tx_bits_T_1; // @[Mux.scala 27:73]
+ assign io_outer_cnt = _io_outer_cnt_T | _io_outer_cnt_T_1; // @[Mux.scala 27:73]
+ assign io_outer_fmt_proto = _io_outer_fmt_T_6 | _io_outer_fmt_T_7; // @[Mux.scala 27:73]
+ assign io_outer_fmt_endian = sel_0 & io_inner_0_fmt_endian | sel_1 & io_inner_1_fmt_endian; // @[Mux.scala 27:73]
+ assign io_outer_fmt_iodir = sel_0 & io_inner_0_fmt_iodir | sel_1 & io_inner_1_fmt_iodir; // @[Mux.scala 27:73]
+ assign io_outer_cs_set = sel_0 | io_inner_1_cs_set; // @[SPIArbiter.scala 25:21]
+ assign io_outer_cs_clear = ~lock ? _GEN_0 : _io_outer_cs_T_clear; // @[SPIArbiter.scala 25:15 38:16]
+ assign io_outer_cs_hold = sel_0; // @[SPIArbiter.scala 25:21]
+ always @(posedge clock) begin
+ sel_0 <= reset | _GEN_1; // @[SPIArbiter.scala 18:{16,16}]
+ if (reset) begin // @[SPIArbiter.scala 18:16]
+ sel_1 <= 1'h0; // @[SPIArbiter.scala 18:16]
+ end else if (~lock) begin // @[SPIArbiter.scala 38:16]
+ sel_1 <= io_sel; // @[SPIArbiter.scala 39:9]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ sel_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ sel_1 = _RAND_1[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLSPIFlash(
+ input clock,
+ input reset,
+ output auto_int_xing_out_sync_0,
+ output auto_mem_xing_in_a_ready,
+ input auto_mem_xing_in_a_valid,
+ input [2:0] auto_mem_xing_in_a_bits_opcode,
+ input [2:0] auto_mem_xing_in_a_bits_param,
+ input auto_mem_xing_in_a_bits_size,
+ input [9:0] auto_mem_xing_in_a_bits_source,
+ input [29:0] auto_mem_xing_in_a_bits_address,
+ input auto_mem_xing_in_a_bits_mask,
+ input auto_mem_xing_in_a_bits_corrupt,
+ input auto_mem_xing_in_d_ready,
+ output auto_mem_xing_in_d_valid,
+ output auto_mem_xing_in_d_bits_size,
+ output [9:0] auto_mem_xing_in_d_bits_source,
+ output [7:0] auto_mem_xing_in_d_bits_data,
+ output auto_control_xing_in_a_ready,
+ input auto_control_xing_in_a_valid,
+ input [2:0] auto_control_xing_in_a_bits_opcode,
+ input [2:0] auto_control_xing_in_a_bits_param,
+ input [1:0] auto_control_xing_in_a_bits_size,
+ input [6:0] auto_control_xing_in_a_bits_source,
+ input [28:0] auto_control_xing_in_a_bits_address,
+ input [7:0] auto_control_xing_in_a_bits_mask,
+ input [63:0] auto_control_xing_in_a_bits_data,
+ input auto_control_xing_in_a_bits_corrupt,
+ input auto_control_xing_in_d_ready,
+ output auto_control_xing_in_d_valid,
+ output [2:0] auto_control_xing_in_d_bits_opcode,
+ output [1:0] auto_control_xing_in_d_bits_size,
+ output [6:0] auto_control_xing_in_d_bits_source,
+ output [63:0] auto_control_xing_in_d_bits_data,
+ output auto_io_out_sck,
+ input auto_io_out_dq_0_i,
+ output auto_io_out_dq_0_o,
+ output auto_io_out_dq_0_oe,
+ input auto_io_out_dq_1_i,
+ output auto_io_out_dq_1_o,
+ output auto_io_out_dq_1_oe,
+ input auto_io_out_dq_2_i,
+ output auto_io_out_dq_2_o,
+ output auto_io_out_dq_2_oe,
+ input auto_io_out_dq_3_i,
+ output auto_io_out_dq_3_o,
+ output auto_io_out_dq_3_oe,
+ output auto_io_out_cs_0
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [31:0] _RAND_30;
+ reg [31:0] _RAND_31;
+`endif // RANDOMIZE_REG_INIT
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [9:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [9:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [9:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [9:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire intsource_clock; // @[Crossing.scala 26:31]
+ wire intsource_reset; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [9:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [9:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_1_clock; // @[Nodes.scala 24:25]
+ wire monitor_1_reset; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_1_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire fifo_clock; // @[TLSPI.scala 69:20]
+ wire fifo_reset; // @[TLSPI.scala 69:20]
+ wire [1:0] fifo_io_ctrl_fmt_proto; // @[TLSPI.scala 69:20]
+ wire fifo_io_ctrl_fmt_endian; // @[TLSPI.scala 69:20]
+ wire fifo_io_ctrl_fmt_iodir; // @[TLSPI.scala 69:20]
+ wire [3:0] fifo_io_ctrl_fmt_len; // @[TLSPI.scala 69:20]
+ wire [1:0] fifo_io_ctrl_cs_mode; // @[TLSPI.scala 69:20]
+ wire [3:0] fifo_io_ctrl_wm_tx; // @[TLSPI.scala 69:20]
+ wire [3:0] fifo_io_ctrl_wm_rx; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_tx_ready; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_tx_valid; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_link_tx_bits; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_rx_valid; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_link_rx_bits; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_link_cnt; // @[TLSPI.scala 69:20]
+ wire [1:0] fifo_io_link_fmt_proto; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_fmt_endian; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_fmt_iodir; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_cs_set; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_cs_clear; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_lock; // @[TLSPI.scala 69:20]
+ wire fifo_io_tx_ready; // @[TLSPI.scala 69:20]
+ wire fifo_io_tx_valid; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_tx_bits; // @[TLSPI.scala 69:20]
+ wire fifo_io_rx_ready; // @[TLSPI.scala 69:20]
+ wire fifo_io_rx_valid; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_rx_bits; // @[TLSPI.scala 69:20]
+ wire fifo_io_ip_txwm; // @[TLSPI.scala 69:20]
+ wire fifo_io_ip_rxwm; // @[TLSPI.scala 69:20]
+ wire mac_clock; // @[TLSPI.scala 70:19]
+ wire mac_reset; // @[TLSPI.scala 70:19]
+ wire mac_io_port_sck; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_0_i; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_0_o; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_0_oe; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_1_i; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_1_o; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_1_oe; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_2_i; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_2_o; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_2_oe; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_3_i; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_3_o; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_3_oe; // @[TLSPI.scala 70:19]
+ wire mac_io_port_cs_0; // @[TLSPI.scala 70:19]
+ wire [11:0] mac_io_ctrl_sck_div; // @[TLSPI.scala 70:19]
+ wire mac_io_ctrl_sck_pol; // @[TLSPI.scala 70:19]
+ wire mac_io_ctrl_sck_pha; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_ctrl_dla_cssck; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_ctrl_dla_sckcs; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_ctrl_dla_intercs; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_ctrl_dla_interxfr; // @[TLSPI.scala 70:19]
+ wire mac_io_ctrl_cs_id; // @[TLSPI.scala 70:19]
+ wire mac_io_ctrl_cs_dflt_0; // @[TLSPI.scala 70:19]
+ wire [11:0] mac_io_ctrl_extradel_coarse; // @[TLSPI.scala 70:19]
+ wire [4:0] mac_io_ctrl_sampledel_sd; // @[TLSPI.scala 70:19]
+ wire mac_io_link_tx_ready; // @[TLSPI.scala 70:19]
+ wire mac_io_link_tx_valid; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_link_tx_bits; // @[TLSPI.scala 70:19]
+ wire mac_io_link_rx_valid; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_link_rx_bits; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_link_cnt; // @[TLSPI.scala 70:19]
+ wire [1:0] mac_io_link_fmt_proto; // @[TLSPI.scala 70:19]
+ wire mac_io_link_fmt_endian; // @[TLSPI.scala 70:19]
+ wire mac_io_link_fmt_iodir; // @[TLSPI.scala 70:19]
+ wire mac_io_link_cs_set; // @[TLSPI.scala 70:19]
+ wire mac_io_link_cs_clear; // @[TLSPI.scala 70:19]
+ wire mac_io_link_cs_hold; // @[TLSPI.scala 70:19]
+ wire mac_io_link_active; // @[TLSPI.scala 70:19]
+ wire flash_clock; // @[TLSPIFlash.scala 57:21]
+ wire flash_reset; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_en; // @[TLSPIFlash.scala 57:21]
+ wire [1:0] flash_io_ctrl_insn_cmd_proto; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_ctrl_insn_cmd_code; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_ctrl_insn_cmd_en; // @[TLSPIFlash.scala 57:21]
+ wire [1:0] flash_io_ctrl_insn_addr_proto; // @[TLSPIFlash.scala 57:21]
+ wire [2:0] flash_io_ctrl_insn_addr_len; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_ctrl_insn_pad_code; // @[TLSPIFlash.scala 57:21]
+ wire [3:0] flash_io_ctrl_insn_pad_cnt; // @[TLSPIFlash.scala 57:21]
+ wire [1:0] flash_io_ctrl_insn_data_proto; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_ctrl_fmt_endian; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_addr_ready; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_addr_valid; // @[TLSPIFlash.scala 57:21]
+ wire [31:0] flash_io_addr_bits_next; // @[TLSPIFlash.scala 57:21]
+ wire [31:0] flash_io_addr_bits_hold; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_data_ready; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_data_valid; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_data_bits; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_tx_ready; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_tx_valid; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_link_tx_bits; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_rx_valid; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_link_rx_bits; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_link_cnt; // @[TLSPIFlash.scala 57:21]
+ wire [1:0] flash_io_link_fmt_proto; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_fmt_endian; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_fmt_iodir; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_cs_clear; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_active; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_lock; // @[TLSPIFlash.scala 57:21]
+ wire arb_clock; // @[TLSPIFlash.scala 58:19]
+ wire arb_reset; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_tx_ready; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_tx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_0_tx_bits; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_rx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_0_rx_bits; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_0_cnt; // @[TLSPIFlash.scala 58:19]
+ wire [1:0] arb_io_inner_0_fmt_proto; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_fmt_endian; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_fmt_iodir; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_cs_clear; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_active; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_lock; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_tx_ready; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_tx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_1_tx_bits; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_rx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_1_rx_bits; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_1_cnt; // @[TLSPIFlash.scala 58:19]
+ wire [1:0] arb_io_inner_1_fmt_proto; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_fmt_endian; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_fmt_iodir; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_cs_set; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_cs_clear; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_lock; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_tx_ready; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_tx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_outer_tx_bits; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_rx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_outer_rx_bits; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_outer_cnt; // @[TLSPIFlash.scala 58:19]
+ wire [1:0] arb_io_outer_fmt_proto; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_fmt_endian; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_fmt_iodir; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_cs_set; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_cs_clear; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_cs_hold; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_active; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_sel; // @[TLSPIFlash.scala 58:19]
+ reg [1:0] ctrl_fmt_proto; // @[TLSPI.scala 68:17]
+ reg ctrl_fmt_endian; // @[TLSPI.scala 68:17]
+ reg ctrl_fmt_iodir; // @[TLSPI.scala 68:17]
+ reg [3:0] ctrl_fmt_len; // @[TLSPI.scala 68:17]
+ reg [11:0] ctrl_sck_div; // @[TLSPI.scala 68:17]
+ reg ctrl_sck_pol; // @[TLSPI.scala 68:17]
+ reg ctrl_sck_pha; // @[TLSPI.scala 68:17]
+ reg ctrl_cs_id; // @[TLSPI.scala 68:17]
+ reg ctrl_cs_dflt_0; // @[TLSPI.scala 68:17]
+ reg [1:0] ctrl_cs_mode; // @[TLSPI.scala 68:17]
+ reg [7:0] ctrl_dla_cssck; // @[TLSPI.scala 68:17]
+ reg [7:0] ctrl_dla_sckcs; // @[TLSPI.scala 68:17]
+ reg [7:0] ctrl_dla_intercs; // @[TLSPI.scala 68:17]
+ reg [7:0] ctrl_dla_interxfr; // @[TLSPI.scala 68:17]
+ reg [3:0] ctrl_wm_tx; // @[TLSPI.scala 68:17]
+ reg [3:0] ctrl_wm_rx; // @[TLSPI.scala 68:17]
+ reg [11:0] ctrl_extradel_coarse; // @[TLSPI.scala 68:17]
+ reg [4:0] ctrl_sampledel_sd; // @[TLSPI.scala 68:17]
+ reg ie_txwm; // @[TLSPI.scala 82:15]
+ reg ie_rxwm; // @[TLSPI.scala 82:15]
+ wire _T = ~fifo_io_tx_ready; // @[RegMapFIFO.scala 25:9]
+ wire _T_1 = ~fifo_io_rx_valid; // @[RegMapFIFO.scala 46:21]
+ reg a_size; // @[TLSPIFlash.scala 66:14]
+ reg [9:0] a_source; // @[TLSPIFlash.scala 66:14]
+ reg [29:0] a_address; // @[TLSPIFlash.scala 66:14]
+ wire bundleIn_0_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
+ wire bundleIn_0_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire _T_2 = bundleIn_0_a_ready & bundleIn_0_a_valid; // @[Decoupled.scala 50:35]
+ wire bundleIn_0_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [9:0] bundleIn_0_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [29:0] bundleIn_0_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ reg [1:0] insn_cmd_proto; // @[TLSPIFlash.scala 82:17]
+ reg [7:0] insn_cmd_code; // @[TLSPIFlash.scala 82:17]
+ reg insn_cmd_en; // @[TLSPIFlash.scala 82:17]
+ reg [1:0] insn_addr_proto; // @[TLSPIFlash.scala 82:17]
+ reg [2:0] insn_addr_len; // @[TLSPIFlash.scala 82:17]
+ reg [7:0] insn_pad_code; // @[TLSPIFlash.scala 82:17]
+ reg [3:0] insn_pad_cnt; // @[TLSPIFlash.scala 82:17]
+ reg [1:0] insn_data_proto; // @[TLSPIFlash.scala 82:17]
+ reg flash_en; // @[TLSPIFlash.scala 83:21]
+ wire [2:0] bundleIn_0_1_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire in_bits_read = bundleIn_0_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [28:0] bundleIn_0_1_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [8:0] in_bits_index = bundleIn_0_1_a_bits_address[11:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire [8:0] out_findex = in_bits_index & 9'h1f0; // @[RegisterRouter.scala 83:24]
+ wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] bundleIn_0_1_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [7:0] _out_frontMask_T_9 = bundleIn_0_1_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_11 = bundleIn_0_1_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_13 = bundleIn_0_1_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_15 = bundleIn_0_1_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_17 = bundleIn_0_1_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_19 = bundleIn_0_1_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_21 = bundleIn_0_1_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_23 = bundleIn_0_1_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_frontMask = {_out_frontMask_T_23,_out_frontMask_T_21,_out_frontMask_T_19,_out_frontMask_T_17,
+ _out_frontMask_T_15,_out_frontMask_T_13,_out_frontMask_T_11,_out_frontMask_T_9}; // @[Cat.scala 31:58]
+ wire out_wimask = &out_frontMask[11:0]; // @[RegisterRouter.scala 83:24]
+ wire bundleIn_0_1_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire bundleIn_0_1_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [3:0] out_oindex = {in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [15:0] _out_frontSel_T = 16'h1 << out_oindex; // @[OneHot.scala 57:35]
+ wire out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_0 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire [63:0] bundleIn_0_1_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire out_wimask_1 = &out_frontMask[32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1 = out_wivalid_0 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T = {{20'd0}, ctrl_sck_div}; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_2 = &out_frontMask[33]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_2 = out_wivalid_0 & out_wimask_2; // @[RegisterRouter.scala 83:24]
+ wire [33:0] out_prepend_1 = {ctrl_sck_pol,ctrl_sck_pha,_out_prepend_T}; // @[Cat.scala 31:58]
+ wire out_wimask_3 = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_5 = _out_frontSel_T[5]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_3 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_5 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_4 = &out_frontMask[23:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_4 = out_wivalid_3 & out_wimask_4; // @[RegisterRouter.scala 83:24]
+ wire [15:0] _out_prepend_T_2 = {{8'd0}, ctrl_dla_cssck}; // @[RegisterRouter.scala 83:24]
+ wire [23:0] out_prepend_2 = {ctrl_dla_sckcs,_out_prepend_T_2}; // @[Cat.scala 31:58]
+ wire out_rimask_5 = |out_frontMask[39:32]; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_5 = &out_frontMask[39:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_5 = out_wivalid_3 & out_wimask_5; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_3 = {{8'd0}, out_prepend_2}; // @[RegisterRouter.scala 83:24]
+ wire [39:0] out_prepend_3 = {ctrl_dla_intercs,_out_prepend_T_3}; // @[Cat.scala 31:58]
+ wire out_wimask_6 = &out_frontMask[55:48]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_6 = out_wivalid_3 & out_wimask_6; // @[RegisterRouter.scala 83:24]
+ wire [47:0] _out_prepend_T_4 = {{8'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
+ wire [55:0] out_prepend_4 = {ctrl_dla_interxfr,_out_prepend_T_4}; // @[Cat.scala 31:58]
+ wire out_wimask_7 = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_7 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_8 = &out_frontMask[35:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_8 = out_wivalid_7 & out_wimask_8; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_5 = {{28'd0}, ctrl_wm_tx}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_5 = {ctrl_wm_rx,_out_prepend_T_5}; // @[Cat.scala 31:58]
+ wire out_wimask_9 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_14 = _out_frontSel_T[14]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_9 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_14 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_10 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_10 = out_wivalid_9 & out_wimask_10; // @[RegisterRouter.scala 83:24]
+ wire [1:0] out_prepend_6 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
+ wire [31:0] _out_prepend_T_7 = {{30'd0}, out_prepend_6}; // @[RegisterRouter.scala 83:24]
+ wire [33:0] out_prepend_8 = {fifo_io_ip_rxwm,fifo_io_ip_txwm,_out_prepend_T_7}; // @[Cat.scala 31:58]
+ wire out_frontSel_9 = _out_frontSel_T[9]; // @[RegisterRouter.scala 83:24]
+ wire out_rivalid_13 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & in_bits_read & out_frontSel_9 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_13 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_9 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_3; // @[RegisterRouter.scala 83:24]
+ wire out_womask_15 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_15 = out_wivalid_13 & out_womask_15; // @[RegisterRouter.scala 83:24]
+ wire quash = out_f_woready_15 & bundleIn_0_1_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
+ wire [40:0] out_prepend_12 = {1'h0,fifo_io_rx_bits,_T,31'h0}; // @[Cat.scala 31:58]
+ wire [62:0] _out_T_202 = {{22'd0}, out_prepend_12}; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_13 = {_T_1,_out_T_202}; // @[Cat.scala 31:58]
+ wire out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_19 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_9; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_20 = out_wivalid_19 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire _GEN_20 = out_f_wivalid_20 ? bundleIn_0_1_a_bits_data[32] : ctrl_cs_dflt_0; // @[RegField.scala 74:{88,92} TLSPI.scala 68:17]
+ wire [31:0] _out_prepend_T_14 = {{31'd0}, ctrl_cs_id}; // @[RegisterRouter.scala 83:24]
+ wire [32:0] out_prepend_14 = {ctrl_cs_dflt_0,_out_prepend_T_14}; // @[Cat.scala 31:58]
+ wire out_frontSel_12 = _out_frontSel_T[12]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_21 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_12 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_9; // @[RegisterRouter.scala 83:24]
+ wire _GEN_21 = out_f_wivalid_21 ? bundleIn_0_1_a_bits_data[0] : flash_en; // @[RegField.scala 74:{88,92} TLSPIFlash.scala 83:21]
+ wire out_f_wivalid_22 = out_wivalid_21 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire _GEN_22 = out_f_wivalid_22 ? bundleIn_0_1_a_bits_data[32] : insn_cmd_en; // @[RegField.scala 74:{88,92} TLSPIFlash.scala 82:17]
+ wire [31:0] _out_prepend_T_15 = {{31'd0}, flash_en}; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_23 = &out_frontMask[35:33]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_23 = out_wivalid_21 & out_wimask_23; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_24 = &out_frontMask[39:36]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_24 = out_wivalid_21 & out_wimask_24; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_25 = &out_frontMask[41:40]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_25 = out_wivalid_21 & out_wimask_25; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_26 = &out_frontMask[43:42]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_26 = out_wivalid_21 & out_wimask_26; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_27 = &out_frontMask[45:44]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_27 = out_wivalid_21 & out_wimask_27; // @[RegisterRouter.scala 83:24]
+ wire [45:0] out_prepend_20 = {insn_data_proto,insn_addr_proto,insn_cmd_proto,insn_pad_cnt,insn_addr_len,insn_cmd_en,
+ _out_prepend_T_15}; // @[Cat.scala 31:58]
+ wire out_f_wivalid_28 = out_wivalid_21 & out_wimask_6; // @[RegisterRouter.scala 83:24]
+ wire [47:0] _out_prepend_T_21 = {{2'd0}, out_prepend_20}; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_29 = &out_frontMask[63:56]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_29 = out_wivalid_21 & out_wimask_29; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_22 = {insn_pad_code,insn_cmd_code,_out_prepend_T_21}; // @[Cat.scala 31:58]
+ wire out_frontSel_7 = _out_frontSel_T[7]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_30 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_7 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_30 = out_wivalid_30 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_31 = &out_frontMask[36:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_31 = out_wivalid_30 & out_wimask_31; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_23 = {{20'd0}, ctrl_extradel_coarse}; // @[RegisterRouter.scala 83:24]
+ wire [36:0] out_prepend_23 = {ctrl_sampledel_sd,_out_prepend_T_23}; // @[Cat.scala 31:58]
+ wire out_wimask_32 = &out_frontMask[1:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_32 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_8 = _out_frontSel_T[8]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_33 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_8 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_32; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_34 = &out_frontMask[2]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_34 = out_wivalid_33 & out_wimask_34; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_35 = &out_frontMask[3]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_35 = out_wivalid_33 & out_wimask_35; // @[RegisterRouter.scala 83:24]
+ wire [3:0] out_prepend_25 = {ctrl_fmt_iodir,ctrl_fmt_endian,ctrl_fmt_proto}; // @[Cat.scala 31:58]
+ wire out_wimask_36 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_36 = out_wivalid_33 & out_wimask_36; // @[RegisterRouter.scala 83:24]
+ wire [15:0] _out_prepend_T_26 = {{12'd0}, out_prepend_25}; // @[RegisterRouter.scala 83:24]
+ wire [19:0] out_prepend_26 = {ctrl_fmt_len,_out_prepend_T_26}; // @[Cat.scala 31:58]
+ wire _GEN_103 = 4'h2 == out_oindex ? _out_T : 4'h1 == out_oindex | _out_T; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_104 = 4'h3 == out_oindex ? _out_T : _GEN_103; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_106 = 4'h5 == out_oindex ? _out_T : 4'h4 == out_oindex | _GEN_104; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_108 = 4'h7 == out_oindex ? _out_T : 4'h6 == out_oindex | _GEN_106; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_109 = 4'h8 == out_oindex ? _out_T : _GEN_108; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_110 = 4'h9 == out_oindex ? _out_T : _GEN_109; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_111 = 4'ha == out_oindex ? _out_T : _GEN_110; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_113 = 4'hc == out_oindex ? _out_T : 4'hb == out_oindex | _GEN_111; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_115 = 4'he == out_oindex ? _out_T : 4'hd == out_oindex | _GEN_113; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_116 = 4'hf == out_oindex | _GEN_115; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_0 = {{30'd0}, out_prepend_1}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_118 = 4'h1 == out_oindex ? 64'h0 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_2 = {{31'd0}, out_prepend_14}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_119 = 4'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_118; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_3 = {{62'd0}, ctrl_cs_mode}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_120 = 4'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_119; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_121 = 4'h4 == out_oindex ? 64'h0 : _GEN_120; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_5 = {{8'd0}, out_prepend_4}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_122 = 4'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_121; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_123 = 4'h6 == out_oindex ? 64'h0 : _GEN_122; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_7 = {{27'd0}, out_prepend_23}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_124 = 4'h7 == out_oindex ? _out_out_bits_data_WIRE_1_7 : _GEN_123; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_8 = {{44'd0}, out_prepend_26}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_125 = 4'h8 == out_oindex ? _out_out_bits_data_WIRE_1_8 : _GEN_124; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_126 = 4'h9 == out_oindex ? out_prepend_13 : _GEN_125; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_10 = {{28'd0}, out_prepend_5}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_127 = 4'ha == out_oindex ? _out_out_bits_data_WIRE_1_10 : _GEN_126; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_128 = 4'hb == out_oindex ? 64'h0 : _GEN_127; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_129 = 4'hc == out_oindex ? out_prepend_22 : _GEN_128; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_130 = 4'hd == out_oindex ? 64'h0 : _GEN_129; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_14 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_131 = 4'he == out_oindex ? _out_out_bits_data_WIRE_1_14 : _GEN_130; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_132 = 4'hf == out_oindex ? 64'h0 : _GEN_131; // @[MuxLiteral.scala 48:{10,10}]
+ TLBuffer_20 buffer ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ TLBuffer_24 buffer_1 ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_1_auto_in_a_ready),
+ .auto_in_a_valid(buffer_1_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_1_auto_in_d_ready),
+ .auto_in_d_valid(buffer_1_auto_in_d_valid),
+ .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_1_auto_out_a_ready),
+ .auto_out_a_valid(buffer_1_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_1_auto_out_d_ready),
+ .auto_out_d_valid(buffer_1_auto_out_d_valid),
+ .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data)
+ );
+ IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
+ .clock(intsource_clock),
+ .reset(intsource_reset),
+ .auto_in_0(intsource_auto_in_0),
+ .auto_out_sync_0(intsource_auto_out_sync_0)
+ );
+ TLMonitor_58 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ TLMonitor_59 monitor_1 ( // @[Nodes.scala 24:25]
+ .clock(monitor_1_clock),
+ .reset(monitor_1_reset),
+ .io_in_a_ready(monitor_1_io_in_a_ready),
+ .io_in_a_valid(monitor_1_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_1_io_in_d_ready),
+ .io_in_d_valid(monitor_1_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_1_io_in_d_bits_source)
+ );
+ SPIFIFO fifo ( // @[TLSPI.scala 69:20]
+ .clock(fifo_clock),
+ .reset(fifo_reset),
+ .io_ctrl_fmt_proto(fifo_io_ctrl_fmt_proto),
+ .io_ctrl_fmt_endian(fifo_io_ctrl_fmt_endian),
+ .io_ctrl_fmt_iodir(fifo_io_ctrl_fmt_iodir),
+ .io_ctrl_fmt_len(fifo_io_ctrl_fmt_len),
+ .io_ctrl_cs_mode(fifo_io_ctrl_cs_mode),
+ .io_ctrl_wm_tx(fifo_io_ctrl_wm_tx),
+ .io_ctrl_wm_rx(fifo_io_ctrl_wm_rx),
+ .io_link_tx_ready(fifo_io_link_tx_ready),
+ .io_link_tx_valid(fifo_io_link_tx_valid),
+ .io_link_tx_bits(fifo_io_link_tx_bits),
+ .io_link_rx_valid(fifo_io_link_rx_valid),
+ .io_link_rx_bits(fifo_io_link_rx_bits),
+ .io_link_cnt(fifo_io_link_cnt),
+ .io_link_fmt_proto(fifo_io_link_fmt_proto),
+ .io_link_fmt_endian(fifo_io_link_fmt_endian),
+ .io_link_fmt_iodir(fifo_io_link_fmt_iodir),
+ .io_link_cs_set(fifo_io_link_cs_set),
+ .io_link_cs_clear(fifo_io_link_cs_clear),
+ .io_link_lock(fifo_io_link_lock),
+ .io_tx_ready(fifo_io_tx_ready),
+ .io_tx_valid(fifo_io_tx_valid),
+ .io_tx_bits(fifo_io_tx_bits),
+ .io_rx_ready(fifo_io_rx_ready),
+ .io_rx_valid(fifo_io_rx_valid),
+ .io_rx_bits(fifo_io_rx_bits),
+ .io_ip_txwm(fifo_io_ip_txwm),
+ .io_ip_rxwm(fifo_io_ip_rxwm)
+ );
+ SPIMedia mac ( // @[TLSPI.scala 70:19]
+ .clock(mac_clock),
+ .reset(mac_reset),
+ .io_port_sck(mac_io_port_sck),
+ .io_port_dq_0_i(mac_io_port_dq_0_i),
+ .io_port_dq_0_o(mac_io_port_dq_0_o),
+ .io_port_dq_0_oe(mac_io_port_dq_0_oe),
+ .io_port_dq_1_i(mac_io_port_dq_1_i),
+ .io_port_dq_1_o(mac_io_port_dq_1_o),
+ .io_port_dq_1_oe(mac_io_port_dq_1_oe),
+ .io_port_dq_2_i(mac_io_port_dq_2_i),
+ .io_port_dq_2_o(mac_io_port_dq_2_o),
+ .io_port_dq_2_oe(mac_io_port_dq_2_oe),
+ .io_port_dq_3_i(mac_io_port_dq_3_i),
+ .io_port_dq_3_o(mac_io_port_dq_3_o),
+ .io_port_dq_3_oe(mac_io_port_dq_3_oe),
+ .io_port_cs_0(mac_io_port_cs_0),
+ .io_ctrl_sck_div(mac_io_ctrl_sck_div),
+ .io_ctrl_sck_pol(mac_io_ctrl_sck_pol),
+ .io_ctrl_sck_pha(mac_io_ctrl_sck_pha),
+ .io_ctrl_dla_cssck(mac_io_ctrl_dla_cssck),
+ .io_ctrl_dla_sckcs(mac_io_ctrl_dla_sckcs),
+ .io_ctrl_dla_intercs(mac_io_ctrl_dla_intercs),
+ .io_ctrl_dla_interxfr(mac_io_ctrl_dla_interxfr),
+ .io_ctrl_cs_id(mac_io_ctrl_cs_id),
+ .io_ctrl_cs_dflt_0(mac_io_ctrl_cs_dflt_0),
+ .io_ctrl_extradel_coarse(mac_io_ctrl_extradel_coarse),
+ .io_ctrl_sampledel_sd(mac_io_ctrl_sampledel_sd),
+ .io_link_tx_ready(mac_io_link_tx_ready),
+ .io_link_tx_valid(mac_io_link_tx_valid),
+ .io_link_tx_bits(mac_io_link_tx_bits),
+ .io_link_rx_valid(mac_io_link_rx_valid),
+ .io_link_rx_bits(mac_io_link_rx_bits),
+ .io_link_cnt(mac_io_link_cnt),
+ .io_link_fmt_proto(mac_io_link_fmt_proto),
+ .io_link_fmt_endian(mac_io_link_fmt_endian),
+ .io_link_fmt_iodir(mac_io_link_fmt_iodir),
+ .io_link_cs_set(mac_io_link_cs_set),
+ .io_link_cs_clear(mac_io_link_cs_clear),
+ .io_link_cs_hold(mac_io_link_cs_hold),
+ .io_link_active(mac_io_link_active)
+ );
+ SPIFlashMap flash ( // @[TLSPIFlash.scala 57:21]
+ .clock(flash_clock),
+ .reset(flash_reset),
+ .io_en(flash_io_en),
+ .io_ctrl_insn_cmd_proto(flash_io_ctrl_insn_cmd_proto),
+ .io_ctrl_insn_cmd_code(flash_io_ctrl_insn_cmd_code),
+ .io_ctrl_insn_cmd_en(flash_io_ctrl_insn_cmd_en),
+ .io_ctrl_insn_addr_proto(flash_io_ctrl_insn_addr_proto),
+ .io_ctrl_insn_addr_len(flash_io_ctrl_insn_addr_len),
+ .io_ctrl_insn_pad_code(flash_io_ctrl_insn_pad_code),
+ .io_ctrl_insn_pad_cnt(flash_io_ctrl_insn_pad_cnt),
+ .io_ctrl_insn_data_proto(flash_io_ctrl_insn_data_proto),
+ .io_ctrl_fmt_endian(flash_io_ctrl_fmt_endian),
+ .io_addr_ready(flash_io_addr_ready),
+ .io_addr_valid(flash_io_addr_valid),
+ .io_addr_bits_next(flash_io_addr_bits_next),
+ .io_addr_bits_hold(flash_io_addr_bits_hold),
+ .io_data_ready(flash_io_data_ready),
+ .io_data_valid(flash_io_data_valid),
+ .io_data_bits(flash_io_data_bits),
+ .io_link_tx_ready(flash_io_link_tx_ready),
+ .io_link_tx_valid(flash_io_link_tx_valid),
+ .io_link_tx_bits(flash_io_link_tx_bits),
+ .io_link_rx_valid(flash_io_link_rx_valid),
+ .io_link_rx_bits(flash_io_link_rx_bits),
+ .io_link_cnt(flash_io_link_cnt),
+ .io_link_fmt_proto(flash_io_link_fmt_proto),
+ .io_link_fmt_endian(flash_io_link_fmt_endian),
+ .io_link_fmt_iodir(flash_io_link_fmt_iodir),
+ .io_link_cs_clear(flash_io_link_cs_clear),
+ .io_link_active(flash_io_link_active),
+ .io_link_lock(flash_io_link_lock)
+ );
+ SPIArbiter arb ( // @[TLSPIFlash.scala 58:19]
+ .clock(arb_clock),
+ .reset(arb_reset),
+ .io_inner_0_tx_ready(arb_io_inner_0_tx_ready),
+ .io_inner_0_tx_valid(arb_io_inner_0_tx_valid),
+ .io_inner_0_tx_bits(arb_io_inner_0_tx_bits),
+ .io_inner_0_rx_valid(arb_io_inner_0_rx_valid),
+ .io_inner_0_rx_bits(arb_io_inner_0_rx_bits),
+ .io_inner_0_cnt(arb_io_inner_0_cnt),
+ .io_inner_0_fmt_proto(arb_io_inner_0_fmt_proto),
+ .io_inner_0_fmt_endian(arb_io_inner_0_fmt_endian),
+ .io_inner_0_fmt_iodir(arb_io_inner_0_fmt_iodir),
+ .io_inner_0_cs_clear(arb_io_inner_0_cs_clear),
+ .io_inner_0_active(arb_io_inner_0_active),
+ .io_inner_0_lock(arb_io_inner_0_lock),
+ .io_inner_1_tx_ready(arb_io_inner_1_tx_ready),
+ .io_inner_1_tx_valid(arb_io_inner_1_tx_valid),
+ .io_inner_1_tx_bits(arb_io_inner_1_tx_bits),
+ .io_inner_1_rx_valid(arb_io_inner_1_rx_valid),
+ .io_inner_1_rx_bits(arb_io_inner_1_rx_bits),
+ .io_inner_1_cnt(arb_io_inner_1_cnt),
+ .io_inner_1_fmt_proto(arb_io_inner_1_fmt_proto),
+ .io_inner_1_fmt_endian(arb_io_inner_1_fmt_endian),
+ .io_inner_1_fmt_iodir(arb_io_inner_1_fmt_iodir),
+ .io_inner_1_cs_set(arb_io_inner_1_cs_set),
+ .io_inner_1_cs_clear(arb_io_inner_1_cs_clear),
+ .io_inner_1_lock(arb_io_inner_1_lock),
+ .io_outer_tx_ready(arb_io_outer_tx_ready),
+ .io_outer_tx_valid(arb_io_outer_tx_valid),
+ .io_outer_tx_bits(arb_io_outer_tx_bits),
+ .io_outer_rx_valid(arb_io_outer_rx_valid),
+ .io_outer_rx_bits(arb_io_outer_rx_bits),
+ .io_outer_cnt(arb_io_outer_cnt),
+ .io_outer_fmt_proto(arb_io_outer_fmt_proto),
+ .io_outer_fmt_endian(arb_io_outer_fmt_endian),
+ .io_outer_fmt_iodir(arb_io_outer_fmt_iodir),
+ .io_outer_cs_set(arb_io_outer_cs_set),
+ .io_outer_cs_clear(arb_io_outer_cs_clear),
+ .io_outer_cs_hold(arb_io_outer_cs_hold),
+ .io_outer_active(arb_io_outer_active),
+ .io_sel(arb_io_sel)
+ );
+ assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_mem_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_mem_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_mem_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_mem_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_io_out_sck = mac_io_port_sck; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_0_o = mac_io_port_dq_0_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_0_oe = mac_io_port_dq_0_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_1_o = mac_io_port_dq_1_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_1_oe = mac_io_port_dq_1_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_2_o = mac_io_port_dq_2_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_2_oe = mac_io_port_dq_2_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_3_o = mac_io_port_dq_3_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_3_oe = mac_io_port_dq_3_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_cs_0 = mac_io_port_cs_0; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = _GEN_116 ? _GEN_132 : 64'h0; // @[RegisterRouter.scala 83:24]
+ assign buffer_1_auto_in_a_valid = auto_mem_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_opcode = auto_mem_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_param = auto_mem_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_size = auto_mem_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_source = auto_mem_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_address = auto_mem_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_mask = auto_mem_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_corrupt = auto_mem_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_d_ready = auto_mem_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_out_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
+ assign buffer_1_auto_out_d_valid = flash_io_data_valid; // @[Nodes.scala 1210:84 TLSPIFlash.scala 79:13]
+ assign buffer_1_auto_out_d_bits_size = a_size; // @[Edges.scala 771:17 774:15]
+ assign buffer_1_auto_out_d_bits_source = a_source; // @[Edges.scala 771:17 775:15]
+ assign buffer_1_auto_out_d_bits_data = flash_io_data_bits; // @[Edges.scala 771:17 778:15]
+ assign intsource_clock = clock;
+ assign intsource_reset = reset;
+ assign intsource_auto_in_0 = fifo_io_ip_txwm & ie_txwm | fifo_io_ip_rxwm & ie_rxwm; // @[TLSPI.scala 84:47]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
+ assign monitor_io_in_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_valid = flash_io_data_valid; // @[Nodes.scala 1210:84 TLSPIFlash.scala 79:13]
+ assign monitor_io_in_d_bits_size = a_size; // @[Edges.scala 771:17 774:15]
+ assign monitor_io_in_d_bits_source = a_source; // @[Edges.scala 771:17 775:15]
+ assign monitor_1_clock = clock;
+ assign monitor_1_reset = reset;
+ assign monitor_1_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_1_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign fifo_clock = clock;
+ assign fifo_reset = reset;
+ assign fifo_io_ctrl_fmt_proto = ctrl_fmt_proto; // @[TLSPI.scala 73:20]
+ assign fifo_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPI.scala 73:20]
+ assign fifo_io_ctrl_fmt_iodir = ctrl_fmt_iodir; // @[TLSPI.scala 73:20]
+ assign fifo_io_ctrl_fmt_len = ctrl_fmt_len; // @[TLSPI.scala 73:20]
+ assign fifo_io_ctrl_cs_mode = ctrl_cs_mode; // @[TLSPI.scala 74:19]
+ assign fifo_io_ctrl_wm_tx = ctrl_wm_tx; // @[TLSPI.scala 75:19]
+ assign fifo_io_ctrl_wm_rx = ctrl_wm_rx; // @[TLSPI.scala 75:19]
+ assign fifo_io_link_tx_ready = arb_io_inner_1_tx_ready; // @[TLSPIFlash.scala 139:21]
+ assign fifo_io_link_rx_valid = arb_io_inner_1_rx_valid; // @[TLSPIFlash.scala 139:21]
+ assign fifo_io_link_rx_bits = arb_io_inner_1_rx_bits; // @[TLSPIFlash.scala 139:21]
+ assign fifo_io_tx_valid = out_f_wivalid_13 & ~quash; // @[RegMapFIFO.scala 19:30]
+ assign fifo_io_tx_bits = bundleIn_0_1_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
+ assign fifo_io_rx_ready = out_rivalid_13 & out_rimask_5; // @[RegisterRouter.scala 83:24]
+ assign mac_clock = clock;
+ assign mac_reset = reset;
+ assign mac_io_port_dq_0_i = auto_io_out_dq_0_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign mac_io_port_dq_1_i = auto_io_out_dq_1_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign mac_io_port_dq_2_i = auto_io_out_dq_2_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign mac_io_port_dq_3_i = auto_io_out_dq_3_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign mac_io_ctrl_sck_div = ctrl_sck_div; // @[TLSPI.scala 76:19]
+ assign mac_io_ctrl_sck_pol = ctrl_sck_pol; // @[TLSPI.scala 76:19]
+ assign mac_io_ctrl_sck_pha = ctrl_sck_pha; // @[TLSPI.scala 76:19]
+ assign mac_io_ctrl_dla_cssck = ctrl_dla_cssck; // @[TLSPI.scala 79:19]
+ assign mac_io_ctrl_dla_sckcs = ctrl_dla_sckcs; // @[TLSPI.scala 79:19]
+ assign mac_io_ctrl_dla_intercs = ctrl_dla_intercs; // @[TLSPI.scala 79:19]
+ assign mac_io_ctrl_dla_interxfr = ctrl_dla_interxfr; // @[TLSPI.scala 79:19]
+ assign mac_io_ctrl_cs_id = ctrl_cs_id; // @[TLSPI.scala 80:18]
+ assign mac_io_ctrl_cs_dflt_0 = ctrl_cs_dflt_0; // @[TLSPI.scala 80:18]
+ assign mac_io_ctrl_extradel_coarse = ctrl_extradel_coarse; // @[TLSPI.scala 77:24]
+ assign mac_io_ctrl_sampledel_sd = ctrl_sampledel_sd; // @[TLSPI.scala 78:25]
+ assign mac_io_link_tx_valid = arb_io_outer_tx_valid; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_tx_bits = arb_io_outer_tx_bits; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_cnt = arb_io_outer_cnt; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_fmt_proto = arb_io_outer_fmt_proto; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_fmt_endian = arb_io_outer_fmt_endian; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_fmt_iodir = arb_io_outer_fmt_iodir; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_cs_set = arb_io_outer_cs_set; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_cs_clear = arb_io_outer_cs_clear; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_cs_hold = arb_io_outer_cs_hold; // @[TLSPIFlash.scala 140:17]
+ assign flash_clock = clock;
+ assign flash_reset = reset;
+ assign flash_io_en = flash_en; // @[TLSPIFlash.scala 87:15]
+ assign flash_io_ctrl_insn_cmd_proto = insn_cmd_proto; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_cmd_code = insn_cmd_code; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_cmd_en = insn_cmd_en; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_addr_proto = insn_addr_proto; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_addr_len = insn_addr_len; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_pad_code = insn_pad_code; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_pad_cnt = insn_pad_cnt; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_data_proto = insn_data_proto; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPIFlash.scala 86:21]
+ assign flash_io_addr_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign flash_io_addr_bits_next = {{4'd0}, bundleIn_0_a_bits_address[27:0]}; // @[TLSPIFlash.scala 73:27]
+ assign flash_io_addr_bits_hold = {{4'd0}, a_address[27:0]}; // @[TLSPIFlash.scala 74:27]
+ assign flash_io_data_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign flash_io_link_tx_ready = arb_io_inner_0_tx_ready; // @[TLSPIFlash.scala 138:21]
+ assign flash_io_link_rx_valid = arb_io_inner_0_rx_valid; // @[TLSPIFlash.scala 138:21]
+ assign flash_io_link_rx_bits = arb_io_inner_0_rx_bits; // @[TLSPIFlash.scala 138:21]
+ assign flash_io_link_active = arb_io_inner_0_active; // @[TLSPIFlash.scala 138:21]
+ assign arb_clock = clock;
+ assign arb_reset = reset;
+ assign arb_io_inner_0_tx_valid = flash_io_link_tx_valid; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_tx_bits = flash_io_link_tx_bits; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_cnt = flash_io_link_cnt; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_fmt_proto = flash_io_link_fmt_proto; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_fmt_endian = flash_io_link_fmt_endian; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_fmt_iodir = flash_io_link_fmt_iodir; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_cs_clear = flash_io_link_cs_clear; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_lock = flash_io_link_lock; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_1_tx_valid = fifo_io_link_tx_valid; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_tx_bits = fifo_io_link_tx_bits; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_cnt = fifo_io_link_cnt; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_fmt_proto = fifo_io_link_fmt_proto; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_fmt_endian = fifo_io_link_fmt_endian; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_fmt_iodir = fifo_io_link_fmt_iodir; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_cs_set = fifo_io_link_cs_set; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_cs_clear = fifo_io_link_cs_clear; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_lock = fifo_io_link_lock; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_outer_tx_ready = mac_io_link_tx_ready; // @[TLSPIFlash.scala 140:17]
+ assign arb_io_outer_rx_valid = mac_io_link_rx_valid; // @[TLSPIFlash.scala 140:17]
+ assign arb_io_outer_rx_bits = mac_io_link_rx_bits; // @[TLSPIFlash.scala 140:17]
+ assign arb_io_outer_active = mac_io_link_active; // @[TLSPIFlash.scala 140:17]
+ assign arb_io_sel = ~flash_en; // @[TLSPIFlash.scala 88:17]
+ always @(posedge clock) begin
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_fmt_proto <= 2'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_33) begin // @[RegField.scala 74:88]
+ ctrl_fmt_proto <= bundleIn_0_1_a_bits_data[1:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_fmt_endian <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_34) begin // @[RegField.scala 74:88]
+ ctrl_fmt_endian <= bundleIn_0_1_a_bits_data[2]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_fmt_iodir <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_35) begin // @[RegField.scala 74:88]
+ ctrl_fmt_iodir <= bundleIn_0_1_a_bits_data[3]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_fmt_len <= 4'h8; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_36) begin // @[RegField.scala 74:88]
+ ctrl_fmt_len <= bundleIn_0_1_a_bits_data[19:16]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_sck_div <= 12'h3; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid) begin // @[RegField.scala 74:88]
+ ctrl_sck_div <= bundleIn_0_1_a_bits_data[11:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_sck_pol <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_2) begin // @[RegField.scala 74:88]
+ ctrl_sck_pol <= bundleIn_0_1_a_bits_data[33]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_sck_pha <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_1) begin // @[RegField.scala 74:88]
+ ctrl_sck_pha <= bundleIn_0_1_a_bits_data[32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_cs_id <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_19) begin // @[RegField.scala 74:88]
+ ctrl_cs_id <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ ctrl_cs_dflt_0 <= reset | _GEN_20; // @[TLSPI.scala 68:{17,17}]
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_cs_mode <= 2'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_32) begin // @[RegField.scala 74:88]
+ ctrl_cs_mode <= bundleIn_0_1_a_bits_data[1:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_dla_cssck <= 8'h1; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_3) begin // @[RegField.scala 74:88]
+ ctrl_dla_cssck <= bundleIn_0_1_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_dla_sckcs <= 8'h1; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_4) begin // @[RegField.scala 74:88]
+ ctrl_dla_sckcs <= bundleIn_0_1_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_dla_intercs <= 8'h1; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_5) begin // @[RegField.scala 74:88]
+ ctrl_dla_intercs <= bundleIn_0_1_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_dla_interxfr <= 8'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
+ ctrl_dla_interxfr <= bundleIn_0_1_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_wm_tx <= 4'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_7) begin // @[RegField.scala 74:88]
+ ctrl_wm_tx <= bundleIn_0_1_a_bits_data[3:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_wm_rx <= 4'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
+ ctrl_wm_rx <= bundleIn_0_1_a_bits_data[35:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_extradel_coarse <= 12'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_30) begin // @[RegField.scala 74:88]
+ ctrl_extradel_coarse <= bundleIn_0_1_a_bits_data[11:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_sampledel_sd <= 5'h3; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_31) begin // @[RegField.scala 74:88]
+ ctrl_sampledel_sd <= bundleIn_0_1_a_bits_data[36:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 82:15]
+ ie_txwm <= 1'h0; // @[TLSPI.scala 82:15]
+ end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
+ ie_txwm <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 82:15]
+ ie_rxwm <= 1'h0; // @[TLSPI.scala 82:15]
+ end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
+ ie_rxwm <= bundleIn_0_1_a_bits_data[1]; // @[RegField.scala 74:92]
+ end
+ if (_T_2) begin // @[TLSPIFlash.scala 69:21]
+ a_size <= bundleIn_0_a_bits_size; // @[TLSPIFlash.scala 70:7]
+ end
+ if (_T_2) begin // @[TLSPIFlash.scala 69:21]
+ a_source <= bundleIn_0_a_bits_source; // @[TLSPIFlash.scala 70:7]
+ end
+ if (_T_2) begin // @[TLSPIFlash.scala 69:21]
+ a_address <= bundleIn_0_a_bits_address; // @[TLSPIFlash.scala 70:7]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_cmd_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_25) begin // @[RegField.scala 74:88]
+ insn_cmd_proto <= bundleIn_0_1_a_bits_data[41:40]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_cmd_code <= 8'h3; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_28) begin // @[RegField.scala 74:88]
+ insn_cmd_code <= bundleIn_0_1_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end
+ insn_cmd_en <= reset | _GEN_22; // @[TLSPIFlash.scala 82:{17,17}]
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_addr_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_26) begin // @[RegField.scala 74:88]
+ insn_addr_proto <= bundleIn_0_1_a_bits_data[43:42]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_addr_len <= 3'h3; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_23) begin // @[RegField.scala 74:88]
+ insn_addr_len <= bundleIn_0_1_a_bits_data[35:33]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_pad_code <= 8'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_29) begin // @[RegField.scala 74:88]
+ insn_pad_code <= bundleIn_0_1_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_pad_cnt <= 4'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_24) begin // @[RegField.scala 74:88]
+ insn_pad_cnt <= bundleIn_0_1_a_bits_data[39:36]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_data_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_27) begin // @[RegField.scala 74:88]
+ insn_data_proto <= bundleIn_0_1_a_bits_data[45:44]; // @[RegField.scala 74:92]
+ end
+ flash_en <= reset | _GEN_21; // @[TLSPIFlash.scala 83:{21,21}]
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ ctrl_fmt_proto = _RAND_0[1:0];
+ _RAND_1 = {1{`RANDOM}};
+ ctrl_fmt_endian = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ ctrl_fmt_iodir = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ ctrl_fmt_len = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ ctrl_sck_div = _RAND_4[11:0];
+ _RAND_5 = {1{`RANDOM}};
+ ctrl_sck_pol = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ ctrl_sck_pha = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ ctrl_cs_id = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ ctrl_cs_dflt_0 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ ctrl_cs_mode = _RAND_9[1:0];
+ _RAND_10 = {1{`RANDOM}};
+ ctrl_dla_cssck = _RAND_10[7:0];
+ _RAND_11 = {1{`RANDOM}};
+ ctrl_dla_sckcs = _RAND_11[7:0];
+ _RAND_12 = {1{`RANDOM}};
+ ctrl_dla_intercs = _RAND_12[7:0];
+ _RAND_13 = {1{`RANDOM}};
+ ctrl_dla_interxfr = _RAND_13[7:0];
+ _RAND_14 = {1{`RANDOM}};
+ ctrl_wm_tx = _RAND_14[3:0];
+ _RAND_15 = {1{`RANDOM}};
+ ctrl_wm_rx = _RAND_15[3:0];
+ _RAND_16 = {1{`RANDOM}};
+ ctrl_extradel_coarse = _RAND_16[11:0];
+ _RAND_17 = {1{`RANDOM}};
+ ctrl_sampledel_sd = _RAND_17[4:0];
+ _RAND_18 = {1{`RANDOM}};
+ ie_txwm = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ ie_rxwm = _RAND_19[0:0];
+ _RAND_20 = {1{`RANDOM}};
+ a_size = _RAND_20[0:0];
+ _RAND_21 = {1{`RANDOM}};
+ a_source = _RAND_21[9:0];
+ _RAND_22 = {1{`RANDOM}};
+ a_address = _RAND_22[29:0];
+ _RAND_23 = {1{`RANDOM}};
+ insn_cmd_proto = _RAND_23[1:0];
+ _RAND_24 = {1{`RANDOM}};
+ insn_cmd_code = _RAND_24[7:0];
+ _RAND_25 = {1{`RANDOM}};
+ insn_cmd_en = _RAND_25[0:0];
+ _RAND_26 = {1{`RANDOM}};
+ insn_addr_proto = _RAND_26[1:0];
+ _RAND_27 = {1{`RANDOM}};
+ insn_addr_len = _RAND_27[2:0];
+ _RAND_28 = {1{`RANDOM}};
+ insn_pad_code = _RAND_28[7:0];
+ _RAND_29 = {1{`RANDOM}};
+ insn_pad_cnt = _RAND_29[3:0];
+ _RAND_30 = {1{`RANDOM}};
+ insn_data_proto = _RAND_30[1:0];
+ _RAND_31 = {1{`RANDOM}};
+ flash_en = _RAND_31[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockSinkDomain_6(
+ output auto_qspi_0_int_xing_out_sync_0,
+ output auto_qspi_0_mem_xing_in_a_ready,
+ input auto_qspi_0_mem_xing_in_a_valid,
+ input [2:0] auto_qspi_0_mem_xing_in_a_bits_opcode,
+ input [2:0] auto_qspi_0_mem_xing_in_a_bits_param,
+ input auto_qspi_0_mem_xing_in_a_bits_size,
+ input [9:0] auto_qspi_0_mem_xing_in_a_bits_source,
+ input [29:0] auto_qspi_0_mem_xing_in_a_bits_address,
+ input auto_qspi_0_mem_xing_in_a_bits_mask,
+ input auto_qspi_0_mem_xing_in_a_bits_corrupt,
+ input auto_qspi_0_mem_xing_in_d_ready,
+ output auto_qspi_0_mem_xing_in_d_valid,
+ output auto_qspi_0_mem_xing_in_d_bits_size,
+ output [9:0] auto_qspi_0_mem_xing_in_d_bits_source,
+ output [7:0] auto_qspi_0_mem_xing_in_d_bits_data,
+ output auto_qspi_0_control_xing_in_a_ready,
+ input auto_qspi_0_control_xing_in_a_valid,
+ input [2:0] auto_qspi_0_control_xing_in_a_bits_opcode,
+ input [2:0] auto_qspi_0_control_xing_in_a_bits_param,
+ input [1:0] auto_qspi_0_control_xing_in_a_bits_size,
+ input [6:0] auto_qspi_0_control_xing_in_a_bits_source,
+ input [28:0] auto_qspi_0_control_xing_in_a_bits_address,
+ input [7:0] auto_qspi_0_control_xing_in_a_bits_mask,
+ input [63:0] auto_qspi_0_control_xing_in_a_bits_data,
+ input auto_qspi_0_control_xing_in_a_bits_corrupt,
+ input auto_qspi_0_control_xing_in_d_ready,
+ output auto_qspi_0_control_xing_in_d_valid,
+ output [2:0] auto_qspi_0_control_xing_in_d_bits_opcode,
+ output [1:0] auto_qspi_0_control_xing_in_d_bits_size,
+ output [6:0] auto_qspi_0_control_xing_in_d_bits_source,
+ output [63:0] auto_qspi_0_control_xing_in_d_bits_data,
+ output auto_qspi_0_io_out_sck,
+ input auto_qspi_0_io_out_dq_0_i,
+ output auto_qspi_0_io_out_dq_0_o,
+ output auto_qspi_0_io_out_dq_0_oe,
+ input auto_qspi_0_io_out_dq_1_i,
+ output auto_qspi_0_io_out_dq_1_o,
+ output auto_qspi_0_io_out_dq_1_oe,
+ input auto_qspi_0_io_out_dq_2_i,
+ output auto_qspi_0_io_out_dq_2_o,
+ output auto_qspi_0_io_out_dq_2_oe,
+ input auto_qspi_0_io_out_dq_3_i,
+ output auto_qspi_0_io_out_dq_3_o,
+ output auto_qspi_0_io_out_dq_3_oe,
+ output auto_qspi_0_io_out_cs_0,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire qspi_0_clock; // @[SPI.scala 93:51]
+ wire qspi_0_reset; // @[SPI.scala 93:51]
+ wire qspi_0_auto_int_xing_out_sync_0; // @[SPI.scala 93:51]
+ wire qspi_0_auto_mem_xing_in_a_ready; // @[SPI.scala 93:51]
+ wire qspi_0_auto_mem_xing_in_a_valid; // @[SPI.scala 93:51]
+ wire [2:0] qspi_0_auto_mem_xing_in_a_bits_opcode; // @[SPI.scala 93:51]
+ wire [2:0] qspi_0_auto_mem_xing_in_a_bits_param; // @[SPI.scala 93:51]
+ wire qspi_0_auto_mem_xing_in_a_bits_size; // @[SPI.scala 93:51]
+ wire [9:0] qspi_0_auto_mem_xing_in_a_bits_source; // @[SPI.scala 93:51]
+ wire [29:0] qspi_0_auto_mem_xing_in_a_bits_address; // @[SPI.scala 93:51]
+ wire qspi_0_auto_mem_xing_in_a_bits_mask; // @[SPI.scala 93:51]
+ wire qspi_0_auto_mem_xing_in_a_bits_corrupt; // @[SPI.scala 93:51]
+ wire qspi_0_auto_mem_xing_in_d_ready; // @[SPI.scala 93:51]
+ wire qspi_0_auto_mem_xing_in_d_valid; // @[SPI.scala 93:51]
+ wire qspi_0_auto_mem_xing_in_d_bits_size; // @[SPI.scala 93:51]
+ wire [9:0] qspi_0_auto_mem_xing_in_d_bits_source; // @[SPI.scala 93:51]
+ wire [7:0] qspi_0_auto_mem_xing_in_d_bits_data; // @[SPI.scala 93:51]
+ wire qspi_0_auto_control_xing_in_a_ready; // @[SPI.scala 93:51]
+ wire qspi_0_auto_control_xing_in_a_valid; // @[SPI.scala 93:51]
+ wire [2:0] qspi_0_auto_control_xing_in_a_bits_opcode; // @[SPI.scala 93:51]
+ wire [2:0] qspi_0_auto_control_xing_in_a_bits_param; // @[SPI.scala 93:51]
+ wire [1:0] qspi_0_auto_control_xing_in_a_bits_size; // @[SPI.scala 93:51]
+ wire [6:0] qspi_0_auto_control_xing_in_a_bits_source; // @[SPI.scala 93:51]
+ wire [28:0] qspi_0_auto_control_xing_in_a_bits_address; // @[SPI.scala 93:51]
+ wire [7:0] qspi_0_auto_control_xing_in_a_bits_mask; // @[SPI.scala 93:51]
+ wire [63:0] qspi_0_auto_control_xing_in_a_bits_data; // @[SPI.scala 93:51]
+ wire qspi_0_auto_control_xing_in_a_bits_corrupt; // @[SPI.scala 93:51]
+ wire qspi_0_auto_control_xing_in_d_ready; // @[SPI.scala 93:51]
+ wire qspi_0_auto_control_xing_in_d_valid; // @[SPI.scala 93:51]
+ wire [2:0] qspi_0_auto_control_xing_in_d_bits_opcode; // @[SPI.scala 93:51]
+ wire [1:0] qspi_0_auto_control_xing_in_d_bits_size; // @[SPI.scala 93:51]
+ wire [6:0] qspi_0_auto_control_xing_in_d_bits_source; // @[SPI.scala 93:51]
+ wire [63:0] qspi_0_auto_control_xing_in_d_bits_data; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_sck; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_0_i; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_0_o; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_0_oe; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_1_i; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_1_o; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_1_oe; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_2_i; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_2_o; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_2_oe; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_3_i; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_3_o; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_dq_3_oe; // @[SPI.scala 93:51]
+ wire qspi_0_auto_io_out_cs_0; // @[SPI.scala 93:51]
+ TLSPIFlash qspi_0 ( // @[SPI.scala 93:51]
+ .clock(qspi_0_clock),
+ .reset(qspi_0_reset),
+ .auto_int_xing_out_sync_0(qspi_0_auto_int_xing_out_sync_0),
+ .auto_mem_xing_in_a_ready(qspi_0_auto_mem_xing_in_a_ready),
+ .auto_mem_xing_in_a_valid(qspi_0_auto_mem_xing_in_a_valid),
+ .auto_mem_xing_in_a_bits_opcode(qspi_0_auto_mem_xing_in_a_bits_opcode),
+ .auto_mem_xing_in_a_bits_param(qspi_0_auto_mem_xing_in_a_bits_param),
+ .auto_mem_xing_in_a_bits_size(qspi_0_auto_mem_xing_in_a_bits_size),
+ .auto_mem_xing_in_a_bits_source(qspi_0_auto_mem_xing_in_a_bits_source),
+ .auto_mem_xing_in_a_bits_address(qspi_0_auto_mem_xing_in_a_bits_address),
+ .auto_mem_xing_in_a_bits_mask(qspi_0_auto_mem_xing_in_a_bits_mask),
+ .auto_mem_xing_in_a_bits_corrupt(qspi_0_auto_mem_xing_in_a_bits_corrupt),
+ .auto_mem_xing_in_d_ready(qspi_0_auto_mem_xing_in_d_ready),
+ .auto_mem_xing_in_d_valid(qspi_0_auto_mem_xing_in_d_valid),
+ .auto_mem_xing_in_d_bits_size(qspi_0_auto_mem_xing_in_d_bits_size),
+ .auto_mem_xing_in_d_bits_source(qspi_0_auto_mem_xing_in_d_bits_source),
+ .auto_mem_xing_in_d_bits_data(qspi_0_auto_mem_xing_in_d_bits_data),
+ .auto_control_xing_in_a_ready(qspi_0_auto_control_xing_in_a_ready),
+ .auto_control_xing_in_a_valid(qspi_0_auto_control_xing_in_a_valid),
+ .auto_control_xing_in_a_bits_opcode(qspi_0_auto_control_xing_in_a_bits_opcode),
+ .auto_control_xing_in_a_bits_param(qspi_0_auto_control_xing_in_a_bits_param),
+ .auto_control_xing_in_a_bits_size(qspi_0_auto_control_xing_in_a_bits_size),
+ .auto_control_xing_in_a_bits_source(qspi_0_auto_control_xing_in_a_bits_source),
+ .auto_control_xing_in_a_bits_address(qspi_0_auto_control_xing_in_a_bits_address),
+ .auto_control_xing_in_a_bits_mask(qspi_0_auto_control_xing_in_a_bits_mask),
+ .auto_control_xing_in_a_bits_data(qspi_0_auto_control_xing_in_a_bits_data),
+ .auto_control_xing_in_a_bits_corrupt(qspi_0_auto_control_xing_in_a_bits_corrupt),
+ .auto_control_xing_in_d_ready(qspi_0_auto_control_xing_in_d_ready),
+ .auto_control_xing_in_d_valid(qspi_0_auto_control_xing_in_d_valid),
+ .auto_control_xing_in_d_bits_opcode(qspi_0_auto_control_xing_in_d_bits_opcode),
+ .auto_control_xing_in_d_bits_size(qspi_0_auto_control_xing_in_d_bits_size),
+ .auto_control_xing_in_d_bits_source(qspi_0_auto_control_xing_in_d_bits_source),
+ .auto_control_xing_in_d_bits_data(qspi_0_auto_control_xing_in_d_bits_data),
+ .auto_io_out_sck(qspi_0_auto_io_out_sck),
+ .auto_io_out_dq_0_i(qspi_0_auto_io_out_dq_0_i),
+ .auto_io_out_dq_0_o(qspi_0_auto_io_out_dq_0_o),
+ .auto_io_out_dq_0_oe(qspi_0_auto_io_out_dq_0_oe),
+ .auto_io_out_dq_1_i(qspi_0_auto_io_out_dq_1_i),
+ .auto_io_out_dq_1_o(qspi_0_auto_io_out_dq_1_o),
+ .auto_io_out_dq_1_oe(qspi_0_auto_io_out_dq_1_oe),
+ .auto_io_out_dq_2_i(qspi_0_auto_io_out_dq_2_i),
+ .auto_io_out_dq_2_o(qspi_0_auto_io_out_dq_2_o),
+ .auto_io_out_dq_2_oe(qspi_0_auto_io_out_dq_2_oe),
+ .auto_io_out_dq_3_i(qspi_0_auto_io_out_dq_3_i),
+ .auto_io_out_dq_3_o(qspi_0_auto_io_out_dq_3_o),
+ .auto_io_out_dq_3_oe(qspi_0_auto_io_out_dq_3_oe),
+ .auto_io_out_cs_0(qspi_0_auto_io_out_cs_0)
+ );
+ assign auto_qspi_0_int_xing_out_sync_0 = qspi_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_mem_xing_in_a_ready = qspi_0_auto_mem_xing_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_mem_xing_in_d_valid = qspi_0_auto_mem_xing_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_mem_xing_in_d_bits_size = qspi_0_auto_mem_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_mem_xing_in_d_bits_source = qspi_0_auto_mem_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_mem_xing_in_d_bits_data = qspi_0_auto_mem_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_control_xing_in_a_ready = qspi_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_control_xing_in_d_valid = qspi_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_control_xing_in_d_bits_opcode = qspi_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_control_xing_in_d_bits_size = qspi_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_control_xing_in_d_bits_source = qspi_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_control_xing_in_d_bits_data = qspi_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_qspi_0_io_out_sck = qspi_0_auto_io_out_sck; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_dq_0_o = qspi_0_auto_io_out_dq_0_o; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_dq_0_oe = qspi_0_auto_io_out_dq_0_oe; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_dq_1_o = qspi_0_auto_io_out_dq_1_o; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_dq_1_oe = qspi_0_auto_io_out_dq_1_oe; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_dq_2_o = qspi_0_auto_io_out_dq_2_o; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_dq_2_oe = qspi_0_auto_io_out_dq_2_oe; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_dq_3_o = qspi_0_auto_io_out_dq_3_o; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_dq_3_oe = qspi_0_auto_io_out_dq_3_oe; // @[LazyModule.scala 311:12]
+ assign auto_qspi_0_io_out_cs_0 = qspi_0_auto_io_out_cs_0; // @[LazyModule.scala 311:12]
+ assign qspi_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign qspi_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_a_valid = auto_qspi_0_mem_xing_in_a_valid; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_a_bits_opcode = auto_qspi_0_mem_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_a_bits_param = auto_qspi_0_mem_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_a_bits_size = auto_qspi_0_mem_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_a_bits_source = auto_qspi_0_mem_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_a_bits_address = auto_qspi_0_mem_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_a_bits_mask = auto_qspi_0_mem_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_a_bits_corrupt = auto_qspi_0_mem_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_mem_xing_in_d_ready = auto_qspi_0_mem_xing_in_d_ready; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_valid = auto_qspi_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_bits_opcode = auto_qspi_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_bits_param = auto_qspi_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_bits_size = auto_qspi_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_bits_source = auto_qspi_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_bits_address = auto_qspi_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_bits_mask = auto_qspi_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_bits_data = auto_qspi_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_a_bits_corrupt = auto_qspi_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_control_xing_in_d_ready = auto_qspi_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
+ assign qspi_0_auto_io_out_dq_0_i = auto_qspi_0_io_out_dq_0_i; // @[LazyModule.scala 311:12]
+ assign qspi_0_auto_io_out_dq_1_i = auto_qspi_0_io_out_dq_1_i; // @[LazyModule.scala 311:12]
+ assign qspi_0_auto_io_out_dq_2_i = auto_qspi_0_io_out_dq_2_i; // @[LazyModule.scala 311:12]
+ assign qspi_0_auto_io_out_dq_3_i = auto_qspi_0_io_out_dq_3_i; // @[LazyModule.scala 311:12]
+endmodule
+module TLMonitor_60(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input io_in_a_bits_size,
+ input [9:0] io_in_a_bits_source,
+ input [29:0] io_in_a_bits_address,
+ input io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input io_in_d_bits_size,
+ input [9:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [639:0] _RAND_9;
+ reg [2559:0] _RAND_10;
+ reg [1279:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 10'h27f; // @[Parameters.scala 57:20]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [29:0] _T_33 = io_in_a_bits_address ^ 30'h30000000; // @[Parameters.scala 137:31]
+ wire [30:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [30:0] _T_36 = $signed(_T_34) & -31'sh10000000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 31'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_163 = ~io_in_a_bits_size; // @[Parameters.scala 91:48]
+ wire _T_170 = _T_163 & _T_37; // @[Parameters.scala 670:56]
+ wire _T_181 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_193 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_231 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire _T_271 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_301 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_309 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_339 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_347 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_377 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 10'h27f; // @[Parameters.scala 57:20]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg size; // @[Monitor.scala 386:22]
+ reg [9:0] source; // @[Monitor.scala 387:22]
+ reg [29:0] address; // @[Monitor.scala 388:22]
+ wire _T_535 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_536 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_540 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_544 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_548 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_552 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg size_1; // @[Monitor.scala 537:22]
+ reg [9:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_559 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_572 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [639:0] inflight; // @[Monitor.scala 611:27]
+ reg [2559:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [1279:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [11:0] _GEN_71 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [12:0] _a_opcode_lookup_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 634:69]
+ wire [2559:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [2559:0] _GEN_72 = {{2544'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [2559:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_72; // @[Monitor.scala 634:97]
+ wire [2559:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[2559:1]}; // @[Monitor.scala 634:152]
+ wire [10:0] _a_size_lookup_T = {io_in_d_bits_source, 1'h0}; // @[Monitor.scala 638:65]
+ wire [1279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
+ wire [3:0] _a_size_lookup_T_5 = 4'h4 - 4'h1; // @[Monitor.scala 609:57]
+ wire [1279:0] _GEN_74 = {{1276'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
+ wire [1279:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_74; // @[Monitor.scala 638:91]
+ wire [1279:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[1279:1]}; // @[Monitor.scala 638:144]
+ wire _T_586 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [1023:0] _a_set_wo_ready_T = 1024'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_589 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [1:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [1:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 2'h1; // @[Monitor.scala 655:59]
+ wire [11:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [12:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [8194:0] _GEN_1 = {{8191'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [8194:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [10:0] _a_sizes_set_T = {io_in_a_bits_source, 1'h0}; // @[Monitor.scala 657:77]
+ wire [1:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 2'h0; // @[Monitor.scala 652:72 655:28]
+ wire [2048:0] _GEN_2 = {{2047'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [2048:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
+ wire [639:0] _T_591 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_593 = ~_T_591[0]; // @[Monitor.scala 658:17]
+ wire [1023:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 1024'h0; // @[Monitor.scala 652:72 653:28]
+ wire [8194:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 8195'h0; // @[Monitor.scala 652:72 656:28]
+ wire [2048:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 2049'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_597 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire [1023:0] _d_clr_wo_ready_T = 1024'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [8206:0] _GEN_3 = {{8191'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [8206:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [2050:0] _GEN_4 = {{2047'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
+ wire [2050:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
+ wire [1023:0] _GEN_22 = d_first_done & d_first_1 ? _d_clr_wo_ready_T : 1024'h0; // @[Monitor.scala 675:91 676:21]
+ wire [8206:0] _GEN_23 = d_first_done & d_first_1 ? _d_opcodes_clr_T_5 : 8207'h0; // @[Monitor.scala 675:91 677:21]
+ wire [2050:0] _GEN_24 = d_first_done & d_first_1 ? _d_sizes_clr_T_5 : 2051'h0; // @[Monitor.scala 675:91 678:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_586 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [639:0] _T_610 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_612 = _T_610[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_617 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_618 = 3'h1 == _GEN_32 | _T_617; // @[Monitor.scala 685:77]
+ wire _T_622 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_629 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_630 = 3'h1 == _GEN_48 | _T_629; // @[Monitor.scala 689:72]
+ wire [1:0] a_size_lookup = _a_size_lookup_T_7[1:0];
+ wire [1:0] _GEN_78 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_634 = _GEN_78 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_642 = _T_597 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
+ wire _T_646 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [639:0] a_set = _GEN_16[639:0];
+ wire [639:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [639:0] d_clr = _GEN_22[639:0];
+ wire [639:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [639:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [2559:0] a_opcodes_set = _GEN_19[2559:0];
+ wire [2559:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [2559:0] d_opcodes_clr = _GEN_23[2559:0];
+ wire [2559:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [2559:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [1279:0] a_sizes_set = _GEN_20[1279:0];
+ wire [1279:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [1279:0] d_sizes_clr = _GEN_24[1279:0];
+ wire [1279:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
+ wire [1279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_655 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 640'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 2560'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 1280'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_170 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_170) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_181 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_181) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_193 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_181 & (io_in_a_valid & _T_193 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset & ~_T_181) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_193 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_193 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_231 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_231 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_231 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_231 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_181 & (io_in_a_valid & _T_231 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_231 & ~reset & ~_T_181) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_301 & (io_in_a_valid & _T_271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset & ~_T_301) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_271 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_271 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_309 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_339 & (io_in_a_valid & _T_309 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset & ~_T_339) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_309 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_309 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_347 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_377 & (io_in_a_valid & _T_347 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset & ~_T_377) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_73 & (io_in_a_valid & _T_347 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset & _T_73) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_347 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_347 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_536 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_536) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_540 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_540) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_535 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_535 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_559 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_559 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_572 & (_T_559 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_559 & _T_2 & ~_T_572) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_593 & (_T_589 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_589 & ~reset & ~_T_593) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_612 & (_T_597 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & _T_2 & ~_T_612) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_618 & (_T_597 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & same_cycle_resp & _T_2 & ~_T_618) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_622 & (_T_597 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & same_cycle_resp & _T_2 & ~_T_622) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_597 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_634 & (_T_597 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~same_cycle_resp & _T_2 & ~_T_634) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_646 & (_T_642 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_642 & _T_2 & ~_T_646) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_655 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_655) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[9:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[29:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ size_1 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ source_1 = _RAND_8[9:0];
+ _RAND_9 = {20{`RANDOM}};
+ inflight = _RAND_9[639:0];
+ _RAND_10 = {80{`RANDOM}};
+ inflight_opcodes = _RAND_10[2559:0];
+ _RAND_11 = {40{`RANDOM}};
+ inflight_sizes = _RAND_11[1279:0];
+ _RAND_12 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ watchdog = _RAND_14[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLMonitor_61(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [28:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [28:0] _GEN_71 = {{26'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10014000; // @[Parameters.scala 137:31]
+ wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [28:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[28:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TLSPIFlash_1(
+ input clock,
+ input reset,
+ output auto_int_xing_out_sync_0,
+ output auto_mem_xing_in_a_ready,
+ input auto_mem_xing_in_a_valid,
+ input [2:0] auto_mem_xing_in_a_bits_opcode,
+ input [2:0] auto_mem_xing_in_a_bits_param,
+ input auto_mem_xing_in_a_bits_size,
+ input [9:0] auto_mem_xing_in_a_bits_source,
+ input [29:0] auto_mem_xing_in_a_bits_address,
+ input auto_mem_xing_in_a_bits_mask,
+ input auto_mem_xing_in_a_bits_corrupt,
+ input auto_mem_xing_in_d_ready,
+ output auto_mem_xing_in_d_valid,
+ output auto_mem_xing_in_d_bits_size,
+ output [9:0] auto_mem_xing_in_d_bits_source,
+ output [7:0] auto_mem_xing_in_d_bits_data,
+ output auto_control_xing_in_a_ready,
+ input auto_control_xing_in_a_valid,
+ input [2:0] auto_control_xing_in_a_bits_opcode,
+ input [2:0] auto_control_xing_in_a_bits_param,
+ input [1:0] auto_control_xing_in_a_bits_size,
+ input [6:0] auto_control_xing_in_a_bits_source,
+ input [28:0] auto_control_xing_in_a_bits_address,
+ input [7:0] auto_control_xing_in_a_bits_mask,
+ input [63:0] auto_control_xing_in_a_bits_data,
+ input auto_control_xing_in_a_bits_corrupt,
+ input auto_control_xing_in_d_ready,
+ output auto_control_xing_in_d_valid,
+ output [2:0] auto_control_xing_in_d_bits_opcode,
+ output [1:0] auto_control_xing_in_d_bits_size,
+ output [6:0] auto_control_xing_in_d_bits_source,
+ output [63:0] auto_control_xing_in_d_bits_data,
+ output auto_io_out_sck,
+ input auto_io_out_dq_0_i,
+ output auto_io_out_dq_0_o,
+ output auto_io_out_dq_0_oe,
+ input auto_io_out_dq_1_i,
+ output auto_io_out_dq_1_o,
+ output auto_io_out_dq_1_oe,
+ input auto_io_out_dq_2_i,
+ output auto_io_out_dq_2_o,
+ output auto_io_out_dq_2_oe,
+ input auto_io_out_dq_3_i,
+ output auto_io_out_dq_3_o,
+ output auto_io_out_dq_3_oe,
+ output auto_io_out_cs_0
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [31:0] _RAND_30;
+ reg [31:0] _RAND_31;
+`endif // RANDOMIZE_REG_INIT
+ wire buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
+ wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
+ wire [9:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
+ wire [9:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
+ wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
+ wire [9:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
+ wire [29:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
+ wire buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
+ wire [9:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
+ wire [7:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
+ wire intsource_clock; // @[Crossing.scala 26:31]
+ wire intsource_reset; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [9:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [9:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire monitor_1_clock; // @[Nodes.scala 24:25]
+ wire monitor_1_reset; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [28:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_1_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire fifo_clock; // @[TLSPI.scala 69:20]
+ wire fifo_reset; // @[TLSPI.scala 69:20]
+ wire [1:0] fifo_io_ctrl_fmt_proto; // @[TLSPI.scala 69:20]
+ wire fifo_io_ctrl_fmt_endian; // @[TLSPI.scala 69:20]
+ wire fifo_io_ctrl_fmt_iodir; // @[TLSPI.scala 69:20]
+ wire [3:0] fifo_io_ctrl_fmt_len; // @[TLSPI.scala 69:20]
+ wire [1:0] fifo_io_ctrl_cs_mode; // @[TLSPI.scala 69:20]
+ wire [3:0] fifo_io_ctrl_wm_tx; // @[TLSPI.scala 69:20]
+ wire [3:0] fifo_io_ctrl_wm_rx; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_tx_ready; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_tx_valid; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_link_tx_bits; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_rx_valid; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_link_rx_bits; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_link_cnt; // @[TLSPI.scala 69:20]
+ wire [1:0] fifo_io_link_fmt_proto; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_fmt_endian; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_fmt_iodir; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_cs_set; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_cs_clear; // @[TLSPI.scala 69:20]
+ wire fifo_io_link_lock; // @[TLSPI.scala 69:20]
+ wire fifo_io_tx_ready; // @[TLSPI.scala 69:20]
+ wire fifo_io_tx_valid; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_tx_bits; // @[TLSPI.scala 69:20]
+ wire fifo_io_rx_ready; // @[TLSPI.scala 69:20]
+ wire fifo_io_rx_valid; // @[TLSPI.scala 69:20]
+ wire [7:0] fifo_io_rx_bits; // @[TLSPI.scala 69:20]
+ wire fifo_io_ip_txwm; // @[TLSPI.scala 69:20]
+ wire fifo_io_ip_rxwm; // @[TLSPI.scala 69:20]
+ wire mac_clock; // @[TLSPI.scala 70:19]
+ wire mac_reset; // @[TLSPI.scala 70:19]
+ wire mac_io_port_sck; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_0_i; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_0_o; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_0_oe; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_1_i; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_1_o; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_1_oe; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_2_i; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_2_o; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_2_oe; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_3_i; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_3_o; // @[TLSPI.scala 70:19]
+ wire mac_io_port_dq_3_oe; // @[TLSPI.scala 70:19]
+ wire mac_io_port_cs_0; // @[TLSPI.scala 70:19]
+ wire [11:0] mac_io_ctrl_sck_div; // @[TLSPI.scala 70:19]
+ wire mac_io_ctrl_sck_pol; // @[TLSPI.scala 70:19]
+ wire mac_io_ctrl_sck_pha; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_ctrl_dla_cssck; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_ctrl_dla_sckcs; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_ctrl_dla_intercs; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_ctrl_dla_interxfr; // @[TLSPI.scala 70:19]
+ wire mac_io_ctrl_cs_id; // @[TLSPI.scala 70:19]
+ wire mac_io_ctrl_cs_dflt_0; // @[TLSPI.scala 70:19]
+ wire [11:0] mac_io_ctrl_extradel_coarse; // @[TLSPI.scala 70:19]
+ wire [4:0] mac_io_ctrl_sampledel_sd; // @[TLSPI.scala 70:19]
+ wire mac_io_link_tx_ready; // @[TLSPI.scala 70:19]
+ wire mac_io_link_tx_valid; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_link_tx_bits; // @[TLSPI.scala 70:19]
+ wire mac_io_link_rx_valid; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_link_rx_bits; // @[TLSPI.scala 70:19]
+ wire [7:0] mac_io_link_cnt; // @[TLSPI.scala 70:19]
+ wire [1:0] mac_io_link_fmt_proto; // @[TLSPI.scala 70:19]
+ wire mac_io_link_fmt_endian; // @[TLSPI.scala 70:19]
+ wire mac_io_link_fmt_iodir; // @[TLSPI.scala 70:19]
+ wire mac_io_link_cs_set; // @[TLSPI.scala 70:19]
+ wire mac_io_link_cs_clear; // @[TLSPI.scala 70:19]
+ wire mac_io_link_cs_hold; // @[TLSPI.scala 70:19]
+ wire mac_io_link_active; // @[TLSPI.scala 70:19]
+ wire flash_clock; // @[TLSPIFlash.scala 57:21]
+ wire flash_reset; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_en; // @[TLSPIFlash.scala 57:21]
+ wire [1:0] flash_io_ctrl_insn_cmd_proto; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_ctrl_insn_cmd_code; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_ctrl_insn_cmd_en; // @[TLSPIFlash.scala 57:21]
+ wire [1:0] flash_io_ctrl_insn_addr_proto; // @[TLSPIFlash.scala 57:21]
+ wire [2:0] flash_io_ctrl_insn_addr_len; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_ctrl_insn_pad_code; // @[TLSPIFlash.scala 57:21]
+ wire [3:0] flash_io_ctrl_insn_pad_cnt; // @[TLSPIFlash.scala 57:21]
+ wire [1:0] flash_io_ctrl_insn_data_proto; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_ctrl_fmt_endian; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_addr_ready; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_addr_valid; // @[TLSPIFlash.scala 57:21]
+ wire [31:0] flash_io_addr_bits_next; // @[TLSPIFlash.scala 57:21]
+ wire [31:0] flash_io_addr_bits_hold; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_data_ready; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_data_valid; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_data_bits; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_tx_ready; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_tx_valid; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_link_tx_bits; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_rx_valid; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_link_rx_bits; // @[TLSPIFlash.scala 57:21]
+ wire [7:0] flash_io_link_cnt; // @[TLSPIFlash.scala 57:21]
+ wire [1:0] flash_io_link_fmt_proto; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_fmt_endian; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_fmt_iodir; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_cs_clear; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_active; // @[TLSPIFlash.scala 57:21]
+ wire flash_io_link_lock; // @[TLSPIFlash.scala 57:21]
+ wire arb_clock; // @[TLSPIFlash.scala 58:19]
+ wire arb_reset; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_tx_ready; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_tx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_0_tx_bits; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_rx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_0_rx_bits; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_0_cnt; // @[TLSPIFlash.scala 58:19]
+ wire [1:0] arb_io_inner_0_fmt_proto; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_fmt_endian; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_fmt_iodir; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_cs_clear; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_active; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_0_lock; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_tx_ready; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_tx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_1_tx_bits; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_rx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_1_rx_bits; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_inner_1_cnt; // @[TLSPIFlash.scala 58:19]
+ wire [1:0] arb_io_inner_1_fmt_proto; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_fmt_endian; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_fmt_iodir; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_cs_set; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_cs_clear; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_inner_1_lock; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_tx_ready; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_tx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_outer_tx_bits; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_rx_valid; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_outer_rx_bits; // @[TLSPIFlash.scala 58:19]
+ wire [7:0] arb_io_outer_cnt; // @[TLSPIFlash.scala 58:19]
+ wire [1:0] arb_io_outer_fmt_proto; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_fmt_endian; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_fmt_iodir; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_cs_set; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_cs_clear; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_cs_hold; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_outer_active; // @[TLSPIFlash.scala 58:19]
+ wire arb_io_sel; // @[TLSPIFlash.scala 58:19]
+ reg [1:0] ctrl_fmt_proto; // @[TLSPI.scala 68:17]
+ reg ctrl_fmt_endian; // @[TLSPI.scala 68:17]
+ reg ctrl_fmt_iodir; // @[TLSPI.scala 68:17]
+ reg [3:0] ctrl_fmt_len; // @[TLSPI.scala 68:17]
+ reg [11:0] ctrl_sck_div; // @[TLSPI.scala 68:17]
+ reg ctrl_sck_pol; // @[TLSPI.scala 68:17]
+ reg ctrl_sck_pha; // @[TLSPI.scala 68:17]
+ reg ctrl_cs_id; // @[TLSPI.scala 68:17]
+ reg ctrl_cs_dflt_0; // @[TLSPI.scala 68:17]
+ reg [1:0] ctrl_cs_mode; // @[TLSPI.scala 68:17]
+ reg [7:0] ctrl_dla_cssck; // @[TLSPI.scala 68:17]
+ reg [7:0] ctrl_dla_sckcs; // @[TLSPI.scala 68:17]
+ reg [7:0] ctrl_dla_intercs; // @[TLSPI.scala 68:17]
+ reg [7:0] ctrl_dla_interxfr; // @[TLSPI.scala 68:17]
+ reg [3:0] ctrl_wm_tx; // @[TLSPI.scala 68:17]
+ reg [3:0] ctrl_wm_rx; // @[TLSPI.scala 68:17]
+ reg [11:0] ctrl_extradel_coarse; // @[TLSPI.scala 68:17]
+ reg [4:0] ctrl_sampledel_sd; // @[TLSPI.scala 68:17]
+ reg ie_txwm; // @[TLSPI.scala 82:15]
+ reg ie_rxwm; // @[TLSPI.scala 82:15]
+ wire _T = ~fifo_io_tx_ready; // @[RegMapFIFO.scala 25:9]
+ wire _T_1 = ~fifo_io_rx_valid; // @[RegMapFIFO.scala 46:21]
+ reg a_size; // @[TLSPIFlash.scala 66:14]
+ reg [9:0] a_source; // @[TLSPIFlash.scala 66:14]
+ reg [29:0] a_address; // @[TLSPIFlash.scala 66:14]
+ wire bundleIn_0_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
+ wire bundleIn_0_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire _T_2 = bundleIn_0_a_ready & bundleIn_0_a_valid; // @[Decoupled.scala 50:35]
+ wire bundleIn_0_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [9:0] bundleIn_0_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [29:0] bundleIn_0_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ reg [1:0] insn_cmd_proto; // @[TLSPIFlash.scala 82:17]
+ reg [7:0] insn_cmd_code; // @[TLSPIFlash.scala 82:17]
+ reg insn_cmd_en; // @[TLSPIFlash.scala 82:17]
+ reg [1:0] insn_addr_proto; // @[TLSPIFlash.scala 82:17]
+ reg [2:0] insn_addr_len; // @[TLSPIFlash.scala 82:17]
+ reg [7:0] insn_pad_code; // @[TLSPIFlash.scala 82:17]
+ reg [3:0] insn_pad_cnt; // @[TLSPIFlash.scala 82:17]
+ reg [1:0] insn_data_proto; // @[TLSPIFlash.scala 82:17]
+ reg flash_en; // @[TLSPIFlash.scala 83:21]
+ wire [2:0] bundleIn_0_1_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire in_bits_read = bundleIn_0_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [28:0] bundleIn_0_1_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [8:0] in_bits_index = bundleIn_0_1_a_bits_address[11:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire [8:0] out_findex = in_bits_index & 9'h1f0; // @[RegisterRouter.scala 83:24]
+ wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] bundleIn_0_1_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [7:0] _out_frontMask_T_9 = bundleIn_0_1_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_11 = bundleIn_0_1_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_13 = bundleIn_0_1_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_15 = bundleIn_0_1_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_17 = bundleIn_0_1_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_19 = bundleIn_0_1_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_21 = bundleIn_0_1_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_23 = bundleIn_0_1_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_frontMask = {_out_frontMask_T_23,_out_frontMask_T_21,_out_frontMask_T_19,_out_frontMask_T_17,
+ _out_frontMask_T_15,_out_frontMask_T_13,_out_frontMask_T_11,_out_frontMask_T_9}; // @[Cat.scala 31:58]
+ wire out_wimask = &out_frontMask[11:0]; // @[RegisterRouter.scala 83:24]
+ wire bundleIn_0_1_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire bundleIn_0_1_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire [3:0] out_oindex = {in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [15:0] _out_frontSel_T = 16'h1 << out_oindex; // @[OneHot.scala 57:35]
+ wire out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_0 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire [63:0] bundleIn_0_1_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ wire out_wimask_1 = &out_frontMask[32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_1 = out_wivalid_0 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T = {{20'd0}, ctrl_sck_div}; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_2 = &out_frontMask[33]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_2 = out_wivalid_0 & out_wimask_2; // @[RegisterRouter.scala 83:24]
+ wire [33:0] out_prepend_1 = {ctrl_sck_pol,ctrl_sck_pha,_out_prepend_T}; // @[Cat.scala 31:58]
+ wire out_wimask_3 = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_5 = _out_frontSel_T[5]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_3 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_5 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_4 = &out_frontMask[23:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_4 = out_wivalid_3 & out_wimask_4; // @[RegisterRouter.scala 83:24]
+ wire [15:0] _out_prepend_T_2 = {{8'd0}, ctrl_dla_cssck}; // @[RegisterRouter.scala 83:24]
+ wire [23:0] out_prepend_2 = {ctrl_dla_sckcs,_out_prepend_T_2}; // @[Cat.scala 31:58]
+ wire out_rimask_5 = |out_frontMask[39:32]; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_5 = &out_frontMask[39:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_5 = out_wivalid_3 & out_wimask_5; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_3 = {{8'd0}, out_prepend_2}; // @[RegisterRouter.scala 83:24]
+ wire [39:0] out_prepend_3 = {ctrl_dla_intercs,_out_prepend_T_3}; // @[Cat.scala 31:58]
+ wire out_wimask_6 = &out_frontMask[55:48]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_6 = out_wivalid_3 & out_wimask_6; // @[RegisterRouter.scala 83:24]
+ wire [47:0] _out_prepend_T_4 = {{8'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
+ wire [55:0] out_prepend_4 = {ctrl_dla_interxfr,_out_prepend_T_4}; // @[Cat.scala 31:58]
+ wire out_wimask_7 = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_7 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_8 = &out_frontMask[35:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_8 = out_wivalid_7 & out_wimask_8; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_5 = {{28'd0}, ctrl_wm_tx}; // @[RegisterRouter.scala 83:24]
+ wire [35:0] out_prepend_5 = {ctrl_wm_rx,_out_prepend_T_5}; // @[Cat.scala 31:58]
+ wire out_wimask_9 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_14 = _out_frontSel_T[14]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_9 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_14 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_10 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_10 = out_wivalid_9 & out_wimask_10; // @[RegisterRouter.scala 83:24]
+ wire [1:0] out_prepend_6 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
+ wire [31:0] _out_prepend_T_7 = {{30'd0}, out_prepend_6}; // @[RegisterRouter.scala 83:24]
+ wire [33:0] out_prepend_8 = {fifo_io_ip_rxwm,fifo_io_ip_txwm,_out_prepend_T_7}; // @[Cat.scala 31:58]
+ wire out_frontSel_9 = _out_frontSel_T[9]; // @[RegisterRouter.scala 83:24]
+ wire out_rivalid_13 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & in_bits_read & out_frontSel_9 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_13 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_9 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_3; // @[RegisterRouter.scala 83:24]
+ wire out_womask_15 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
+ wire out_f_woready_15 = out_wivalid_13 & out_womask_15; // @[RegisterRouter.scala 83:24]
+ wire quash = out_f_woready_15 & bundleIn_0_1_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
+ wire [40:0] out_prepend_12 = {1'h0,fifo_io_rx_bits,_T,31'h0}; // @[Cat.scala 31:58]
+ wire [62:0] _out_T_202 = {{22'd0}, out_prepend_12}; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_13 = {_T_1,_out_T_202}; // @[Cat.scala 31:58]
+ wire out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_19 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_9; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_20 = out_wivalid_19 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire _GEN_20 = out_f_wivalid_20 ? bundleIn_0_1_a_bits_data[32] : ctrl_cs_dflt_0; // @[RegField.scala 74:{88,92} TLSPI.scala 68:17]
+ wire [31:0] _out_prepend_T_14 = {{31'd0}, ctrl_cs_id}; // @[RegisterRouter.scala 83:24]
+ wire [32:0] out_prepend_14 = {ctrl_cs_dflt_0,_out_prepend_T_14}; // @[Cat.scala 31:58]
+ wire out_frontSel_12 = _out_frontSel_T[12]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_21 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_12 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_9; // @[RegisterRouter.scala 83:24]
+ wire _GEN_21 = out_f_wivalid_21 ? bundleIn_0_1_a_bits_data[0] : flash_en; // @[RegField.scala 74:{88,92} TLSPIFlash.scala 83:21]
+ wire out_f_wivalid_22 = out_wivalid_21 & out_wimask_1; // @[RegisterRouter.scala 83:24]
+ wire _GEN_22 = out_f_wivalid_22 ? bundleIn_0_1_a_bits_data[32] : insn_cmd_en; // @[RegField.scala 74:{88,92} TLSPIFlash.scala 82:17]
+ wire [31:0] _out_prepend_T_15 = {{31'd0}, flash_en}; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_23 = &out_frontMask[35:33]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_23 = out_wivalid_21 & out_wimask_23; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_24 = &out_frontMask[39:36]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_24 = out_wivalid_21 & out_wimask_24; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_25 = &out_frontMask[41:40]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_25 = out_wivalid_21 & out_wimask_25; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_26 = &out_frontMask[43:42]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_26 = out_wivalid_21 & out_wimask_26; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_27 = &out_frontMask[45:44]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_27 = out_wivalid_21 & out_wimask_27; // @[RegisterRouter.scala 83:24]
+ wire [45:0] out_prepend_20 = {insn_data_proto,insn_addr_proto,insn_cmd_proto,insn_pad_cnt,insn_addr_len,insn_cmd_en,
+ _out_prepend_T_15}; // @[Cat.scala 31:58]
+ wire out_f_wivalid_28 = out_wivalid_21 & out_wimask_6; // @[RegisterRouter.scala 83:24]
+ wire [47:0] _out_prepend_T_21 = {{2'd0}, out_prepend_20}; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_29 = &out_frontMask[63:56]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_29 = out_wivalid_21 & out_wimask_29; // @[RegisterRouter.scala 83:24]
+ wire [63:0] out_prepend_22 = {insn_pad_code,insn_cmd_code,_out_prepend_T_21}; // @[Cat.scala 31:58]
+ wire out_frontSel_7 = _out_frontSel_T[7]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_30 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_7 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_30 = out_wivalid_30 & out_wimask; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_31 = &out_frontMask[36:32]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_31 = out_wivalid_30 & out_wimask_31; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_23 = {{20'd0}, ctrl_extradel_coarse}; // @[RegisterRouter.scala 83:24]
+ wire [36:0] out_prepend_23 = {ctrl_sampledel_sd,_out_prepend_T_23}; // @[Cat.scala 31:58]
+ wire out_wimask_32 = &out_frontMask[1:0]; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_32 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_8 = _out_frontSel_T[8]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_33 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_8 & out_findex == 9'h0
+ ; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_32; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_34 = &out_frontMask[2]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_34 = out_wivalid_33 & out_wimask_34; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_35 = &out_frontMask[3]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_35 = out_wivalid_33 & out_wimask_35; // @[RegisterRouter.scala 83:24]
+ wire [3:0] out_prepend_25 = {ctrl_fmt_iodir,ctrl_fmt_endian,ctrl_fmt_proto}; // @[Cat.scala 31:58]
+ wire out_wimask_36 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
+ wire out_f_wivalid_36 = out_wivalid_33 & out_wimask_36; // @[RegisterRouter.scala 83:24]
+ wire [15:0] _out_prepend_T_26 = {{12'd0}, out_prepend_25}; // @[RegisterRouter.scala 83:24]
+ wire [19:0] out_prepend_26 = {ctrl_fmt_len,_out_prepend_T_26}; // @[Cat.scala 31:58]
+ wire _GEN_103 = 4'h2 == out_oindex ? _out_T : 4'h1 == out_oindex | _out_T; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_104 = 4'h3 == out_oindex ? _out_T : _GEN_103; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_106 = 4'h5 == out_oindex ? _out_T : 4'h4 == out_oindex | _GEN_104; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_108 = 4'h7 == out_oindex ? _out_T : 4'h6 == out_oindex | _GEN_106; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_109 = 4'h8 == out_oindex ? _out_T : _GEN_108; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_110 = 4'h9 == out_oindex ? _out_T : _GEN_109; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_111 = 4'ha == out_oindex ? _out_T : _GEN_110; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_113 = 4'hc == out_oindex ? _out_T : 4'hb == out_oindex | _GEN_111; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_115 = 4'he == out_oindex ? _out_T : 4'hd == out_oindex | _GEN_113; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_116 = 4'hf == out_oindex | _GEN_115; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_0 = {{30'd0}, out_prepend_1}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_118 = 4'h1 == out_oindex ? 64'h0 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_2 = {{31'd0}, out_prepend_14}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_119 = 4'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_118; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_3 = {{62'd0}, ctrl_cs_mode}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_120 = 4'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_119; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_121 = 4'h4 == out_oindex ? 64'h0 : _GEN_120; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_5 = {{8'd0}, out_prepend_4}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_122 = 4'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_121; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_123 = 4'h6 == out_oindex ? 64'h0 : _GEN_122; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_7 = {{27'd0}, out_prepend_23}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_124 = 4'h7 == out_oindex ? _out_out_bits_data_WIRE_1_7 : _GEN_123; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_8 = {{44'd0}, out_prepend_26}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_125 = 4'h8 == out_oindex ? _out_out_bits_data_WIRE_1_8 : _GEN_124; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_126 = 4'h9 == out_oindex ? out_prepend_13 : _GEN_125; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_10 = {{28'd0}, out_prepend_5}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_127 = 4'ha == out_oindex ? _out_out_bits_data_WIRE_1_10 : _GEN_126; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_128 = 4'hb == out_oindex ? 64'h0 : _GEN_127; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_129 = 4'hc == out_oindex ? out_prepend_22 : _GEN_128; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_130 = 4'hd == out_oindex ? 64'h0 : _GEN_129; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _out_out_bits_data_WIRE_1_14 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [63:0] _GEN_131 = 4'he == out_oindex ? _out_out_bits_data_WIRE_1_14 : _GEN_130; // @[MuxLiteral.scala 48:{10,10}]
+ wire [63:0] _GEN_132 = 4'hf == out_oindex ? 64'h0 : _GEN_131; // @[MuxLiteral.scala 48:{10,10}]
+ TLBuffer_20 buffer ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_auto_in_a_ready),
+ .auto_in_a_valid(buffer_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_auto_in_d_ready),
+ .auto_in_d_valid(buffer_auto_in_d_valid),
+ .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_auto_out_a_ready),
+ .auto_out_a_valid(buffer_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
+ .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
+ .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_auto_out_d_ready),
+ .auto_out_d_valid(buffer_auto_out_d_valid),
+ .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
+ .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
+ );
+ TLBuffer_24 buffer_1 ( // @[Buffer.scala 68:28]
+ .auto_in_a_ready(buffer_1_auto_in_a_ready),
+ .auto_in_a_valid(buffer_1_auto_in_a_valid),
+ .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
+ .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
+ .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
+ .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
+ .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(buffer_1_auto_in_d_ready),
+ .auto_in_d_valid(buffer_1_auto_in_d_valid),
+ .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
+ .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
+ .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
+ .auto_out_a_ready(buffer_1_auto_out_a_ready),
+ .auto_out_a_valid(buffer_1_auto_out_a_valid),
+ .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
+ .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
+ .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
+ .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
+ .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
+ .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
+ .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
+ .auto_out_d_ready(buffer_1_auto_out_d_ready),
+ .auto_out_d_valid(buffer_1_auto_out_d_valid),
+ .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
+ .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
+ .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data)
+ );
+ IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
+ .clock(intsource_clock),
+ .reset(intsource_reset),
+ .auto_in_0(intsource_auto_in_0),
+ .auto_out_sync_0(intsource_auto_out_sync_0)
+ );
+ TLMonitor_60 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ TLMonitor_61 monitor_1 ( // @[Nodes.scala 24:25]
+ .clock(monitor_1_clock),
+ .reset(monitor_1_reset),
+ .io_in_a_ready(monitor_1_io_in_a_ready),
+ .io_in_a_valid(monitor_1_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_1_io_in_d_ready),
+ .io_in_d_valid(monitor_1_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_1_io_in_d_bits_source)
+ );
+ SPIFIFO fifo ( // @[TLSPI.scala 69:20]
+ .clock(fifo_clock),
+ .reset(fifo_reset),
+ .io_ctrl_fmt_proto(fifo_io_ctrl_fmt_proto),
+ .io_ctrl_fmt_endian(fifo_io_ctrl_fmt_endian),
+ .io_ctrl_fmt_iodir(fifo_io_ctrl_fmt_iodir),
+ .io_ctrl_fmt_len(fifo_io_ctrl_fmt_len),
+ .io_ctrl_cs_mode(fifo_io_ctrl_cs_mode),
+ .io_ctrl_wm_tx(fifo_io_ctrl_wm_tx),
+ .io_ctrl_wm_rx(fifo_io_ctrl_wm_rx),
+ .io_link_tx_ready(fifo_io_link_tx_ready),
+ .io_link_tx_valid(fifo_io_link_tx_valid),
+ .io_link_tx_bits(fifo_io_link_tx_bits),
+ .io_link_rx_valid(fifo_io_link_rx_valid),
+ .io_link_rx_bits(fifo_io_link_rx_bits),
+ .io_link_cnt(fifo_io_link_cnt),
+ .io_link_fmt_proto(fifo_io_link_fmt_proto),
+ .io_link_fmt_endian(fifo_io_link_fmt_endian),
+ .io_link_fmt_iodir(fifo_io_link_fmt_iodir),
+ .io_link_cs_set(fifo_io_link_cs_set),
+ .io_link_cs_clear(fifo_io_link_cs_clear),
+ .io_link_lock(fifo_io_link_lock),
+ .io_tx_ready(fifo_io_tx_ready),
+ .io_tx_valid(fifo_io_tx_valid),
+ .io_tx_bits(fifo_io_tx_bits),
+ .io_rx_ready(fifo_io_rx_ready),
+ .io_rx_valid(fifo_io_rx_valid),
+ .io_rx_bits(fifo_io_rx_bits),
+ .io_ip_txwm(fifo_io_ip_txwm),
+ .io_ip_rxwm(fifo_io_ip_rxwm)
+ );
+ SPIMedia mac ( // @[TLSPI.scala 70:19]
+ .clock(mac_clock),
+ .reset(mac_reset),
+ .io_port_sck(mac_io_port_sck),
+ .io_port_dq_0_i(mac_io_port_dq_0_i),
+ .io_port_dq_0_o(mac_io_port_dq_0_o),
+ .io_port_dq_0_oe(mac_io_port_dq_0_oe),
+ .io_port_dq_1_i(mac_io_port_dq_1_i),
+ .io_port_dq_1_o(mac_io_port_dq_1_o),
+ .io_port_dq_1_oe(mac_io_port_dq_1_oe),
+ .io_port_dq_2_i(mac_io_port_dq_2_i),
+ .io_port_dq_2_o(mac_io_port_dq_2_o),
+ .io_port_dq_2_oe(mac_io_port_dq_2_oe),
+ .io_port_dq_3_i(mac_io_port_dq_3_i),
+ .io_port_dq_3_o(mac_io_port_dq_3_o),
+ .io_port_dq_3_oe(mac_io_port_dq_3_oe),
+ .io_port_cs_0(mac_io_port_cs_0),
+ .io_ctrl_sck_div(mac_io_ctrl_sck_div),
+ .io_ctrl_sck_pol(mac_io_ctrl_sck_pol),
+ .io_ctrl_sck_pha(mac_io_ctrl_sck_pha),
+ .io_ctrl_dla_cssck(mac_io_ctrl_dla_cssck),
+ .io_ctrl_dla_sckcs(mac_io_ctrl_dla_sckcs),
+ .io_ctrl_dla_intercs(mac_io_ctrl_dla_intercs),
+ .io_ctrl_dla_interxfr(mac_io_ctrl_dla_interxfr),
+ .io_ctrl_cs_id(mac_io_ctrl_cs_id),
+ .io_ctrl_cs_dflt_0(mac_io_ctrl_cs_dflt_0),
+ .io_ctrl_extradel_coarse(mac_io_ctrl_extradel_coarse),
+ .io_ctrl_sampledel_sd(mac_io_ctrl_sampledel_sd),
+ .io_link_tx_ready(mac_io_link_tx_ready),
+ .io_link_tx_valid(mac_io_link_tx_valid),
+ .io_link_tx_bits(mac_io_link_tx_bits),
+ .io_link_rx_valid(mac_io_link_rx_valid),
+ .io_link_rx_bits(mac_io_link_rx_bits),
+ .io_link_cnt(mac_io_link_cnt),
+ .io_link_fmt_proto(mac_io_link_fmt_proto),
+ .io_link_fmt_endian(mac_io_link_fmt_endian),
+ .io_link_fmt_iodir(mac_io_link_fmt_iodir),
+ .io_link_cs_set(mac_io_link_cs_set),
+ .io_link_cs_clear(mac_io_link_cs_clear),
+ .io_link_cs_hold(mac_io_link_cs_hold),
+ .io_link_active(mac_io_link_active)
+ );
+ SPIFlashMap flash ( // @[TLSPIFlash.scala 57:21]
+ .clock(flash_clock),
+ .reset(flash_reset),
+ .io_en(flash_io_en),
+ .io_ctrl_insn_cmd_proto(flash_io_ctrl_insn_cmd_proto),
+ .io_ctrl_insn_cmd_code(flash_io_ctrl_insn_cmd_code),
+ .io_ctrl_insn_cmd_en(flash_io_ctrl_insn_cmd_en),
+ .io_ctrl_insn_addr_proto(flash_io_ctrl_insn_addr_proto),
+ .io_ctrl_insn_addr_len(flash_io_ctrl_insn_addr_len),
+ .io_ctrl_insn_pad_code(flash_io_ctrl_insn_pad_code),
+ .io_ctrl_insn_pad_cnt(flash_io_ctrl_insn_pad_cnt),
+ .io_ctrl_insn_data_proto(flash_io_ctrl_insn_data_proto),
+ .io_ctrl_fmt_endian(flash_io_ctrl_fmt_endian),
+ .io_addr_ready(flash_io_addr_ready),
+ .io_addr_valid(flash_io_addr_valid),
+ .io_addr_bits_next(flash_io_addr_bits_next),
+ .io_addr_bits_hold(flash_io_addr_bits_hold),
+ .io_data_ready(flash_io_data_ready),
+ .io_data_valid(flash_io_data_valid),
+ .io_data_bits(flash_io_data_bits),
+ .io_link_tx_ready(flash_io_link_tx_ready),
+ .io_link_tx_valid(flash_io_link_tx_valid),
+ .io_link_tx_bits(flash_io_link_tx_bits),
+ .io_link_rx_valid(flash_io_link_rx_valid),
+ .io_link_rx_bits(flash_io_link_rx_bits),
+ .io_link_cnt(flash_io_link_cnt),
+ .io_link_fmt_proto(flash_io_link_fmt_proto),
+ .io_link_fmt_endian(flash_io_link_fmt_endian),
+ .io_link_fmt_iodir(flash_io_link_fmt_iodir),
+ .io_link_cs_clear(flash_io_link_cs_clear),
+ .io_link_active(flash_io_link_active),
+ .io_link_lock(flash_io_link_lock)
+ );
+ SPIArbiter arb ( // @[TLSPIFlash.scala 58:19]
+ .clock(arb_clock),
+ .reset(arb_reset),
+ .io_inner_0_tx_ready(arb_io_inner_0_tx_ready),
+ .io_inner_0_tx_valid(arb_io_inner_0_tx_valid),
+ .io_inner_0_tx_bits(arb_io_inner_0_tx_bits),
+ .io_inner_0_rx_valid(arb_io_inner_0_rx_valid),
+ .io_inner_0_rx_bits(arb_io_inner_0_rx_bits),
+ .io_inner_0_cnt(arb_io_inner_0_cnt),
+ .io_inner_0_fmt_proto(arb_io_inner_0_fmt_proto),
+ .io_inner_0_fmt_endian(arb_io_inner_0_fmt_endian),
+ .io_inner_0_fmt_iodir(arb_io_inner_0_fmt_iodir),
+ .io_inner_0_cs_clear(arb_io_inner_0_cs_clear),
+ .io_inner_0_active(arb_io_inner_0_active),
+ .io_inner_0_lock(arb_io_inner_0_lock),
+ .io_inner_1_tx_ready(arb_io_inner_1_tx_ready),
+ .io_inner_1_tx_valid(arb_io_inner_1_tx_valid),
+ .io_inner_1_tx_bits(arb_io_inner_1_tx_bits),
+ .io_inner_1_rx_valid(arb_io_inner_1_rx_valid),
+ .io_inner_1_rx_bits(arb_io_inner_1_rx_bits),
+ .io_inner_1_cnt(arb_io_inner_1_cnt),
+ .io_inner_1_fmt_proto(arb_io_inner_1_fmt_proto),
+ .io_inner_1_fmt_endian(arb_io_inner_1_fmt_endian),
+ .io_inner_1_fmt_iodir(arb_io_inner_1_fmt_iodir),
+ .io_inner_1_cs_set(arb_io_inner_1_cs_set),
+ .io_inner_1_cs_clear(arb_io_inner_1_cs_clear),
+ .io_inner_1_lock(arb_io_inner_1_lock),
+ .io_outer_tx_ready(arb_io_outer_tx_ready),
+ .io_outer_tx_valid(arb_io_outer_tx_valid),
+ .io_outer_tx_bits(arb_io_outer_tx_bits),
+ .io_outer_rx_valid(arb_io_outer_rx_valid),
+ .io_outer_rx_bits(arb_io_outer_rx_bits),
+ .io_outer_cnt(arb_io_outer_cnt),
+ .io_outer_fmt_proto(arb_io_outer_fmt_proto),
+ .io_outer_fmt_endian(arb_io_outer_fmt_endian),
+ .io_outer_fmt_iodir(arb_io_outer_fmt_iodir),
+ .io_outer_cs_set(arb_io_outer_cs_set),
+ .io_outer_cs_clear(arb_io_outer_cs_clear),
+ .io_outer_cs_hold(arb_io_outer_cs_hold),
+ .io_outer_active(arb_io_outer_active),
+ .io_sel(arb_io_sel)
+ );
+ assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign auto_mem_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_mem_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_mem_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_mem_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_mem_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
+ assign auto_io_out_sck = mac_io_port_sck; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_0_o = mac_io_port_dq_0_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_0_oe = mac_io_port_dq_0_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_1_o = mac_io_port_dq_1_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_1_oe = mac_io_port_dq_1_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_2_o = mac_io_port_dq_2_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_2_oe = mac_io_port_dq_2_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_3_o = mac_io_port_dq_3_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_dq_3_oe = mac_io_port_dq_3_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign auto_io_out_cs_0 = mac_io_port_cs_0; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
+ assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign buffer_auto_out_d_bits_data = _GEN_116 ? _GEN_132 : 64'h0; // @[RegisterRouter.scala 83:24]
+ assign buffer_1_auto_in_a_valid = auto_mem_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_opcode = auto_mem_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_param = auto_mem_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_size = auto_mem_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_source = auto_mem_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_address = auto_mem_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_mask = auto_mem_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_a_bits_corrupt = auto_mem_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_in_d_ready = auto_mem_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign buffer_1_auto_out_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
+ assign buffer_1_auto_out_d_valid = flash_io_data_valid; // @[Nodes.scala 1210:84 TLSPIFlash.scala 79:13]
+ assign buffer_1_auto_out_d_bits_size = a_size; // @[Edges.scala 771:17 774:15]
+ assign buffer_1_auto_out_d_bits_source = a_source; // @[Edges.scala 771:17 775:15]
+ assign buffer_1_auto_out_d_bits_data = flash_io_data_bits; // @[Edges.scala 771:17 778:15]
+ assign intsource_clock = clock;
+ assign intsource_reset = reset;
+ assign intsource_auto_in_0 = fifo_io_ip_txwm & ie_txwm | fifo_io_ip_rxwm & ie_rxwm; // @[TLSPI.scala 84:47]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
+ assign monitor_io_in_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_io_in_d_valid = flash_io_data_valid; // @[Nodes.scala 1210:84 TLSPIFlash.scala 79:13]
+ assign monitor_io_in_d_bits_size = a_size; // @[Edges.scala 771:17 774:15]
+ assign monitor_io_in_d_bits_source = a_source; // @[Edges.scala 771:17 775:15]
+ assign monitor_1_clock = clock;
+ assign monitor_1_reset = reset;
+ assign monitor_1_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_1_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign monitor_1_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign fifo_clock = clock;
+ assign fifo_reset = reset;
+ assign fifo_io_ctrl_fmt_proto = ctrl_fmt_proto; // @[TLSPI.scala 73:20]
+ assign fifo_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPI.scala 73:20]
+ assign fifo_io_ctrl_fmt_iodir = ctrl_fmt_iodir; // @[TLSPI.scala 73:20]
+ assign fifo_io_ctrl_fmt_len = ctrl_fmt_len; // @[TLSPI.scala 73:20]
+ assign fifo_io_ctrl_cs_mode = ctrl_cs_mode; // @[TLSPI.scala 74:19]
+ assign fifo_io_ctrl_wm_tx = ctrl_wm_tx; // @[TLSPI.scala 75:19]
+ assign fifo_io_ctrl_wm_rx = ctrl_wm_rx; // @[TLSPI.scala 75:19]
+ assign fifo_io_link_tx_ready = arb_io_inner_1_tx_ready; // @[TLSPIFlash.scala 139:21]
+ assign fifo_io_link_rx_valid = arb_io_inner_1_rx_valid; // @[TLSPIFlash.scala 139:21]
+ assign fifo_io_link_rx_bits = arb_io_inner_1_rx_bits; // @[TLSPIFlash.scala 139:21]
+ assign fifo_io_tx_valid = out_f_wivalid_13 & ~quash; // @[RegMapFIFO.scala 19:30]
+ assign fifo_io_tx_bits = bundleIn_0_1_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
+ assign fifo_io_rx_ready = out_rivalid_13 & out_rimask_5; // @[RegisterRouter.scala 83:24]
+ assign mac_clock = clock;
+ assign mac_reset = reset;
+ assign mac_io_port_dq_0_i = auto_io_out_dq_0_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign mac_io_port_dq_1_i = auto_io_out_dq_1_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign mac_io_port_dq_2_i = auto_io_out_dq_2_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign mac_io_port_dq_3_i = auto_io_out_dq_3_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
+ assign mac_io_ctrl_sck_div = ctrl_sck_div; // @[TLSPI.scala 76:19]
+ assign mac_io_ctrl_sck_pol = ctrl_sck_pol; // @[TLSPI.scala 76:19]
+ assign mac_io_ctrl_sck_pha = ctrl_sck_pha; // @[TLSPI.scala 76:19]
+ assign mac_io_ctrl_dla_cssck = ctrl_dla_cssck; // @[TLSPI.scala 79:19]
+ assign mac_io_ctrl_dla_sckcs = ctrl_dla_sckcs; // @[TLSPI.scala 79:19]
+ assign mac_io_ctrl_dla_intercs = ctrl_dla_intercs; // @[TLSPI.scala 79:19]
+ assign mac_io_ctrl_dla_interxfr = ctrl_dla_interxfr; // @[TLSPI.scala 79:19]
+ assign mac_io_ctrl_cs_id = ctrl_cs_id; // @[TLSPI.scala 80:18]
+ assign mac_io_ctrl_cs_dflt_0 = ctrl_cs_dflt_0; // @[TLSPI.scala 80:18]
+ assign mac_io_ctrl_extradel_coarse = ctrl_extradel_coarse; // @[TLSPI.scala 77:24]
+ assign mac_io_ctrl_sampledel_sd = ctrl_sampledel_sd; // @[TLSPI.scala 78:25]
+ assign mac_io_link_tx_valid = arb_io_outer_tx_valid; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_tx_bits = arb_io_outer_tx_bits; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_cnt = arb_io_outer_cnt; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_fmt_proto = arb_io_outer_fmt_proto; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_fmt_endian = arb_io_outer_fmt_endian; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_fmt_iodir = arb_io_outer_fmt_iodir; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_cs_set = arb_io_outer_cs_set; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_cs_clear = arb_io_outer_cs_clear; // @[TLSPIFlash.scala 140:17]
+ assign mac_io_link_cs_hold = arb_io_outer_cs_hold; // @[TLSPIFlash.scala 140:17]
+ assign flash_clock = clock;
+ assign flash_reset = reset;
+ assign flash_io_en = flash_en; // @[TLSPIFlash.scala 87:15]
+ assign flash_io_ctrl_insn_cmd_proto = insn_cmd_proto; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_cmd_code = insn_cmd_code; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_cmd_en = insn_cmd_en; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_addr_proto = insn_addr_proto; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_addr_len = insn_addr_len; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_pad_code = insn_pad_code; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_pad_cnt = insn_pad_cnt; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_insn_data_proto = insn_data_proto; // @[TLSPIFlash.scala 85:22]
+ assign flash_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPIFlash.scala 86:21]
+ assign flash_io_addr_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign flash_io_addr_bits_next = {{4'd0}, bundleIn_0_a_bits_address[27:0]}; // @[TLSPIFlash.scala 73:27]
+ assign flash_io_addr_bits_hold = {{4'd0}, a_address[27:0]}; // @[TLSPIFlash.scala 74:27]
+ assign flash_io_data_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign flash_io_link_tx_ready = arb_io_inner_0_tx_ready; // @[TLSPIFlash.scala 138:21]
+ assign flash_io_link_rx_valid = arb_io_inner_0_rx_valid; // @[TLSPIFlash.scala 138:21]
+ assign flash_io_link_rx_bits = arb_io_inner_0_rx_bits; // @[TLSPIFlash.scala 138:21]
+ assign flash_io_link_active = arb_io_inner_0_active; // @[TLSPIFlash.scala 138:21]
+ assign arb_clock = clock;
+ assign arb_reset = reset;
+ assign arb_io_inner_0_tx_valid = flash_io_link_tx_valid; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_tx_bits = flash_io_link_tx_bits; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_cnt = flash_io_link_cnt; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_fmt_proto = flash_io_link_fmt_proto; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_fmt_endian = flash_io_link_fmt_endian; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_fmt_iodir = flash_io_link_fmt_iodir; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_cs_clear = flash_io_link_cs_clear; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_0_lock = flash_io_link_lock; // @[TLSPIFlash.scala 138:21]
+ assign arb_io_inner_1_tx_valid = fifo_io_link_tx_valid; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_tx_bits = fifo_io_link_tx_bits; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_cnt = fifo_io_link_cnt; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_fmt_proto = fifo_io_link_fmt_proto; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_fmt_endian = fifo_io_link_fmt_endian; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_fmt_iodir = fifo_io_link_fmt_iodir; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_cs_set = fifo_io_link_cs_set; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_cs_clear = fifo_io_link_cs_clear; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_inner_1_lock = fifo_io_link_lock; // @[TLSPIFlash.scala 139:21]
+ assign arb_io_outer_tx_ready = mac_io_link_tx_ready; // @[TLSPIFlash.scala 140:17]
+ assign arb_io_outer_rx_valid = mac_io_link_rx_valid; // @[TLSPIFlash.scala 140:17]
+ assign arb_io_outer_rx_bits = mac_io_link_rx_bits; // @[TLSPIFlash.scala 140:17]
+ assign arb_io_outer_active = mac_io_link_active; // @[TLSPIFlash.scala 140:17]
+ assign arb_io_sel = ~flash_en; // @[TLSPIFlash.scala 88:17]
+ always @(posedge clock) begin
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_fmt_proto <= 2'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_33) begin // @[RegField.scala 74:88]
+ ctrl_fmt_proto <= bundleIn_0_1_a_bits_data[1:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_fmt_endian <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_34) begin // @[RegField.scala 74:88]
+ ctrl_fmt_endian <= bundleIn_0_1_a_bits_data[2]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_fmt_iodir <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_35) begin // @[RegField.scala 74:88]
+ ctrl_fmt_iodir <= bundleIn_0_1_a_bits_data[3]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_fmt_len <= 4'h8; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_36) begin // @[RegField.scala 74:88]
+ ctrl_fmt_len <= bundleIn_0_1_a_bits_data[19:16]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_sck_div <= 12'h3; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid) begin // @[RegField.scala 74:88]
+ ctrl_sck_div <= bundleIn_0_1_a_bits_data[11:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_sck_pol <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_2) begin // @[RegField.scala 74:88]
+ ctrl_sck_pol <= bundleIn_0_1_a_bits_data[33]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_sck_pha <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_1) begin // @[RegField.scala 74:88]
+ ctrl_sck_pha <= bundleIn_0_1_a_bits_data[32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_cs_id <= 1'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_19) begin // @[RegField.scala 74:88]
+ ctrl_cs_id <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ ctrl_cs_dflt_0 <= reset | _GEN_20; // @[TLSPI.scala 68:{17,17}]
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_cs_mode <= 2'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_32) begin // @[RegField.scala 74:88]
+ ctrl_cs_mode <= bundleIn_0_1_a_bits_data[1:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_dla_cssck <= 8'h1; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_3) begin // @[RegField.scala 74:88]
+ ctrl_dla_cssck <= bundleIn_0_1_a_bits_data[7:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_dla_sckcs <= 8'h1; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_4) begin // @[RegField.scala 74:88]
+ ctrl_dla_sckcs <= bundleIn_0_1_a_bits_data[23:16]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_dla_intercs <= 8'h1; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_5) begin // @[RegField.scala 74:88]
+ ctrl_dla_intercs <= bundleIn_0_1_a_bits_data[39:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_dla_interxfr <= 8'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
+ ctrl_dla_interxfr <= bundleIn_0_1_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_wm_tx <= 4'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_7) begin // @[RegField.scala 74:88]
+ ctrl_wm_tx <= bundleIn_0_1_a_bits_data[3:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_wm_rx <= 4'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
+ ctrl_wm_rx <= bundleIn_0_1_a_bits_data[35:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_extradel_coarse <= 12'h0; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_30) begin // @[RegField.scala 74:88]
+ ctrl_extradel_coarse <= bundleIn_0_1_a_bits_data[11:0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 68:17]
+ ctrl_sampledel_sd <= 5'h3; // @[TLSPI.scala 68:17]
+ end else if (out_f_wivalid_31) begin // @[RegField.scala 74:88]
+ ctrl_sampledel_sd <= bundleIn_0_1_a_bits_data[36:32]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 82:15]
+ ie_txwm <= 1'h0; // @[TLSPI.scala 82:15]
+ end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
+ ie_txwm <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPI.scala 82:15]
+ ie_rxwm <= 1'h0; // @[TLSPI.scala 82:15]
+ end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
+ ie_rxwm <= bundleIn_0_1_a_bits_data[1]; // @[RegField.scala 74:92]
+ end
+ if (_T_2) begin // @[TLSPIFlash.scala 69:21]
+ a_size <= bundleIn_0_a_bits_size; // @[TLSPIFlash.scala 70:7]
+ end
+ if (_T_2) begin // @[TLSPIFlash.scala 69:21]
+ a_source <= bundleIn_0_a_bits_source; // @[TLSPIFlash.scala 70:7]
+ end
+ if (_T_2) begin // @[TLSPIFlash.scala 69:21]
+ a_address <= bundleIn_0_a_bits_address; // @[TLSPIFlash.scala 70:7]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_cmd_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_25) begin // @[RegField.scala 74:88]
+ insn_cmd_proto <= bundleIn_0_1_a_bits_data[41:40]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_cmd_code <= 8'h3; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_28) begin // @[RegField.scala 74:88]
+ insn_cmd_code <= bundleIn_0_1_a_bits_data[55:48]; // @[RegField.scala 74:92]
+ end
+ insn_cmd_en <= reset | _GEN_22; // @[TLSPIFlash.scala 82:{17,17}]
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_addr_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_26) begin // @[RegField.scala 74:88]
+ insn_addr_proto <= bundleIn_0_1_a_bits_data[43:42]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_addr_len <= 3'h3; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_23) begin // @[RegField.scala 74:88]
+ insn_addr_len <= bundleIn_0_1_a_bits_data[35:33]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_pad_code <= 8'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_29) begin // @[RegField.scala 74:88]
+ insn_pad_code <= bundleIn_0_1_a_bits_data[63:56]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_pad_cnt <= 4'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_24) begin // @[RegField.scala 74:88]
+ insn_pad_cnt <= bundleIn_0_1_a_bits_data[39:36]; // @[RegField.scala 74:92]
+ end
+ if (reset) begin // @[TLSPIFlash.scala 82:17]
+ insn_data_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
+ end else if (out_f_wivalid_27) begin // @[RegField.scala 74:88]
+ insn_data_proto <= bundleIn_0_1_a_bits_data[45:44]; // @[RegField.scala 74:92]
+ end
+ flash_en <= reset | _GEN_21; // @[TLSPIFlash.scala 83:{21,21}]
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ ctrl_fmt_proto = _RAND_0[1:0];
+ _RAND_1 = {1{`RANDOM}};
+ ctrl_fmt_endian = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ ctrl_fmt_iodir = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ ctrl_fmt_len = _RAND_3[3:0];
+ _RAND_4 = {1{`RANDOM}};
+ ctrl_sck_div = _RAND_4[11:0];
+ _RAND_5 = {1{`RANDOM}};
+ ctrl_sck_pol = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ ctrl_sck_pha = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ ctrl_cs_id = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ ctrl_cs_dflt_0 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ ctrl_cs_mode = _RAND_9[1:0];
+ _RAND_10 = {1{`RANDOM}};
+ ctrl_dla_cssck = _RAND_10[7:0];
+ _RAND_11 = {1{`RANDOM}};
+ ctrl_dla_sckcs = _RAND_11[7:0];
+ _RAND_12 = {1{`RANDOM}};
+ ctrl_dla_intercs = _RAND_12[7:0];
+ _RAND_13 = {1{`RANDOM}};
+ ctrl_dla_interxfr = _RAND_13[7:0];
+ _RAND_14 = {1{`RANDOM}};
+ ctrl_wm_tx = _RAND_14[3:0];
+ _RAND_15 = {1{`RANDOM}};
+ ctrl_wm_rx = _RAND_15[3:0];
+ _RAND_16 = {1{`RANDOM}};
+ ctrl_extradel_coarse = _RAND_16[11:0];
+ _RAND_17 = {1{`RANDOM}};
+ ctrl_sampledel_sd = _RAND_17[4:0];
+ _RAND_18 = {1{`RANDOM}};
+ ie_txwm = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ ie_rxwm = _RAND_19[0:0];
+ _RAND_20 = {1{`RANDOM}};
+ a_size = _RAND_20[0:0];
+ _RAND_21 = {1{`RANDOM}};
+ a_source = _RAND_21[9:0];
+ _RAND_22 = {1{`RANDOM}};
+ a_address = _RAND_22[29:0];
+ _RAND_23 = {1{`RANDOM}};
+ insn_cmd_proto = _RAND_23[1:0];
+ _RAND_24 = {1{`RANDOM}};
+ insn_cmd_code = _RAND_24[7:0];
+ _RAND_25 = {1{`RANDOM}};
+ insn_cmd_en = _RAND_25[0:0];
+ _RAND_26 = {1{`RANDOM}};
+ insn_addr_proto = _RAND_26[1:0];
+ _RAND_27 = {1{`RANDOM}};
+ insn_addr_len = _RAND_27[2:0];
+ _RAND_28 = {1{`RANDOM}};
+ insn_pad_code = _RAND_28[7:0];
+ _RAND_29 = {1{`RANDOM}};
+ insn_pad_cnt = _RAND_29[3:0];
+ _RAND_30 = {1{`RANDOM}};
+ insn_data_proto = _RAND_30[1:0];
+ _RAND_31 = {1{`RANDOM}};
+ flash_en = _RAND_31[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockSinkDomain_7(
+ output auto_qspi_1_int_xing_out_sync_0,
+ output auto_qspi_1_mem_xing_in_a_ready,
+ input auto_qspi_1_mem_xing_in_a_valid,
+ input [2:0] auto_qspi_1_mem_xing_in_a_bits_opcode,
+ input [2:0] auto_qspi_1_mem_xing_in_a_bits_param,
+ input auto_qspi_1_mem_xing_in_a_bits_size,
+ input [9:0] auto_qspi_1_mem_xing_in_a_bits_source,
+ input [29:0] auto_qspi_1_mem_xing_in_a_bits_address,
+ input auto_qspi_1_mem_xing_in_a_bits_mask,
+ input auto_qspi_1_mem_xing_in_a_bits_corrupt,
+ input auto_qspi_1_mem_xing_in_d_ready,
+ output auto_qspi_1_mem_xing_in_d_valid,
+ output auto_qspi_1_mem_xing_in_d_bits_size,
+ output [9:0] auto_qspi_1_mem_xing_in_d_bits_source,
+ output [7:0] auto_qspi_1_mem_xing_in_d_bits_data,
+ output auto_qspi_1_control_xing_in_a_ready,
+ input auto_qspi_1_control_xing_in_a_valid,
+ input [2:0] auto_qspi_1_control_xing_in_a_bits_opcode,
+ input [2:0] auto_qspi_1_control_xing_in_a_bits_param,
+ input [1:0] auto_qspi_1_control_xing_in_a_bits_size,
+ input [6:0] auto_qspi_1_control_xing_in_a_bits_source,
+ input [28:0] auto_qspi_1_control_xing_in_a_bits_address,
+ input [7:0] auto_qspi_1_control_xing_in_a_bits_mask,
+ input [63:0] auto_qspi_1_control_xing_in_a_bits_data,
+ input auto_qspi_1_control_xing_in_a_bits_corrupt,
+ input auto_qspi_1_control_xing_in_d_ready,
+ output auto_qspi_1_control_xing_in_d_valid,
+ output [2:0] auto_qspi_1_control_xing_in_d_bits_opcode,
+ output [1:0] auto_qspi_1_control_xing_in_d_bits_size,
+ output [6:0] auto_qspi_1_control_xing_in_d_bits_source,
+ output [63:0] auto_qspi_1_control_xing_in_d_bits_data,
+ output auto_qspi_1_io_out_sck,
+ input auto_qspi_1_io_out_dq_0_i,
+ output auto_qspi_1_io_out_dq_0_o,
+ output auto_qspi_1_io_out_dq_0_oe,
+ input auto_qspi_1_io_out_dq_1_i,
+ output auto_qspi_1_io_out_dq_1_o,
+ output auto_qspi_1_io_out_dq_1_oe,
+ input auto_qspi_1_io_out_dq_2_i,
+ output auto_qspi_1_io_out_dq_2_o,
+ output auto_qspi_1_io_out_dq_2_oe,
+ input auto_qspi_1_io_out_dq_3_i,
+ output auto_qspi_1_io_out_dq_3_o,
+ output auto_qspi_1_io_out_dq_3_oe,
+ output auto_qspi_1_io_out_cs_0,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire qspi_1_clock; // @[SPI.scala 93:51]
+ wire qspi_1_reset; // @[SPI.scala 93:51]
+ wire qspi_1_auto_int_xing_out_sync_0; // @[SPI.scala 93:51]
+ wire qspi_1_auto_mem_xing_in_a_ready; // @[SPI.scala 93:51]
+ wire qspi_1_auto_mem_xing_in_a_valid; // @[SPI.scala 93:51]
+ wire [2:0] qspi_1_auto_mem_xing_in_a_bits_opcode; // @[SPI.scala 93:51]
+ wire [2:0] qspi_1_auto_mem_xing_in_a_bits_param; // @[SPI.scala 93:51]
+ wire qspi_1_auto_mem_xing_in_a_bits_size; // @[SPI.scala 93:51]
+ wire [9:0] qspi_1_auto_mem_xing_in_a_bits_source; // @[SPI.scala 93:51]
+ wire [29:0] qspi_1_auto_mem_xing_in_a_bits_address; // @[SPI.scala 93:51]
+ wire qspi_1_auto_mem_xing_in_a_bits_mask; // @[SPI.scala 93:51]
+ wire qspi_1_auto_mem_xing_in_a_bits_corrupt; // @[SPI.scala 93:51]
+ wire qspi_1_auto_mem_xing_in_d_ready; // @[SPI.scala 93:51]
+ wire qspi_1_auto_mem_xing_in_d_valid; // @[SPI.scala 93:51]
+ wire qspi_1_auto_mem_xing_in_d_bits_size; // @[SPI.scala 93:51]
+ wire [9:0] qspi_1_auto_mem_xing_in_d_bits_source; // @[SPI.scala 93:51]
+ wire [7:0] qspi_1_auto_mem_xing_in_d_bits_data; // @[SPI.scala 93:51]
+ wire qspi_1_auto_control_xing_in_a_ready; // @[SPI.scala 93:51]
+ wire qspi_1_auto_control_xing_in_a_valid; // @[SPI.scala 93:51]
+ wire [2:0] qspi_1_auto_control_xing_in_a_bits_opcode; // @[SPI.scala 93:51]
+ wire [2:0] qspi_1_auto_control_xing_in_a_bits_param; // @[SPI.scala 93:51]
+ wire [1:0] qspi_1_auto_control_xing_in_a_bits_size; // @[SPI.scala 93:51]
+ wire [6:0] qspi_1_auto_control_xing_in_a_bits_source; // @[SPI.scala 93:51]
+ wire [28:0] qspi_1_auto_control_xing_in_a_bits_address; // @[SPI.scala 93:51]
+ wire [7:0] qspi_1_auto_control_xing_in_a_bits_mask; // @[SPI.scala 93:51]
+ wire [63:0] qspi_1_auto_control_xing_in_a_bits_data; // @[SPI.scala 93:51]
+ wire qspi_1_auto_control_xing_in_a_bits_corrupt; // @[SPI.scala 93:51]
+ wire qspi_1_auto_control_xing_in_d_ready; // @[SPI.scala 93:51]
+ wire qspi_1_auto_control_xing_in_d_valid; // @[SPI.scala 93:51]
+ wire [2:0] qspi_1_auto_control_xing_in_d_bits_opcode; // @[SPI.scala 93:51]
+ wire [1:0] qspi_1_auto_control_xing_in_d_bits_size; // @[SPI.scala 93:51]
+ wire [6:0] qspi_1_auto_control_xing_in_d_bits_source; // @[SPI.scala 93:51]
+ wire [63:0] qspi_1_auto_control_xing_in_d_bits_data; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_sck; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_0_i; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_0_o; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_0_oe; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_1_i; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_1_o; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_1_oe; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_2_i; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_2_o; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_2_oe; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_3_i; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_3_o; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_dq_3_oe; // @[SPI.scala 93:51]
+ wire qspi_1_auto_io_out_cs_0; // @[SPI.scala 93:51]
+ TLSPIFlash_1 qspi_1 ( // @[SPI.scala 93:51]
+ .clock(qspi_1_clock),
+ .reset(qspi_1_reset),
+ .auto_int_xing_out_sync_0(qspi_1_auto_int_xing_out_sync_0),
+ .auto_mem_xing_in_a_ready(qspi_1_auto_mem_xing_in_a_ready),
+ .auto_mem_xing_in_a_valid(qspi_1_auto_mem_xing_in_a_valid),
+ .auto_mem_xing_in_a_bits_opcode(qspi_1_auto_mem_xing_in_a_bits_opcode),
+ .auto_mem_xing_in_a_bits_param(qspi_1_auto_mem_xing_in_a_bits_param),
+ .auto_mem_xing_in_a_bits_size(qspi_1_auto_mem_xing_in_a_bits_size),
+ .auto_mem_xing_in_a_bits_source(qspi_1_auto_mem_xing_in_a_bits_source),
+ .auto_mem_xing_in_a_bits_address(qspi_1_auto_mem_xing_in_a_bits_address),
+ .auto_mem_xing_in_a_bits_mask(qspi_1_auto_mem_xing_in_a_bits_mask),
+ .auto_mem_xing_in_a_bits_corrupt(qspi_1_auto_mem_xing_in_a_bits_corrupt),
+ .auto_mem_xing_in_d_ready(qspi_1_auto_mem_xing_in_d_ready),
+ .auto_mem_xing_in_d_valid(qspi_1_auto_mem_xing_in_d_valid),
+ .auto_mem_xing_in_d_bits_size(qspi_1_auto_mem_xing_in_d_bits_size),
+ .auto_mem_xing_in_d_bits_source(qspi_1_auto_mem_xing_in_d_bits_source),
+ .auto_mem_xing_in_d_bits_data(qspi_1_auto_mem_xing_in_d_bits_data),
+ .auto_control_xing_in_a_ready(qspi_1_auto_control_xing_in_a_ready),
+ .auto_control_xing_in_a_valid(qspi_1_auto_control_xing_in_a_valid),
+ .auto_control_xing_in_a_bits_opcode(qspi_1_auto_control_xing_in_a_bits_opcode),
+ .auto_control_xing_in_a_bits_param(qspi_1_auto_control_xing_in_a_bits_param),
+ .auto_control_xing_in_a_bits_size(qspi_1_auto_control_xing_in_a_bits_size),
+ .auto_control_xing_in_a_bits_source(qspi_1_auto_control_xing_in_a_bits_source),
+ .auto_control_xing_in_a_bits_address(qspi_1_auto_control_xing_in_a_bits_address),
+ .auto_control_xing_in_a_bits_mask(qspi_1_auto_control_xing_in_a_bits_mask),
+ .auto_control_xing_in_a_bits_data(qspi_1_auto_control_xing_in_a_bits_data),
+ .auto_control_xing_in_a_bits_corrupt(qspi_1_auto_control_xing_in_a_bits_corrupt),
+ .auto_control_xing_in_d_ready(qspi_1_auto_control_xing_in_d_ready),
+ .auto_control_xing_in_d_valid(qspi_1_auto_control_xing_in_d_valid),
+ .auto_control_xing_in_d_bits_opcode(qspi_1_auto_control_xing_in_d_bits_opcode),
+ .auto_control_xing_in_d_bits_size(qspi_1_auto_control_xing_in_d_bits_size),
+ .auto_control_xing_in_d_bits_source(qspi_1_auto_control_xing_in_d_bits_source),
+ .auto_control_xing_in_d_bits_data(qspi_1_auto_control_xing_in_d_bits_data),
+ .auto_io_out_sck(qspi_1_auto_io_out_sck),
+ .auto_io_out_dq_0_i(qspi_1_auto_io_out_dq_0_i),
+ .auto_io_out_dq_0_o(qspi_1_auto_io_out_dq_0_o),
+ .auto_io_out_dq_0_oe(qspi_1_auto_io_out_dq_0_oe),
+ .auto_io_out_dq_1_i(qspi_1_auto_io_out_dq_1_i),
+ .auto_io_out_dq_1_o(qspi_1_auto_io_out_dq_1_o),
+ .auto_io_out_dq_1_oe(qspi_1_auto_io_out_dq_1_oe),
+ .auto_io_out_dq_2_i(qspi_1_auto_io_out_dq_2_i),
+ .auto_io_out_dq_2_o(qspi_1_auto_io_out_dq_2_o),
+ .auto_io_out_dq_2_oe(qspi_1_auto_io_out_dq_2_oe),
+ .auto_io_out_dq_3_i(qspi_1_auto_io_out_dq_3_i),
+ .auto_io_out_dq_3_o(qspi_1_auto_io_out_dq_3_o),
+ .auto_io_out_dq_3_oe(qspi_1_auto_io_out_dq_3_oe),
+ .auto_io_out_cs_0(qspi_1_auto_io_out_cs_0)
+ );
+ assign auto_qspi_1_int_xing_out_sync_0 = qspi_1_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_mem_xing_in_a_ready = qspi_1_auto_mem_xing_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_mem_xing_in_d_valid = qspi_1_auto_mem_xing_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_mem_xing_in_d_bits_size = qspi_1_auto_mem_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_mem_xing_in_d_bits_source = qspi_1_auto_mem_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_mem_xing_in_d_bits_data = qspi_1_auto_mem_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_control_xing_in_a_ready = qspi_1_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_control_xing_in_d_valid = qspi_1_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_control_xing_in_d_bits_opcode = qspi_1_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_control_xing_in_d_bits_size = qspi_1_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_control_xing_in_d_bits_source = qspi_1_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_control_xing_in_d_bits_data = qspi_1_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_qspi_1_io_out_sck = qspi_1_auto_io_out_sck; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_dq_0_o = qspi_1_auto_io_out_dq_0_o; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_dq_0_oe = qspi_1_auto_io_out_dq_0_oe; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_dq_1_o = qspi_1_auto_io_out_dq_1_o; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_dq_1_oe = qspi_1_auto_io_out_dq_1_oe; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_dq_2_o = qspi_1_auto_io_out_dq_2_o; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_dq_2_oe = qspi_1_auto_io_out_dq_2_oe; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_dq_3_o = qspi_1_auto_io_out_dq_3_o; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_dq_3_oe = qspi_1_auto_io_out_dq_3_oe; // @[LazyModule.scala 311:12]
+ assign auto_qspi_1_io_out_cs_0 = qspi_1_auto_io_out_cs_0; // @[LazyModule.scala 311:12]
+ assign qspi_1_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign qspi_1_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_a_valid = auto_qspi_1_mem_xing_in_a_valid; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_a_bits_opcode = auto_qspi_1_mem_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_a_bits_param = auto_qspi_1_mem_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_a_bits_size = auto_qspi_1_mem_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_a_bits_source = auto_qspi_1_mem_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_a_bits_address = auto_qspi_1_mem_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_a_bits_mask = auto_qspi_1_mem_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_a_bits_corrupt = auto_qspi_1_mem_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_mem_xing_in_d_ready = auto_qspi_1_mem_xing_in_d_ready; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_valid = auto_qspi_1_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_bits_opcode = auto_qspi_1_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_bits_param = auto_qspi_1_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_bits_size = auto_qspi_1_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_bits_source = auto_qspi_1_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_bits_address = auto_qspi_1_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_bits_mask = auto_qspi_1_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_bits_data = auto_qspi_1_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_a_bits_corrupt = auto_qspi_1_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_control_xing_in_d_ready = auto_qspi_1_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
+ assign qspi_1_auto_io_out_dq_0_i = auto_qspi_1_io_out_dq_0_i; // @[LazyModule.scala 311:12]
+ assign qspi_1_auto_io_out_dq_1_i = auto_qspi_1_io_out_dq_1_i; // @[LazyModule.scala 311:12]
+ assign qspi_1_auto_io_out_dq_2_i = auto_qspi_1_io_out_dq_2_i; // @[LazyModule.scala 311:12]
+ assign qspi_1_auto_io_out_dq_3_i = auto_qspi_1_io_out_dq_3_i; // @[LazyModule.scala 311:12]
+endmodule
+module TLMonitor_62(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [20:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [20:0] _GEN_71 = {{18'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [20:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [20:0] _T_33 = io_in_a_bits_address ^ 21'h100000; // @[Parameters.scala 137:31]
+ wire [21:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [21:0] _T_36 = $signed(_T_34) & -22'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 22'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [20:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at TileClockGater.scala:52:68)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at TileClockGater.scala:52:68)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[20:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module AsyncResetRegVec_w1_i1(
+ input clock,
+ input reset,
+ input io_d,
+ output io_q,
+ input io_en
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg reg_; // @[AsyncResetReg.scala 64:50]
+ assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncResetReg.scala 65:16]
+ reg_ <= 1'h1; // @[AsyncResetReg.scala 66:9]
+ end else if (io_en) begin // @[AsyncResetReg.scala 64:50]
+ reg_ <= io_d;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ reg_ = _RAND_0[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ reg_ = 1'h1;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TileClockGater(
+ input clock,
+ input reset,
+ output auto_chipyard_prci_in_1_a_ready,
+ input auto_chipyard_prci_in_1_a_valid,
+ input [2:0] auto_chipyard_prci_in_1_a_bits_opcode,
+ input [2:0] auto_chipyard_prci_in_1_a_bits_param,
+ input [1:0] auto_chipyard_prci_in_1_a_bits_size,
+ input [6:0] auto_chipyard_prci_in_1_a_bits_source,
+ input [20:0] auto_chipyard_prci_in_1_a_bits_address,
+ input [7:0] auto_chipyard_prci_in_1_a_bits_mask,
+ input [63:0] auto_chipyard_prci_in_1_a_bits_data,
+ input auto_chipyard_prci_in_1_a_bits_corrupt,
+ input auto_chipyard_prci_in_1_d_ready,
+ output auto_chipyard_prci_in_1_d_valid,
+ output [2:0] auto_chipyard_prci_in_1_d_bits_opcode,
+ output [1:0] auto_chipyard_prci_in_1_d_bits_size,
+ output [6:0] auto_chipyard_prci_in_1_d_bits_source,
+ output [63:0] auto_chipyard_prci_in_1_d_bits_data,
+ input auto_chipyard_prci_in_0_member_allClocks_implicit_clock_clock,
+ input auto_chipyard_prci_in_0_member_allClocks_implicit_clock_reset,
+ input auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_clock,
+ input auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_reset,
+ input auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_clock,
+ input auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_reset,
+ input auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_clock,
+ input auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_reset,
+ input auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_clock,
+ input auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_reset,
+ output auto_chipyard_prci_out_member_allClocks_implicit_clock_clock,
+ output auto_chipyard_prci_out_member_allClocks_implicit_clock_reset,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [20:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire regs_0_clock; // @[TileClockGater.scala 33:53]
+ wire regs_0_reset; // @[TileClockGater.scala 33:53]
+ wire regs_0_io_d; // @[TileClockGater.scala 33:53]
+ wire regs_0_io_q; // @[TileClockGater.scala 33:53]
+ wire regs_0_io_en; // @[TileClockGater.scala 33:53]
+ wire regs_1_clock; // @[TileClockGater.scala 33:53]
+ wire regs_1_reset; // @[TileClockGater.scala 33:53]
+ wire regs_1_io_d; // @[TileClockGater.scala 33:53]
+ wire regs_1_io_q; // @[TileClockGater.scala 33:53]
+ wire regs_1_io_en; // @[TileClockGater.scala 33:53]
+ wire regs_2_clock; // @[TileClockGater.scala 33:53]
+ wire regs_2_reset; // @[TileClockGater.scala 33:53]
+ wire regs_2_io_d; // @[TileClockGater.scala 33:53]
+ wire regs_2_io_q; // @[TileClockGater.scala 33:53]
+ wire regs_2_io_en; // @[TileClockGater.scala 33:53]
+ wire regs_3_clock; // @[TileClockGater.scala 33:53]
+ wire regs_3_reset; // @[TileClockGater.scala 33:53]
+ wire regs_3_io_d; // @[TileClockGater.scala 33:53]
+ wire regs_3_io_q; // @[TileClockGater.scala 33:53]
+ wire regs_3_io_en; // @[TileClockGater.scala 33:53]
+ wire regs_4_clock; // @[TileClockGater.scala 33:53]
+ wire regs_4_reset; // @[TileClockGater.scala 33:53]
+ wire regs_4_io_d; // @[TileClockGater.scala 33:53]
+ wire regs_4_io_q; // @[TileClockGater.scala 33:53]
+ wire regs_4_io_en; // @[TileClockGater.scala 33:53]
+ wire in_bits_read = auto_chipyard_prci_in_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [8:0] in_bits_index = auto_chipyard_prci_in_1_a_bits_address[11:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire [8:0] out_findex = in_bits_index & 9'h1fc; // @[RegisterRouter.scala 83:24]
+ wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire [7:0] _out_frontMask_T_9 = auto_chipyard_prci_in_1_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_11 = auto_chipyard_prci_in_1_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_13 = auto_chipyard_prci_in_1_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_15 = auto_chipyard_prci_in_1_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_17 = auto_chipyard_prci_in_1_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_19 = auto_chipyard_prci_in_1_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_21 = auto_chipyard_prci_in_1_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_23 = auto_chipyard_prci_in_1_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_frontMask = {_out_frontMask_T_23,_out_frontMask_T_21,_out_frontMask_T_19,_out_frontMask_T_17,
+ _out_frontMask_T_15,_out_frontMask_T_13,_out_frontMask_T_11,_out_frontMask_T_9}; // @[Cat.scala 31:58]
+ wire out_wimask = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
+ wire [1:0] out_oindex = {in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
+ wire [3:0] _out_frontSel_T = 4'h1 << out_oindex; // @[OneHot.scala 57:35]
+ wire out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_0 = auto_chipyard_prci_in_1_a_valid & auto_chipyard_prci_in_1_d_ready & ~in_bits_read &
+ out_frontSel_2 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire _out_T_11 = regs_4_io_q; // @[RegisterRouter.scala 83:24]
+ wire out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_1 = auto_chipyard_prci_in_1_a_valid & auto_chipyard_prci_in_1_d_ready & ~in_bits_read &
+ out_frontSel_1 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire _out_T_18 = regs_2_io_q; // @[RegisterRouter.scala 83:24]
+ wire out_wimask_2 = &out_frontMask[32]; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T = {{31'd0}, _out_T_18}; // @[RegisterRouter.scala 83:24]
+ wire [32:0] out_prepend = {regs_3_io_q,_out_prepend_T}; // @[Cat.scala 31:58]
+ wire out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_3 = auto_chipyard_prci_in_1_a_valid & auto_chipyard_prci_in_1_d_ready & ~in_bits_read &
+ out_frontSel_0 & out_findex == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire _out_T_32 = regs_0_io_q; // @[RegisterRouter.scala 83:24]
+ wire [31:0] _out_prepend_T_1 = {{31'd0}, _out_T_32}; // @[RegisterRouter.scala 83:24]
+ wire [32:0] out_prepend_1 = {regs_1_io_q,_out_prepend_T_1}; // @[Cat.scala 31:58]
+ wire _GEN_17 = 2'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_18 = 2'h2 == out_oindex ? _out_T : _GEN_17; // @[MuxLiteral.scala 48:{10,10}]
+ wire _GEN_19 = 2'h3 == out_oindex | _GEN_18; // @[MuxLiteral.scala 48:{10,10}]
+ wire [32:0] _GEN_21 = 2'h1 == out_oindex ? out_prepend : out_prepend_1; // @[MuxLiteral.scala 48:{10,10}]
+ wire [32:0] _out_out_bits_data_WIRE_1_2 = {{32'd0}, _out_T_11}; // @[MuxLiteral.scala 48:{48,48}]
+ wire [32:0] _GEN_22 = 2'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_21; // @[MuxLiteral.scala 48:{10,10}]
+ wire [32:0] _GEN_23 = 2'h3 == out_oindex ? 33'h0 : _GEN_22; // @[MuxLiteral.scala 48:{10,10}]
+ wire [32:0] _out_out_bits_data_T_4 = _GEN_19 ? _GEN_23 : 33'h0; // @[RegisterRouter.scala 83:24]
+ TLMonitor_62 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala 33:53]
+ .clock(regs_0_clock),
+ .reset(regs_0_reset),
+ .io_d(regs_0_io_d),
+ .io_q(regs_0_io_q),
+ .io_en(regs_0_io_en)
+ );
+ AsyncResetRegVec_w1_i1 regs_1 ( // @[TileClockGater.scala 33:53]
+ .clock(regs_1_clock),
+ .reset(regs_1_reset),
+ .io_d(regs_1_io_d),
+ .io_q(regs_1_io_q),
+ .io_en(regs_1_io_en)
+ );
+ AsyncResetRegVec_w1_i1 regs_2 ( // @[TileClockGater.scala 33:53]
+ .clock(regs_2_clock),
+ .reset(regs_2_reset),
+ .io_d(regs_2_io_d),
+ .io_q(regs_2_io_q),
+ .io_en(regs_2_io_en)
+ );
+ AsyncResetRegVec_w1_i1 regs_3 ( // @[TileClockGater.scala 33:53]
+ .clock(regs_3_clock),
+ .reset(regs_3_reset),
+ .io_d(regs_3_io_d),
+ .io_q(regs_3_io_q),
+ .io_en(regs_3_io_en)
+ );
+ AsyncResetRegVec_w1_i1 regs_4 ( // @[TileClockGater.scala 33:53]
+ .clock(regs_4_clock),
+ .reset(regs_4_reset),
+ .io_d(regs_4_io_d),
+ .io_q(regs_4_io_q),
+ .io_en(regs_4_io_en)
+ );
+ assign auto_chipyard_prci_in_1_a_ready = auto_chipyard_prci_in_1_d_ready; // @[RegisterRouter.scala 83:24]
+ assign auto_chipyard_prci_in_1_d_valid = auto_chipyard_prci_in_1_a_valid; // @[RegisterRouter.scala 83:24]
+ assign auto_chipyard_prci_in_1_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign auto_chipyard_prci_in_1_d_bits_size = auto_chipyard_prci_in_1_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_in_1_d_bits_source = auto_chipyard_prci_in_1_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_in_1_d_bits_data = {{31'd0}, _out_out_bits_data_T_4}; // @[RegisterRouter.scala 83:{24,24}]
+ assign auto_chipyard_prci_out_member_allClocks_implicit_clock_clock =
+ auto_chipyard_prci_in_0_member_allClocks_implicit_clock_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_implicit_clock_reset =
+ auto_chipyard_prci_in_0_member_allClocks_implicit_clock_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock =
+ auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset =
+ auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock =
+ auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset =
+ auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock =
+ auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset =
+ auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock =
+ auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset =
+ auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_chipyard_prci_in_1_d_ready; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_a_valid = auto_chipyard_prci_in_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_chipyard_prci_in_1_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_chipyard_prci_in_1_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_chipyard_prci_in_1_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_chipyard_prci_in_1_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_chipyard_prci_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_chipyard_prci_in_1_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_chipyard_prci_in_1_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_chipyard_prci_in_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_chipyard_prci_in_1_a_valid; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = auto_chipyard_prci_in_1_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_bits_source = auto_chipyard_prci_in_1_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign regs_0_clock = clock;
+ assign regs_0_reset = auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign regs_0_io_d = auto_chipyard_prci_in_1_a_bits_data[0]; // @[RegisterRouter.scala 83:24]
+ assign regs_0_io_en = out_wivalid_3 & out_wimask; // @[RegisterRouter.scala 83:24]
+ assign regs_1_clock = clock;
+ assign regs_1_reset = auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign regs_1_io_d = auto_chipyard_prci_in_1_a_bits_data[32]; // @[RegisterRouter.scala 83:24]
+ assign regs_1_io_en = out_wivalid_3 & out_wimask_2; // @[RegisterRouter.scala 83:24]
+ assign regs_2_clock = clock;
+ assign regs_2_reset = auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign regs_2_io_d = auto_chipyard_prci_in_1_a_bits_data[0]; // @[RegisterRouter.scala 83:24]
+ assign regs_2_io_en = out_wivalid_1 & out_wimask; // @[RegisterRouter.scala 83:24]
+ assign regs_3_clock = clock;
+ assign regs_3_reset = auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign regs_3_io_d = auto_chipyard_prci_in_1_a_bits_data[32]; // @[RegisterRouter.scala 83:24]
+ assign regs_3_io_en = out_wivalid_1 & out_wimask_2; // @[RegisterRouter.scala 83:24]
+ assign regs_4_clock = clock;
+ assign regs_4_reset = auto_chipyard_prci_in_0_member_allClocks_implicit_clock_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign regs_4_io_d = auto_chipyard_prci_in_1_a_bits_data[0]; // @[RegisterRouter.scala 83:24]
+ assign regs_4_io_en = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
+endmodule
+module TLMonitor_63(
+ input clock,
+ input reset,
+ input io_in_a_ready,
+ input io_in_a_valid,
+ input [2:0] io_in_a_bits_opcode,
+ input [2:0] io_in_a_bits_param,
+ input [1:0] io_in_a_bits_size,
+ input [6:0] io_in_a_bits_source,
+ input [20:0] io_in_a_bits_address,
+ input [7:0] io_in_a_bits_mask,
+ input io_in_a_bits_corrupt,
+ input io_in_d_ready,
+ input io_in_d_valid,
+ input [2:0] io_in_d_bits_opcode,
+ input [1:0] io_in_d_bits_size,
+ input [6:0] io_in_d_bits_source
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [95:0] _RAND_10;
+ reg [319:0] _RAND_11;
+ reg [319:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [95:0] _RAND_16;
+ reg [319:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+`endif // RANDOMIZE_REG_INIT
+ wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
+ wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
+ wire _T_2 = ~reset; // @[Monitor.scala 42:11]
+ wire _source_ok_T_4 = io_in_a_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire [5:0] _is_aligned_mask_T_1 = 6'h7 << io_in_a_bits_size; // @[package.scala 234:77]
+ wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1[2:0]; // @[package.scala 234:46]
+ wire [20:0] _GEN_71 = {{18'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
+ wire [20:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
+ wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala 20:24]
+ wire [2:0] _mask_sizeOH_T = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 201:34]
+ wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala 63:49]
+ wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
+ wire [2:0] mask_sizeOH = _mask_sizeOH_T_1[2:0] | 3'h1; // @[Misc.scala 201:81]
+ wire _mask_T = io_in_a_bits_size >= 2'h3; // @[Misc.scala 205:21]
+ wire mask_size = mask_sizeOH[2]; // @[Misc.scala 208:26]
+ wire mask_bit = io_in_a_bits_address[2]; // @[Misc.scala 209:26]
+ wire mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
+ wire mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
+ wire mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
+ wire mask_size_1 = mask_sizeOH[1]; // @[Misc.scala 208:26]
+ wire mask_bit_1 = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
+ wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
+ wire mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
+ wire mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
+ wire mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
+ wire mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
+ wire mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
+ wire mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
+ wire mask_size_2 = mask_sizeOH[0]; // @[Misc.scala 208:26]
+ wire mask_bit_2 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
+ wire mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
+ wire mask_eq_6 = mask_eq_2 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_6 = mask_acc_2 | mask_size_2 & mask_eq_6; // @[Misc.scala 214:29]
+ wire mask_eq_7 = mask_eq_2 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_7 = mask_acc_2 | mask_size_2 & mask_eq_7; // @[Misc.scala 214:29]
+ wire mask_eq_8 = mask_eq_3 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_8 = mask_acc_3 | mask_size_2 & mask_eq_8; // @[Misc.scala 214:29]
+ wire mask_eq_9 = mask_eq_3 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_9 = mask_acc_3 | mask_size_2 & mask_eq_9; // @[Misc.scala 214:29]
+ wire mask_eq_10 = mask_eq_4 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_10 = mask_acc_4 | mask_size_2 & mask_eq_10; // @[Misc.scala 214:29]
+ wire mask_eq_11 = mask_eq_4 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_11 = mask_acc_4 | mask_size_2 & mask_eq_11; // @[Misc.scala 214:29]
+ wire mask_eq_12 = mask_eq_5 & mask_nbit_2; // @[Misc.scala 213:27]
+ wire mask_acc_12 = mask_acc_5 | mask_size_2 & mask_eq_12; // @[Misc.scala 214:29]
+ wire mask_eq_13 = mask_eq_5 & mask_bit_2; // @[Misc.scala 213:27]
+ wire mask_acc_13 = mask_acc_5 | mask_size_2 & mask_eq_13; // @[Misc.scala 214:29]
+ wire [7:0] mask = {mask_acc_13,mask_acc_12,mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8,mask_acc_7,mask_acc_6}; // @[Cat.scala 31:58]
+ wire _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
+ wire _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
+ wire [20:0] _T_33 = io_in_a_bits_address ^ 21'h110000; // @[Parameters.scala 137:31]
+ wire [21:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
+ wire [21:0] _T_36 = $signed(_T_34) & -22'sh1000; // @[Parameters.scala 137:52]
+ wire _T_37 = $signed(_T_36) == 22'sh0; // @[Parameters.scala 137:67]
+ wire _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
+ wire [7:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
+ wire _T_74 = _T_73 == 8'h0; // @[Monitor.scala 88:31]
+ wire _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
+ wire _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
+ wire _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
+ wire _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
+ wire _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
+ wire _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
+ wire _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
+ wire _T_218 = _source_ok_T_4 & _T_37; // @[Monitor.scala 115:71]
+ wire _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
+ wire [7:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
+ wire [7:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
+ wire _T_275 = _T_274 == 8'h0; // @[Monitor.scala 127:40]
+ wire _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
+ wire _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
+ wire _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
+ wire _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
+ wire _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
+ wire _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
+ wire _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
+ wire _source_ok_T_10 = io_in_d_bits_source <= 7'h4f; // @[Parameters.scala 57:20]
+ wire _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
+ wire _T_405 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 312:27]
+ wire _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
+ wire _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
+ wire _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
+ wire _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
+ wire _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
+ wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
+ reg a_first_counter; // @[Edges.scala 228:27]
+ wire a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire a_first = ~a_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode; // @[Monitor.scala 384:22]
+ reg [2:0] param; // @[Monitor.scala 385:22]
+ reg [1:0] size; // @[Monitor.scala 386:22]
+ reg [6:0] source; // @[Monitor.scala 387:22]
+ reg [20:0] address; // @[Monitor.scala 388:22]
+ wire _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
+ wire _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
+ wire _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
+ wire _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
+ wire _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
+ wire _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
+ wire d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
+ reg d_first_counter; // @[Edges.scala 228:27]
+ wire d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
+ wire d_first = ~d_first_counter; // @[Edges.scala 230:25]
+ reg [2:0] opcode_1; // @[Monitor.scala 535:22]
+ reg [1:0] size_1; // @[Monitor.scala 537:22]
+ reg [6:0] source_1; // @[Monitor.scala 538:22]
+ wire _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
+ wire _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
+ wire _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
+ wire _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
+ reg [79:0] inflight; // @[Monitor.scala 611:27]
+ reg [319:0] inflight_opcodes; // @[Monitor.scala 613:35]
+ reg [319:0] inflight_sizes; // @[Monitor.scala 615:33]
+ reg a_first_counter_1; // @[Edges.scala 228:27]
+ wire a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
+ reg d_first_counter_1; // @[Edges.scala 228:27]
+ wire d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
+ wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
+ wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
+ wire [319:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
+ wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
+ wire [319:0] _GEN_73 = {{304'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
+ wire [319:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[319:1]}; // @[Monitor.scala 634:152]
+ wire [319:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
+ wire [319:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
+ wire [319:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[319:1]}; // @[Monitor.scala 638:144]
+ wire _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
+ wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
+ wire _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
+ wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
+ wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
+ wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
+ wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
+ wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
+ wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
+ wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
+ wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
+ wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
+ wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
+ wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
+ wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
+ wire [79:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
+ wire _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
+ wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
+ wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
+ wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
+ wire _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
+ wire _T_607 = ~_T_401; // @[Monitor.scala 671:74]
+ wire _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
+ wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
+ wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
+ wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
+ wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
+ wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
+ wire _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
+ wire same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
+ wire [79:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
+ wire _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
+ wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
+ wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
+ wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
+ wire _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
+ wire _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
+ wire _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
+ wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
+ wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
+ wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
+ wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
+ wire _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
+ wire _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
+ wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
+ wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
+ wire _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
+ wire _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
+ wire _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
+ wire [79:0] a_set = _GEN_16[79:0];
+ wire [79:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
+ wire [79:0] d_clr = _GEN_22[79:0];
+ wire [79:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
+ wire [79:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
+ wire [319:0] a_opcodes_set = _GEN_19[319:0];
+ wire [319:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
+ wire [319:0] d_opcodes_clr = _GEN_23[319:0];
+ wire [319:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
+ wire [319:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
+ wire [319:0] a_sizes_set = _GEN_20[319:0];
+ wire [319:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
+ wire [319:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
+ reg [31:0] watchdog; // @[Monitor.scala 706:27]
+ wire _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
+ wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
+ reg [79:0] inflight_1; // @[Monitor.scala 723:35]
+ reg [319:0] inflight_sizes_1; // @[Monitor.scala 725:35]
+ reg d_first_counter_2; // @[Edges.scala 228:27]
+ wire d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
+ wire d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
+ wire [319:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
+ wire [319:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
+ wire [319:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[319:1]}; // @[Monitor.scala 747:146]
+ wire _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
+ wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
+ wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
+ wire [79:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
+ wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
+ wire _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
+ wire [79:0] d_clr_1 = _GEN_67[79:0];
+ wire [79:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
+ wire [79:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
+ wire [319:0] d_opcodes_clr_1 = _GEN_68[319:0];
+ wire [319:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
+ wire [319:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
+ reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
+ wire _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
+ wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_out)
+ );
+ plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
+ .out(plusarg_reader_1_out)
+ );
+ always @(posedge clock) begin
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first) begin // @[Edges.scala 235:21]
+ a_first_counter <= 1'h0;
+ end else begin
+ a_first_counter <= a_first_counter1;
+ end
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
+ end
+ if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
+ address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first) begin // @[Edges.scala 235:21]
+ d_first_counter <= 1'h0;
+ end else begin
+ d_first_counter <= d_first_counter1;
+ end
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
+ end
+ if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
+ source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
+ end
+ if (reset) begin // @[Monitor.scala 611:27]
+ inflight <= 80'h0; // @[Monitor.scala 611:27]
+ end else begin
+ inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
+ end
+ if (reset) begin // @[Monitor.scala 613:35]
+ inflight_opcodes <= 320'h0; // @[Monitor.scala 613:35]
+ end else begin
+ inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
+ end
+ if (reset) begin // @[Monitor.scala 615:33]
+ inflight_sizes <= 320'h0; // @[Monitor.scala 615:33]
+ end else begin
+ inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (a_first_done) begin // @[Edges.scala 234:17]
+ if (a_first_1) begin // @[Edges.scala 235:21]
+ a_first_counter_1 <= 1'h0;
+ end else begin
+ a_first_counter_1 <= a_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_1) begin // @[Edges.scala 235:21]
+ d_first_counter_1 <= 1'h0;
+ end else begin
+ d_first_counter_1 <= d_first_counter1_1;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 706:27]
+ watchdog <= 32'h0; // @[Monitor.scala 706:27]
+ end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
+ watchdog <= 32'h0; // @[Monitor.scala 712:58]
+ end else begin
+ watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
+ end
+ if (reset) begin // @[Monitor.scala 723:35]
+ inflight_1 <= 80'h0; // @[Monitor.scala 723:35]
+ end else begin
+ inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
+ end
+ if (reset) begin // @[Monitor.scala 725:35]
+ inflight_sizes_1 <= 320'h0; // @[Monitor.scala 725:35]
+ end else begin
+ inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
+ end
+ if (reset) begin // @[Edges.scala 228:27]
+ d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
+ end else if (d_first_done) begin // @[Edges.scala 234:17]
+ if (d_first_2) begin // @[Edges.scala 235:21]
+ d_first_counter_2 <= 1'h0;
+ end else begin
+ d_first_counter_2 <= d_first_counter1_2;
+ end
+ end
+ if (reset) begin // @[Monitor.scala 813:27]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
+ end else if (d_first_done) begin // @[Monitor.scala 819:47]
+ watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
+ end else begin
+ watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_37 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_37) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get address not aligned to size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get carries invalid param (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get contains invalid mask (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Get is corrupt (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull address not aligned to size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull carries invalid param (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutFull contains invalid mask (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial carries invalid param (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical address not aligned to size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Logical contains invalid mask (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint address not aligned to size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint contains invalid mask (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel Hint is corrupt (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_397 & (io_in_d_valid & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_2 & ~_T_397) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel has invalid opcode (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel Grant smaller than a beat (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel GrantData smaller than a beat (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_544 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_544) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_548 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_548) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel param changed within multibeat operation (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_552 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_552) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel size changed within multibeat operation (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_556 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_556) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel source changed within multibeat operation (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_560 & (_T_543 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_543 & ~reset & ~_T_560) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel address changed with multibeat operation (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_568 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_568) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_576 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_576) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel size changed within multibeat operation (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_580 & (_T_567 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_567 & _T_2 & ~_T_580) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel source changed within multibeat operation (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_601 & (_T_597 & ~reset)) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_597 & ~reset & ~_T_601) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'A' channel re-used a source ID (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_620 & (_T_608 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & _T_2 & ~_T_620) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper opcode response (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_654 & (_T_652 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_652 & _T_2 & ~_T_654) begin
+ $fwrite(32'h80000002,"Assertion failed: ready check\n at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_663 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_663) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_697[0] & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_697[0]) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_707 & (_T_689 & _T_2)) begin
+ $fatal; // @[Monitor.scala 49:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_689 & _T_2 & ~_T_707) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: 'D' channel contains improper response size (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:49 assert(cond, message)\n"
+ ); // @[Monitor.scala 49:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_727 & ~reset) begin
+ $fatal; // @[Monitor.scala 42:11]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_727) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: TileLink timeout expired (connected at TileResetSetter.scala:69:75)\n at Monitor.scala:42 assert(cond, message)\n"
+ ); // @[Monitor.scala 42:11]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ a_first_counter = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ opcode = _RAND_1[2:0];
+ _RAND_2 = {1{`RANDOM}};
+ param = _RAND_2[2:0];
+ _RAND_3 = {1{`RANDOM}};
+ size = _RAND_3[1:0];
+ _RAND_4 = {1{`RANDOM}};
+ source = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ address = _RAND_5[20:0];
+ _RAND_6 = {1{`RANDOM}};
+ d_first_counter = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ opcode_1 = _RAND_7[2:0];
+ _RAND_8 = {1{`RANDOM}};
+ size_1 = _RAND_8[1:0];
+ _RAND_9 = {1{`RANDOM}};
+ source_1 = _RAND_9[6:0];
+ _RAND_10 = {3{`RANDOM}};
+ inflight = _RAND_10[79:0];
+ _RAND_11 = {10{`RANDOM}};
+ inflight_opcodes = _RAND_11[319:0];
+ _RAND_12 = {10{`RANDOM}};
+ inflight_sizes = _RAND_12[319:0];
+ _RAND_13 = {1{`RANDOM}};
+ a_first_counter_1 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ d_first_counter_1 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ watchdog = _RAND_15[31:0];
+ _RAND_16 = {3{`RANDOM}};
+ inflight_1 = _RAND_16[79:0];
+ _RAND_17 = {10{`RANDOM}};
+ inflight_sizes_1 = _RAND_17[319:0];
+ _RAND_18 = {1{`RANDOM}};
+ d_first_counter_2 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ watchdog_1 = _RAND_19[31:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module AsyncResetRegVec_w1_i0_8(
+ input clock,
+ input reset,
+ input io_d,
+ output io_q,
+ input io_en
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg reg_; // @[AsyncResetReg.scala 64:50]
+ assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[AsyncResetReg.scala 65:16]
+ reg_ <= 1'h0; // @[AsyncResetReg.scala 66:9]
+ end else if (io_en) begin // @[AsyncResetReg.scala 64:50]
+ reg_ <= io_d;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ reg_ = _RAND_0[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ reg_ = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module TileResetSetter(
+ input clock,
+ input reset,
+ input auto_clock_in_member_allClocks_implicit_clock_clock,
+ input auto_clock_in_member_allClocks_implicit_clock_reset,
+ input auto_clock_in_member_allClocks_subsystem_cbus_0_clock,
+ input auto_clock_in_member_allClocks_subsystem_cbus_0_reset,
+ input auto_clock_in_member_allClocks_subsystem_fbus_0_clock,
+ input auto_clock_in_member_allClocks_subsystem_fbus_0_reset,
+ input auto_clock_in_member_allClocks_subsystem_pbus_0_clock,
+ input auto_clock_in_member_allClocks_subsystem_pbus_0_reset,
+ input auto_clock_in_member_allClocks_subsystem_sbus_0_clock,
+ input auto_clock_in_member_allClocks_subsystem_sbus_0_reset,
+ output auto_clock_out_member_allClocks_implicit_clock_clock,
+ output auto_clock_out_member_allClocks_implicit_clock_reset,
+ output auto_clock_out_member_allClocks_subsystem_cbus_0_clock,
+ output auto_clock_out_member_allClocks_subsystem_cbus_0_reset,
+ output auto_clock_out_member_allClocks_subsystem_fbus_0_clock,
+ output auto_clock_out_member_allClocks_subsystem_fbus_0_reset,
+ output auto_clock_out_member_allClocks_subsystem_pbus_0_clock,
+ output auto_clock_out_member_allClocks_subsystem_pbus_0_reset,
+ output auto_clock_out_member_allClocks_subsystem_sbus_0_clock,
+ output auto_clock_out_member_allClocks_subsystem_sbus_0_reset,
+ output auto_tl_in_a_ready,
+ input auto_tl_in_a_valid,
+ input [2:0] auto_tl_in_a_bits_opcode,
+ input [2:0] auto_tl_in_a_bits_param,
+ input [1:0] auto_tl_in_a_bits_size,
+ input [6:0] auto_tl_in_a_bits_source,
+ input [20:0] auto_tl_in_a_bits_address,
+ input [7:0] auto_tl_in_a_bits_mask,
+ input [63:0] auto_tl_in_a_bits_data,
+ input auto_tl_in_a_bits_corrupt,
+ input auto_tl_in_d_ready,
+ output auto_tl_in_d_valid,
+ output [2:0] auto_tl_in_d_bits_opcode,
+ output [1:0] auto_tl_in_d_bits_size,
+ output [6:0] auto_tl_in_d_bits_source,
+ output [63:0] auto_tl_in_d_bits_data
+);
+ wire monitor_clock; // @[Nodes.scala 24:25]
+ wire monitor_reset; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
+ wire [20:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
+ wire [7:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
+ wire monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_ready; // @[Nodes.scala 24:25]
+ wire monitor_io_in_d_valid; // @[Nodes.scala 24:25]
+ wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
+ wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
+ wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
+ wire r_tile_resets_0_clock; // @[TileResetSetter.scala 33:15]
+ wire r_tile_resets_0_reset; // @[TileResetSetter.scala 33:15]
+ wire r_tile_resets_0_io_d; // @[TileResetSetter.scala 33:15]
+ wire r_tile_resets_0_io_q; // @[TileResetSetter.scala 33:15]
+ wire r_tile_resets_0_io_en; // @[TileResetSetter.scala 33:15]
+ wire in_bits_read = auto_tl_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
+ wire [8:0] in_bits_index = auto_tl_in_a_bits_address[11:3]; // @[RegisterRouter.scala 71:18 73:19]
+ wire [7:0] _out_frontMask_T_9 = auto_tl_in_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_11 = auto_tl_in_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_13 = auto_tl_in_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_15 = auto_tl_in_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_17 = auto_tl_in_a_bits_mask[4] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_19 = auto_tl_in_a_bits_mask[5] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_21 = auto_tl_in_a_bits_mask[6] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [7:0] _out_frontMask_T_23 = auto_tl_in_a_bits_mask[7] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
+ wire [63:0] out_frontMask = {_out_frontMask_T_23,_out_frontMask_T_21,_out_frontMask_T_19,_out_frontMask_T_17,
+ _out_frontMask_T_15,_out_frontMask_T_13,_out_frontMask_T_11,_out_frontMask_T_9}; // @[Cat.scala 31:58]
+ wire out_wimask = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
+ wire out_wivalid_0 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_bits_read & in_bits_index == 9'h0; // @[RegisterRouter.scala 83:24]
+ wire _out_out_bits_data_T_4 = in_bits_index == 9'h0 & r_tile_resets_0_io_q; // @[RegisterRouter.scala 83:24]
+ TLMonitor_63 monitor ( // @[Nodes.scala 24:25]
+ .clock(monitor_clock),
+ .reset(monitor_reset),
+ .io_in_a_ready(monitor_io_in_a_ready),
+ .io_in_a_valid(monitor_io_in_a_valid),
+ .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
+ .io_in_a_bits_param(monitor_io_in_a_bits_param),
+ .io_in_a_bits_size(monitor_io_in_a_bits_size),
+ .io_in_a_bits_source(monitor_io_in_a_bits_source),
+ .io_in_a_bits_address(monitor_io_in_a_bits_address),
+ .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
+ .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
+ .io_in_d_ready(monitor_io_in_d_ready),
+ .io_in_d_valid(monitor_io_in_d_valid),
+ .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
+ .io_in_d_bits_size(monitor_io_in_d_bits_size),
+ .io_in_d_bits_source(monitor_io_in_d_bits_source)
+ );
+ AsyncResetRegVec_w1_i0_8 r_tile_resets_0 ( // @[TileResetSetter.scala 33:15]
+ .clock(r_tile_resets_0_clock),
+ .reset(r_tile_resets_0_reset),
+ .io_d(r_tile_resets_0_io_d),
+ .io_q(r_tile_resets_0_io_q),
+ .io_en(r_tile_resets_0_io_en)
+ );
+ assign auto_clock_out_member_allClocks_implicit_clock_clock = auto_clock_in_member_allClocks_implicit_clock_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_implicit_clock_reset = auto_clock_in_member_allClocks_implicit_clock_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_subsystem_cbus_0_clock = auto_clock_in_member_allClocks_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_subsystem_cbus_0_reset = auto_clock_in_member_allClocks_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_subsystem_fbus_0_clock = auto_clock_in_member_allClocks_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_subsystem_fbus_0_reset = auto_clock_in_member_allClocks_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_subsystem_pbus_0_clock = auto_clock_in_member_allClocks_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_subsystem_pbus_0_reset = auto_clock_in_member_allClocks_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_subsystem_sbus_0_clock = auto_clock_in_member_allClocks_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_clock_out_member_allClocks_subsystem_sbus_0_reset = auto_clock_in_member_allClocks_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign auto_tl_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_tl_in_d_bits_data = {{63'd0}, _out_out_bits_data_T_4}; // @[RegisterRouter.scala 83:{24,24}]
+ assign monitor_clock = clock;
+ assign monitor_reset = reset;
+ assign monitor_io_in_a_ready = auto_tl_in_d_ready; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_valid = auto_tl_in_a_valid; // @[RegisterRouter.scala 83:24]
+ assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
+ assign monitor_io_in_d_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign monitor_io_in_d_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign r_tile_resets_0_clock = clock;
+ assign r_tile_resets_0_reset = 1'h1; // @[TileResetSetter.scala 31:38]
+ assign r_tile_resets_0_io_d = auto_tl_in_a_bits_data[0]; // @[RegisterRouter.scala 83:24]
+ assign r_tile_resets_0_io_en = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
+endmodule
+module ClockSinkDomain_8(
+ input auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock,
+ input auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset,
+ input auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock,
+ input auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset,
+ input auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock,
+ input auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset,
+ input auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock,
+ input auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset,
+ input auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock,
+ input auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset,
+ output auto_chipyardPRCI_tl_in_a_ready,
+ input auto_chipyardPRCI_tl_in_a_valid,
+ input [2:0] auto_chipyardPRCI_tl_in_a_bits_opcode,
+ input [2:0] auto_chipyardPRCI_tl_in_a_bits_param,
+ input [1:0] auto_chipyardPRCI_tl_in_a_bits_size,
+ input [6:0] auto_chipyardPRCI_tl_in_a_bits_source,
+ input [20:0] auto_chipyardPRCI_tl_in_a_bits_address,
+ input [7:0] auto_chipyardPRCI_tl_in_a_bits_mask,
+ input [63:0] auto_chipyardPRCI_tl_in_a_bits_data,
+ input auto_chipyardPRCI_tl_in_a_bits_corrupt,
+ input auto_chipyardPRCI_tl_in_d_ready,
+ output auto_chipyardPRCI_tl_in_d_valid,
+ output [2:0] auto_chipyardPRCI_tl_in_d_bits_opcode,
+ output [1:0] auto_chipyardPRCI_tl_in_d_bits_size,
+ output [6:0] auto_chipyardPRCI_tl_in_d_bits_source,
+ output [63:0] auto_chipyardPRCI_tl_in_d_bits_data,
+ output auto_chipyardPRCI_chipyard_prci_in_a_ready,
+ input auto_chipyardPRCI_chipyard_prci_in_a_valid,
+ input [2:0] auto_chipyardPRCI_chipyard_prci_in_a_bits_opcode,
+ input [2:0] auto_chipyardPRCI_chipyard_prci_in_a_bits_param,
+ input [1:0] auto_chipyardPRCI_chipyard_prci_in_a_bits_size,
+ input [6:0] auto_chipyardPRCI_chipyard_prci_in_a_bits_source,
+ input [20:0] auto_chipyardPRCI_chipyard_prci_in_a_bits_address,
+ input [7:0] auto_chipyardPRCI_chipyard_prci_in_a_bits_mask,
+ input [63:0] auto_chipyardPRCI_chipyard_prci_in_a_bits_data,
+ input auto_chipyardPRCI_chipyard_prci_in_a_bits_corrupt,
+ input auto_chipyardPRCI_chipyard_prci_in_d_ready,
+ output auto_chipyardPRCI_chipyard_prci_in_d_valid,
+ output [2:0] auto_chipyardPRCI_chipyard_prci_in_d_bits_opcode,
+ output [1:0] auto_chipyardPRCI_chipyard_prci_in_d_bits_size,
+ output [6:0] auto_chipyardPRCI_chipyard_prci_in_d_bits_source,
+ output [63:0] auto_chipyardPRCI_chipyard_prci_in_d_bits_data,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_clock,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_reset,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock,
+ output auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset,
+ input auto_clock_in_clock,
+ input auto_clock_in_reset
+);
+ wire chipyardPRCI_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_1_a_ready; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_1_a_valid; // @[TileClockGater.scala 51:27]
+ wire [2:0] chipyardPRCI_auto_chipyard_prci_in_1_a_bits_opcode; // @[TileClockGater.scala 51:27]
+ wire [2:0] chipyardPRCI_auto_chipyard_prci_in_1_a_bits_param; // @[TileClockGater.scala 51:27]
+ wire [1:0] chipyardPRCI_auto_chipyard_prci_in_1_a_bits_size; // @[TileClockGater.scala 51:27]
+ wire [6:0] chipyardPRCI_auto_chipyard_prci_in_1_a_bits_source; // @[TileClockGater.scala 51:27]
+ wire [20:0] chipyardPRCI_auto_chipyard_prci_in_1_a_bits_address; // @[TileClockGater.scala 51:27]
+ wire [7:0] chipyardPRCI_auto_chipyard_prci_in_1_a_bits_mask; // @[TileClockGater.scala 51:27]
+ wire [63:0] chipyardPRCI_auto_chipyard_prci_in_1_a_bits_data; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_1_a_bits_corrupt; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_1_d_ready; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_1_d_valid; // @[TileClockGater.scala 51:27]
+ wire [2:0] chipyardPRCI_auto_chipyard_prci_in_1_d_bits_opcode; // @[TileClockGater.scala 51:27]
+ wire [1:0] chipyardPRCI_auto_chipyard_prci_in_1_d_bits_size; // @[TileClockGater.scala 51:27]
+ wire [6:0] chipyardPRCI_auto_chipyard_prci_in_1_d_bits_source; // @[TileClockGater.scala 51:27]
+ wire [63:0] chipyardPRCI_auto_chipyard_prci_in_1_d_bits_data; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_implicit_clock_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_implicit_clock_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset; // @[TileClockGater.scala 51:27]
+ wire chipyardPRCI_1_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_implicit_clock_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_implicit_clock_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_cbus_0_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_cbus_0_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_fbus_0_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_fbus_0_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_pbus_0_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_pbus_0_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_sbus_0_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_sbus_0_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_implicit_clock_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_implicit_clock_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_cbus_0_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_cbus_0_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_fbus_0_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_fbus_0_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_pbus_0_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_pbus_0_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_sbus_0_clock; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_sbus_0_reset; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_tl_in_a_ready; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_tl_in_a_valid; // @[TileResetSetter.scala 68:28]
+ wire [2:0] chipyardPRCI_1_auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala 68:28]
+ wire [2:0] chipyardPRCI_1_auto_tl_in_a_bits_param; // @[TileResetSetter.scala 68:28]
+ wire [1:0] chipyardPRCI_1_auto_tl_in_a_bits_size; // @[TileResetSetter.scala 68:28]
+ wire [6:0] chipyardPRCI_1_auto_tl_in_a_bits_source; // @[TileResetSetter.scala 68:28]
+ wire [20:0] chipyardPRCI_1_auto_tl_in_a_bits_address; // @[TileResetSetter.scala 68:28]
+ wire [7:0] chipyardPRCI_1_auto_tl_in_a_bits_mask; // @[TileResetSetter.scala 68:28]
+ wire [63:0] chipyardPRCI_1_auto_tl_in_a_bits_data; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_tl_in_d_ready; // @[TileResetSetter.scala 68:28]
+ wire chipyardPRCI_1_auto_tl_in_d_valid; // @[TileResetSetter.scala 68:28]
+ wire [2:0] chipyardPRCI_1_auto_tl_in_d_bits_opcode; // @[TileResetSetter.scala 68:28]
+ wire [1:0] chipyardPRCI_1_auto_tl_in_d_bits_size; // @[TileResetSetter.scala 68:28]
+ wire [6:0] chipyardPRCI_1_auto_tl_in_d_bits_source; // @[TileResetSetter.scala 68:28]
+ wire [63:0] chipyardPRCI_1_auto_tl_in_d_bits_data; // @[TileResetSetter.scala 68:28]
+ TileClockGater chipyardPRCI ( // @[TileClockGater.scala 51:27]
+ .clock(chipyardPRCI_clock),
+ .reset(chipyardPRCI_reset),
+ .auto_chipyard_prci_in_1_a_ready(chipyardPRCI_auto_chipyard_prci_in_1_a_ready),
+ .auto_chipyard_prci_in_1_a_valid(chipyardPRCI_auto_chipyard_prci_in_1_a_valid),
+ .auto_chipyard_prci_in_1_a_bits_opcode(chipyardPRCI_auto_chipyard_prci_in_1_a_bits_opcode),
+ .auto_chipyard_prci_in_1_a_bits_param(chipyardPRCI_auto_chipyard_prci_in_1_a_bits_param),
+ .auto_chipyard_prci_in_1_a_bits_size(chipyardPRCI_auto_chipyard_prci_in_1_a_bits_size),
+ .auto_chipyard_prci_in_1_a_bits_source(chipyardPRCI_auto_chipyard_prci_in_1_a_bits_source),
+ .auto_chipyard_prci_in_1_a_bits_address(chipyardPRCI_auto_chipyard_prci_in_1_a_bits_address),
+ .auto_chipyard_prci_in_1_a_bits_mask(chipyardPRCI_auto_chipyard_prci_in_1_a_bits_mask),
+ .auto_chipyard_prci_in_1_a_bits_data(chipyardPRCI_auto_chipyard_prci_in_1_a_bits_data),
+ .auto_chipyard_prci_in_1_a_bits_corrupt(chipyardPRCI_auto_chipyard_prci_in_1_a_bits_corrupt),
+ .auto_chipyard_prci_in_1_d_ready(chipyardPRCI_auto_chipyard_prci_in_1_d_ready),
+ .auto_chipyard_prci_in_1_d_valid(chipyardPRCI_auto_chipyard_prci_in_1_d_valid),
+ .auto_chipyard_prci_in_1_d_bits_opcode(chipyardPRCI_auto_chipyard_prci_in_1_d_bits_opcode),
+ .auto_chipyard_prci_in_1_d_bits_size(chipyardPRCI_auto_chipyard_prci_in_1_d_bits_size),
+ .auto_chipyard_prci_in_1_d_bits_source(chipyardPRCI_auto_chipyard_prci_in_1_d_bits_source),
+ .auto_chipyard_prci_in_1_d_bits_data(chipyardPRCI_auto_chipyard_prci_in_1_d_bits_data),
+ .auto_chipyard_prci_in_0_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_implicit_clock_clock),
+ .auto_chipyard_prci_in_0_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_implicit_clock_reset),
+ .auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock),
+ .auto_chipyard_prci_out_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset)
+ );
+ TileResetSetter chipyardPRCI_1 ( // @[TileResetSetter.scala 68:28]
+ .clock(chipyardPRCI_1_clock),
+ .reset(chipyardPRCI_1_reset),
+ .auto_clock_in_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_implicit_clock_clock),
+ .auto_clock_in_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_implicit_clock_reset),
+ .auto_clock_in_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_cbus_0_clock),
+ .auto_clock_in_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_cbus_0_reset),
+ .auto_clock_in_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_fbus_0_clock),
+ .auto_clock_in_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_fbus_0_reset),
+ .auto_clock_in_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_pbus_0_clock),
+ .auto_clock_in_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_pbus_0_reset),
+ .auto_clock_in_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_sbus_0_clock),
+ .auto_clock_in_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_sbus_0_reset),
+ .auto_clock_out_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_implicit_clock_clock),
+ .auto_clock_out_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_implicit_clock_reset),
+ .auto_clock_out_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_cbus_0_clock),
+ .auto_clock_out_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_cbus_0_reset),
+ .auto_clock_out_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_fbus_0_clock),
+ .auto_clock_out_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_fbus_0_reset),
+ .auto_clock_out_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_pbus_0_clock),
+ .auto_clock_out_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_pbus_0_reset),
+ .auto_clock_out_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_sbus_0_clock),
+ .auto_clock_out_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_sbus_0_reset),
+ .auto_tl_in_a_ready(chipyardPRCI_1_auto_tl_in_a_ready),
+ .auto_tl_in_a_valid(chipyardPRCI_1_auto_tl_in_a_valid),
+ .auto_tl_in_a_bits_opcode(chipyardPRCI_1_auto_tl_in_a_bits_opcode),
+ .auto_tl_in_a_bits_param(chipyardPRCI_1_auto_tl_in_a_bits_param),
+ .auto_tl_in_a_bits_size(chipyardPRCI_1_auto_tl_in_a_bits_size),
+ .auto_tl_in_a_bits_source(chipyardPRCI_1_auto_tl_in_a_bits_source),
+ .auto_tl_in_a_bits_address(chipyardPRCI_1_auto_tl_in_a_bits_address),
+ .auto_tl_in_a_bits_mask(chipyardPRCI_1_auto_tl_in_a_bits_mask),
+ .auto_tl_in_a_bits_data(chipyardPRCI_1_auto_tl_in_a_bits_data),
+ .auto_tl_in_a_bits_corrupt(chipyardPRCI_1_auto_tl_in_a_bits_corrupt),
+ .auto_tl_in_d_ready(chipyardPRCI_1_auto_tl_in_d_ready),
+ .auto_tl_in_d_valid(chipyardPRCI_1_auto_tl_in_d_valid),
+ .auto_tl_in_d_bits_opcode(chipyardPRCI_1_auto_tl_in_d_bits_opcode),
+ .auto_tl_in_d_bits_size(chipyardPRCI_1_auto_tl_in_d_bits_size),
+ .auto_tl_in_d_bits_source(chipyardPRCI_1_auto_tl_in_d_bits_source),
+ .auto_tl_in_d_bits_data(chipyardPRCI_1_auto_tl_in_d_bits_data)
+ );
+ assign auto_chipyardPRCI_tl_in_a_ready = chipyardPRCI_1_auto_tl_in_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_tl_in_d_valid = chipyardPRCI_1_auto_tl_in_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_tl_in_d_bits_opcode = chipyardPRCI_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_tl_in_d_bits_size = chipyardPRCI_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_tl_in_d_bits_source = chipyardPRCI_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_tl_in_d_bits_data = chipyardPRCI_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_chipyard_prci_in_a_ready = chipyardPRCI_auto_chipyard_prci_in_1_a_ready; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_chipyard_prci_in_d_valid = chipyardPRCI_auto_chipyard_prci_in_1_d_valid; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_chipyard_prci_in_d_bits_opcode = chipyardPRCI_auto_chipyard_prci_in_1_d_bits_opcode; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_chipyard_prci_in_d_bits_size = chipyardPRCI_auto_chipyard_prci_in_1_d_bits_size; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_chipyard_prci_in_d_bits_source = chipyardPRCI_auto_chipyard_prci_in_1_d_bits_source; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_chipyard_prci_in_d_bits_data = chipyardPRCI_auto_chipyard_prci_in_1_d_bits_data; // @[LazyModule.scala 309:16]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_clock =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_reset =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset =
+ chipyardPRCI_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 311:12]
+ assign chipyardPRCI_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign chipyardPRCI_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_valid = auto_chipyardPRCI_chipyard_prci_in_a_valid; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_bits_opcode = auto_chipyardPRCI_chipyard_prci_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_bits_param = auto_chipyardPRCI_chipyard_prci_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_bits_size = auto_chipyardPRCI_chipyard_prci_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_bits_source = auto_chipyardPRCI_chipyard_prci_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_bits_address = auto_chipyardPRCI_chipyard_prci_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_bits_mask = auto_chipyardPRCI_chipyard_prci_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_bits_data = auto_chipyardPRCI_chipyard_prci_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_a_bits_corrupt = auto_chipyardPRCI_chipyard_prci_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_1_d_ready = auto_chipyardPRCI_chipyard_prci_in_d_ready; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_implicit_clock_clock =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_implicit_clock_reset =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_clock =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_cbus_0_reset =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_clock =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_fbus_0_reset =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_clock =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_pbus_0_reset =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_clock =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyard_prci_in_0_member_allClocks_subsystem_sbus_0_reset =
+ chipyardPRCI_1_auto_clock_out_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign chipyardPRCI_1_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_implicit_clock_clock =
+ auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_implicit_clock_reset =
+ auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_cbus_0_clock =
+ auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_cbus_0_reset =
+ auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_fbus_0_clock =
+ auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_fbus_0_reset =
+ auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_pbus_0_clock =
+ auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_pbus_0_reset =
+ auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_sbus_0_clock =
+ auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_clock_in_member_allClocks_subsystem_sbus_0_reset =
+ auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_valid = auto_chipyardPRCI_tl_in_a_valid; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_bits_opcode = auto_chipyardPRCI_tl_in_a_bits_opcode; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_bits_param = auto_chipyardPRCI_tl_in_a_bits_param; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_bits_size = auto_chipyardPRCI_tl_in_a_bits_size; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_bits_source = auto_chipyardPRCI_tl_in_a_bits_source; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_bits_address = auto_chipyardPRCI_tl_in_a_bits_address; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_bits_mask = auto_chipyardPRCI_tl_in_a_bits_mask; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_bits_data = auto_chipyardPRCI_tl_in_a_bits_data; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_a_bits_corrupt = auto_chipyardPRCI_tl_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_1_auto_tl_in_d_ready = auto_chipyardPRCI_tl_in_d_ready; // @[LazyModule.scala 309:16]
+endmodule
+module ClockGroupAggregator_4(
+ input auto_in_member_allClocks_implicit_clock_clock,
+ input auto_in_member_allClocks_implicit_clock_reset,
+ input auto_in_member_allClocks_subsystem_cbus_0_clock,
+ input auto_in_member_allClocks_subsystem_cbus_0_reset,
+ input auto_in_member_allClocks_subsystem_fbus_0_clock,
+ input auto_in_member_allClocks_subsystem_fbus_0_reset,
+ input auto_in_member_allClocks_subsystem_pbus_0_clock,
+ input auto_in_member_allClocks_subsystem_pbus_0_reset,
+ input auto_in_member_allClocks_subsystem_sbus_0_clock,
+ input auto_in_member_allClocks_subsystem_sbus_0_reset,
+ output auto_out_4_member_chipyardPRCI_implicit_clock_clock,
+ output auto_out_4_member_chipyardPRCI_implicit_clock_reset,
+ output auto_out_3_member_subsystem_cbus_subsystem_cbus_0_clock,
+ output auto_out_3_member_subsystem_cbus_subsystem_cbus_0_reset,
+ output auto_out_2_member_subsystem_fbus_subsystem_fbus_0_clock,
+ output auto_out_2_member_subsystem_fbus_subsystem_fbus_0_reset,
+ output auto_out_1_member_subsystem_pbus_subsystem_pbus_0_clock,
+ output auto_out_1_member_subsystem_pbus_subsystem_pbus_0_reset,
+ output auto_out_0_member_subsystem_sbus_subsystem_sbus_0_clock,
+ output auto_out_0_member_subsystem_sbus_subsystem_sbus_0_reset
+);
+ assign auto_out_4_member_chipyardPRCI_implicit_clock_clock = auto_in_member_allClocks_implicit_clock_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_4_member_chipyardPRCI_implicit_clock_reset = auto_in_member_allClocks_implicit_clock_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_member_subsystem_cbus_subsystem_cbus_0_clock = auto_in_member_allClocks_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_3_member_subsystem_cbus_subsystem_cbus_0_reset = auto_in_member_allClocks_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_member_subsystem_fbus_subsystem_fbus_0_clock = auto_in_member_allClocks_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_2_member_subsystem_fbus_subsystem_fbus_0_reset = auto_in_member_allClocks_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_member_subsystem_pbus_subsystem_pbus_0_clock = auto_in_member_allClocks_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_1_member_subsystem_pbus_subsystem_pbus_0_reset = auto_in_member_allClocks_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_member_subsystem_sbus_subsystem_sbus_0_clock = auto_in_member_allClocks_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_0_member_subsystem_sbus_subsystem_sbus_0_reset = auto_in_member_allClocks_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockGroupParameterModifier(
+ input auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_clock,
+ input auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_reset,
+ input auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_clock,
+ input auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_reset,
+ input auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_clock,
+ input auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_reset,
+ input auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_clock,
+ input auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_reset,
+ output auto_chipyard_prci_out_3_member_subsystem_cbus_0_clock,
+ output auto_chipyard_prci_out_3_member_subsystem_cbus_0_reset,
+ output auto_chipyard_prci_out_2_member_subsystem_fbus_0_clock,
+ output auto_chipyard_prci_out_2_member_subsystem_fbus_0_reset,
+ output auto_chipyard_prci_out_1_member_subsystem_pbus_0_clock,
+ output auto_chipyard_prci_out_1_member_subsystem_pbus_0_reset,
+ output auto_chipyard_prci_out_0_member_subsystem_sbus_0_clock,
+ output auto_chipyard_prci_out_0_member_subsystem_sbus_0_reset
+);
+ assign auto_chipyard_prci_out_3_member_subsystem_cbus_0_clock =
+ auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_3_member_subsystem_cbus_0_reset =
+ auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_2_member_subsystem_fbus_0_clock =
+ auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_2_member_subsystem_fbus_0_reset =
+ auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_1_member_subsystem_pbus_0_clock =
+ auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_1_member_subsystem_pbus_0_reset =
+ auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_0_member_subsystem_sbus_0_clock =
+ auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_0_member_subsystem_sbus_0_reset =
+ auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ClockGroupParameterModifier_1(
+ input auto_chipyard_prci_in_member_allClocks_implicit_clock_clock,
+ input auto_chipyard_prci_in_member_allClocks_implicit_clock_reset,
+ input auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock,
+ input auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset,
+ input auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock,
+ input auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset,
+ input auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock,
+ input auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset,
+ input auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock,
+ input auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset,
+ output auto_chipyard_prci_out_member_allClocks_implicit_clock_clock,
+ output auto_chipyard_prci_out_member_allClocks_implicit_clock_reset,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock,
+ output auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset
+);
+ assign auto_chipyard_prci_out_member_allClocks_implicit_clock_clock =
+ auto_chipyard_prci_in_member_allClocks_implicit_clock_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_implicit_clock_reset =
+ auto_chipyard_prci_in_member_allClocks_implicit_clock_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock =
+ auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset =
+ auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock =
+ auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset =
+ auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock =
+ auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset =
+ auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock =
+ auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset =
+ auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ResetCatchAndSync_d3(
+ input clock,
+ input reset,
+ output io_sync_reset
+);
+ wire io_sync_reset_chain_clock; // @[ShiftReg.scala 45:23]
+ wire io_sync_reset_chain_reset; // @[ShiftReg.scala 45:23]
+ wire io_sync_reset_chain_io_d; // @[ShiftReg.scala 45:23]
+ wire io_sync_reset_chain_io_q; // @[ShiftReg.scala 45:23]
+ wire _io_sync_reset_WIRE = io_sync_reset_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 io_sync_reset_chain ( // @[ShiftReg.scala 45:23]
+ .clock(io_sync_reset_chain_clock),
+ .reset(io_sync_reset_chain_reset),
+ .io_d(io_sync_reset_chain_io_d),
+ .io_q(io_sync_reset_chain_io_q)
+ );
+ assign io_sync_reset = ~_io_sync_reset_WIRE; // @[ResetCatchAndSync.scala 29:7]
+ assign io_sync_reset_chain_clock = clock;
+ assign io_sync_reset_chain_reset = reset; // @[ResetCatchAndSync.scala 26:27]
+ assign io_sync_reset_chain_io_d = 1'h1; // @[ShiftReg.scala 47:16]
+endmodule
+module ClockGroupResetSynchronizer(
+ input auto_in_member_allClocks_implicit_clock_clock,
+ input auto_in_member_allClocks_implicit_clock_reset,
+ input auto_in_member_allClocks_subsystem_cbus_0_clock,
+ input auto_in_member_allClocks_subsystem_cbus_0_reset,
+ input auto_in_member_allClocks_subsystem_fbus_0_clock,
+ input auto_in_member_allClocks_subsystem_fbus_0_reset,
+ input auto_in_member_allClocks_subsystem_pbus_0_clock,
+ input auto_in_member_allClocks_subsystem_pbus_0_reset,
+ input auto_in_member_allClocks_subsystem_sbus_0_clock,
+ input auto_in_member_allClocks_subsystem_sbus_0_reset,
+ output auto_out_member_allClocks_implicit_clock_clock,
+ output auto_out_member_allClocks_implicit_clock_reset,
+ output auto_out_member_allClocks_subsystem_cbus_0_clock,
+ output auto_out_member_allClocks_subsystem_cbus_0_reset,
+ output auto_out_member_allClocks_subsystem_fbus_0_clock,
+ output auto_out_member_allClocks_subsystem_fbus_0_reset,
+ output auto_out_member_allClocks_subsystem_pbus_0_clock,
+ output auto_out_member_allClocks_subsystem_pbus_0_reset,
+ output auto_out_member_allClocks_subsystem_sbus_0_clock,
+ output auto_out_member_allClocks_subsystem_sbus_0_reset
+);
+ wire bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_clock; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_clock; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_clock; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_clock; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_implicit_clock_reset_catcher_clock; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_implicit_clock_reset_catcher_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire bundleOut_0_member_allClocks_implicit_clock_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala 39:28]
+ ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher ( // @[ResetCatchAndSync.scala 39:28]
+ .clock(bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_clock),
+ .reset(bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_reset),
+ .io_sync_reset(bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_io_sync_reset)
+ );
+ ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher ( // @[ResetCatchAndSync.scala 39:28]
+ .clock(bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_clock),
+ .reset(bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_reset),
+ .io_sync_reset(bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_io_sync_reset)
+ );
+ ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher ( // @[ResetCatchAndSync.scala 39:28]
+ .clock(bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_clock),
+ .reset(bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_reset),
+ .io_sync_reset(bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_io_sync_reset)
+ );
+ ResetCatchAndSync_d3 bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher ( // @[ResetCatchAndSync.scala 39:28]
+ .clock(bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_clock),
+ .reset(bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_reset),
+ .io_sync_reset(bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_io_sync_reset)
+ );
+ ResetCatchAndSync_d3 bundleOut_0_member_allClocks_implicit_clock_reset_catcher ( // @[ResetCatchAndSync.scala 39:28]
+ .clock(bundleOut_0_member_allClocks_implicit_clock_reset_catcher_clock),
+ .reset(bundleOut_0_member_allClocks_implicit_clock_reset_catcher_reset),
+ .io_sync_reset(bundleOut_0_member_allClocks_implicit_clock_reset_catcher_io_sync_reset)
+ );
+ assign auto_out_member_allClocks_implicit_clock_clock = auto_in_member_allClocks_implicit_clock_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_allClocks_implicit_clock_reset =
+ bundleOut_0_member_allClocks_implicit_clock_reset_catcher_io_sync_reset; // @[Nodes.scala 1207:84 ResetSynchronizer.scala 35:17]
+ assign auto_out_member_allClocks_subsystem_cbus_0_clock = auto_in_member_allClocks_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_allClocks_subsystem_cbus_0_reset =
+ bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_io_sync_reset; // @[Nodes.scala 1207:84 ResetSynchronizer.scala 35:17]
+ assign auto_out_member_allClocks_subsystem_fbus_0_clock = auto_in_member_allClocks_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_allClocks_subsystem_fbus_0_reset =
+ bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_io_sync_reset; // @[Nodes.scala 1207:84 ResetSynchronizer.scala 35:17]
+ assign auto_out_member_allClocks_subsystem_pbus_0_clock = auto_in_member_allClocks_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_allClocks_subsystem_pbus_0_reset =
+ bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_io_sync_reset; // @[Nodes.scala 1207:84 ResetSynchronizer.scala 35:17]
+ assign auto_out_member_allClocks_subsystem_sbus_0_clock = auto_in_member_allClocks_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_member_allClocks_subsystem_sbus_0_reset =
+ bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_io_sync_reset; // @[Nodes.scala 1207:84 ResetSynchronizer.scala 35:17]
+ assign bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_clock =
+ auto_in_member_allClocks_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_member_allClocks_subsystem_sbus_0_reset_catcher_reset =
+ auto_in_member_allClocks_subsystem_sbus_0_reset; // @[ResetSynchronizer.scala 35:55]
+ assign bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_clock =
+ auto_in_member_allClocks_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_member_allClocks_subsystem_pbus_0_reset_catcher_reset =
+ auto_in_member_allClocks_subsystem_pbus_0_reset; // @[ResetSynchronizer.scala 35:55]
+ assign bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_clock =
+ auto_in_member_allClocks_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_member_allClocks_subsystem_fbus_0_reset_catcher_reset =
+ auto_in_member_allClocks_subsystem_fbus_0_reset; // @[ResetSynchronizer.scala 35:55]
+ assign bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_clock =
+ auto_in_member_allClocks_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_member_allClocks_subsystem_cbus_0_reset_catcher_reset =
+ auto_in_member_allClocks_subsystem_cbus_0_reset; // @[ResetSynchronizer.scala 35:55]
+ assign bundleOut_0_member_allClocks_implicit_clock_reset_catcher_clock = auto_in_member_allClocks_implicit_clock_clock
+ ; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_member_allClocks_implicit_clock_reset_catcher_reset = auto_in_member_allClocks_implicit_clock_reset
+ ; // @[ResetSynchronizer.scala 35:55]
+endmodule
+module CaptureUpdateChain(
+ input clock,
+ input reset,
+ input io_chainIn_shift,
+ input io_chainIn_data,
+ input io_chainIn_capture,
+ input io_chainIn_update,
+ output io_chainOut_data,
+ input [1:0] io_capture_bits_dmiStatus,
+ output io_update_valid,
+ output io_update_bits_dmireset
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [31:0] _RAND_30;
+ reg [31:0] _RAND_31;
+`endif // RANDOMIZE_REG_INIT
+ reg regs_0; // @[JtagShifter.scala 154:39]
+ reg regs_1; // @[JtagShifter.scala 154:39]
+ reg regs_2; // @[JtagShifter.scala 154:39]
+ reg regs_3; // @[JtagShifter.scala 154:39]
+ reg regs_4; // @[JtagShifter.scala 154:39]
+ reg regs_5; // @[JtagShifter.scala 154:39]
+ reg regs_6; // @[JtagShifter.scala 154:39]
+ reg regs_7; // @[JtagShifter.scala 154:39]
+ reg regs_8; // @[JtagShifter.scala 154:39]
+ reg regs_9; // @[JtagShifter.scala 154:39]
+ reg regs_10; // @[JtagShifter.scala 154:39]
+ reg regs_11; // @[JtagShifter.scala 154:39]
+ reg regs_12; // @[JtagShifter.scala 154:39]
+ reg regs_13; // @[JtagShifter.scala 154:39]
+ reg regs_14; // @[JtagShifter.scala 154:39]
+ reg regs_15; // @[JtagShifter.scala 154:39]
+ reg regs_16; // @[JtagShifter.scala 154:39]
+ reg regs_17; // @[JtagShifter.scala 154:39]
+ reg regs_18; // @[JtagShifter.scala 154:39]
+ reg regs_19; // @[JtagShifter.scala 154:39]
+ reg regs_20; // @[JtagShifter.scala 154:39]
+ reg regs_21; // @[JtagShifter.scala 154:39]
+ reg regs_22; // @[JtagShifter.scala 154:39]
+ reg regs_23; // @[JtagShifter.scala 154:39]
+ reg regs_24; // @[JtagShifter.scala 154:39]
+ reg regs_25; // @[JtagShifter.scala 154:39]
+ reg regs_26; // @[JtagShifter.scala 154:39]
+ reg regs_27; // @[JtagShifter.scala 154:39]
+ reg regs_28; // @[JtagShifter.scala 154:39]
+ reg regs_29; // @[JtagShifter.scala 154:39]
+ reg regs_30; // @[JtagShifter.scala 154:39]
+ reg regs_31; // @[JtagShifter.scala 154:39]
+ wire [7:0] updateBits_lo_lo = {regs_7,regs_6,regs_5,regs_4,regs_3,regs_2,regs_1,regs_0}; // @[Cat.scala 31:58]
+ wire [15:0] updateBits_lo = {regs_15,regs_14,regs_13,regs_12,regs_11,regs_10,regs_9,regs_8,updateBits_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] updateBits_hi_lo = {regs_23,regs_22,regs_21,regs_20,regs_19,regs_18,regs_17,regs_16}; // @[Cat.scala 31:58]
+ wire [31:0] updateBits = {regs_31,regs_30,regs_29,regs_28,regs_27,regs_26,regs_25,regs_24,updateBits_hi_lo,
+ updateBits_lo}; // @[Cat.scala 31:58]
+ wire [31:0] captureBits = {20'h5,io_capture_bits_dmiStatus,6'h7,4'h1}; // @[JtagShifter.scala 161:43]
+ wire _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 183:10]
+ wire _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 184:7]
+ wire _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 185:7]
+ assign io_chainOut_data = regs_0; // @[JtagShifter.scala 156:20]
+ assign io_update_valid = io_chainIn_capture ? 1'h0 : io_chainIn_update; // @[JtagShifter.scala 166:29 170:21]
+ assign io_update_bits_dmireset = updateBits[16]; // @[JtagShifter.scala 159:40]
+ always @(posedge clock) begin
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_0 <= captureBits[0]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_0 <= regs_1; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_1 <= captureBits[1]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_1 <= regs_2; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_2 <= captureBits[2]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_2 <= regs_3; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_3 <= captureBits[3]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_3 <= regs_4; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_4 <= captureBits[4]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_4 <= regs_5; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_5 <= captureBits[5]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_5 <= regs_6; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_6 <= captureBits[6]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_6 <= regs_7; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_7 <= captureBits[7]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_7 <= regs_8; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_8 <= captureBits[8]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_8 <= regs_9; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_9 <= captureBits[9]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_9 <= regs_10; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_10 <= captureBits[10]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_10 <= regs_11; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_11 <= captureBits[11]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_11 <= regs_12; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_12 <= captureBits[12]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_12 <= regs_13; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_13 <= captureBits[13]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_13 <= regs_14; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_14 <= captureBits[14]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_14 <= regs_15; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_15 <= captureBits[15]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_15 <= regs_16; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_16 <= captureBits[16]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_16 <= regs_17; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_17 <= captureBits[17]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_17 <= regs_18; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_18 <= captureBits[18]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_18 <= regs_19; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_19 <= captureBits[19]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_19 <= regs_20; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_20 <= captureBits[20]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_20 <= regs_21; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_21 <= captureBits[21]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_21 <= regs_22; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_22 <= captureBits[22]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_22 <= regs_23; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_23 <= captureBits[23]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_23 <= regs_24; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_24 <= captureBits[24]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_24 <= regs_25; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_25 <= captureBits[25]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_25 <= regs_26; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_26 <= captureBits[26]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_26 <= regs_27; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_27 <= captureBits[27]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_27 <= regs_28; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_28 <= captureBits[28]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_28 <= regs_29; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_29 <= captureBits[29]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_29 <= regs_30; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_30 <= captureBits[30]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_30 <= regs_31; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_31 <= captureBits[31]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_31 <= io_chainIn_data; // @[JtagShifter.scala 175:15]
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_7 & ~reset) begin
+ $fatal; // @[JtagShifter.scala 183:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_7) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at JtagShifter.scala:183 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 183:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ regs_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ regs_1 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ regs_2 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ regs_3 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ regs_4 = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ regs_5 = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ regs_6 = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ regs_7 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ regs_8 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ regs_9 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ regs_10 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ regs_11 = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ regs_12 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ regs_13 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ regs_14 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ regs_15 = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ regs_16 = _RAND_16[0:0];
+ _RAND_17 = {1{`RANDOM}};
+ regs_17 = _RAND_17[0:0];
+ _RAND_18 = {1{`RANDOM}};
+ regs_18 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ regs_19 = _RAND_19[0:0];
+ _RAND_20 = {1{`RANDOM}};
+ regs_20 = _RAND_20[0:0];
+ _RAND_21 = {1{`RANDOM}};
+ regs_21 = _RAND_21[0:0];
+ _RAND_22 = {1{`RANDOM}};
+ regs_22 = _RAND_22[0:0];
+ _RAND_23 = {1{`RANDOM}};
+ regs_23 = _RAND_23[0:0];
+ _RAND_24 = {1{`RANDOM}};
+ regs_24 = _RAND_24[0:0];
+ _RAND_25 = {1{`RANDOM}};
+ regs_25 = _RAND_25[0:0];
+ _RAND_26 = {1{`RANDOM}};
+ regs_26 = _RAND_26[0:0];
+ _RAND_27 = {1{`RANDOM}};
+ regs_27 = _RAND_27[0:0];
+ _RAND_28 = {1{`RANDOM}};
+ regs_28 = _RAND_28[0:0];
+ _RAND_29 = {1{`RANDOM}};
+ regs_29 = _RAND_29[0:0];
+ _RAND_30 = {1{`RANDOM}};
+ regs_30 = _RAND_30[0:0];
+ _RAND_31 = {1{`RANDOM}};
+ regs_31 = _RAND_31[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module CaptureUpdateChain_1(
+ input clock,
+ input reset,
+ input io_chainIn_shift,
+ input io_chainIn_data,
+ input io_chainIn_capture,
+ input io_chainIn_update,
+ output io_chainOut_data,
+ input [6:0] io_capture_bits_addr,
+ input [31:0] io_capture_bits_data,
+ input [1:0] io_capture_bits_resp,
+ output io_capture_capture,
+ output io_update_valid,
+ output [6:0] io_update_bits_addr,
+ output [31:0] io_update_bits_data,
+ output [1:0] io_update_bits_op
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [31:0] _RAND_30;
+ reg [31:0] _RAND_31;
+ reg [31:0] _RAND_32;
+ reg [31:0] _RAND_33;
+ reg [31:0] _RAND_34;
+ reg [31:0] _RAND_35;
+ reg [31:0] _RAND_36;
+ reg [31:0] _RAND_37;
+ reg [31:0] _RAND_38;
+ reg [31:0] _RAND_39;
+ reg [31:0] _RAND_40;
+`endif // RANDOMIZE_REG_INIT
+ reg regs_0; // @[JtagShifter.scala 154:39]
+ reg regs_1; // @[JtagShifter.scala 154:39]
+ reg regs_2; // @[JtagShifter.scala 154:39]
+ reg regs_3; // @[JtagShifter.scala 154:39]
+ reg regs_4; // @[JtagShifter.scala 154:39]
+ reg regs_5; // @[JtagShifter.scala 154:39]
+ reg regs_6; // @[JtagShifter.scala 154:39]
+ reg regs_7; // @[JtagShifter.scala 154:39]
+ reg regs_8; // @[JtagShifter.scala 154:39]
+ reg regs_9; // @[JtagShifter.scala 154:39]
+ reg regs_10; // @[JtagShifter.scala 154:39]
+ reg regs_11; // @[JtagShifter.scala 154:39]
+ reg regs_12; // @[JtagShifter.scala 154:39]
+ reg regs_13; // @[JtagShifter.scala 154:39]
+ reg regs_14; // @[JtagShifter.scala 154:39]
+ reg regs_15; // @[JtagShifter.scala 154:39]
+ reg regs_16; // @[JtagShifter.scala 154:39]
+ reg regs_17; // @[JtagShifter.scala 154:39]
+ reg regs_18; // @[JtagShifter.scala 154:39]
+ reg regs_19; // @[JtagShifter.scala 154:39]
+ reg regs_20; // @[JtagShifter.scala 154:39]
+ reg regs_21; // @[JtagShifter.scala 154:39]
+ reg regs_22; // @[JtagShifter.scala 154:39]
+ reg regs_23; // @[JtagShifter.scala 154:39]
+ reg regs_24; // @[JtagShifter.scala 154:39]
+ reg regs_25; // @[JtagShifter.scala 154:39]
+ reg regs_26; // @[JtagShifter.scala 154:39]
+ reg regs_27; // @[JtagShifter.scala 154:39]
+ reg regs_28; // @[JtagShifter.scala 154:39]
+ reg regs_29; // @[JtagShifter.scala 154:39]
+ reg regs_30; // @[JtagShifter.scala 154:39]
+ reg regs_31; // @[JtagShifter.scala 154:39]
+ reg regs_32; // @[JtagShifter.scala 154:39]
+ reg regs_33; // @[JtagShifter.scala 154:39]
+ reg regs_34; // @[JtagShifter.scala 154:39]
+ reg regs_35; // @[JtagShifter.scala 154:39]
+ reg regs_36; // @[JtagShifter.scala 154:39]
+ reg regs_37; // @[JtagShifter.scala 154:39]
+ reg regs_38; // @[JtagShifter.scala 154:39]
+ reg regs_39; // @[JtagShifter.scala 154:39]
+ reg regs_40; // @[JtagShifter.scala 154:39]
+ wire [9:0] updateBits_lo_lo = {regs_9,regs_8,regs_7,regs_6,regs_5,regs_4,regs_3,regs_2,regs_1,regs_0}; // @[Cat.scala 31:58]
+ wire [9:0] updateBits_lo_hi = {regs_19,regs_18,regs_17,regs_16,regs_15,regs_14,regs_13,regs_12,regs_11,regs_10}; // @[Cat.scala 31:58]
+ wire [9:0] updateBits_hi_lo = {regs_29,regs_28,regs_27,regs_26,regs_25,regs_24,regs_23,regs_22,regs_21,regs_20}; // @[Cat.scala 31:58]
+ wire [4:0] updateBits_hi_hi_lo = {regs_34,regs_33,regs_32,regs_31,regs_30}; // @[Cat.scala 31:58]
+ wire [40:0] updateBits = {regs_40,regs_39,regs_38,regs_37,regs_36,regs_35,updateBits_hi_hi_lo,updateBits_hi_lo,
+ updateBits_lo_hi,updateBits_lo_lo}; // @[Cat.scala 31:58]
+ wire [40:0] captureBits = {io_capture_bits_addr,io_capture_bits_data,io_capture_bits_resp}; // @[JtagShifter.scala 161:43]
+ wire _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 183:10]
+ wire _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 184:7]
+ wire _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 185:7]
+ assign io_chainOut_data = regs_0; // @[JtagShifter.scala 156:20]
+ assign io_capture_capture = io_chainIn_capture; // @[JtagShifter.scala 166:29 169:24]
+ assign io_update_valid = io_chainIn_capture ? 1'h0 : io_chainIn_update; // @[JtagShifter.scala 166:29 170:21]
+ assign io_update_bits_addr = updateBits[40:34]; // @[JtagShifter.scala 159:40]
+ assign io_update_bits_data = updateBits[33:2]; // @[JtagShifter.scala 159:40]
+ assign io_update_bits_op = updateBits[1:0]; // @[JtagShifter.scala 159:40]
+ always @(posedge clock) begin
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_0 <= captureBits[0]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_0 <= regs_1; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_1 <= captureBits[1]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_1 <= regs_2; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_2 <= captureBits[2]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_2 <= regs_3; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_3 <= captureBits[3]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_3 <= regs_4; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_4 <= captureBits[4]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_4 <= regs_5; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_5 <= captureBits[5]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_5 <= regs_6; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_6 <= captureBits[6]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_6 <= regs_7; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_7 <= captureBits[7]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_7 <= regs_8; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_8 <= captureBits[8]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_8 <= regs_9; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_9 <= captureBits[9]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_9 <= regs_10; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_10 <= captureBits[10]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_10 <= regs_11; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_11 <= captureBits[11]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_11 <= regs_12; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_12 <= captureBits[12]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_12 <= regs_13; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_13 <= captureBits[13]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_13 <= regs_14; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_14 <= captureBits[14]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_14 <= regs_15; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_15 <= captureBits[15]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_15 <= regs_16; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_16 <= captureBits[16]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_16 <= regs_17; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_17 <= captureBits[17]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_17 <= regs_18; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_18 <= captureBits[18]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_18 <= regs_19; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_19 <= captureBits[19]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_19 <= regs_20; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_20 <= captureBits[20]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_20 <= regs_21; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_21 <= captureBits[21]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_21 <= regs_22; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_22 <= captureBits[22]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_22 <= regs_23; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_23 <= captureBits[23]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_23 <= regs_24; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_24 <= captureBits[24]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_24 <= regs_25; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_25 <= captureBits[25]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_25 <= regs_26; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_26 <= captureBits[26]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_26 <= regs_27; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_27 <= captureBits[27]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_27 <= regs_28; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_28 <= captureBits[28]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_28 <= regs_29; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_29 <= captureBits[29]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_29 <= regs_30; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_30 <= captureBits[30]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_30 <= regs_31; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_31 <= captureBits[31]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_31 <= regs_32; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_32 <= captureBits[32]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_32 <= regs_33; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_33 <= captureBits[33]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_33 <= regs_34; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_34 <= captureBits[34]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_34 <= regs_35; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_35 <= captureBits[35]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_35 <= regs_36; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_36 <= captureBits[36]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_36 <= regs_37; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_37 <= captureBits[37]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_37 <= regs_38; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_38 <= captureBits[38]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_38 <= regs_39; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_39 <= captureBits[39]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_39 <= regs_40; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_40 <= captureBits[40]; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_40 <= io_chainIn_data; // @[JtagShifter.scala 175:15]
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_7 & ~reset) begin
+ $fatal; // @[JtagShifter.scala 183:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_7) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at JtagShifter.scala:183 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 183:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ regs_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ regs_1 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ regs_2 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ regs_3 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ regs_4 = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ regs_5 = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ regs_6 = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ regs_7 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ regs_8 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ regs_9 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ regs_10 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ regs_11 = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ regs_12 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ regs_13 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ regs_14 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ regs_15 = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ regs_16 = _RAND_16[0:0];
+ _RAND_17 = {1{`RANDOM}};
+ regs_17 = _RAND_17[0:0];
+ _RAND_18 = {1{`RANDOM}};
+ regs_18 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ regs_19 = _RAND_19[0:0];
+ _RAND_20 = {1{`RANDOM}};
+ regs_20 = _RAND_20[0:0];
+ _RAND_21 = {1{`RANDOM}};
+ regs_21 = _RAND_21[0:0];
+ _RAND_22 = {1{`RANDOM}};
+ regs_22 = _RAND_22[0:0];
+ _RAND_23 = {1{`RANDOM}};
+ regs_23 = _RAND_23[0:0];
+ _RAND_24 = {1{`RANDOM}};
+ regs_24 = _RAND_24[0:0];
+ _RAND_25 = {1{`RANDOM}};
+ regs_25 = _RAND_25[0:0];
+ _RAND_26 = {1{`RANDOM}};
+ regs_26 = _RAND_26[0:0];
+ _RAND_27 = {1{`RANDOM}};
+ regs_27 = _RAND_27[0:0];
+ _RAND_28 = {1{`RANDOM}};
+ regs_28 = _RAND_28[0:0];
+ _RAND_29 = {1{`RANDOM}};
+ regs_29 = _RAND_29[0:0];
+ _RAND_30 = {1{`RANDOM}};
+ regs_30 = _RAND_30[0:0];
+ _RAND_31 = {1{`RANDOM}};
+ regs_31 = _RAND_31[0:0];
+ _RAND_32 = {1{`RANDOM}};
+ regs_32 = _RAND_32[0:0];
+ _RAND_33 = {1{`RANDOM}};
+ regs_33 = _RAND_33[0:0];
+ _RAND_34 = {1{`RANDOM}};
+ regs_34 = _RAND_34[0:0];
+ _RAND_35 = {1{`RANDOM}};
+ regs_35 = _RAND_35[0:0];
+ _RAND_36 = {1{`RANDOM}};
+ regs_36 = _RAND_36[0:0];
+ _RAND_37 = {1{`RANDOM}};
+ regs_37 = _RAND_37[0:0];
+ _RAND_38 = {1{`RANDOM}};
+ regs_38 = _RAND_38[0:0];
+ _RAND_39 = {1{`RANDOM}};
+ regs_39 = _RAND_39[0:0];
+ _RAND_40 = {1{`RANDOM}};
+ regs_40 = _RAND_40[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module CaptureChain(
+ input clock,
+ input reset,
+ input io_chainIn_shift,
+ input io_chainIn_data,
+ input io_chainIn_capture,
+ input io_chainIn_update,
+ output io_chainOut_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+ reg [31:0] _RAND_8;
+ reg [31:0] _RAND_9;
+ reg [31:0] _RAND_10;
+ reg [31:0] _RAND_11;
+ reg [31:0] _RAND_12;
+ reg [31:0] _RAND_13;
+ reg [31:0] _RAND_14;
+ reg [31:0] _RAND_15;
+ reg [31:0] _RAND_16;
+ reg [31:0] _RAND_17;
+ reg [31:0] _RAND_18;
+ reg [31:0] _RAND_19;
+ reg [31:0] _RAND_20;
+ reg [31:0] _RAND_21;
+ reg [31:0] _RAND_22;
+ reg [31:0] _RAND_23;
+ reg [31:0] _RAND_24;
+ reg [31:0] _RAND_25;
+ reg [31:0] _RAND_26;
+ reg [31:0] _RAND_27;
+ reg [31:0] _RAND_28;
+ reg [31:0] _RAND_29;
+ reg [31:0] _RAND_30;
+ reg [31:0] _RAND_31;
+`endif // RANDOMIZE_REG_INIT
+ reg regs_0; // @[JtagShifter.scala 101:39]
+ reg regs_1; // @[JtagShifter.scala 101:39]
+ reg regs_2; // @[JtagShifter.scala 101:39]
+ reg regs_3; // @[JtagShifter.scala 101:39]
+ reg regs_4; // @[JtagShifter.scala 101:39]
+ reg regs_5; // @[JtagShifter.scala 101:39]
+ reg regs_6; // @[JtagShifter.scala 101:39]
+ reg regs_7; // @[JtagShifter.scala 101:39]
+ reg regs_8; // @[JtagShifter.scala 101:39]
+ reg regs_9; // @[JtagShifter.scala 101:39]
+ reg regs_10; // @[JtagShifter.scala 101:39]
+ reg regs_11; // @[JtagShifter.scala 101:39]
+ reg regs_12; // @[JtagShifter.scala 101:39]
+ reg regs_13; // @[JtagShifter.scala 101:39]
+ reg regs_14; // @[JtagShifter.scala 101:39]
+ reg regs_15; // @[JtagShifter.scala 101:39]
+ reg regs_16; // @[JtagShifter.scala 101:39]
+ reg regs_17; // @[JtagShifter.scala 101:39]
+ reg regs_18; // @[JtagShifter.scala 101:39]
+ reg regs_19; // @[JtagShifter.scala 101:39]
+ reg regs_20; // @[JtagShifter.scala 101:39]
+ reg regs_21; // @[JtagShifter.scala 101:39]
+ reg regs_22; // @[JtagShifter.scala 101:39]
+ reg regs_23; // @[JtagShifter.scala 101:39]
+ reg regs_24; // @[JtagShifter.scala 101:39]
+ reg regs_25; // @[JtagShifter.scala 101:39]
+ reg regs_26; // @[JtagShifter.scala 101:39]
+ reg regs_27; // @[JtagShifter.scala 101:39]
+ reg regs_28; // @[JtagShifter.scala 101:39]
+ reg regs_29; // @[JtagShifter.scala 101:39]
+ reg regs_30; // @[JtagShifter.scala 101:39]
+ reg regs_31; // @[JtagShifter.scala 101:39]
+ wire _GEN_1 = io_chainIn_shift ? regs_1 : regs_0; // @[JtagShifter.scala 110:34 112:37 101:39]
+ wire _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 117:10]
+ wire _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 118:7]
+ wire _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 119:7]
+ assign io_chainOut_data = regs_0; // @[JtagShifter.scala 103:20]
+ always @(posedge clock) begin
+ regs_0 <= io_chainIn_capture | _GEN_1; // @[JtagShifter.scala 107:29 108:35]
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_1 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_1 <= regs_2; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_2 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_2 <= regs_3; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_3 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_3 <= regs_4; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_4 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_4 <= regs_5; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_5 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_5 <= regs_6; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_6 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_6 <= regs_7; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_7 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_7 <= regs_8; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_8 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_8 <= regs_9; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_9 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_9 <= regs_10; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_10 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_10 <= regs_11; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_11 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_11 <= regs_12; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_12 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_12 <= regs_13; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_13 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_13 <= regs_14; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_14 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_14 <= regs_15; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_15 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_15 <= regs_16; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_16 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_16 <= regs_17; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_17 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_17 <= regs_18; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_18 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_18 <= regs_19; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_19 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_19 <= regs_20; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_20 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_20 <= regs_21; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_21 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_21 <= regs_22; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_22 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_22 <= regs_23; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_23 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_23 <= regs_24; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_24 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_24 <= regs_25; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_25 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_25 <= regs_26; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_26 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_26 <= regs_27; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_27 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_27 <= regs_28; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_28 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_28 <= regs_29; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_29 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_29 <= regs_30; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_30 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_30 <= regs_31; // @[JtagShifter.scala 112:37]
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
+ regs_31 <= 1'h0; // @[JtagShifter.scala 108:35]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
+ regs_31 <= io_chainIn_data; // @[JtagShifter.scala 111:15]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_7 & ~reset) begin
+ $fatal; // @[JtagShifter.scala 117:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_7) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at JtagShifter.scala:117 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 117:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ regs_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ regs_1 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ regs_2 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ regs_3 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ regs_4 = _RAND_4[0:0];
+ _RAND_5 = {1{`RANDOM}};
+ regs_5 = _RAND_5[0:0];
+ _RAND_6 = {1{`RANDOM}};
+ regs_6 = _RAND_6[0:0];
+ _RAND_7 = {1{`RANDOM}};
+ regs_7 = _RAND_7[0:0];
+ _RAND_8 = {1{`RANDOM}};
+ regs_8 = _RAND_8[0:0];
+ _RAND_9 = {1{`RANDOM}};
+ regs_9 = _RAND_9[0:0];
+ _RAND_10 = {1{`RANDOM}};
+ regs_10 = _RAND_10[0:0];
+ _RAND_11 = {1{`RANDOM}};
+ regs_11 = _RAND_11[0:0];
+ _RAND_12 = {1{`RANDOM}};
+ regs_12 = _RAND_12[0:0];
+ _RAND_13 = {1{`RANDOM}};
+ regs_13 = _RAND_13[0:0];
+ _RAND_14 = {1{`RANDOM}};
+ regs_14 = _RAND_14[0:0];
+ _RAND_15 = {1{`RANDOM}};
+ regs_15 = _RAND_15[0:0];
+ _RAND_16 = {1{`RANDOM}};
+ regs_16 = _RAND_16[0:0];
+ _RAND_17 = {1{`RANDOM}};
+ regs_17 = _RAND_17[0:0];
+ _RAND_18 = {1{`RANDOM}};
+ regs_18 = _RAND_18[0:0];
+ _RAND_19 = {1{`RANDOM}};
+ regs_19 = _RAND_19[0:0];
+ _RAND_20 = {1{`RANDOM}};
+ regs_20 = _RAND_20[0:0];
+ _RAND_21 = {1{`RANDOM}};
+ regs_21 = _RAND_21[0:0];
+ _RAND_22 = {1{`RANDOM}};
+ regs_22 = _RAND_22[0:0];
+ _RAND_23 = {1{`RANDOM}};
+ regs_23 = _RAND_23[0:0];
+ _RAND_24 = {1{`RANDOM}};
+ regs_24 = _RAND_24[0:0];
+ _RAND_25 = {1{`RANDOM}};
+ regs_25 = _RAND_25[0:0];
+ _RAND_26 = {1{`RANDOM}};
+ regs_26 = _RAND_26[0:0];
+ _RAND_27 = {1{`RANDOM}};
+ regs_27 = _RAND_27[0:0];
+ _RAND_28 = {1{`RANDOM}};
+ regs_28 = _RAND_28[0:0];
+ _RAND_29 = {1{`RANDOM}};
+ regs_29 = _RAND_29[0:0];
+ _RAND_30 = {1{`RANDOM}};
+ regs_30 = _RAND_30[0:0];
+ _RAND_31 = {1{`RANDOM}};
+ regs_31 = _RAND_31[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module JtagStateMachine(
+ input clock,
+ input reset,
+ input io_tms,
+ output [3:0] io_currState
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg [3:0] currState; // @[JtagStateMachine.scala 78:26]
+ wire [3:0] _nextState_T_1 = io_tms ? 4'h7 : 4'hc; // @[JtagStateMachine.scala 85:23]
+ wire [3:0] _nextState_T_3 = io_tms ? 4'h1 : 4'h2; // @[JtagStateMachine.scala 91:23]
+ wire [3:0] _nextState_T_5 = io_tms ? 4'h5 : 4'h3; // @[JtagStateMachine.scala 97:23]
+ wire [3:0] _nextState_T_6 = io_tms ? 4'h0 : 4'h3; // @[JtagStateMachine.scala 100:23]
+ wire [3:0] _nextState_T_7 = io_tms ? 4'h5 : 4'h2; // @[JtagStateMachine.scala 103:23]
+ wire [3:0] _nextState_T_9 = io_tms ? 4'hf : 4'he; // @[JtagStateMachine.scala 109:23]
+ wire [3:0] _nextState_T_10 = io_tms ? 4'h9 : 4'ha; // @[JtagStateMachine.scala 112:23]
+ wire [3:0] _nextState_T_12 = io_tms ? 4'hd : 4'hb; // @[JtagStateMachine.scala 118:23]
+ wire [3:0] _nextState_T_13 = io_tms ? 4'h8 : 4'hb; // @[JtagStateMachine.scala 121:23]
+ wire [3:0] _nextState_T_14 = io_tms ? 4'hd : 4'ha; // @[JtagStateMachine.scala 124:23]
+ wire [3:0] _GEN_0 = 4'hd == currState ? _nextState_T_1 : 4'hf; // @[JtagStateMachine.scala 127:17 80:22]
+ wire [3:0] _GEN_1 = 4'h8 == currState ? _nextState_T_14 : _GEN_0; // @[JtagStateMachine.scala 124:17 80:22]
+ wire [3:0] _GEN_2 = 4'hb == currState ? _nextState_T_13 : _GEN_1; // @[JtagStateMachine.scala 121:17 80:22]
+ wire [3:0] _GEN_3 = 4'h9 == currState ? _nextState_T_12 : _GEN_2; // @[JtagStateMachine.scala 118:17 80:22]
+ wire [3:0] _GEN_4 = 4'ha == currState ? _nextState_T_10 : _GEN_3; // @[JtagStateMachine.scala 115:17 80:22]
+ wire [3:0] _GEN_5 = 4'he == currState ? _nextState_T_10 : _GEN_4; // @[JtagStateMachine.scala 112:17 80:22]
+ wire [3:0] _GEN_6 = 4'h4 == currState ? _nextState_T_9 : _GEN_5; // @[JtagStateMachine.scala 109:17 80:22]
+ wire [3:0] _GEN_7 = 4'h5 == currState ? _nextState_T_1 : _GEN_6; // @[JtagStateMachine.scala 106:17 80:22]
+ wire [3:0] _GEN_8 = 4'h0 == currState ? _nextState_T_7 : _GEN_7; // @[JtagStateMachine.scala 103:17 80:22]
+ wire [3:0] _GEN_9 = 4'h3 == currState ? _nextState_T_6 : _GEN_8; // @[JtagStateMachine.scala 100:17 80:22]
+ wire [3:0] _GEN_10 = 4'h1 == currState ? _nextState_T_5 : _GEN_9; // @[JtagStateMachine.scala 80:22 97:17]
+ wire [3:0] _GEN_11 = 4'h2 == currState ? _nextState_T_3 : _GEN_10; // @[JtagStateMachine.scala 80:22 94:17]
+ assign io_currState = currState; // @[JtagStateMachine.scala 131:16]
+ always @(posedge clock or posedge reset) begin
+ if (reset) begin // @[JtagStateMachine.scala 80:22]
+ currState <= 4'hf; // @[JtagStateMachine.scala 82:23]
+ end else if (4'hf == currState) begin // @[JtagStateMachine.scala 80:22]
+ if (io_tms) begin // @[JtagStateMachine.scala 85:23]
+ currState <= 4'hf;
+ end else begin
+ currState <= 4'hc;
+ end
+ end else if (4'hc == currState) begin // @[JtagStateMachine.scala 80:22]
+ if (io_tms) begin // @[JtagStateMachine.scala 88:23]
+ currState <= 4'h7;
+ end else begin
+ currState <= 4'hc;
+ end
+ end else if (4'h7 == currState) begin // @[JtagStateMachine.scala 80:22]
+ if (io_tms) begin // @[JtagStateMachine.scala 91:17]
+ currState <= 4'h4;
+ end else begin
+ currState <= 4'h6;
+ end
+ end else if (4'h6 == currState) begin
+ currState <= _nextState_T_3;
+ end else begin
+ currState <= _GEN_11;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ currState = _RAND_0[3:0];
+`endif // RANDOMIZE_REG_INIT
+ if (reset) begin
+ currState = 4'hf;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module CaptureUpdateChain_2(
+ input clock,
+ input reset,
+ input io_chainIn_shift,
+ input io_chainIn_data,
+ input io_chainIn_capture,
+ input io_chainIn_update,
+ output io_chainOut_data,
+ output [4:0] io_update_bits
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+`endif // RANDOMIZE_REG_INIT
+ reg regs_0; // @[JtagShifter.scala 154:39]
+ reg regs_1; // @[JtagShifter.scala 154:39]
+ reg regs_2; // @[JtagShifter.scala 154:39]
+ reg regs_3; // @[JtagShifter.scala 154:39]
+ reg regs_4; // @[JtagShifter.scala 154:39]
+ wire [1:0] updateBits_lo = {regs_1,regs_0}; // @[Cat.scala 31:58]
+ wire [2:0] updateBits_hi = {regs_4,regs_3,regs_2}; // @[Cat.scala 31:58]
+ wire _GEN_1 = io_chainIn_shift ? regs_1 : regs_0; // @[JtagShifter.scala 174:34 176:37 154:39]
+ wire _GEN_9 = io_chainIn_update ? regs_0 : _GEN_1; // @[JtagShifter.scala 171:35 154:39]
+ wire _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 183:10]
+ wire _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 184:7]
+ wire _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 185:7]
+ assign io_chainOut_data = regs_0; // @[JtagShifter.scala 156:20]
+ assign io_update_bits = {updateBits_hi,updateBits_lo}; // @[Cat.scala 31:58]
+ always @(posedge clock) begin
+ regs_0 <= io_chainIn_capture | _GEN_9; // @[JtagShifter.scala 166:29 167:59]
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_1 <= 1'h0; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_1 <= regs_2; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_2 <= 1'h0; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_2 <= regs_3; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_3 <= 1'h0; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_3 <= regs_4; // @[JtagShifter.scala 176:37]
+ end
+ end
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
+ regs_4 <= 1'h0; // @[JtagShifter.scala 167:59]
+ end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
+ if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
+ regs_4 <= io_chainIn_data; // @[JtagShifter.scala 175:15]
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_7 & ~reset) begin
+ $fatal; // @[JtagShifter.scala 183:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_7) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at JtagShifter.scala:183 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 183:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ regs_0 = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ regs_1 = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ regs_2 = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ regs_3 = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ regs_4 = _RAND_4[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module JtagTapController(
+ input clock,
+ input reset,
+ input io_jtag_TMS,
+ input io_jtag_TDI,
+ output io_jtag_TDO_data,
+ input io_control_jtag_reset,
+ output [4:0] io_output_instruction,
+ output io_output_tapIsInTestLogicReset,
+ output io_dataChainOut_shift,
+ output io_dataChainOut_data,
+ output io_dataChainOut_capture,
+ output io_dataChainOut_update,
+ input io_dataChainIn_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+ wire stateMachine_clock; // @[JtagTap.scala 82:30]
+ wire stateMachine_reset; // @[JtagTap.scala 82:30]
+ wire stateMachine_io_tms; // @[JtagTap.scala 82:30]
+ wire [3:0] stateMachine_io_currState; // @[JtagTap.scala 82:30]
+ wire irChain_clock; // @[JtagTap.scala 102:23]
+ wire irChain_reset; // @[JtagTap.scala 102:23]
+ wire irChain_io_chainIn_shift; // @[JtagTap.scala 102:23]
+ wire irChain_io_chainIn_data; // @[JtagTap.scala 102:23]
+ wire irChain_io_chainIn_capture; // @[JtagTap.scala 102:23]
+ wire irChain_io_chainIn_update; // @[JtagTap.scala 102:23]
+ wire irChain_io_chainOut_data; // @[JtagTap.scala 102:23]
+ wire [4:0] irChain_io_update_bits; // @[JtagTap.scala 102:23]
+ wire clock_falling = ~clock; // @[JtagTap.scala 67:48]
+ reg tdoReg; // @[JtagTap.scala 89:30]
+ wire [3:0] currState = stateMachine_io_currState; // @[JtagTap.scala 75:23 85:15]
+ wire _irChain_io_chainIn_update_T = currState == 4'hd; // @[JtagTap.scala 107:42]
+ reg [4:0] activeInstruction; // @[JtagTap.scala 111:36]
+ wire tapIsInTestLogicReset = currState == 4'hf; // @[JtagTap.scala 120:38]
+ wire _io_dataChainOut_shift_T = currState == 4'h2; // @[JtagTap.scala 126:38]
+ wire _GEN_2 = irChain_io_chainOut_data; // @[JtagTap.scala 137:51 138:9]
+ JtagStateMachine stateMachine ( // @[JtagTap.scala 82:30]
+ .clock(stateMachine_clock),
+ .reset(stateMachine_reset),
+ .io_tms(stateMachine_io_tms),
+ .io_currState(stateMachine_io_currState)
+ );
+ CaptureUpdateChain_2 irChain ( // @[JtagTap.scala 102:23]
+ .clock(irChain_clock),
+ .reset(irChain_reset),
+ .io_chainIn_shift(irChain_io_chainIn_shift),
+ .io_chainIn_data(irChain_io_chainIn_data),
+ .io_chainIn_capture(irChain_io_chainIn_capture),
+ .io_chainIn_update(irChain_io_chainIn_update),
+ .io_chainOut_data(irChain_io_chainOut_data),
+ .io_update_bits(irChain_io_update_bits)
+ );
+ assign io_jtag_TDO_data = tdoReg; // @[JtagTap.scala 91:26]
+ assign io_output_instruction = activeInstruction; // @[JtagTap.scala 117:27]
+ assign io_output_tapIsInTestLogicReset = currState == 4'hf; // @[JtagTap.scala 120:38]
+ assign io_dataChainOut_shift = currState == 4'h2; // @[JtagTap.scala 126:38]
+ assign io_dataChainOut_data = io_jtag_TDI; // @[JtagTap.scala 127:24]
+ assign io_dataChainOut_capture = currState == 4'h6; // @[JtagTap.scala 128:40]
+ assign io_dataChainOut_update = currState == 4'h5; // @[JtagTap.scala 129:39]
+ assign stateMachine_clock = clock;
+ assign stateMachine_reset = io_control_jtag_reset;
+ assign stateMachine_io_tms = io_jtag_TMS; // @[JtagTap.scala 84:25]
+ assign irChain_clock = clock;
+ assign irChain_reset = reset;
+ assign irChain_io_chainIn_shift = currState == 4'ha; // @[JtagTap.scala 104:41]
+ assign irChain_io_chainIn_data = io_jtag_TDI; // @[JtagTap.scala 105:27]
+ assign irChain_io_chainIn_capture = currState == 4'he; // @[JtagTap.scala 106:43]
+ assign irChain_io_chainIn_update = currState == 4'hd; // @[JtagTap.scala 107:42]
+ always @(posedge clock_falling or posedge io_control_jtag_reset) begin
+ if (io_control_jtag_reset) begin // @[JtagTap.scala 134:44]
+ tdoReg <= 1'h0; // @[JtagTap.scala 135:9]
+ end else if (_io_dataChainOut_shift_T) begin
+ tdoReg <= io_dataChainIn_data;
+ end else begin
+ tdoReg <= _GEN_2;
+ end
+ end
+ always @(posedge clock_falling or posedge io_control_jtag_reset) begin
+ if (io_control_jtag_reset) begin // @[JtagTap.scala 112:34]
+ activeInstruction <= 5'h1; // @[JtagTap.scala 113:25]
+ end else if (tapIsInTestLogicReset) begin // @[JtagTap.scala 114:53]
+ activeInstruction <= 5'h1; // @[JtagTap.scala 115:25]
+ end else if (_irChain_io_chainIn_update_T) begin // @[JtagTap.scala 111:36]
+ activeInstruction <= irChain_io_update_bits;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ tdoReg = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ activeInstruction = _RAND_1[4:0];
+`endif // RANDOMIZE_REG_INIT
+ if (io_control_jtag_reset) begin
+ tdoReg = 1'h0;
+ end
+ if (io_control_jtag_reset) begin
+ activeInstruction = 5'h1;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module JtagBypassChain(
+ input clock,
+ input reset,
+ input io_chainIn_shift,
+ input io_chainIn_data,
+ input io_chainIn_capture,
+ input io_chainIn_update,
+ output io_chainOut_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ reg reg_; // @[JtagShifter.scala 61:16]
+ wire _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 72:10]
+ wire _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 73:7]
+ wire _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 74:7]
+ assign io_chainOut_data = reg_; // @[JtagShifter.scala 63:20]
+ always @(posedge clock) begin
+ if (io_chainIn_capture) begin // @[JtagShifter.scala 67:29]
+ reg_ <= 1'h0; // @[JtagShifter.scala 68:9]
+ end else if (io_chainIn_shift) begin // @[JtagShifter.scala 69:34]
+ reg_ <= io_chainIn_data; // @[JtagShifter.scala 70:9]
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~_T_7 & ~reset) begin
+ $fatal; // @[JtagShifter.scala 72:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~reset & ~_T_7) begin
+ $fwrite(32'h80000002,
+ "Assertion failed\n at JtagShifter.scala:72 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 72:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ reg_ = _RAND_0[0:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module DebugTransportModuleJTAG(
+ input io_jtag_clock,
+ input io_jtag_reset,
+ input io_dmi_req_ready,
+ output io_dmi_req_valid,
+ output [6:0] io_dmi_req_bits_addr,
+ output [31:0] io_dmi_req_bits_data,
+ output [1:0] io_dmi_req_bits_op,
+ output io_dmi_resp_ready,
+ input io_dmi_resp_valid,
+ input [31:0] io_dmi_resp_bits_data,
+ input [1:0] io_dmi_resp_bits_resp,
+ input io_jtag_TMS,
+ input io_jtag_TDI,
+ output io_jtag_TDO_data
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+ reg [31:0] _RAND_1;
+ reg [31:0] _RAND_2;
+ reg [31:0] _RAND_3;
+ reg [31:0] _RAND_4;
+ reg [31:0] _RAND_5;
+ reg [31:0] _RAND_6;
+ reg [31:0] _RAND_7;
+`endif // RANDOMIZE_REG_INIT
+ wire dtmInfoChain_clock; // @[DebugTransport.scala 128:29]
+ wire dtmInfoChain_reset; // @[DebugTransport.scala 128:29]
+ wire dtmInfoChain_io_chainIn_shift; // @[DebugTransport.scala 128:29]
+ wire dtmInfoChain_io_chainIn_data; // @[DebugTransport.scala 128:29]
+ wire dtmInfoChain_io_chainIn_capture; // @[DebugTransport.scala 128:29]
+ wire dtmInfoChain_io_chainIn_update; // @[DebugTransport.scala 128:29]
+ wire dtmInfoChain_io_chainOut_data; // @[DebugTransport.scala 128:29]
+ wire [1:0] dtmInfoChain_io_capture_bits_dmiStatus; // @[DebugTransport.scala 128:29]
+ wire dtmInfoChain_io_update_valid; // @[DebugTransport.scala 128:29]
+ wire dtmInfoChain_io_update_bits_dmireset; // @[DebugTransport.scala 128:29]
+ wire dmiAccessChain_clock; // @[DebugTransport.scala 134:31]
+ wire dmiAccessChain_reset; // @[DebugTransport.scala 134:31]
+ wire dmiAccessChain_io_chainIn_shift; // @[DebugTransport.scala 134:31]
+ wire dmiAccessChain_io_chainIn_data; // @[DebugTransport.scala 134:31]
+ wire dmiAccessChain_io_chainIn_capture; // @[DebugTransport.scala 134:31]
+ wire dmiAccessChain_io_chainIn_update; // @[DebugTransport.scala 134:31]
+ wire dmiAccessChain_io_chainOut_data; // @[DebugTransport.scala 134:31]
+ wire [6:0] dmiAccessChain_io_capture_bits_addr; // @[DebugTransport.scala 134:31]
+ wire [31:0] dmiAccessChain_io_capture_bits_data; // @[DebugTransport.scala 134:31]
+ wire [1:0] dmiAccessChain_io_capture_bits_resp; // @[DebugTransport.scala 134:31]
+ wire dmiAccessChain_io_capture_capture; // @[DebugTransport.scala 134:31]
+ wire dmiAccessChain_io_update_valid; // @[DebugTransport.scala 134:31]
+ wire [6:0] dmiAccessChain_io_update_bits_addr; // @[DebugTransport.scala 134:31]
+ wire [31:0] dmiAccessChain_io_update_bits_data; // @[DebugTransport.scala 134:31]
+ wire [1:0] dmiAccessChain_io_update_bits_op; // @[DebugTransport.scala 134:31]
+ wire tapIO_idcodeChain_clock; // @[JtagTap.scala 181:33]
+ wire tapIO_idcodeChain_reset; // @[JtagTap.scala 181:33]
+ wire tapIO_idcodeChain_io_chainIn_shift; // @[JtagTap.scala 181:33]
+ wire tapIO_idcodeChain_io_chainIn_data; // @[JtagTap.scala 181:33]
+ wire tapIO_idcodeChain_io_chainIn_capture; // @[JtagTap.scala 181:33]
+ wire tapIO_idcodeChain_io_chainIn_update; // @[JtagTap.scala 181:33]
+ wire tapIO_idcodeChain_io_chainOut_data; // @[JtagTap.scala 181:33]
+ wire tapIO_controllerInternal_clock; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_reset; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_jtag_TMS; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_jtag_TDI; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_jtag_TDO_data; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_control_jtag_reset; // @[JtagTap.scala 199:36]
+ wire [4:0] tapIO_controllerInternal_io_output_instruction; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_output_tapIsInTestLogicReset; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 199:36]
+ wire tapIO_controllerInternal_io_dataChainIn_data; // @[JtagTap.scala 199:36]
+ wire tapIO_bypassChain_clock; // @[JtagTap.scala 207:29]
+ wire tapIO_bypassChain_reset; // @[JtagTap.scala 207:29]
+ wire tapIO_bypassChain_io_chainIn_shift; // @[JtagTap.scala 207:29]
+ wire tapIO_bypassChain_io_chainIn_data; // @[JtagTap.scala 207:29]
+ wire tapIO_bypassChain_io_chainIn_capture; // @[JtagTap.scala 207:29]
+ wire tapIO_bypassChain_io_chainIn_update; // @[JtagTap.scala 207:29]
+ wire tapIO_bypassChain_io_chainOut_data; // @[JtagTap.scala 207:29]
+ reg busyReg; // @[DebugTransport.scala 96:24]
+ reg stickyBusyReg; // @[DebugTransport.scala 97:30]
+ reg stickyNonzeroRespReg; // @[DebugTransport.scala 98:37]
+ reg downgradeOpReg; // @[DebugTransport.scala 100:31]
+ reg [6:0] dmiReqReg_addr; // @[DebugTransport.scala 110:23]
+ reg [31:0] dmiReqReg_data; // @[DebugTransport.scala 110:23]
+ reg [1:0] dmiReqReg_op; // @[DebugTransport.scala 110:23]
+ reg dmiReqValidReg; // @[DebugTransport.scala 111:31]
+ wire _dmiStatus_T = stickyNonzeroRespReg | stickyBusyReg; // @[DebugTransport.scala 118:63]
+ wire _GEN_0 = io_dmi_req_valid | busyReg; // @[DebugTransport.scala 143:27 144:13 96:24]
+ wire _T_1 = io_dmi_resp_ready & io_dmi_resp_valid; // @[Decoupled.scala 50:35]
+ wire busy = busyReg & ~io_dmi_resp_valid | stickyBusyReg; // @[DebugTransport.scala 155:42]
+ wire _downgradeOpReg_T = ~busy; // @[DebugTransport.scala 164:24]
+ wire nonzeroResp = stickyNonzeroRespReg | io_dmi_resp_valid & io_dmi_resp_bits_resp != 2'h0; // @[DebugTransport.scala 178:39]
+ wire _GEN_4 = dmiAccessChain_io_capture_capture ? busy : stickyBusyReg; // @[DebugTransport.scala 163:44 165:19 97:30]
+ wire _GEN_5 = dmiAccessChain_io_capture_capture ? nonzeroResp : stickyNonzeroRespReg; // @[DebugTransport.scala 163:44 166:26 98:37]
+ wire [6:0] _dmiAccessChain_io_capture_bits_T_addr = io_dmi_resp_valid ? dmiReqReg_addr : 7'h0; // @[DebugTransport.scala 197:60]
+ wire [31:0] _dmiAccessChain_io_capture_bits_T_data = io_dmi_resp_valid ? io_dmi_resp_bits_data : 32'h0; // @[DebugTransport.scala 197:60]
+ wire [1:0] _dmiAccessChain_io_capture_bits_T_resp = io_dmi_resp_valid ? io_dmi_resp_bits_resp : 2'h0; // @[DebugTransport.scala 197:60]
+ wire _T_4 = io_dmi_req_ready & io_dmi_req_valid; // @[Decoupled.scala 50:35]
+ wire _GEN_14 = downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0 ? 1'h0 : 1'h1; // @[DebugTransport.scala 208:97 216:24]
+ wire _GEN_19 = stickyBusyReg ? 1'h0 : _GEN_14; // @[DebugTransport.scala 206:26]
+ wire dmiReqValidCheck = dmiAccessChain_io_update_valid & _GEN_19; // @[DebugTransport.scala 205:41]
+ wire _T_8 = ~io_jtag_reset; // @[DebugTransport.scala 203:9]
+ wire _GEN_13 = downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0 ? dmiReqValidReg : 1'h1; // @[DebugTransport.scala 111:31 208:97 215:22]
+ wire _io_dmi_resp_ready_T = dmiReqReg_op == 2'h2; // @[DebugTransport.scala 225:18]
+ wire _io_dmi_resp_ready_T_2 = dmiAccessChain_io_capture_capture & _downgradeOpReg_T; // @[DebugTransport.scala 229:41]
+ wire [31:0] _GEN_1 = 32'h1 % 32'h2; // @[JtagTap.scala 184:18]
+ wire [1:0] _tapIO_T = _GEN_1[1:0]; // @[JtagTap.scala 184:18]
+ wire tapIO_icodeSelects_0 = tapIO_controllerInternal_io_output_instruction == 5'h1; // @[JtagTap.scala 223:82]
+ wire tapIO_icodeSelects_0_1 = tapIO_controllerInternal_io_output_instruction == 5'h10; // @[JtagTap.scala 223:82]
+ wire tapIO_icodeSelects_0_2 = tapIO_controllerInternal_io_output_instruction == 5'h11; // @[JtagTap.scala 223:82]
+ wire _GEN_28 = tapIO_icodeSelects_0_2 ? dmiAccessChain_io_chainOut_data : tapIO_bypassChain_io_chainOut_data; // @[JtagTap.scala 233:28 234:43 240:41]
+ wire _GEN_32 = tapIO_icodeSelects_0_1 ? dtmInfoChain_io_chainOut_data : _GEN_28; // @[JtagTap.scala 233:28 234:43]
+ wire tapIO_output_tapIsInTestLogicReset = tapIO_controllerInternal_io_output_tapIsInTestLogicReset; // @[JtagTap.scala 174:26 256:23]
+ CaptureUpdateChain dtmInfoChain ( // @[DebugTransport.scala 128:29]
+ .clock(dtmInfoChain_clock),
+ .reset(dtmInfoChain_reset),
+ .io_chainIn_shift(dtmInfoChain_io_chainIn_shift),
+ .io_chainIn_data(dtmInfoChain_io_chainIn_data),
+ .io_chainIn_capture(dtmInfoChain_io_chainIn_capture),
+ .io_chainIn_update(dtmInfoChain_io_chainIn_update),
+ .io_chainOut_data(dtmInfoChain_io_chainOut_data),
+ .io_capture_bits_dmiStatus(dtmInfoChain_io_capture_bits_dmiStatus),
+ .io_update_valid(dtmInfoChain_io_update_valid),
+ .io_update_bits_dmireset(dtmInfoChain_io_update_bits_dmireset)
+ );
+ CaptureUpdateChain_1 dmiAccessChain ( // @[DebugTransport.scala 134:31]
+ .clock(dmiAccessChain_clock),
+ .reset(dmiAccessChain_reset),
+ .io_chainIn_shift(dmiAccessChain_io_chainIn_shift),
+ .io_chainIn_data(dmiAccessChain_io_chainIn_data),
+ .io_chainIn_capture(dmiAccessChain_io_chainIn_capture),
+ .io_chainIn_update(dmiAccessChain_io_chainIn_update),
+ .io_chainOut_data(dmiAccessChain_io_chainOut_data),
+ .io_capture_bits_addr(dmiAccessChain_io_capture_bits_addr),
+ .io_capture_bits_data(dmiAccessChain_io_capture_bits_data),
+ .io_capture_bits_resp(dmiAccessChain_io_capture_bits_resp),
+ .io_capture_capture(dmiAccessChain_io_capture_capture),
+ .io_update_valid(dmiAccessChain_io_update_valid),
+ .io_update_bits_addr(dmiAccessChain_io_update_bits_addr),
+ .io_update_bits_data(dmiAccessChain_io_update_bits_data),
+ .io_update_bits_op(dmiAccessChain_io_update_bits_op)
+ );
+ CaptureChain tapIO_idcodeChain ( // @[JtagTap.scala 181:33]
+ .clock(tapIO_idcodeChain_clock),
+ .reset(tapIO_idcodeChain_reset),
+ .io_chainIn_shift(tapIO_idcodeChain_io_chainIn_shift),
+ .io_chainIn_data(tapIO_idcodeChain_io_chainIn_data),
+ .io_chainIn_capture(tapIO_idcodeChain_io_chainIn_capture),
+ .io_chainIn_update(tapIO_idcodeChain_io_chainIn_update),
+ .io_chainOut_data(tapIO_idcodeChain_io_chainOut_data)
+ );
+ JtagTapController tapIO_controllerInternal ( // @[JtagTap.scala 199:36]
+ .clock(tapIO_controllerInternal_clock),
+ .reset(tapIO_controllerInternal_reset),
+ .io_jtag_TMS(tapIO_controllerInternal_io_jtag_TMS),
+ .io_jtag_TDI(tapIO_controllerInternal_io_jtag_TDI),
+ .io_jtag_TDO_data(tapIO_controllerInternal_io_jtag_TDO_data),
+ .io_control_jtag_reset(tapIO_controllerInternal_io_control_jtag_reset),
+ .io_output_instruction(tapIO_controllerInternal_io_output_instruction),
+ .io_output_tapIsInTestLogicReset(tapIO_controllerInternal_io_output_tapIsInTestLogicReset),
+ .io_dataChainOut_shift(tapIO_controllerInternal_io_dataChainOut_shift),
+ .io_dataChainOut_data(tapIO_controllerInternal_io_dataChainOut_data),
+ .io_dataChainOut_capture(tapIO_controllerInternal_io_dataChainOut_capture),
+ .io_dataChainOut_update(tapIO_controllerInternal_io_dataChainOut_update),
+ .io_dataChainIn_data(tapIO_controllerInternal_io_dataChainIn_data)
+ );
+ JtagBypassChain tapIO_bypassChain ( // @[JtagTap.scala 207:29]
+ .clock(tapIO_bypassChain_clock),
+ .reset(tapIO_bypassChain_reset),
+ .io_chainIn_shift(tapIO_bypassChain_io_chainIn_shift),
+ .io_chainIn_data(tapIO_bypassChain_io_chainIn_data),
+ .io_chainIn_capture(tapIO_bypassChain_io_chainIn_capture),
+ .io_chainIn_update(tapIO_bypassChain_io_chainIn_update),
+ .io_chainOut_data(tapIO_bypassChain_io_chainOut_data)
+ );
+ assign io_dmi_req_valid = dmiReqValidReg; // @[DebugTransport.scala 241:20]
+ assign io_dmi_req_bits_addr = dmiReqReg_addr; // @[DebugTransport.scala 244:19]
+ assign io_dmi_req_bits_data = dmiReqReg_data; // @[DebugTransport.scala 244:19]
+ assign io_dmi_req_bits_op = dmiReqReg_op; // @[DebugTransport.scala 244:19]
+ assign io_dmi_resp_ready = _io_dmi_resp_ready_T ? io_dmi_resp_valid : _io_dmi_resp_ready_T_2; // @[DebugTransport.scala 224:27]
+ assign io_jtag_TDO_data = tapIO_controllerInternal_io_jtag_TDO_data; // @[JtagTap.scala 174:26 254:21]
+ assign dtmInfoChain_clock = io_jtag_clock;
+ assign dtmInfoChain_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
+ assign dtmInfoChain_io_chainIn_shift = tapIO_icodeSelects_0_1 & tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign dtmInfoChain_io_chainIn_data = tapIO_icodeSelects_0_1 & tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign dtmInfoChain_io_chainIn_capture = tapIO_icodeSelects_0_1 & tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign dtmInfoChain_io_chainIn_update = tapIO_icodeSelects_0_1 & tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign dtmInfoChain_io_capture_bits_dmiStatus = {stickyNonzeroRespReg,_dmiStatus_T}; // @[Cat.scala 31:58]
+ assign dmiAccessChain_clock = io_jtag_clock;
+ assign dmiAccessChain_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
+ assign dmiAccessChain_io_chainIn_shift = tapIO_icodeSelects_0_2 & tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign dmiAccessChain_io_chainIn_data = tapIO_icodeSelects_0_2 & tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign dmiAccessChain_io_chainIn_capture = tapIO_icodeSelects_0_2 & tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign dmiAccessChain_io_chainIn_update = tapIO_icodeSelects_0_2 & tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign dmiAccessChain_io_capture_bits_addr = busy ? 7'h0 : _dmiAccessChain_io_capture_bits_T_addr; // @[DebugTransport.scala 197:40]
+ assign dmiAccessChain_io_capture_bits_data = busy ? 32'h0 : _dmiAccessChain_io_capture_bits_T_data; // @[DebugTransport.scala 197:40]
+ assign dmiAccessChain_io_capture_bits_resp = busy ? 2'h3 : _dmiAccessChain_io_capture_bits_T_resp; // @[DebugTransport.scala 197:40]
+ assign tapIO_idcodeChain_clock = io_jtag_clock;
+ assign tapIO_idcodeChain_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
+ assign tapIO_idcodeChain_io_chainIn_shift = tapIO_icodeSelects_0 & tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign tapIO_idcodeChain_io_chainIn_data = tapIO_icodeSelects_0 & tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign tapIO_idcodeChain_io_chainIn_capture = tapIO_icodeSelects_0 & tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign tapIO_idcodeChain_io_chainIn_update = tapIO_icodeSelects_0 & tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 245:21 246:26 248:26]
+ assign tapIO_controllerInternal_clock = io_jtag_clock;
+ assign tapIO_controllerInternal_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
+ assign tapIO_controllerInternal_io_jtag_TMS = io_jtag_TMS; // @[JtagTap.scala 174:26 DebugTransport.scala 262:14]
+ assign tapIO_controllerInternal_io_jtag_TDI = io_jtag_TDI; // @[JtagTap.scala 174:26 DebugTransport.scala 262:14]
+ assign tapIO_controllerInternal_io_control_jtag_reset = io_jtag_reset; // @[DebugTransport.scala 264:45]
+ assign tapIO_controllerInternal_io_dataChainIn_data = tapIO_icodeSelects_0 ? tapIO_idcodeChain_io_chainOut_data :
+ _GEN_32; // @[JtagTap.scala 233:28 234:43]
+ assign tapIO_bypassChain_clock = io_jtag_clock;
+ assign tapIO_bypassChain_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
+ assign tapIO_bypassChain_io_chainIn_shift = tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 210:28]
+ assign tapIO_bypassChain_io_chainIn_data = tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 210:28]
+ assign tapIO_bypassChain_io_chainIn_capture = tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 210:28]
+ assign tapIO_bypassChain_io_chainIn_update = tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 210:28]
+ always @(posedge io_jtag_clock) begin
+ if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 205:41]
+ if (!(stickyBusyReg)) begin // @[DebugTransport.scala 206:26]
+ if (downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0) begin // @[DebugTransport.scala 208:97]
+ dmiReqReg_addr <= 7'h0; // @[DebugTransport.scala 210:22]
+ end else begin
+ dmiReqReg_addr <= dmiAccessChain_io_update_bits_addr; // @[DebugTransport.scala 214:17]
+ end
+ end
+ end
+ if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 205:41]
+ if (!(stickyBusyReg)) begin // @[DebugTransport.scala 206:26]
+ if (downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0) begin // @[DebugTransport.scala 208:97]
+ dmiReqReg_data <= 32'h0; // @[DebugTransport.scala 211:22]
+ end else begin
+ dmiReqReg_data <= dmiAccessChain_io_update_bits_data; // @[DebugTransport.scala 214:17]
+ end
+ end
+ end
+ if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 205:41]
+ if (!(stickyBusyReg)) begin // @[DebugTransport.scala 206:26]
+ if (downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0) begin // @[DebugTransport.scala 208:97]
+ dmiReqReg_op <= 2'h0; // @[DebugTransport.scala 212:22]
+ end else begin
+ dmiReqReg_op <= dmiAccessChain_io_update_bits_op; // @[DebugTransport.scala 214:17]
+ end
+ end
+ end
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(~(dmiReqValidCheck & _T_4)) & ~io_jtag_reset) begin
+ $fatal; // @[DebugTransport.scala 203:9]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (~io_jtag_reset & ~(~(dmiReqValidCheck & _T_4))) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: Conflicting updates for dmiReqValidReg, should not happen.\n at DebugTransport.scala:203 assert(!(dmiReqValidCheck && io.dmi.req.fire()), \"Conflicting updates for dmiReqValidReg, should not happen.\");\n"
+ ); // @[DebugTransport.scala 203:9]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef STOP_COND
+ if (`STOP_COND) begin
+ `endif
+ if (~(_tapIO_T == 2'h1) & _T_8) begin
+ $fatal; // @[JtagTap.scala 184:15]
+ end
+ `ifdef STOP_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ `ifndef SYNTHESIS
+ `ifdef PRINTF_COND
+ if (`PRINTF_COND) begin
+ `endif
+ if (_T_8 & ~(_tapIO_T == 2'h1)) begin
+ $fwrite(32'h80000002,
+ "Assertion failed: LSB must be set in IDCODE, see 12.1.1d\n at JtagTap.scala:184 assert(i %% 2.U === 1.U, \"LSB must be set in IDCODE, see 12.1.1d\")\n"
+ ); // @[JtagTap.scala 184:15]
+ end
+ `ifdef PRINTF_COND
+ end
+ `endif
+ `endif // SYNTHESIS
+ end
+ always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
+ if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
+ busyReg <= 1'h0; // @[DebugTransport.scala 270:13]
+ end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 146:29]
+ busyReg <= 1'h0; // @[DebugTransport.scala 147:13]
+ end else if (_T_1) begin
+ busyReg <= 1'h0;
+ end else begin
+ busyReg <= _GEN_0;
+ end
+ end
+ always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
+ if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
+ stickyBusyReg <= 1'h0; // @[DebugTransport.scala 271:19]
+ end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 168:39]
+ stickyBusyReg <= 1'h0; // @[DebugTransport.scala 169:49 171:21]
+ end else if (dtmInfoChain_io_update_valid) begin
+ if (dtmInfoChain_io_update_bits_dmireset) begin
+ stickyBusyReg <= 1'h0;
+ end else begin
+ stickyBusyReg <= _GEN_4;
+ end
+ end else begin
+ stickyBusyReg <= _GEN_4;
+ end
+ end
+ always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
+ if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
+ stickyNonzeroRespReg <= 1'h0; // @[DebugTransport.scala 272:26]
+ end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 168:39]
+ stickyNonzeroRespReg <= 1'h0; // @[DebugTransport.scala 169:49 170:28]
+ end else if (dtmInfoChain_io_update_valid) begin
+ if (dtmInfoChain_io_update_bits_dmireset) begin
+ stickyNonzeroRespReg <= 1'h0;
+ end else begin
+ stickyNonzeroRespReg <= _GEN_5;
+ end
+ end else begin
+ stickyNonzeroRespReg <= _GEN_5;
+ end
+ end
+ always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
+ if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
+ downgradeOpReg <= 1'h0; // @[DebugTransport.scala 273:20]
+ end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 163:44]
+ downgradeOpReg <= 1'h0; // @[DebugTransport.scala 164:20]
+ end else if (dmiAccessChain_io_capture_capture) begin // @[DebugTransport.scala 160:41]
+ downgradeOpReg <= ~busy & nonzeroResp; // @[DebugTransport.scala 161:20]
+ end else if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 100:31]
+ downgradeOpReg <= 1'h0;
+ end
+ end
+ always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
+ if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
+ dmiReqValidReg <= 1'h0; // @[DebugTransport.scala 274:20]
+ end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 220:28]
+ dmiReqValidReg <= 1'h0; // @[DebugTransport.scala 221:20]
+ end else if (_T_4) begin // @[DebugTransport.scala 205:41]
+ dmiReqValidReg <= 1'h0; // @[DebugTransport.scala 206:26 111:31]
+ end else if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 111:31]
+ if (!(stickyBusyReg)) begin
+ dmiReqValidReg <= _GEN_13;
+ end
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ busyReg = _RAND_0[0:0];
+ _RAND_1 = {1{`RANDOM}};
+ stickyBusyReg = _RAND_1[0:0];
+ _RAND_2 = {1{`RANDOM}};
+ stickyNonzeroRespReg = _RAND_2[0:0];
+ _RAND_3 = {1{`RANDOM}};
+ downgradeOpReg = _RAND_3[0:0];
+ _RAND_4 = {1{`RANDOM}};
+ dmiReqReg_addr = _RAND_4[6:0];
+ _RAND_5 = {1{`RANDOM}};
+ dmiReqReg_data = _RAND_5[31:0];
+ _RAND_6 = {1{`RANDOM}};
+ dmiReqReg_op = _RAND_6[1:0];
+ _RAND_7 = {1{`RANDOM}};
+ dmiReqValidReg = _RAND_7[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (io_jtag_reset) begin
+ busyReg = 1'h0;
+ end
+ if (io_jtag_reset) begin
+ stickyBusyReg = 1'h0;
+ end
+ if (io_jtag_reset) begin
+ stickyNonzeroRespReg = 1'h0;
+ end
+ if (io_jtag_reset) begin
+ downgradeOpReg = 1'h0;
+ end
+ if (io_jtag_reset) begin
+ dmiReqValidReg = 1'h0;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module DigitalTop(
+ input clock,
+ input reset,
+ output auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_clock,
+ output auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_reset,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock,
+ input auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset,
+ output auto_subsystem_cbus_fixedClockNode_out_clock,
+ output auto_subsystem_cbus_fixedClockNode_out_reset,
+ input custom_boot,
+ output serial_tl_clock,
+ output serial_tl_bits_in_ready,
+ input serial_tl_bits_in_valid,
+ input [31:0] serial_tl_bits_in_bits,
+ input serial_tl_bits_out_ready,
+ output serial_tl_bits_out_valid,
+ output [31:0] serial_tl_bits_out_bits,
+ input resetctrl_hartIsInReset_0,
+ input debug_clock,
+ input debug_reset,
+ input debug_systemjtag_jtag_TCK,
+ input debug_systemjtag_jtag_TMS,
+ input debug_systemjtag_jtag_TDI,
+ output debug_systemjtag_jtag_TDO_data,
+ input debug_systemjtag_reset,
+ output debug_dmactive,
+ input debug_dmactiveAck,
+ output uart_0_txd,
+ input uart_0_rxd,
+ output uart_1_txd,
+ input uart_1_rxd,
+ input gpio_0_pins_0_i_ival,
+ output gpio_0_pins_0_o_oval,
+ output gpio_0_pins_0_o_oe,
+ output gpio_0_pins_0_o_ie,
+ input gpio_0_pins_1_i_ival,
+ output gpio_0_pins_1_o_oval,
+ output gpio_0_pins_1_o_oe,
+ output gpio_0_pins_1_o_ie,
+ input gpio_0_pins_2_i_ival,
+ output gpio_0_pins_2_o_oval,
+ output gpio_0_pins_2_o_oe,
+ output gpio_0_pins_2_o_ie,
+ input gpio_0_pins_3_i_ival,
+ output gpio_0_pins_3_o_oval,
+ output gpio_0_pins_3_o_oe,
+ output gpio_0_pins_3_o_ie,
+ output qspi_0_sck,
+ input qspi_0_dq_0_i,
+ output qspi_0_dq_0_o,
+ output qspi_0_dq_0_oe,
+ input qspi_0_dq_1_i,
+ output qspi_0_dq_1_o,
+ output qspi_0_dq_1_oe,
+ input qspi_0_dq_2_i,
+ output qspi_0_dq_2_o,
+ output qspi_0_dq_2_oe,
+ input qspi_0_dq_3_i,
+ output qspi_0_dq_3_o,
+ output qspi_0_dq_3_oe,
+ output qspi_0_cs_0,
+ output qspi_1_sck,
+ input qspi_1_dq_0_i,
+ output qspi_1_dq_0_o,
+ output qspi_1_dq_0_oe,
+ input qspi_1_dq_1_i,
+ output qspi_1_dq_1_o,
+ output qspi_1_dq_1_oe,
+ input qspi_1_dq_2_i,
+ output qspi_1_dq_2_o,
+ output qspi_1_dq_2_oe,
+ input qspi_1_dq_3_i,
+ output qspi_1_dq_3_o,
+ output qspi_1_dq_3_oe,
+ output qspi_1_cs_0
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ wire ibus_auto_int_bus_int_in_4_0; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_in_3_0; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_in_2_0; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_in_2_1; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_in_2_2; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_in_2_3; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_in_1_0; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_in_0_0; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_out_0; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_out_1; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_out_2; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_out_3; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_out_4; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_out_5; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_out_6; // @[BaseSubsystem.scala 50:24]
+ wire ibus_auto_int_bus_int_out_7; // @[BaseSubsystem.scala 50:24]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_valid; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param; // @[SystemBus.scala 24:26]
+ wire [3:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source; // @[SystemBus.scala 24:26]
+ wire [31:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address; // @[SystemBus.scala 24:26]
+ wire [7:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask; // @[SystemBus.scala 24:26]
+ wire [63:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_ready; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala 24:26]
+ wire [1:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala 24:26]
+ wire [3:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala 24:26]
+ wire [63:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_valid; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_opcode; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_param; // @[SystemBus.scala 24:26]
+ wire [3:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_size; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_source; // @[SystemBus.scala 24:26]
+ wire [31:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_address; // @[SystemBus.scala 24:26]
+ wire [7:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_mask; // @[SystemBus.scala 24:26]
+ wire [63:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_data; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_corrupt; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_ready; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala 24:26]
+ wire [1:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala 24:26]
+ wire [3:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala 24:26]
+ wire [63:0] subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala 24:26]
+ wire [3:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala 24:26]
+ wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala 24:26]
+ wire [31:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala 24:26]
+ wire [7:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala 24:26]
+ wire [63:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid; // @[SystemBus.scala 24:26]
+ wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode; // @[SystemBus.scala 24:26]
+ wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param; // @[SystemBus.scala 24:26]
+ wire [3:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size; // @[SystemBus.scala 24:26]
+ wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied; // @[SystemBus.scala 24:26]
+ wire [63:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_fixedClockNode_out_1_clock; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_fixedClockNode_out_1_reset; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock; // @[SystemBus.scala 24:26]
+ wire subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset; // @[SystemBus.scala 24:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [9:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [29:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [9:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [28:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [9:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [29:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [9:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [28:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [28:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [28:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [28:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [28:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_sink; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_denied; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_4_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_4_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_3_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_3_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_2_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_2_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_1_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_1_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_0_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_fixedClockNode_out_0_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_bus_xing_in_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_bus_xing_in_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_bus_xing_in_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_bus_xing_in_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_bus_xing_in_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [29:0] subsystem_pbus_auto_bus_xing_in_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_pbus_auto_bus_xing_in_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_bus_xing_in_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_bus_xing_in_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_bus_xing_in_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_pbus_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_valid; // @[FrontBus.scala 22:26]
+ wire [2:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_opcode; // @[FrontBus.scala 22:26]
+ wire [2:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_param; // @[FrontBus.scala 22:26]
+ wire [3:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_size; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_source; // @[FrontBus.scala 22:26]
+ wire [31:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_address; // @[FrontBus.scala 22:26]
+ wire [7:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_mask; // @[FrontBus.scala 22:26]
+ wire [63:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_data; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_corrupt; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_ready; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid; // @[FrontBus.scala 22:26]
+ wire [2:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode; // @[FrontBus.scala 22:26]
+ wire [1:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param; // @[FrontBus.scala 22:26]
+ wire [3:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied; // @[FrontBus.scala 22:26]
+ wire [63:0] subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_fixedClockNode_out_clock; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_fixedClockNode_out_reset; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_a_ready; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala 22:26]
+ wire [2:0] subsystem_fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala 22:26]
+ wire [2:0] subsystem_fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala 22:26]
+ wire [3:0] subsystem_fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala 22:26]
+ wire [31:0] subsystem_fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala 22:26]
+ wire [7:0] subsystem_fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala 22:26]
+ wire [63:0] subsystem_fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_d_valid; // @[FrontBus.scala 22:26]
+ wire [2:0] subsystem_fbus_auto_bus_xing_out_d_bits_opcode; // @[FrontBus.scala 22:26]
+ wire [1:0] subsystem_fbus_auto_bus_xing_out_d_bits_param; // @[FrontBus.scala 22:26]
+ wire [3:0] subsystem_fbus_auto_bus_xing_out_d_bits_size; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_d_bits_sink; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_d_bits_denied; // @[FrontBus.scala 22:26]
+ wire [63:0] subsystem_fbus_auto_bus_xing_out_d_bits_data; // @[FrontBus.scala 22:26]
+ wire subsystem_fbus_auto_bus_xing_out_d_bits_corrupt; // @[FrontBus.scala 22:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [20:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [20:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [16:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [31:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [11:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [25:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [27:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [6:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [29:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_fixedClockNode_out_4_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_fixedClockNode_out_4_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_fixedClockNode_out_3_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_fixedClockNode_out_3_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_fixedClockNode_out_2_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_fixedClockNode_out_2_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_fixedClockNode_out_0_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_fixedClockNode_out_0_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_bus_xing_in_a_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_bus_xing_in_a_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_bus_xing_in_a_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [3:0] subsystem_cbus_auto_bus_xing_in_a_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_bus_xing_in_a_bits_source; // @[PeripheryBus.scala 31:26]
+ wire [31:0] subsystem_cbus_auto_bus_xing_in_a_bits_address; // @[PeripheryBus.scala 31:26]
+ wire [7:0] subsystem_cbus_auto_bus_xing_in_a_bits_mask; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_bus_xing_in_a_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_bus_xing_in_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_bus_xing_in_d_ready; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala 31:26]
+ wire [2:0] subsystem_cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala 31:26]
+ wire [3:0] subsystem_cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala 31:26]
+ wire [1:0] subsystem_cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala 31:26]
+ wire [63:0] subsystem_cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_custom_boot; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_clock; // @[PeripheryBus.scala 31:26]
+ wire subsystem_cbus_reset; // @[PeripheryBus.scala 31:26]
+ wire tile_prci_domain_auto_intsink_in_sync_0; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tile_reset_domain_tile_hartid_in; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_int_in_clock_xing_in_1_sync_0; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_int_in_clock_xing_in_0_sync_0; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_int_in_clock_xing_in_0_sync_1; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_slave_clock_xing_in_a_valid; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_opcode; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_param; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_size; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_source; // @[HasTiles.scala 252:38]
+ wire [31:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_address; // @[HasTiles.scala 252:38]
+ wire [7:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_mask; // @[HasTiles.scala 252:38]
+ wire [63:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_data; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_slave_clock_xing_in_d_ready; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode; // @[HasTiles.scala 252:38]
+ wire [1:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied; // @[HasTiles.scala 252:38]
+ wire [63:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_a_ready; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala 252:38]
+ wire [3:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala 252:38]
+ wire [31:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala 252:38]
+ wire [7:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala 252:38]
+ wire [63:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_d_valid; // @[HasTiles.scala 252:38]
+ wire [2:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_opcode; // @[HasTiles.scala 252:38]
+ wire [1:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_param; // @[HasTiles.scala 252:38]
+ wire [3:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_size; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_source; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_sink; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_denied; // @[HasTiles.scala 252:38]
+ wire [63:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_data; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_corrupt; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tap_clock_in_clock; // @[HasTiles.scala 252:38]
+ wire tile_prci_domain_auto_tap_clock_in_reset; // @[HasTiles.scala 252:38]
+ wire plicDomainWrapper_auto_plic_int_in_0; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_int_in_1; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_int_in_2; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_int_in_3; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_int_in_4; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_int_in_5; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_int_in_6; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_int_in_7; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_int_out_0; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_in_a_ready; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_in_a_valid; // @[Plic.scala 359:39]
+ wire [2:0] plicDomainWrapper_auto_plic_in_a_bits_opcode; // @[Plic.scala 359:39]
+ wire [2:0] plicDomainWrapper_auto_plic_in_a_bits_param; // @[Plic.scala 359:39]
+ wire [1:0] plicDomainWrapper_auto_plic_in_a_bits_size; // @[Plic.scala 359:39]
+ wire [6:0] plicDomainWrapper_auto_plic_in_a_bits_source; // @[Plic.scala 359:39]
+ wire [27:0] plicDomainWrapper_auto_plic_in_a_bits_address; // @[Plic.scala 359:39]
+ wire [7:0] plicDomainWrapper_auto_plic_in_a_bits_mask; // @[Plic.scala 359:39]
+ wire [63:0] plicDomainWrapper_auto_plic_in_a_bits_data; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_in_a_bits_corrupt; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_in_d_ready; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_plic_in_d_valid; // @[Plic.scala 359:39]
+ wire [2:0] plicDomainWrapper_auto_plic_in_d_bits_opcode; // @[Plic.scala 359:39]
+ wire [1:0] plicDomainWrapper_auto_plic_in_d_bits_size; // @[Plic.scala 359:39]
+ wire [6:0] plicDomainWrapper_auto_plic_in_d_bits_source; // @[Plic.scala 359:39]
+ wire [63:0] plicDomainWrapper_auto_plic_in_d_bits_data; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_clock_in_clock; // @[Plic.scala 359:39]
+ wire plicDomainWrapper_auto_clock_in_reset; // @[Plic.scala 359:39]
+ wire clint_clock; // @[CLINT.scala 109:27]
+ wire clint_reset; // @[CLINT.scala 109:27]
+ wire clint_auto_int_out_0; // @[CLINT.scala 109:27]
+ wire clint_auto_int_out_1; // @[CLINT.scala 109:27]
+ wire clint_auto_in_a_ready; // @[CLINT.scala 109:27]
+ wire clint_auto_in_a_valid; // @[CLINT.scala 109:27]
+ wire [2:0] clint_auto_in_a_bits_opcode; // @[CLINT.scala 109:27]
+ wire [2:0] clint_auto_in_a_bits_param; // @[CLINT.scala 109:27]
+ wire [1:0] clint_auto_in_a_bits_size; // @[CLINT.scala 109:27]
+ wire [6:0] clint_auto_in_a_bits_source; // @[CLINT.scala 109:27]
+ wire [25:0] clint_auto_in_a_bits_address; // @[CLINT.scala 109:27]
+ wire [7:0] clint_auto_in_a_bits_mask; // @[CLINT.scala 109:27]
+ wire [63:0] clint_auto_in_a_bits_data; // @[CLINT.scala 109:27]
+ wire clint_auto_in_a_bits_corrupt; // @[CLINT.scala 109:27]
+ wire clint_auto_in_d_ready; // @[CLINT.scala 109:27]
+ wire clint_auto_in_d_valid; // @[CLINT.scala 109:27]
+ wire [2:0] clint_auto_in_d_bits_opcode; // @[CLINT.scala 109:27]
+ wire [1:0] clint_auto_in_d_bits_size; // @[CLINT.scala 109:27]
+ wire [6:0] clint_auto_in_d_bits_source; // @[CLINT.scala 109:27]
+ wire [63:0] clint_auto_in_d_bits_data; // @[CLINT.scala 109:27]
+ wire clint_io_rtcTick; // @[CLINT.scala 109:27]
+ wire debug_1_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala 84:27]
+ wire debug_1_auto_dmInner_dmInner_tl_in_a_valid; // @[Periphery.scala 84:27]
+ wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode; // @[Periphery.scala 84:27]
+ wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_param; // @[Periphery.scala 84:27]
+ wire [1:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_size; // @[Periphery.scala 84:27]
+ wire [6:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_source; // @[Periphery.scala 84:27]
+ wire [11:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_address; // @[Periphery.scala 84:27]
+ wire [7:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask; // @[Periphery.scala 84:27]
+ wire [63:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_data; // @[Periphery.scala 84:27]
+ wire debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt; // @[Periphery.scala 84:27]
+ wire debug_1_auto_dmInner_dmInner_tl_in_d_ready; // @[Periphery.scala 84:27]
+ wire debug_1_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala 84:27]
+ wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala 84:27]
+ wire [1:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala 84:27]
+ wire [6:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala 84:27]
+ wire [63:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala 84:27]
+ wire debug_1_auto_dmOuter_intsource_out_sync_0; // @[Periphery.scala 84:27]
+ wire debug_1_io_debug_clock; // @[Periphery.scala 84:27]
+ wire debug_1_io_debug_reset; // @[Periphery.scala 84:27]
+ wire debug_1_io_ctrl_dmactive; // @[Periphery.scala 84:27]
+ wire debug_1_io_ctrl_dmactiveAck; // @[Periphery.scala 84:27]
+ wire debug_1_io_dmi_dmi_req_ready; // @[Periphery.scala 84:27]
+ wire debug_1_io_dmi_dmi_req_valid; // @[Periphery.scala 84:27]
+ wire [6:0] debug_1_io_dmi_dmi_req_bits_addr; // @[Periphery.scala 84:27]
+ wire [31:0] debug_1_io_dmi_dmi_req_bits_data; // @[Periphery.scala 84:27]
+ wire [1:0] debug_1_io_dmi_dmi_req_bits_op; // @[Periphery.scala 84:27]
+ wire debug_1_io_dmi_dmi_resp_ready; // @[Periphery.scala 84:27]
+ wire debug_1_io_dmi_dmi_resp_valid; // @[Periphery.scala 84:27]
+ wire [31:0] debug_1_io_dmi_dmi_resp_bits_data; // @[Periphery.scala 84:27]
+ wire [1:0] debug_1_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala 84:27]
+ wire debug_1_io_dmi_dmiClock; // @[Periphery.scala 84:27]
+ wire debug_1_io_dmi_dmiReset; // @[Periphery.scala 84:27]
+ wire debug_1_io_hartIsInReset_0; // @[Periphery.scala 84:27]
+ wire tileHartIdNexusNode_auto_out; // @[HasTiles.scala 159:39]
+ wire intsource_clock; // @[Crossing.scala 26:31]
+ wire intsource_reset; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_in_1; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire intsource_auto_out_sync_1; // @[Crossing.scala 26:31]
+ wire intsource_1_clock; // @[Crossing.scala 26:31]
+ wire intsource_1_reset; // @[Crossing.scala 26:31]
+ wire intsource_1_auto_in_0; // @[Crossing.scala 26:31]
+ wire intsource_1_auto_out_sync_0; // @[Crossing.scala 26:31]
+ wire intsink_1_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_1_auto_out_0; // @[Crossing.scala 94:29]
+ wire intsink_2_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_2_auto_out_0; // @[Crossing.scala 94:29]
+ wire intsink_3_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_3_auto_out_0; // @[Crossing.scala 94:29]
+ wire bootROMDomainWrapper_auto_bootrom_in_a_ready; // @[BootROM.scala 70:42]
+ wire bootROMDomainWrapper_auto_bootrom_in_a_valid; // @[BootROM.scala 70:42]
+ wire [2:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_opcode; // @[BootROM.scala 70:42]
+ wire [2:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_param; // @[BootROM.scala 70:42]
+ wire [1:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_size; // @[BootROM.scala 70:42]
+ wire [6:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_source; // @[BootROM.scala 70:42]
+ wire [16:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_address; // @[BootROM.scala 70:42]
+ wire [7:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_mask; // @[BootROM.scala 70:42]
+ wire bootROMDomainWrapper_auto_bootrom_in_a_bits_corrupt; // @[BootROM.scala 70:42]
+ wire bootROMDomainWrapper_auto_bootrom_in_d_ready; // @[BootROM.scala 70:42]
+ wire bootROMDomainWrapper_auto_bootrom_in_d_valid; // @[BootROM.scala 70:42]
+ wire [1:0] bootROMDomainWrapper_auto_bootrom_in_d_bits_size; // @[BootROM.scala 70:42]
+ wire [6:0] bootROMDomainWrapper_auto_bootrom_in_d_bits_source; // @[BootROM.scala 70:42]
+ wire [63:0] bootROMDomainWrapper_auto_bootrom_in_d_bits_data; // @[BootROM.scala 70:42]
+ wire bootROMDomainWrapper_auto_clock_in_clock; // @[BootROM.scala 70:42]
+ wire bootROMDomainWrapper_auto_clock_in_reset; // @[BootROM.scala 70:42]
+ wire domain_auto_serdesser_client_out_a_ready; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_a_valid; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_serdesser_client_out_a_bits_opcode; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_serdesser_client_out_a_bits_param; // @[SerialAdapter.scala 373:28]
+ wire [3:0] domain_auto_serdesser_client_out_a_bits_size; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_a_bits_source; // @[SerialAdapter.scala 373:28]
+ wire [31:0] domain_auto_serdesser_client_out_a_bits_address; // @[SerialAdapter.scala 373:28]
+ wire [7:0] domain_auto_serdesser_client_out_a_bits_mask; // @[SerialAdapter.scala 373:28]
+ wire [63:0] domain_auto_serdesser_client_out_a_bits_data; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_a_bits_corrupt; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_d_ready; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_d_valid; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_serdesser_client_out_d_bits_opcode; // @[SerialAdapter.scala 373:28]
+ wire [1:0] domain_auto_serdesser_client_out_d_bits_param; // @[SerialAdapter.scala 373:28]
+ wire [3:0] domain_auto_serdesser_client_out_d_bits_size; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_d_bits_source; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_d_bits_sink; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_d_bits_denied; // @[SerialAdapter.scala 373:28]
+ wire [63:0] domain_auto_serdesser_client_out_d_bits_data; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_serdesser_client_out_d_bits_corrupt; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_tlserial_manager_crossing_in_a_ready; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_tlserial_manager_crossing_in_a_valid; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_tlserial_manager_crossing_in_a_bits_opcode; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_tlserial_manager_crossing_in_a_bits_param; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_tlserial_manager_crossing_in_a_bits_size; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_tlserial_manager_crossing_in_a_bits_source; // @[SerialAdapter.scala 373:28]
+ wire [28:0] domain_auto_tlserial_manager_crossing_in_a_bits_address; // @[SerialAdapter.scala 373:28]
+ wire [7:0] domain_auto_tlserial_manager_crossing_in_a_bits_mask; // @[SerialAdapter.scala 373:28]
+ wire [63:0] domain_auto_tlserial_manager_crossing_in_a_bits_data; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_tlserial_manager_crossing_in_a_bits_corrupt; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_tlserial_manager_crossing_in_d_ready; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_tlserial_manager_crossing_in_d_valid; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_tlserial_manager_crossing_in_d_bits_opcode; // @[SerialAdapter.scala 373:28]
+ wire [1:0] domain_auto_tlserial_manager_crossing_in_d_bits_param; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_tlserial_manager_crossing_in_d_bits_size; // @[SerialAdapter.scala 373:28]
+ wire [2:0] domain_auto_tlserial_manager_crossing_in_d_bits_source; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_tlserial_manager_crossing_in_d_bits_sink; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_tlserial_manager_crossing_in_d_bits_denied; // @[SerialAdapter.scala 373:28]
+ wire [63:0] domain_auto_tlserial_manager_crossing_in_d_bits_data; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_tlserial_manager_crossing_in_d_bits_corrupt; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_clock_in_clock; // @[SerialAdapter.scala 373:28]
+ wire domain_auto_clock_in_reset; // @[SerialAdapter.scala 373:28]
+ wire domain_serial_tl_in_ready; // @[SerialAdapter.scala 373:28]
+ wire domain_serial_tl_in_valid; // @[SerialAdapter.scala 373:28]
+ wire [31:0] domain_serial_tl_in_bits; // @[SerialAdapter.scala 373:28]
+ wire domain_serial_tl_out_ready; // @[SerialAdapter.scala 373:28]
+ wire domain_serial_tl_out_valid; // @[SerialAdapter.scala 373:28]
+ wire [31:0] domain_serial_tl_out_bits; // @[SerialAdapter.scala 373:28]
+ wire domain_clock; // @[SerialAdapter.scala 373:28]
+ wire uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_uart_0_control_xing_in_a_valid; // @[UART.scala 242:44]
+ wire [2:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_opcode; // @[UART.scala 242:44]
+ wire [2:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_param; // @[UART.scala 242:44]
+ wire [1:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_size; // @[UART.scala 242:44]
+ wire [6:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_source; // @[UART.scala 242:44]
+ wire [28:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_address; // @[UART.scala 242:44]
+ wire [7:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_mask; // @[UART.scala 242:44]
+ wire [63:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_data; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_corrupt; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_uart_0_control_xing_in_d_ready; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala 242:44]
+ wire [2:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala 242:44]
+ wire [1:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala 242:44]
+ wire [6:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala 242:44]
+ wire [63:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_uart_0_io_out_txd; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_uart_0_io_out_rxd; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_clock_in_clock; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_auto_clock_in_reset; // @[UART.scala 242:44]
+ wire intsink_4_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_4_auto_out_0; // @[Crossing.scala 94:29]
+ wire uartClockDomainWrapper_1_auto_uart_1_int_xing_out_sync_0; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_ready; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_valid; // @[UART.scala 242:44]
+ wire [2:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_opcode; // @[UART.scala 242:44]
+ wire [2:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_param; // @[UART.scala 242:44]
+ wire [1:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_size; // @[UART.scala 242:44]
+ wire [6:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_source; // @[UART.scala 242:44]
+ wire [28:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_address; // @[UART.scala 242:44]
+ wire [7:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_mask; // @[UART.scala 242:44]
+ wire [63:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_data; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_corrupt; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_ready; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_valid; // @[UART.scala 242:44]
+ wire [2:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_opcode; // @[UART.scala 242:44]
+ wire [1:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_size; // @[UART.scala 242:44]
+ wire [6:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_source; // @[UART.scala 242:44]
+ wire [63:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_data; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_uart_1_io_out_txd; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_uart_1_io_out_rxd; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_clock_in_clock; // @[UART.scala 242:44]
+ wire uartClockDomainWrapper_1_auto_clock_in_reset; // @[UART.scala 242:44]
+ wire intsink_5_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_5_auto_out_0; // @[Crossing.scala 94:29]
+ wire gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_0; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_1; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_2; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_3; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_ready; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_valid; // @[GPIO.scala 281:44]
+ wire [2:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_opcode; // @[GPIO.scala 281:44]
+ wire [2:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_param; // @[GPIO.scala 281:44]
+ wire [1:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_size; // @[GPIO.scala 281:44]
+ wire [6:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_source; // @[GPIO.scala 281:44]
+ wire [28:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_address; // @[GPIO.scala 281:44]
+ wire [7:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_mask; // @[GPIO.scala 281:44]
+ wire [63:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_data; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_corrupt; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_ready; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_valid; // @[GPIO.scala 281:44]
+ wire [2:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_opcode; // @[GPIO.scala 281:44]
+ wire [1:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_size; // @[GPIO.scala 281:44]
+ wire [6:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_source; // @[GPIO.scala 281:44]
+ wire [63:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_data; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_i_ival; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oval; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oe; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_ie; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_i_ival; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oval; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oe; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_ie; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_i_ival; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oval; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oe; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_ie; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_i_ival; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oval; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oe; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_ie; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_clock_in_clock; // @[GPIO.scala 281:44]
+ wire gpioClockDomainWrapper_auto_clock_in_reset; // @[GPIO.scala 281:44]
+ wire intsink_6_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_6_auto_in_sync_1; // @[Crossing.scala 94:29]
+ wire intsink_6_auto_in_sync_2; // @[Crossing.scala 94:29]
+ wire intsink_6_auto_in_sync_3; // @[Crossing.scala 94:29]
+ wire intsink_6_auto_out_0; // @[Crossing.scala 94:29]
+ wire intsink_6_auto_out_1; // @[Crossing.scala 94:29]
+ wire intsink_6_auto_out_2; // @[Crossing.scala 94:29]
+ wire intsink_6_auto_out_3; // @[Crossing.scala 94:29]
+ wire qspiClockDomainWrapper_auto_qspi_0_int_xing_out_sync_0; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_ready; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_valid; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_opcode; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_param; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_size; // @[SPI.scala 92:44]
+ wire [9:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_source; // @[SPI.scala 92:44]
+ wire [29:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_address; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_mask; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_corrupt; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_ready; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_valid; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_size; // @[SPI.scala 92:44]
+ wire [9:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_source; // @[SPI.scala 92:44]
+ wire [7:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_data; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_ready; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_valid; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_opcode; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_param; // @[SPI.scala 92:44]
+ wire [1:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_size; // @[SPI.scala 92:44]
+ wire [6:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_source; // @[SPI.scala 92:44]
+ wire [28:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_address; // @[SPI.scala 92:44]
+ wire [7:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_mask; // @[SPI.scala 92:44]
+ wire [63:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_data; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_corrupt; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_ready; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_valid; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_opcode; // @[SPI.scala 92:44]
+ wire [1:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_size; // @[SPI.scala 92:44]
+ wire [6:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_source; // @[SPI.scala 92:44]
+ wire [63:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_data; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_sck; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_i; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_o; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_oe; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_i; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_o; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_oe; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_i; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_o; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_oe; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_i; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_o; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_oe; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_qspi_0_io_out_cs_0; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_clock_in_clock; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_auto_clock_in_reset; // @[SPI.scala 92:44]
+ wire intsink_7_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_7_auto_out_0; // @[Crossing.scala 94:29]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_int_xing_out_sync_0; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_ready; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_valid; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_opcode; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_param; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_size; // @[SPI.scala 92:44]
+ wire [9:0] qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_source; // @[SPI.scala 92:44]
+ wire [29:0] qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_address; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_mask; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_corrupt; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_ready; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_valid; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_size; // @[SPI.scala 92:44]
+ wire [9:0] qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_source; // @[SPI.scala 92:44]
+ wire [7:0] qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_data; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_ready; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_valid; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_opcode; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_param; // @[SPI.scala 92:44]
+ wire [1:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_size; // @[SPI.scala 92:44]
+ wire [6:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_source; // @[SPI.scala 92:44]
+ wire [28:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_address; // @[SPI.scala 92:44]
+ wire [7:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_mask; // @[SPI.scala 92:44]
+ wire [63:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_data; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_corrupt; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_ready; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_valid; // @[SPI.scala 92:44]
+ wire [2:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_opcode; // @[SPI.scala 92:44]
+ wire [1:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_size; // @[SPI.scala 92:44]
+ wire [6:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_source; // @[SPI.scala 92:44]
+ wire [63:0] qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_data; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_sck; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_i; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_o; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_oe; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_i; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_o; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_oe; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_i; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_o; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_oe; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_i; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_o; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_oe; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_qspi_1_io_out_cs_0; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_clock_in_clock; // @[SPI.scala 92:44]
+ wire qspiClockDomainWrapper_1_auto_clock_in_reset; // @[SPI.scala 92:44]
+ wire intsink_8_auto_in_sync_0; // @[Crossing.scala 94:29]
+ wire intsink_8_auto_out_0; // @[Crossing.scala 94:29]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_tl_in_a_ready; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_tl_in_a_valid; // @[HasChipyardPRCI.scala 38:36]
+ wire [2:0] chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_opcode; // @[HasChipyardPRCI.scala 38:36]
+ wire [2:0] chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_param; // @[HasChipyardPRCI.scala 38:36]
+ wire [1:0] chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_size; // @[HasChipyardPRCI.scala 38:36]
+ wire [6:0] chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_source; // @[HasChipyardPRCI.scala 38:36]
+ wire [20:0] chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_address; // @[HasChipyardPRCI.scala 38:36]
+ wire [7:0] chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_mask; // @[HasChipyardPRCI.scala 38:36]
+ wire [63:0] chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_data; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_corrupt; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_tl_in_d_ready; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_tl_in_d_valid; // @[HasChipyardPRCI.scala 38:36]
+ wire [2:0] chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_opcode; // @[HasChipyardPRCI.scala 38:36]
+ wire [1:0] chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_size; // @[HasChipyardPRCI.scala 38:36]
+ wire [6:0] chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_source; // @[HasChipyardPRCI.scala 38:36]
+ wire [63:0] chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_data; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_ready; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_valid; // @[HasChipyardPRCI.scala 38:36]
+ wire [2:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_opcode; // @[HasChipyardPRCI.scala 38:36]
+ wire [2:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_param; // @[HasChipyardPRCI.scala 38:36]
+ wire [1:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_size; // @[HasChipyardPRCI.scala 38:36]
+ wire [6:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_source; // @[HasChipyardPRCI.scala 38:36]
+ wire [20:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_address; // @[HasChipyardPRCI.scala 38:36]
+ wire [7:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_mask; // @[HasChipyardPRCI.scala 38:36]
+ wire [63:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_data; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_corrupt; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_ready; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_valid; // @[HasChipyardPRCI.scala 38:36]
+ wire [2:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_opcode; // @[HasChipyardPRCI.scala 38:36]
+ wire [1:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_size; // @[HasChipyardPRCI.scala 38:36]
+ wire [6:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_source; // @[HasChipyardPRCI.scala 38:36]
+ wire [63:0] chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_data; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_clock_in_clock; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_auto_clock_in_reset; // @[HasChipyardPRCI.scala 38:36]
+ wire chipyardPRCI_1_auto_in_member_allClocks_implicit_clock_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_implicit_clock_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_subsystem_cbus_0_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_subsystem_cbus_0_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_subsystem_fbus_0_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_subsystem_fbus_0_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_subsystem_pbus_0_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_subsystem_pbus_0_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_subsystem_sbus_0_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_in_member_allClocks_subsystem_sbus_0_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_4_member_chipyardPRCI_implicit_clock_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_4_member_chipyardPRCI_implicit_clock_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_3_member_subsystem_cbus_subsystem_cbus_0_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_3_member_subsystem_cbus_subsystem_cbus_0_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_2_member_subsystem_fbus_subsystem_fbus_0_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_2_member_subsystem_fbus_subsystem_fbus_0_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_1_member_subsystem_pbus_subsystem_pbus_0_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_1_member_subsystem_pbus_subsystem_pbus_0_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_0_member_subsystem_sbus_subsystem_sbus_0_clock; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_1_auto_out_0_member_subsystem_sbus_subsystem_sbus_0_reset; // @[HasChipyardPRCI.scala 42:30]
+ wire chipyardPRCI_2_auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_clock; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_reset; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_clock; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_reset; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_clock; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_reset; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_clock; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_reset; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_out_3_member_subsystem_cbus_0_clock; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_out_3_member_subsystem_cbus_0_reset; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_out_2_member_subsystem_fbus_0_clock; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_out_2_member_subsystem_fbus_0_reset; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_out_1_member_subsystem_pbus_0_clock; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_out_1_member_subsystem_pbus_0_reset; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_out_0_member_subsystem_sbus_0_clock; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_2_auto_chipyard_prci_out_0_member_subsystem_sbus_0_reset; // @[ClockGroupNamePrefixer.scala 45:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_implicit_clock_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_implicit_clock_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset; // @[ClockGroupNamePrefixer.scala 81:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_implicit_clock_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_implicit_clock_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset; // @[ClockGroupCombiner.scala 19:15]
+ wire chipyardPRCI_5_auto_in_member_allClocks_implicit_clock_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_implicit_clock_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_subsystem_cbus_0_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_subsystem_cbus_0_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_subsystem_fbus_0_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_subsystem_fbus_0_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_subsystem_pbus_0_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_subsystem_pbus_0_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_subsystem_sbus_0_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_in_member_allClocks_subsystem_sbus_0_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_implicit_clock_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_implicit_clock_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_subsystem_cbus_0_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_subsystem_cbus_0_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_subsystem_fbus_0_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_subsystem_fbus_0_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_subsystem_pbus_0_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_subsystem_pbus_0_reset; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_subsystem_sbus_0_clock; // @[ResetSynchronizer.scala 42:69]
+ wire chipyardPRCI_5_auto_out_member_allClocks_subsystem_sbus_0_reset; // @[ResetSynchronizer.scala 42:69]
+ wire dtm_io_jtag_clock; // @[Periphery.scala 161:21]
+ wire dtm_io_jtag_reset; // @[Periphery.scala 161:21]
+ wire dtm_io_dmi_req_ready; // @[Periphery.scala 161:21]
+ wire dtm_io_dmi_req_valid; // @[Periphery.scala 161:21]
+ wire [6:0] dtm_io_dmi_req_bits_addr; // @[Periphery.scala 161:21]
+ wire [31:0] dtm_io_dmi_req_bits_data; // @[Periphery.scala 161:21]
+ wire [1:0] dtm_io_dmi_req_bits_op; // @[Periphery.scala 161:21]
+ wire dtm_io_dmi_resp_ready; // @[Periphery.scala 161:21]
+ wire dtm_io_dmi_resp_valid; // @[Periphery.scala 161:21]
+ wire [31:0] dtm_io_dmi_resp_bits_data; // @[Periphery.scala 161:21]
+ wire [1:0] dtm_io_dmi_resp_bits_resp; // @[Periphery.scala 161:21]
+ wire dtm_io_jtag_TMS; // @[Periphery.scala 161:21]
+ wire dtm_io_jtag_TDI; // @[Periphery.scala 161:21]
+ wire dtm_io_jtag_TDO_data; // @[Periphery.scala 161:21]
+ reg [6:0] int_rtc_tick_value; // @[Counter.scala 62:40]
+ wire int_rtc_tick_wrap_wrap = int_rtc_tick_value == 7'h63; // @[Counter.scala 74:24]
+ wire [6:0] _int_rtc_tick_wrap_value_T_1 = int_rtc_tick_value + 7'h1; // @[Counter.scala 78:24]
+ InterruptBusWrapper ibus ( // @[BaseSubsystem.scala 50:24]
+ .auto_int_bus_int_in_4_0(ibus_auto_int_bus_int_in_4_0),
+ .auto_int_bus_int_in_3_0(ibus_auto_int_bus_int_in_3_0),
+ .auto_int_bus_int_in_2_0(ibus_auto_int_bus_int_in_2_0),
+ .auto_int_bus_int_in_2_1(ibus_auto_int_bus_int_in_2_1),
+ .auto_int_bus_int_in_2_2(ibus_auto_int_bus_int_in_2_2),
+ .auto_int_bus_int_in_2_3(ibus_auto_int_bus_int_in_2_3),
+ .auto_int_bus_int_in_1_0(ibus_auto_int_bus_int_in_1_0),
+ .auto_int_bus_int_in_0_0(ibus_auto_int_bus_int_in_0_0),
+ .auto_int_bus_int_out_0(ibus_auto_int_bus_int_out_0),
+ .auto_int_bus_int_out_1(ibus_auto_int_bus_int_out_1),
+ .auto_int_bus_int_out_2(ibus_auto_int_bus_int_out_2),
+ .auto_int_bus_int_out_3(ibus_auto_int_bus_int_out_3),
+ .auto_int_bus_int_out_4(ibus_auto_int_bus_int_out_4),
+ .auto_int_bus_int_out_5(ibus_auto_int_bus_int_out_5),
+ .auto_int_bus_int_out_6(ibus_auto_int_bus_int_out_6),
+ .auto_int_bus_int_out_7(ibus_auto_int_bus_int_out_7)
+ );
+ SystemBus subsystem_sbus ( // @[SystemBus.scala 24:26]
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_ready(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_ready),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_valid(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_valid),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_ready(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_ready),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_valid(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_valid),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data),
+ .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt(
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_valid(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_valid),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_opcode(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_opcode),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_param(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_param),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_size(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_size),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_source(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_source),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_address(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_address),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_mask(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_mask),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_data(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_data),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_corrupt(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_corrupt),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_ready(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_ready),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data),
+ .auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt(
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data),
+ .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt(
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt),
+ .auto_fixedClockNode_out_1_clock(subsystem_sbus_auto_fixedClockNode_out_1_clock),
+ .auto_fixedClockNode_out_1_reset(subsystem_sbus_auto_fixedClockNode_out_1_reset),
+ .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock(
+ subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock),
+ .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset(
+ subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset)
+ );
+ PeripheryBus subsystem_pbus ( // @[PeripheryBus.scala 31:26]
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_ready(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_ready),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_valid(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_valid),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_opcode),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_param(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_param),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_size),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_source),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_address(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_address),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_mask(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_mask),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_corrupt),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_d_ready(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_ready),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_d_valid(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_valid),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_size),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_source),
+ .auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_data),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_ready(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_ready),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_valid(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_valid),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_opcode),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_param(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_param),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_size),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_source),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_address(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_address),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_mask(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_mask),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_data),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_corrupt),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_d_ready(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_ready),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_d_valid(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_valid),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_opcode),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_size),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_source),
+ .auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_data),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source),
+ .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source),
+ .auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source),
+ .auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_ready(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_ready),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_valid(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_valid),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_d_ready(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_ready),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_d_valid(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_valid),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source),
+ .auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_ready),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_valid),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source),
+ .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data(
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_ready(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_ready),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_valid(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_valid),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_opcode(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_opcode),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_param(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_param),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_size(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_size),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_source(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_source),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_sink(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_sink),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_denied(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_denied),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_data(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_data),
+ .auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_corrupt(
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_corrupt),
+ .auto_fixedClockNode_out_4_clock(subsystem_pbus_auto_fixedClockNode_out_4_clock),
+ .auto_fixedClockNode_out_4_reset(subsystem_pbus_auto_fixedClockNode_out_4_reset),
+ .auto_fixedClockNode_out_3_clock(subsystem_pbus_auto_fixedClockNode_out_3_clock),
+ .auto_fixedClockNode_out_3_reset(subsystem_pbus_auto_fixedClockNode_out_3_reset),
+ .auto_fixedClockNode_out_2_clock(subsystem_pbus_auto_fixedClockNode_out_2_clock),
+ .auto_fixedClockNode_out_2_reset(subsystem_pbus_auto_fixedClockNode_out_2_reset),
+ .auto_fixedClockNode_out_1_clock(subsystem_pbus_auto_fixedClockNode_out_1_clock),
+ .auto_fixedClockNode_out_1_reset(subsystem_pbus_auto_fixedClockNode_out_1_reset),
+ .auto_fixedClockNode_out_0_clock(subsystem_pbus_auto_fixedClockNode_out_0_clock),
+ .auto_fixedClockNode_out_0_reset(subsystem_pbus_auto_fixedClockNode_out_0_reset),
+ .auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock(
+ subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock),
+ .auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset(
+ subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset),
+ .auto_bus_xing_in_a_ready(subsystem_pbus_auto_bus_xing_in_a_ready),
+ .auto_bus_xing_in_a_valid(subsystem_pbus_auto_bus_xing_in_a_valid),
+ .auto_bus_xing_in_a_bits_opcode(subsystem_pbus_auto_bus_xing_in_a_bits_opcode),
+ .auto_bus_xing_in_a_bits_param(subsystem_pbus_auto_bus_xing_in_a_bits_param),
+ .auto_bus_xing_in_a_bits_size(subsystem_pbus_auto_bus_xing_in_a_bits_size),
+ .auto_bus_xing_in_a_bits_source(subsystem_pbus_auto_bus_xing_in_a_bits_source),
+ .auto_bus_xing_in_a_bits_address(subsystem_pbus_auto_bus_xing_in_a_bits_address),
+ .auto_bus_xing_in_a_bits_mask(subsystem_pbus_auto_bus_xing_in_a_bits_mask),
+ .auto_bus_xing_in_a_bits_data(subsystem_pbus_auto_bus_xing_in_a_bits_data),
+ .auto_bus_xing_in_a_bits_corrupt(subsystem_pbus_auto_bus_xing_in_a_bits_corrupt),
+ .auto_bus_xing_in_d_ready(subsystem_pbus_auto_bus_xing_in_d_ready),
+ .auto_bus_xing_in_d_valid(subsystem_pbus_auto_bus_xing_in_d_valid),
+ .auto_bus_xing_in_d_bits_opcode(subsystem_pbus_auto_bus_xing_in_d_bits_opcode),
+ .auto_bus_xing_in_d_bits_param(subsystem_pbus_auto_bus_xing_in_d_bits_param),
+ .auto_bus_xing_in_d_bits_size(subsystem_pbus_auto_bus_xing_in_d_bits_size),
+ .auto_bus_xing_in_d_bits_source(subsystem_pbus_auto_bus_xing_in_d_bits_source),
+ .auto_bus_xing_in_d_bits_sink(subsystem_pbus_auto_bus_xing_in_d_bits_sink),
+ .auto_bus_xing_in_d_bits_denied(subsystem_pbus_auto_bus_xing_in_d_bits_denied),
+ .auto_bus_xing_in_d_bits_data(subsystem_pbus_auto_bus_xing_in_d_bits_data),
+ .auto_bus_xing_in_d_bits_corrupt(subsystem_pbus_auto_bus_xing_in_d_bits_corrupt),
+ .clock(subsystem_pbus_clock),
+ .reset(subsystem_pbus_reset)
+ );
+ FrontBus subsystem_fbus ( // @[FrontBus.scala 22:26]
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_valid(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_valid),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_opcode(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_opcode),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_param(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_param),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_size(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_size),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_source(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_source),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_address(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_address),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_mask(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_mask),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_data(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_data),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_corrupt(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_corrupt),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_ready(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_ready),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data),
+ .auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt(
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt),
+ .auto_fixedClockNode_out_clock(subsystem_fbus_auto_fixedClockNode_out_clock),
+ .auto_fixedClockNode_out_reset(subsystem_fbus_auto_fixedClockNode_out_reset),
+ .auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock(
+ subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock),
+ .auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset(
+ subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset),
+ .auto_bus_xing_out_a_ready(subsystem_fbus_auto_bus_xing_out_a_ready),
+ .auto_bus_xing_out_a_valid(subsystem_fbus_auto_bus_xing_out_a_valid),
+ .auto_bus_xing_out_a_bits_opcode(subsystem_fbus_auto_bus_xing_out_a_bits_opcode),
+ .auto_bus_xing_out_a_bits_param(subsystem_fbus_auto_bus_xing_out_a_bits_param),
+ .auto_bus_xing_out_a_bits_size(subsystem_fbus_auto_bus_xing_out_a_bits_size),
+ .auto_bus_xing_out_a_bits_source(subsystem_fbus_auto_bus_xing_out_a_bits_source),
+ .auto_bus_xing_out_a_bits_address(subsystem_fbus_auto_bus_xing_out_a_bits_address),
+ .auto_bus_xing_out_a_bits_mask(subsystem_fbus_auto_bus_xing_out_a_bits_mask),
+ .auto_bus_xing_out_a_bits_data(subsystem_fbus_auto_bus_xing_out_a_bits_data),
+ .auto_bus_xing_out_a_bits_corrupt(subsystem_fbus_auto_bus_xing_out_a_bits_corrupt),
+ .auto_bus_xing_out_d_ready(subsystem_fbus_auto_bus_xing_out_d_ready),
+ .auto_bus_xing_out_d_valid(subsystem_fbus_auto_bus_xing_out_d_valid),
+ .auto_bus_xing_out_d_bits_opcode(subsystem_fbus_auto_bus_xing_out_d_bits_opcode),
+ .auto_bus_xing_out_d_bits_param(subsystem_fbus_auto_bus_xing_out_d_bits_param),
+ .auto_bus_xing_out_d_bits_size(subsystem_fbus_auto_bus_xing_out_d_bits_size),
+ .auto_bus_xing_out_d_bits_sink(subsystem_fbus_auto_bus_xing_out_d_bits_sink),
+ .auto_bus_xing_out_d_bits_denied(subsystem_fbus_auto_bus_xing_out_d_bits_denied),
+ .auto_bus_xing_out_d_bits_data(subsystem_fbus_auto_bus_xing_out_d_bits_data),
+ .auto_bus_xing_out_d_bits_corrupt(subsystem_fbus_auto_bus_xing_out_d_bits_corrupt)
+ );
+ PeripheryBus_1 subsystem_cbus ( // @[PeripheryBus.scala 31:26]
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_ready(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_ready),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_valid(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_valid),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_opcode(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_opcode),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_param(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_param),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_size(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_size),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_source(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_source),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_address(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_address),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_mask(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_mask),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_data(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_data),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_corrupt),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_ready(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_ready),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_valid(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_valid),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_opcode(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_opcode),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_size(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_size),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_source(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_source),
+ .auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_data(
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_data),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_ready(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_ready),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_valid(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_valid),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_opcode(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_opcode),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_param(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_param),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_size(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_size),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_source(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_source),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_address(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_address),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_mask(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_mask),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_data(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_data),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_corrupt),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_d_ready(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_ready),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_d_valid(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_valid),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_opcode(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_opcode),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_size(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_size),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_source(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_source),
+ .auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_data(
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_data),
+ .auto_coupler_to_bootrom_fragmenter_out_a_ready(subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready),
+ .auto_coupler_to_bootrom_fragmenter_out_a_valid(subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid),
+ .auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode),
+ .auto_coupler_to_bootrom_fragmenter_out_a_bits_param(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param),
+ .auto_coupler_to_bootrom_fragmenter_out_a_bits_size(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size),
+ .auto_coupler_to_bootrom_fragmenter_out_a_bits_source(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source),
+ .auto_coupler_to_bootrom_fragmenter_out_a_bits_address(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address),
+ .auto_coupler_to_bootrom_fragmenter_out_a_bits_mask(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask),
+ .auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt),
+ .auto_coupler_to_bootrom_fragmenter_out_d_ready(subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready),
+ .auto_coupler_to_bootrom_fragmenter_out_d_valid(subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid),
+ .auto_coupler_to_bootrom_fragmenter_out_d_bits_size(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size),
+ .auto_coupler_to_bootrom_fragmenter_out_d_bits_source(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source),
+ .auto_coupler_to_bootrom_fragmenter_out_d_bits_data(
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data),
+ .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt),
+ .auto_coupler_to_debug_fragmenter_out_a_ready(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_ready),
+ .auto_coupler_to_debug_fragmenter_out_a_valid(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid),
+ .auto_coupler_to_debug_fragmenter_out_a_bits_opcode(
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode),
+ .auto_coupler_to_debug_fragmenter_out_a_bits_param(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param)
+ ,
+ .auto_coupler_to_debug_fragmenter_out_a_bits_size(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size),
+ .auto_coupler_to_debug_fragmenter_out_a_bits_source(
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source),
+ .auto_coupler_to_debug_fragmenter_out_a_bits_address(
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address),
+ .auto_coupler_to_debug_fragmenter_out_a_bits_mask(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask),
+ .auto_coupler_to_debug_fragmenter_out_a_bits_data(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data),
+ .auto_coupler_to_debug_fragmenter_out_a_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt),
+ .auto_coupler_to_debug_fragmenter_out_d_ready(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready),
+ .auto_coupler_to_debug_fragmenter_out_d_valid(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_valid),
+ .auto_coupler_to_debug_fragmenter_out_d_bits_opcode(
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode),
+ .auto_coupler_to_debug_fragmenter_out_d_bits_size(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size),
+ .auto_coupler_to_debug_fragmenter_out_d_bits_source(
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source),
+ .auto_coupler_to_debug_fragmenter_out_d_bits_data(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data),
+ .auto_coupler_to_clint_fragmenter_out_a_ready(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_ready),
+ .auto_coupler_to_clint_fragmenter_out_a_valid(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid),
+ .auto_coupler_to_clint_fragmenter_out_a_bits_opcode(
+ subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode),
+ .auto_coupler_to_clint_fragmenter_out_a_bits_param(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param)
+ ,
+ .auto_coupler_to_clint_fragmenter_out_a_bits_size(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size),
+ .auto_coupler_to_clint_fragmenter_out_a_bits_source(
+ subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source),
+ .auto_coupler_to_clint_fragmenter_out_a_bits_address(
+ subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address),
+ .auto_coupler_to_clint_fragmenter_out_a_bits_mask(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask),
+ .auto_coupler_to_clint_fragmenter_out_a_bits_data(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data),
+ .auto_coupler_to_clint_fragmenter_out_a_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt),
+ .auto_coupler_to_clint_fragmenter_out_d_ready(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready),
+ .auto_coupler_to_clint_fragmenter_out_d_valid(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_valid),
+ .auto_coupler_to_clint_fragmenter_out_d_bits_opcode(
+ subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode),
+ .auto_coupler_to_clint_fragmenter_out_d_bits_size(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size),
+ .auto_coupler_to_clint_fragmenter_out_d_bits_source(
+ subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source),
+ .auto_coupler_to_clint_fragmenter_out_d_bits_data(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data),
+ .auto_coupler_to_plic_fragmenter_out_a_ready(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_ready),
+ .auto_coupler_to_plic_fragmenter_out_a_valid(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid),
+ .auto_coupler_to_plic_fragmenter_out_a_bits_opcode(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode)
+ ,
+ .auto_coupler_to_plic_fragmenter_out_a_bits_param(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param),
+ .auto_coupler_to_plic_fragmenter_out_a_bits_size(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size),
+ .auto_coupler_to_plic_fragmenter_out_a_bits_source(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source)
+ ,
+ .auto_coupler_to_plic_fragmenter_out_a_bits_address(
+ subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address),
+ .auto_coupler_to_plic_fragmenter_out_a_bits_mask(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask),
+ .auto_coupler_to_plic_fragmenter_out_a_bits_data(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data),
+ .auto_coupler_to_plic_fragmenter_out_a_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt),
+ .auto_coupler_to_plic_fragmenter_out_d_ready(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready),
+ .auto_coupler_to_plic_fragmenter_out_d_valid(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_valid),
+ .auto_coupler_to_plic_fragmenter_out_d_bits_opcode(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode)
+ ,
+ .auto_coupler_to_plic_fragmenter_out_d_bits_size(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size),
+ .auto_coupler_to_plic_fragmenter_out_d_bits_source(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source)
+ ,
+ .auto_coupler_to_plic_fragmenter_out_d_bits_data(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data),
+ .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt(
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt),
+ .auto_fixedClockNode_out_4_clock(subsystem_cbus_auto_fixedClockNode_out_4_clock),
+ .auto_fixedClockNode_out_4_reset(subsystem_cbus_auto_fixedClockNode_out_4_reset),
+ .auto_fixedClockNode_out_3_clock(subsystem_cbus_auto_fixedClockNode_out_3_clock),
+ .auto_fixedClockNode_out_3_reset(subsystem_cbus_auto_fixedClockNode_out_3_reset),
+ .auto_fixedClockNode_out_2_clock(subsystem_cbus_auto_fixedClockNode_out_2_clock),
+ .auto_fixedClockNode_out_2_reset(subsystem_cbus_auto_fixedClockNode_out_2_reset),
+ .auto_fixedClockNode_out_0_clock(subsystem_cbus_auto_fixedClockNode_out_0_clock),
+ .auto_fixedClockNode_out_0_reset(subsystem_cbus_auto_fixedClockNode_out_0_reset),
+ .auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock(
+ subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock),
+ .auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset(
+ subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset),
+ .auto_bus_xing_in_a_ready(subsystem_cbus_auto_bus_xing_in_a_ready),
+ .auto_bus_xing_in_a_valid(subsystem_cbus_auto_bus_xing_in_a_valid),
+ .auto_bus_xing_in_a_bits_opcode(subsystem_cbus_auto_bus_xing_in_a_bits_opcode),
+ .auto_bus_xing_in_a_bits_param(subsystem_cbus_auto_bus_xing_in_a_bits_param),
+ .auto_bus_xing_in_a_bits_size(subsystem_cbus_auto_bus_xing_in_a_bits_size),
+ .auto_bus_xing_in_a_bits_source(subsystem_cbus_auto_bus_xing_in_a_bits_source),
+ .auto_bus_xing_in_a_bits_address(subsystem_cbus_auto_bus_xing_in_a_bits_address),
+ .auto_bus_xing_in_a_bits_mask(subsystem_cbus_auto_bus_xing_in_a_bits_mask),
+ .auto_bus_xing_in_a_bits_data(subsystem_cbus_auto_bus_xing_in_a_bits_data),
+ .auto_bus_xing_in_a_bits_corrupt(subsystem_cbus_auto_bus_xing_in_a_bits_corrupt),
+ .auto_bus_xing_in_d_ready(subsystem_cbus_auto_bus_xing_in_d_ready),
+ .auto_bus_xing_in_d_valid(subsystem_cbus_auto_bus_xing_in_d_valid),
+ .auto_bus_xing_in_d_bits_opcode(subsystem_cbus_auto_bus_xing_in_d_bits_opcode),
+ .auto_bus_xing_in_d_bits_param(subsystem_cbus_auto_bus_xing_in_d_bits_param),
+ .auto_bus_xing_in_d_bits_size(subsystem_cbus_auto_bus_xing_in_d_bits_size),
+ .auto_bus_xing_in_d_bits_source(subsystem_cbus_auto_bus_xing_in_d_bits_source),
+ .auto_bus_xing_in_d_bits_sink(subsystem_cbus_auto_bus_xing_in_d_bits_sink),
+ .auto_bus_xing_in_d_bits_denied(subsystem_cbus_auto_bus_xing_in_d_bits_denied),
+ .auto_bus_xing_in_d_bits_data(subsystem_cbus_auto_bus_xing_in_d_bits_data),
+ .auto_bus_xing_in_d_bits_corrupt(subsystem_cbus_auto_bus_xing_in_d_bits_corrupt),
+ .custom_boot(subsystem_cbus_custom_boot),
+ .clock(subsystem_cbus_clock),
+ .reset(subsystem_cbus_reset)
+ );
+ TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala 252:38]
+ .auto_intsink_in_sync_0(tile_prci_domain_auto_intsink_in_sync_0),
+ .auto_tile_reset_domain_tile_hartid_in(tile_prci_domain_auto_tile_reset_domain_tile_hartid_in),
+ .auto_int_out_clock_xing_out_2_sync_0(tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0),
+ .auto_int_out_clock_xing_out_1_sync_0(tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0),
+ .auto_int_out_clock_xing_out_0_sync_0(tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0),
+ .auto_int_in_clock_xing_in_1_sync_0(tile_prci_domain_auto_int_in_clock_xing_in_1_sync_0),
+ .auto_int_in_clock_xing_in_0_sync_0(tile_prci_domain_auto_int_in_clock_xing_in_0_sync_0),
+ .auto_int_in_clock_xing_in_0_sync_1(tile_prci_domain_auto_int_in_clock_xing_in_0_sync_1),
+ .auto_tl_slave_clock_xing_in_a_ready(tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready),
+ .auto_tl_slave_clock_xing_in_a_valid(tile_prci_domain_auto_tl_slave_clock_xing_in_a_valid),
+ .auto_tl_slave_clock_xing_in_a_bits_opcode(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_opcode),
+ .auto_tl_slave_clock_xing_in_a_bits_param(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_param),
+ .auto_tl_slave_clock_xing_in_a_bits_size(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_size),
+ .auto_tl_slave_clock_xing_in_a_bits_source(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_source),
+ .auto_tl_slave_clock_xing_in_a_bits_address(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_address),
+ .auto_tl_slave_clock_xing_in_a_bits_mask(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_mask),
+ .auto_tl_slave_clock_xing_in_a_bits_data(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_data),
+ .auto_tl_slave_clock_xing_in_d_ready(tile_prci_domain_auto_tl_slave_clock_xing_in_d_ready),
+ .auto_tl_slave_clock_xing_in_d_valid(tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid),
+ .auto_tl_slave_clock_xing_in_d_bits_opcode(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode),
+ .auto_tl_slave_clock_xing_in_d_bits_param(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param),
+ .auto_tl_slave_clock_xing_in_d_bits_size(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size),
+ .auto_tl_slave_clock_xing_in_d_bits_source(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source),
+ .auto_tl_slave_clock_xing_in_d_bits_sink(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink),
+ .auto_tl_slave_clock_xing_in_d_bits_denied(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied),
+ .auto_tl_slave_clock_xing_in_d_bits_data(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data),
+ .auto_tl_slave_clock_xing_in_d_bits_corrupt(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt),
+ .auto_tl_master_clock_xing_out_a_ready(tile_prci_domain_auto_tl_master_clock_xing_out_a_ready),
+ .auto_tl_master_clock_xing_out_a_valid(tile_prci_domain_auto_tl_master_clock_xing_out_a_valid),
+ .auto_tl_master_clock_xing_out_a_bits_opcode(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode),
+ .auto_tl_master_clock_xing_out_a_bits_param(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param),
+ .auto_tl_master_clock_xing_out_a_bits_size(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size),
+ .auto_tl_master_clock_xing_out_a_bits_source(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source),
+ .auto_tl_master_clock_xing_out_a_bits_address(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address),
+ .auto_tl_master_clock_xing_out_a_bits_mask(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask),
+ .auto_tl_master_clock_xing_out_a_bits_data(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data),
+ .auto_tl_master_clock_xing_out_a_bits_corrupt(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt),
+ .auto_tl_master_clock_xing_out_d_ready(tile_prci_domain_auto_tl_master_clock_xing_out_d_ready),
+ .auto_tl_master_clock_xing_out_d_valid(tile_prci_domain_auto_tl_master_clock_xing_out_d_valid),
+ .auto_tl_master_clock_xing_out_d_bits_opcode(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_opcode),
+ .auto_tl_master_clock_xing_out_d_bits_param(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_param),
+ .auto_tl_master_clock_xing_out_d_bits_size(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_size),
+ .auto_tl_master_clock_xing_out_d_bits_source(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_source),
+ .auto_tl_master_clock_xing_out_d_bits_sink(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_sink),
+ .auto_tl_master_clock_xing_out_d_bits_denied(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_denied),
+ .auto_tl_master_clock_xing_out_d_bits_data(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_data),
+ .auto_tl_master_clock_xing_out_d_bits_corrupt(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_corrupt),
+ .auto_tap_clock_in_clock(tile_prci_domain_auto_tap_clock_in_clock),
+ .auto_tap_clock_in_reset(tile_prci_domain_auto_tap_clock_in_reset)
+ );
+ ClockSinkDomain plicDomainWrapper ( // @[Plic.scala 359:39]
+ .auto_plic_int_in_0(plicDomainWrapper_auto_plic_int_in_0),
+ .auto_plic_int_in_1(plicDomainWrapper_auto_plic_int_in_1),
+ .auto_plic_int_in_2(plicDomainWrapper_auto_plic_int_in_2),
+ .auto_plic_int_in_3(plicDomainWrapper_auto_plic_int_in_3),
+ .auto_plic_int_in_4(plicDomainWrapper_auto_plic_int_in_4),
+ .auto_plic_int_in_5(plicDomainWrapper_auto_plic_int_in_5),
+ .auto_plic_int_in_6(plicDomainWrapper_auto_plic_int_in_6),
+ .auto_plic_int_in_7(plicDomainWrapper_auto_plic_int_in_7),
+ .auto_plic_int_out_0(plicDomainWrapper_auto_plic_int_out_0),
+ .auto_plic_in_a_ready(plicDomainWrapper_auto_plic_in_a_ready),
+ .auto_plic_in_a_valid(plicDomainWrapper_auto_plic_in_a_valid),
+ .auto_plic_in_a_bits_opcode(plicDomainWrapper_auto_plic_in_a_bits_opcode),
+ .auto_plic_in_a_bits_param(plicDomainWrapper_auto_plic_in_a_bits_param),
+ .auto_plic_in_a_bits_size(plicDomainWrapper_auto_plic_in_a_bits_size),
+ .auto_plic_in_a_bits_source(plicDomainWrapper_auto_plic_in_a_bits_source),
+ .auto_plic_in_a_bits_address(plicDomainWrapper_auto_plic_in_a_bits_address),
+ .auto_plic_in_a_bits_mask(plicDomainWrapper_auto_plic_in_a_bits_mask),
+ .auto_plic_in_a_bits_data(plicDomainWrapper_auto_plic_in_a_bits_data),
+ .auto_plic_in_a_bits_corrupt(plicDomainWrapper_auto_plic_in_a_bits_corrupt),
+ .auto_plic_in_d_ready(plicDomainWrapper_auto_plic_in_d_ready),
+ .auto_plic_in_d_valid(plicDomainWrapper_auto_plic_in_d_valid),
+ .auto_plic_in_d_bits_opcode(plicDomainWrapper_auto_plic_in_d_bits_opcode),
+ .auto_plic_in_d_bits_size(plicDomainWrapper_auto_plic_in_d_bits_size),
+ .auto_plic_in_d_bits_source(plicDomainWrapper_auto_plic_in_d_bits_source),
+ .auto_plic_in_d_bits_data(plicDomainWrapper_auto_plic_in_d_bits_data),
+ .auto_clock_in_clock(plicDomainWrapper_auto_clock_in_clock),
+ .auto_clock_in_reset(plicDomainWrapper_auto_clock_in_reset)
+ );
+ CLINT clint ( // @[CLINT.scala 109:27]
+ .clock(clint_clock),
+ .reset(clint_reset),
+ .auto_int_out_0(clint_auto_int_out_0),
+ .auto_int_out_1(clint_auto_int_out_1),
+ .auto_in_a_ready(clint_auto_in_a_ready),
+ .auto_in_a_valid(clint_auto_in_a_valid),
+ .auto_in_a_bits_opcode(clint_auto_in_a_bits_opcode),
+ .auto_in_a_bits_param(clint_auto_in_a_bits_param),
+ .auto_in_a_bits_size(clint_auto_in_a_bits_size),
+ .auto_in_a_bits_source(clint_auto_in_a_bits_source),
+ .auto_in_a_bits_address(clint_auto_in_a_bits_address),
+ .auto_in_a_bits_mask(clint_auto_in_a_bits_mask),
+ .auto_in_a_bits_data(clint_auto_in_a_bits_data),
+ .auto_in_a_bits_corrupt(clint_auto_in_a_bits_corrupt),
+ .auto_in_d_ready(clint_auto_in_d_ready),
+ .auto_in_d_valid(clint_auto_in_d_valid),
+ .auto_in_d_bits_opcode(clint_auto_in_d_bits_opcode),
+ .auto_in_d_bits_size(clint_auto_in_d_bits_size),
+ .auto_in_d_bits_source(clint_auto_in_d_bits_source),
+ .auto_in_d_bits_data(clint_auto_in_d_bits_data),
+ .io_rtcTick(clint_io_rtcTick)
+ );
+ TLDebugModule debug_1 ( // @[Periphery.scala 84:27]
+ .auto_dmInner_dmInner_tl_in_a_ready(debug_1_auto_dmInner_dmInner_tl_in_a_ready),
+ .auto_dmInner_dmInner_tl_in_a_valid(debug_1_auto_dmInner_dmInner_tl_in_a_valid),
+ .auto_dmInner_dmInner_tl_in_a_bits_opcode(debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode),
+ .auto_dmInner_dmInner_tl_in_a_bits_param(debug_1_auto_dmInner_dmInner_tl_in_a_bits_param),
+ .auto_dmInner_dmInner_tl_in_a_bits_size(debug_1_auto_dmInner_dmInner_tl_in_a_bits_size),
+ .auto_dmInner_dmInner_tl_in_a_bits_source(debug_1_auto_dmInner_dmInner_tl_in_a_bits_source),
+ .auto_dmInner_dmInner_tl_in_a_bits_address(debug_1_auto_dmInner_dmInner_tl_in_a_bits_address),
+ .auto_dmInner_dmInner_tl_in_a_bits_mask(debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask),
+ .auto_dmInner_dmInner_tl_in_a_bits_data(debug_1_auto_dmInner_dmInner_tl_in_a_bits_data),
+ .auto_dmInner_dmInner_tl_in_a_bits_corrupt(debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt),
+ .auto_dmInner_dmInner_tl_in_d_ready(debug_1_auto_dmInner_dmInner_tl_in_d_ready),
+ .auto_dmInner_dmInner_tl_in_d_valid(debug_1_auto_dmInner_dmInner_tl_in_d_valid),
+ .auto_dmInner_dmInner_tl_in_d_bits_opcode(debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode),
+ .auto_dmInner_dmInner_tl_in_d_bits_size(debug_1_auto_dmInner_dmInner_tl_in_d_bits_size),
+ .auto_dmInner_dmInner_tl_in_d_bits_source(debug_1_auto_dmInner_dmInner_tl_in_d_bits_source),
+ .auto_dmInner_dmInner_tl_in_d_bits_data(debug_1_auto_dmInner_dmInner_tl_in_d_bits_data),
+ .auto_dmOuter_intsource_out_sync_0(debug_1_auto_dmOuter_intsource_out_sync_0),
+ .io_debug_clock(debug_1_io_debug_clock),
+ .io_debug_reset(debug_1_io_debug_reset),
+ .io_ctrl_dmactive(debug_1_io_ctrl_dmactive),
+ .io_ctrl_dmactiveAck(debug_1_io_ctrl_dmactiveAck),
+ .io_dmi_dmi_req_ready(debug_1_io_dmi_dmi_req_ready),
+ .io_dmi_dmi_req_valid(debug_1_io_dmi_dmi_req_valid),
+ .io_dmi_dmi_req_bits_addr(debug_1_io_dmi_dmi_req_bits_addr),
+ .io_dmi_dmi_req_bits_data(debug_1_io_dmi_dmi_req_bits_data),
+ .io_dmi_dmi_req_bits_op(debug_1_io_dmi_dmi_req_bits_op),
+ .io_dmi_dmi_resp_ready(debug_1_io_dmi_dmi_resp_ready),
+ .io_dmi_dmi_resp_valid(debug_1_io_dmi_dmi_resp_valid),
+ .io_dmi_dmi_resp_bits_data(debug_1_io_dmi_dmi_resp_bits_data),
+ .io_dmi_dmi_resp_bits_resp(debug_1_io_dmi_dmi_resp_bits_resp),
+ .io_dmi_dmiClock(debug_1_io_dmi_dmiClock),
+ .io_dmi_dmiReset(debug_1_io_dmi_dmiReset),
+ .io_hartIsInReset_0(debug_1_io_hartIsInReset_0)
+ );
+ BundleBridgeNexus_13 tileHartIdNexusNode ( // @[HasTiles.scala 159:39]
+ .auto_out(tileHartIdNexusNode_auto_out)
+ );
+ IntSyncCrossingSource_5 intsource ( // @[Crossing.scala 26:31]
+ .clock(intsource_clock),
+ .reset(intsource_reset),
+ .auto_in_0(intsource_auto_in_0),
+ .auto_in_1(intsource_auto_in_1),
+ .auto_out_sync_0(intsource_auto_out_sync_0),
+ .auto_out_sync_1(intsource_auto_out_sync_1)
+ );
+ IntSyncCrossingSource_1 intsource_1 ( // @[Crossing.scala 26:31]
+ .clock(intsource_1_clock),
+ .reset(intsource_1_reset),
+ .auto_in_0(intsource_1_auto_in_0),
+ .auto_out_sync_0(intsource_1_auto_out_sync_0)
+ );
+ IntSyncSyncCrossingSink_1 intsink_1 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_1_auto_in_sync_0),
+ .auto_out_0(intsink_1_auto_out_0)
+ );
+ IntSyncSyncCrossingSink_1 intsink_2 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_2_auto_in_sync_0),
+ .auto_out_0(intsink_2_auto_out_0)
+ );
+ IntSyncSyncCrossingSink_1 intsink_3 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_3_auto_in_sync_0),
+ .auto_out_0(intsink_3_auto_out_0)
+ );
+ ClockSinkDomain_1 bootROMDomainWrapper ( // @[BootROM.scala 70:42]
+ .auto_bootrom_in_a_ready(bootROMDomainWrapper_auto_bootrom_in_a_ready),
+ .auto_bootrom_in_a_valid(bootROMDomainWrapper_auto_bootrom_in_a_valid),
+ .auto_bootrom_in_a_bits_opcode(bootROMDomainWrapper_auto_bootrom_in_a_bits_opcode),
+ .auto_bootrom_in_a_bits_param(bootROMDomainWrapper_auto_bootrom_in_a_bits_param),
+ .auto_bootrom_in_a_bits_size(bootROMDomainWrapper_auto_bootrom_in_a_bits_size),
+ .auto_bootrom_in_a_bits_source(bootROMDomainWrapper_auto_bootrom_in_a_bits_source),
+ .auto_bootrom_in_a_bits_address(bootROMDomainWrapper_auto_bootrom_in_a_bits_address),
+ .auto_bootrom_in_a_bits_mask(bootROMDomainWrapper_auto_bootrom_in_a_bits_mask),
+ .auto_bootrom_in_a_bits_corrupt(bootROMDomainWrapper_auto_bootrom_in_a_bits_corrupt),
+ .auto_bootrom_in_d_ready(bootROMDomainWrapper_auto_bootrom_in_d_ready),
+ .auto_bootrom_in_d_valid(bootROMDomainWrapper_auto_bootrom_in_d_valid),
+ .auto_bootrom_in_d_bits_size(bootROMDomainWrapper_auto_bootrom_in_d_bits_size),
+ .auto_bootrom_in_d_bits_source(bootROMDomainWrapper_auto_bootrom_in_d_bits_source),
+ .auto_bootrom_in_d_bits_data(bootROMDomainWrapper_auto_bootrom_in_d_bits_data),
+ .auto_clock_in_clock(bootROMDomainWrapper_auto_clock_in_clock),
+ .auto_clock_in_reset(bootROMDomainWrapper_auto_clock_in_reset)
+ );
+ ClockSinkDomain_2 domain ( // @[SerialAdapter.scala 373:28]
+ .auto_serdesser_client_out_a_ready(domain_auto_serdesser_client_out_a_ready),
+ .auto_serdesser_client_out_a_valid(domain_auto_serdesser_client_out_a_valid),
+ .auto_serdesser_client_out_a_bits_opcode(domain_auto_serdesser_client_out_a_bits_opcode),
+ .auto_serdesser_client_out_a_bits_param(domain_auto_serdesser_client_out_a_bits_param),
+ .auto_serdesser_client_out_a_bits_size(domain_auto_serdesser_client_out_a_bits_size),
+ .auto_serdesser_client_out_a_bits_source(domain_auto_serdesser_client_out_a_bits_source),
+ .auto_serdesser_client_out_a_bits_address(domain_auto_serdesser_client_out_a_bits_address),
+ .auto_serdesser_client_out_a_bits_mask(domain_auto_serdesser_client_out_a_bits_mask),
+ .auto_serdesser_client_out_a_bits_data(domain_auto_serdesser_client_out_a_bits_data),
+ .auto_serdesser_client_out_a_bits_corrupt(domain_auto_serdesser_client_out_a_bits_corrupt),
+ .auto_serdesser_client_out_d_ready(domain_auto_serdesser_client_out_d_ready),
+ .auto_serdesser_client_out_d_valid(domain_auto_serdesser_client_out_d_valid),
+ .auto_serdesser_client_out_d_bits_opcode(domain_auto_serdesser_client_out_d_bits_opcode),
+ .auto_serdesser_client_out_d_bits_param(domain_auto_serdesser_client_out_d_bits_param),
+ .auto_serdesser_client_out_d_bits_size(domain_auto_serdesser_client_out_d_bits_size),
+ .auto_serdesser_client_out_d_bits_source(domain_auto_serdesser_client_out_d_bits_source),
+ .auto_serdesser_client_out_d_bits_sink(domain_auto_serdesser_client_out_d_bits_sink),
+ .auto_serdesser_client_out_d_bits_denied(domain_auto_serdesser_client_out_d_bits_denied),
+ .auto_serdesser_client_out_d_bits_data(domain_auto_serdesser_client_out_d_bits_data),
+ .auto_serdesser_client_out_d_bits_corrupt(domain_auto_serdesser_client_out_d_bits_corrupt),
+ .auto_tlserial_manager_crossing_in_a_ready(domain_auto_tlserial_manager_crossing_in_a_ready),
+ .auto_tlserial_manager_crossing_in_a_valid(domain_auto_tlserial_manager_crossing_in_a_valid),
+ .auto_tlserial_manager_crossing_in_a_bits_opcode(domain_auto_tlserial_manager_crossing_in_a_bits_opcode),
+ .auto_tlserial_manager_crossing_in_a_bits_param(domain_auto_tlserial_manager_crossing_in_a_bits_param),
+ .auto_tlserial_manager_crossing_in_a_bits_size(domain_auto_tlserial_manager_crossing_in_a_bits_size),
+ .auto_tlserial_manager_crossing_in_a_bits_source(domain_auto_tlserial_manager_crossing_in_a_bits_source),
+ .auto_tlserial_manager_crossing_in_a_bits_address(domain_auto_tlserial_manager_crossing_in_a_bits_address),
+ .auto_tlserial_manager_crossing_in_a_bits_mask(domain_auto_tlserial_manager_crossing_in_a_bits_mask),
+ .auto_tlserial_manager_crossing_in_a_bits_data(domain_auto_tlserial_manager_crossing_in_a_bits_data),
+ .auto_tlserial_manager_crossing_in_a_bits_corrupt(domain_auto_tlserial_manager_crossing_in_a_bits_corrupt),
+ .auto_tlserial_manager_crossing_in_d_ready(domain_auto_tlserial_manager_crossing_in_d_ready),
+ .auto_tlserial_manager_crossing_in_d_valid(domain_auto_tlserial_manager_crossing_in_d_valid),
+ .auto_tlserial_manager_crossing_in_d_bits_opcode(domain_auto_tlserial_manager_crossing_in_d_bits_opcode),
+ .auto_tlserial_manager_crossing_in_d_bits_param(domain_auto_tlserial_manager_crossing_in_d_bits_param),
+ .auto_tlserial_manager_crossing_in_d_bits_size(domain_auto_tlserial_manager_crossing_in_d_bits_size),
+ .auto_tlserial_manager_crossing_in_d_bits_source(domain_auto_tlserial_manager_crossing_in_d_bits_source),
+ .auto_tlserial_manager_crossing_in_d_bits_sink(domain_auto_tlserial_manager_crossing_in_d_bits_sink),
+ .auto_tlserial_manager_crossing_in_d_bits_denied(domain_auto_tlserial_manager_crossing_in_d_bits_denied),
+ .auto_tlserial_manager_crossing_in_d_bits_data(domain_auto_tlserial_manager_crossing_in_d_bits_data),
+ .auto_tlserial_manager_crossing_in_d_bits_corrupt(domain_auto_tlserial_manager_crossing_in_d_bits_corrupt),
+ .auto_clock_in_clock(domain_auto_clock_in_clock),
+ .auto_clock_in_reset(domain_auto_clock_in_reset),
+ .serial_tl_in_ready(domain_serial_tl_in_ready),
+ .serial_tl_in_valid(domain_serial_tl_in_valid),
+ .serial_tl_in_bits(domain_serial_tl_in_bits),
+ .serial_tl_out_ready(domain_serial_tl_out_ready),
+ .serial_tl_out_valid(domain_serial_tl_out_valid),
+ .serial_tl_out_bits(domain_serial_tl_out_bits),
+ .clock(domain_clock)
+ );
+ ClockSinkDomain_3 uartClockDomainWrapper ( // @[UART.scala 242:44]
+ .auto_uart_0_int_xing_out_sync_0(uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0),
+ .auto_uart_0_control_xing_in_a_ready(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready),
+ .auto_uart_0_control_xing_in_a_valid(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_valid),
+ .auto_uart_0_control_xing_in_a_bits_opcode(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_opcode),
+ .auto_uart_0_control_xing_in_a_bits_param(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_param),
+ .auto_uart_0_control_xing_in_a_bits_size(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_size),
+ .auto_uart_0_control_xing_in_a_bits_source(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_source),
+ .auto_uart_0_control_xing_in_a_bits_address(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_address),
+ .auto_uart_0_control_xing_in_a_bits_mask(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_mask),
+ .auto_uart_0_control_xing_in_a_bits_data(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_data),
+ .auto_uart_0_control_xing_in_a_bits_corrupt(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_corrupt),
+ .auto_uart_0_control_xing_in_d_ready(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_ready),
+ .auto_uart_0_control_xing_in_d_valid(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid),
+ .auto_uart_0_control_xing_in_d_bits_opcode(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode),
+ .auto_uart_0_control_xing_in_d_bits_size(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size),
+ .auto_uart_0_control_xing_in_d_bits_source(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source),
+ .auto_uart_0_control_xing_in_d_bits_data(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data),
+ .auto_uart_0_io_out_txd(uartClockDomainWrapper_auto_uart_0_io_out_txd),
+ .auto_uart_0_io_out_rxd(uartClockDomainWrapper_auto_uart_0_io_out_rxd),
+ .auto_clock_in_clock(uartClockDomainWrapper_auto_clock_in_clock),
+ .auto_clock_in_reset(uartClockDomainWrapper_auto_clock_in_reset)
+ );
+ IntSyncSyncCrossingSink_1 intsink_4 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_4_auto_in_sync_0),
+ .auto_out_0(intsink_4_auto_out_0)
+ );
+ ClockSinkDomain_4 uartClockDomainWrapper_1 ( // @[UART.scala 242:44]
+ .auto_uart_1_int_xing_out_sync_0(uartClockDomainWrapper_1_auto_uart_1_int_xing_out_sync_0),
+ .auto_uart_1_control_xing_in_a_ready(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_ready),
+ .auto_uart_1_control_xing_in_a_valid(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_valid),
+ .auto_uart_1_control_xing_in_a_bits_opcode(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_opcode),
+ .auto_uart_1_control_xing_in_a_bits_param(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_param),
+ .auto_uart_1_control_xing_in_a_bits_size(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_size),
+ .auto_uart_1_control_xing_in_a_bits_source(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_source),
+ .auto_uart_1_control_xing_in_a_bits_address(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_address),
+ .auto_uart_1_control_xing_in_a_bits_mask(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_mask),
+ .auto_uart_1_control_xing_in_a_bits_data(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_data),
+ .auto_uart_1_control_xing_in_a_bits_corrupt(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_corrupt),
+ .auto_uart_1_control_xing_in_d_ready(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_ready),
+ .auto_uart_1_control_xing_in_d_valid(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_valid),
+ .auto_uart_1_control_xing_in_d_bits_opcode(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_opcode),
+ .auto_uart_1_control_xing_in_d_bits_size(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_size),
+ .auto_uart_1_control_xing_in_d_bits_source(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_source),
+ .auto_uart_1_control_xing_in_d_bits_data(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_data),
+ .auto_uart_1_io_out_txd(uartClockDomainWrapper_1_auto_uart_1_io_out_txd),
+ .auto_uart_1_io_out_rxd(uartClockDomainWrapper_1_auto_uart_1_io_out_rxd),
+ .auto_clock_in_clock(uartClockDomainWrapper_1_auto_clock_in_clock),
+ .auto_clock_in_reset(uartClockDomainWrapper_1_auto_clock_in_reset)
+ );
+ IntSyncSyncCrossingSink_1 intsink_5 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_5_auto_in_sync_0),
+ .auto_out_0(intsink_5_auto_out_0)
+ );
+ ClockSinkDomain_5 gpioClockDomainWrapper ( // @[GPIO.scala 281:44]
+ .auto_gpio_0_int_xing_out_sync_0(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_0),
+ .auto_gpio_0_int_xing_out_sync_1(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_1),
+ .auto_gpio_0_int_xing_out_sync_2(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_2),
+ .auto_gpio_0_int_xing_out_sync_3(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_3),
+ .auto_gpio_0_control_xing_in_a_ready(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_ready),
+ .auto_gpio_0_control_xing_in_a_valid(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_valid),
+ .auto_gpio_0_control_xing_in_a_bits_opcode(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_opcode),
+ .auto_gpio_0_control_xing_in_a_bits_param(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_param),
+ .auto_gpio_0_control_xing_in_a_bits_size(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_size),
+ .auto_gpio_0_control_xing_in_a_bits_source(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_source),
+ .auto_gpio_0_control_xing_in_a_bits_address(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_address),
+ .auto_gpio_0_control_xing_in_a_bits_mask(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_mask),
+ .auto_gpio_0_control_xing_in_a_bits_data(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_data),
+ .auto_gpio_0_control_xing_in_a_bits_corrupt(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_corrupt),
+ .auto_gpio_0_control_xing_in_d_ready(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_ready),
+ .auto_gpio_0_control_xing_in_d_valid(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_valid),
+ .auto_gpio_0_control_xing_in_d_bits_opcode(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_opcode),
+ .auto_gpio_0_control_xing_in_d_bits_size(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_size),
+ .auto_gpio_0_control_xing_in_d_bits_source(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_source),
+ .auto_gpio_0_control_xing_in_d_bits_data(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_data),
+ .auto_gpio_0_io_out_pins_0_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_i_ival),
+ .auto_gpio_0_io_out_pins_0_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oval),
+ .auto_gpio_0_io_out_pins_0_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oe),
+ .auto_gpio_0_io_out_pins_0_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_ie),
+ .auto_gpio_0_io_out_pins_1_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_i_ival),
+ .auto_gpio_0_io_out_pins_1_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oval),
+ .auto_gpio_0_io_out_pins_1_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oe),
+ .auto_gpio_0_io_out_pins_1_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_ie),
+ .auto_gpio_0_io_out_pins_2_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_i_ival),
+ .auto_gpio_0_io_out_pins_2_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oval),
+ .auto_gpio_0_io_out_pins_2_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oe),
+ .auto_gpio_0_io_out_pins_2_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_ie),
+ .auto_gpio_0_io_out_pins_3_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_i_ival),
+ .auto_gpio_0_io_out_pins_3_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oval),
+ .auto_gpio_0_io_out_pins_3_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oe),
+ .auto_gpio_0_io_out_pins_3_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_ie),
+ .auto_clock_in_clock(gpioClockDomainWrapper_auto_clock_in_clock),
+ .auto_clock_in_reset(gpioClockDomainWrapper_auto_clock_in_reset)
+ );
+ IntSyncSyncCrossingSink_8 intsink_6 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_6_auto_in_sync_0),
+ .auto_in_sync_1(intsink_6_auto_in_sync_1),
+ .auto_in_sync_2(intsink_6_auto_in_sync_2),
+ .auto_in_sync_3(intsink_6_auto_in_sync_3),
+ .auto_out_0(intsink_6_auto_out_0),
+ .auto_out_1(intsink_6_auto_out_1),
+ .auto_out_2(intsink_6_auto_out_2),
+ .auto_out_3(intsink_6_auto_out_3)
+ );
+ ClockSinkDomain_6 qspiClockDomainWrapper ( // @[SPI.scala 92:44]
+ .auto_qspi_0_int_xing_out_sync_0(qspiClockDomainWrapper_auto_qspi_0_int_xing_out_sync_0),
+ .auto_qspi_0_mem_xing_in_a_ready(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_ready),
+ .auto_qspi_0_mem_xing_in_a_valid(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_valid),
+ .auto_qspi_0_mem_xing_in_a_bits_opcode(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_opcode),
+ .auto_qspi_0_mem_xing_in_a_bits_param(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_param),
+ .auto_qspi_0_mem_xing_in_a_bits_size(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_size),
+ .auto_qspi_0_mem_xing_in_a_bits_source(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_source),
+ .auto_qspi_0_mem_xing_in_a_bits_address(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_address),
+ .auto_qspi_0_mem_xing_in_a_bits_mask(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_mask),
+ .auto_qspi_0_mem_xing_in_a_bits_corrupt(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_corrupt),
+ .auto_qspi_0_mem_xing_in_d_ready(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_ready),
+ .auto_qspi_0_mem_xing_in_d_valid(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_valid),
+ .auto_qspi_0_mem_xing_in_d_bits_size(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_size),
+ .auto_qspi_0_mem_xing_in_d_bits_source(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_source),
+ .auto_qspi_0_mem_xing_in_d_bits_data(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_data),
+ .auto_qspi_0_control_xing_in_a_ready(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_ready),
+ .auto_qspi_0_control_xing_in_a_valid(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_valid),
+ .auto_qspi_0_control_xing_in_a_bits_opcode(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_opcode),
+ .auto_qspi_0_control_xing_in_a_bits_param(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_param),
+ .auto_qspi_0_control_xing_in_a_bits_size(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_size),
+ .auto_qspi_0_control_xing_in_a_bits_source(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_source),
+ .auto_qspi_0_control_xing_in_a_bits_address(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_address),
+ .auto_qspi_0_control_xing_in_a_bits_mask(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_mask),
+ .auto_qspi_0_control_xing_in_a_bits_data(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_data),
+ .auto_qspi_0_control_xing_in_a_bits_corrupt(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_corrupt),
+ .auto_qspi_0_control_xing_in_d_ready(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_ready),
+ .auto_qspi_0_control_xing_in_d_valid(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_valid),
+ .auto_qspi_0_control_xing_in_d_bits_opcode(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_opcode),
+ .auto_qspi_0_control_xing_in_d_bits_size(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_size),
+ .auto_qspi_0_control_xing_in_d_bits_source(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_source),
+ .auto_qspi_0_control_xing_in_d_bits_data(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_data),
+ .auto_qspi_0_io_out_sck(qspiClockDomainWrapper_auto_qspi_0_io_out_sck),
+ .auto_qspi_0_io_out_dq_0_i(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_i),
+ .auto_qspi_0_io_out_dq_0_o(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_o),
+ .auto_qspi_0_io_out_dq_0_oe(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_oe),
+ .auto_qspi_0_io_out_dq_1_i(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_i),
+ .auto_qspi_0_io_out_dq_1_o(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_o),
+ .auto_qspi_0_io_out_dq_1_oe(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_oe),
+ .auto_qspi_0_io_out_dq_2_i(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_i),
+ .auto_qspi_0_io_out_dq_2_o(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_o),
+ .auto_qspi_0_io_out_dq_2_oe(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_oe),
+ .auto_qspi_0_io_out_dq_3_i(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_i),
+ .auto_qspi_0_io_out_dq_3_o(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_o),
+ .auto_qspi_0_io_out_dq_3_oe(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_oe),
+ .auto_qspi_0_io_out_cs_0(qspiClockDomainWrapper_auto_qspi_0_io_out_cs_0),
+ .auto_clock_in_clock(qspiClockDomainWrapper_auto_clock_in_clock),
+ .auto_clock_in_reset(qspiClockDomainWrapper_auto_clock_in_reset)
+ );
+ IntSyncSyncCrossingSink_1 intsink_7 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_7_auto_in_sync_0),
+ .auto_out_0(intsink_7_auto_out_0)
+ );
+ ClockSinkDomain_7 qspiClockDomainWrapper_1 ( // @[SPI.scala 92:44]
+ .auto_qspi_1_int_xing_out_sync_0(qspiClockDomainWrapper_1_auto_qspi_1_int_xing_out_sync_0),
+ .auto_qspi_1_mem_xing_in_a_ready(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_ready),
+ .auto_qspi_1_mem_xing_in_a_valid(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_valid),
+ .auto_qspi_1_mem_xing_in_a_bits_opcode(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_opcode),
+ .auto_qspi_1_mem_xing_in_a_bits_param(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_param),
+ .auto_qspi_1_mem_xing_in_a_bits_size(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_size),
+ .auto_qspi_1_mem_xing_in_a_bits_source(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_source),
+ .auto_qspi_1_mem_xing_in_a_bits_address(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_address),
+ .auto_qspi_1_mem_xing_in_a_bits_mask(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_mask),
+ .auto_qspi_1_mem_xing_in_a_bits_corrupt(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_corrupt),
+ .auto_qspi_1_mem_xing_in_d_ready(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_ready),
+ .auto_qspi_1_mem_xing_in_d_valid(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_valid),
+ .auto_qspi_1_mem_xing_in_d_bits_size(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_size),
+ .auto_qspi_1_mem_xing_in_d_bits_source(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_source),
+ .auto_qspi_1_mem_xing_in_d_bits_data(qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_data),
+ .auto_qspi_1_control_xing_in_a_ready(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_ready),
+ .auto_qspi_1_control_xing_in_a_valid(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_valid),
+ .auto_qspi_1_control_xing_in_a_bits_opcode(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_opcode),
+ .auto_qspi_1_control_xing_in_a_bits_param(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_param),
+ .auto_qspi_1_control_xing_in_a_bits_size(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_size),
+ .auto_qspi_1_control_xing_in_a_bits_source(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_source),
+ .auto_qspi_1_control_xing_in_a_bits_address(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_address),
+ .auto_qspi_1_control_xing_in_a_bits_mask(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_mask),
+ .auto_qspi_1_control_xing_in_a_bits_data(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_data),
+ .auto_qspi_1_control_xing_in_a_bits_corrupt(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_corrupt),
+ .auto_qspi_1_control_xing_in_d_ready(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_ready),
+ .auto_qspi_1_control_xing_in_d_valid(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_valid),
+ .auto_qspi_1_control_xing_in_d_bits_opcode(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_opcode),
+ .auto_qspi_1_control_xing_in_d_bits_size(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_size),
+ .auto_qspi_1_control_xing_in_d_bits_source(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_source),
+ .auto_qspi_1_control_xing_in_d_bits_data(qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_data),
+ .auto_qspi_1_io_out_sck(qspiClockDomainWrapper_1_auto_qspi_1_io_out_sck),
+ .auto_qspi_1_io_out_dq_0_i(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_i),
+ .auto_qspi_1_io_out_dq_0_o(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_o),
+ .auto_qspi_1_io_out_dq_0_oe(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_oe),
+ .auto_qspi_1_io_out_dq_1_i(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_i),
+ .auto_qspi_1_io_out_dq_1_o(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_o),
+ .auto_qspi_1_io_out_dq_1_oe(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_oe),
+ .auto_qspi_1_io_out_dq_2_i(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_i),
+ .auto_qspi_1_io_out_dq_2_o(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_o),
+ .auto_qspi_1_io_out_dq_2_oe(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_oe),
+ .auto_qspi_1_io_out_dq_3_i(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_i),
+ .auto_qspi_1_io_out_dq_3_o(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_o),
+ .auto_qspi_1_io_out_dq_3_oe(qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_oe),
+ .auto_qspi_1_io_out_cs_0(qspiClockDomainWrapper_1_auto_qspi_1_io_out_cs_0),
+ .auto_clock_in_clock(qspiClockDomainWrapper_1_auto_clock_in_clock),
+ .auto_clock_in_reset(qspiClockDomainWrapper_1_auto_clock_in_reset)
+ );
+ IntSyncSyncCrossingSink_1 intsink_8 ( // @[Crossing.scala 94:29]
+ .auto_in_sync_0(intsink_8_auto_in_sync_0),
+ .auto_out_0(intsink_8_auto_out_0)
+ );
+ ClockSinkDomain_8 chipyardPRCI ( // @[HasChipyardPRCI.scala 38:36]
+ .auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock),
+ .auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset),
+ .auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset),
+ .auto_chipyardPRCI_tl_in_a_ready(chipyardPRCI_auto_chipyardPRCI_tl_in_a_ready),
+ .auto_chipyardPRCI_tl_in_a_valid(chipyardPRCI_auto_chipyardPRCI_tl_in_a_valid),
+ .auto_chipyardPRCI_tl_in_a_bits_opcode(chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_opcode),
+ .auto_chipyardPRCI_tl_in_a_bits_param(chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_param),
+ .auto_chipyardPRCI_tl_in_a_bits_size(chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_size),
+ .auto_chipyardPRCI_tl_in_a_bits_source(chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_source),
+ .auto_chipyardPRCI_tl_in_a_bits_address(chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_address),
+ .auto_chipyardPRCI_tl_in_a_bits_mask(chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_mask),
+ .auto_chipyardPRCI_tl_in_a_bits_data(chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_data),
+ .auto_chipyardPRCI_tl_in_a_bits_corrupt(chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_corrupt),
+ .auto_chipyardPRCI_tl_in_d_ready(chipyardPRCI_auto_chipyardPRCI_tl_in_d_ready),
+ .auto_chipyardPRCI_tl_in_d_valid(chipyardPRCI_auto_chipyardPRCI_tl_in_d_valid),
+ .auto_chipyardPRCI_tl_in_d_bits_opcode(chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_opcode),
+ .auto_chipyardPRCI_tl_in_d_bits_size(chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_size),
+ .auto_chipyardPRCI_tl_in_d_bits_source(chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_source),
+ .auto_chipyardPRCI_tl_in_d_bits_data(chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_data),
+ .auto_chipyardPRCI_chipyard_prci_in_a_ready(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_ready),
+ .auto_chipyardPRCI_chipyard_prci_in_a_valid(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_valid),
+ .auto_chipyardPRCI_chipyard_prci_in_a_bits_opcode(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_opcode),
+ .auto_chipyardPRCI_chipyard_prci_in_a_bits_param(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_param),
+ .auto_chipyardPRCI_chipyard_prci_in_a_bits_size(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_size),
+ .auto_chipyardPRCI_chipyard_prci_in_a_bits_source(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_source),
+ .auto_chipyardPRCI_chipyard_prci_in_a_bits_address(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_address),
+ .auto_chipyardPRCI_chipyard_prci_in_a_bits_mask(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_mask),
+ .auto_chipyardPRCI_chipyard_prci_in_a_bits_data(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_data),
+ .auto_chipyardPRCI_chipyard_prci_in_a_bits_corrupt(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_corrupt),
+ .auto_chipyardPRCI_chipyard_prci_in_d_ready(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_ready),
+ .auto_chipyardPRCI_chipyard_prci_in_d_valid(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_valid),
+ .auto_chipyardPRCI_chipyard_prci_in_d_bits_opcode(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_opcode),
+ .auto_chipyardPRCI_chipyard_prci_in_d_bits_size(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_size),
+ .auto_chipyardPRCI_chipyard_prci_in_d_bits_source(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_source),
+ .auto_chipyardPRCI_chipyard_prci_in_d_bits_data(chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_data),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_clock),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_reset),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset),
+ .auto_clock_in_clock(chipyardPRCI_auto_clock_in_clock),
+ .auto_clock_in_reset(chipyardPRCI_auto_clock_in_reset)
+ );
+ ClockGroupAggregator_4 chipyardPRCI_1 ( // @[HasChipyardPRCI.scala 42:30]
+ .auto_in_member_allClocks_implicit_clock_clock(chipyardPRCI_1_auto_in_member_allClocks_implicit_clock_clock),
+ .auto_in_member_allClocks_implicit_clock_reset(chipyardPRCI_1_auto_in_member_allClocks_implicit_clock_reset),
+ .auto_in_member_allClocks_subsystem_cbus_0_clock(chipyardPRCI_1_auto_in_member_allClocks_subsystem_cbus_0_clock),
+ .auto_in_member_allClocks_subsystem_cbus_0_reset(chipyardPRCI_1_auto_in_member_allClocks_subsystem_cbus_0_reset),
+ .auto_in_member_allClocks_subsystem_fbus_0_clock(chipyardPRCI_1_auto_in_member_allClocks_subsystem_fbus_0_clock),
+ .auto_in_member_allClocks_subsystem_fbus_0_reset(chipyardPRCI_1_auto_in_member_allClocks_subsystem_fbus_0_reset),
+ .auto_in_member_allClocks_subsystem_pbus_0_clock(chipyardPRCI_1_auto_in_member_allClocks_subsystem_pbus_0_clock),
+ .auto_in_member_allClocks_subsystem_pbus_0_reset(chipyardPRCI_1_auto_in_member_allClocks_subsystem_pbus_0_reset),
+ .auto_in_member_allClocks_subsystem_sbus_0_clock(chipyardPRCI_1_auto_in_member_allClocks_subsystem_sbus_0_clock),
+ .auto_in_member_allClocks_subsystem_sbus_0_reset(chipyardPRCI_1_auto_in_member_allClocks_subsystem_sbus_0_reset),
+ .auto_out_4_member_chipyardPRCI_implicit_clock_clock(
+ chipyardPRCI_1_auto_out_4_member_chipyardPRCI_implicit_clock_clock),
+ .auto_out_4_member_chipyardPRCI_implicit_clock_reset(
+ chipyardPRCI_1_auto_out_4_member_chipyardPRCI_implicit_clock_reset),
+ .auto_out_3_member_subsystem_cbus_subsystem_cbus_0_clock(
+ chipyardPRCI_1_auto_out_3_member_subsystem_cbus_subsystem_cbus_0_clock),
+ .auto_out_3_member_subsystem_cbus_subsystem_cbus_0_reset(
+ chipyardPRCI_1_auto_out_3_member_subsystem_cbus_subsystem_cbus_0_reset),
+ .auto_out_2_member_subsystem_fbus_subsystem_fbus_0_clock(
+ chipyardPRCI_1_auto_out_2_member_subsystem_fbus_subsystem_fbus_0_clock),
+ .auto_out_2_member_subsystem_fbus_subsystem_fbus_0_reset(
+ chipyardPRCI_1_auto_out_2_member_subsystem_fbus_subsystem_fbus_0_reset),
+ .auto_out_1_member_subsystem_pbus_subsystem_pbus_0_clock(
+ chipyardPRCI_1_auto_out_1_member_subsystem_pbus_subsystem_pbus_0_clock),
+ .auto_out_1_member_subsystem_pbus_subsystem_pbus_0_reset(
+ chipyardPRCI_1_auto_out_1_member_subsystem_pbus_subsystem_pbus_0_reset),
+ .auto_out_0_member_subsystem_sbus_subsystem_sbus_0_clock(
+ chipyardPRCI_1_auto_out_0_member_subsystem_sbus_subsystem_sbus_0_clock),
+ .auto_out_0_member_subsystem_sbus_subsystem_sbus_0_reset(
+ chipyardPRCI_1_auto_out_0_member_subsystem_sbus_subsystem_sbus_0_reset)
+ );
+ ClockGroupParameterModifier chipyardPRCI_2 ( // @[ClockGroupNamePrefixer.scala 45:15]
+ .auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_clock(
+ chipyardPRCI_2_auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_clock),
+ .auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_reset(
+ chipyardPRCI_2_auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_reset),
+ .auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_clock(
+ chipyardPRCI_2_auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_clock),
+ .auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_reset(
+ chipyardPRCI_2_auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_reset),
+ .auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_clock(
+ chipyardPRCI_2_auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_clock),
+ .auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_reset(
+ chipyardPRCI_2_auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_reset),
+ .auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_clock(
+ chipyardPRCI_2_auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_clock),
+ .auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_reset(
+ chipyardPRCI_2_auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_reset),
+ .auto_chipyard_prci_out_3_member_subsystem_cbus_0_clock(
+ chipyardPRCI_2_auto_chipyard_prci_out_3_member_subsystem_cbus_0_clock),
+ .auto_chipyard_prci_out_3_member_subsystem_cbus_0_reset(
+ chipyardPRCI_2_auto_chipyard_prci_out_3_member_subsystem_cbus_0_reset),
+ .auto_chipyard_prci_out_2_member_subsystem_fbus_0_clock(
+ chipyardPRCI_2_auto_chipyard_prci_out_2_member_subsystem_fbus_0_clock),
+ .auto_chipyard_prci_out_2_member_subsystem_fbus_0_reset(
+ chipyardPRCI_2_auto_chipyard_prci_out_2_member_subsystem_fbus_0_reset),
+ .auto_chipyard_prci_out_1_member_subsystem_pbus_0_clock(
+ chipyardPRCI_2_auto_chipyard_prci_out_1_member_subsystem_pbus_0_clock),
+ .auto_chipyard_prci_out_1_member_subsystem_pbus_0_reset(
+ chipyardPRCI_2_auto_chipyard_prci_out_1_member_subsystem_pbus_0_reset),
+ .auto_chipyard_prci_out_0_member_subsystem_sbus_0_clock(
+ chipyardPRCI_2_auto_chipyard_prci_out_0_member_subsystem_sbus_0_clock),
+ .auto_chipyard_prci_out_0_member_subsystem_sbus_0_reset(
+ chipyardPRCI_2_auto_chipyard_prci_out_0_member_subsystem_sbus_0_reset)
+ );
+ ClockGroupParameterModifier_1 chipyardPRCI_3 ( // @[ClockGroupNamePrefixer.scala 81:15]
+ .auto_chipyard_prci_in_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_implicit_clock_clock),
+ .auto_chipyard_prci_in_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_implicit_clock_reset),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock),
+ .auto_chipyard_prci_out_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset)
+ );
+ ClockGroupParameterModifier_1 chipyardPRCI_4 ( // @[ClockGroupCombiner.scala 19:15]
+ .auto_chipyard_prci_in_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_implicit_clock_clock),
+ .auto_chipyard_prci_in_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_implicit_clock_reset),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_implicit_clock_clock(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock),
+ .auto_chipyard_prci_out_member_allClocks_implicit_clock_reset(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset(
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset)
+ );
+ ClockGroupResetSynchronizer chipyardPRCI_5 ( // @[ResetSynchronizer.scala 42:69]
+ .auto_in_member_allClocks_implicit_clock_clock(chipyardPRCI_5_auto_in_member_allClocks_implicit_clock_clock),
+ .auto_in_member_allClocks_implicit_clock_reset(chipyardPRCI_5_auto_in_member_allClocks_implicit_clock_reset),
+ .auto_in_member_allClocks_subsystem_cbus_0_clock(chipyardPRCI_5_auto_in_member_allClocks_subsystem_cbus_0_clock),
+ .auto_in_member_allClocks_subsystem_cbus_0_reset(chipyardPRCI_5_auto_in_member_allClocks_subsystem_cbus_0_reset),
+ .auto_in_member_allClocks_subsystem_fbus_0_clock(chipyardPRCI_5_auto_in_member_allClocks_subsystem_fbus_0_clock),
+ .auto_in_member_allClocks_subsystem_fbus_0_reset(chipyardPRCI_5_auto_in_member_allClocks_subsystem_fbus_0_reset),
+ .auto_in_member_allClocks_subsystem_pbus_0_clock(chipyardPRCI_5_auto_in_member_allClocks_subsystem_pbus_0_clock),
+ .auto_in_member_allClocks_subsystem_pbus_0_reset(chipyardPRCI_5_auto_in_member_allClocks_subsystem_pbus_0_reset),
+ .auto_in_member_allClocks_subsystem_sbus_0_clock(chipyardPRCI_5_auto_in_member_allClocks_subsystem_sbus_0_clock),
+ .auto_in_member_allClocks_subsystem_sbus_0_reset(chipyardPRCI_5_auto_in_member_allClocks_subsystem_sbus_0_reset),
+ .auto_out_member_allClocks_implicit_clock_clock(chipyardPRCI_5_auto_out_member_allClocks_implicit_clock_clock),
+ .auto_out_member_allClocks_implicit_clock_reset(chipyardPRCI_5_auto_out_member_allClocks_implicit_clock_reset),
+ .auto_out_member_allClocks_subsystem_cbus_0_clock(chipyardPRCI_5_auto_out_member_allClocks_subsystem_cbus_0_clock),
+ .auto_out_member_allClocks_subsystem_cbus_0_reset(chipyardPRCI_5_auto_out_member_allClocks_subsystem_cbus_0_reset),
+ .auto_out_member_allClocks_subsystem_fbus_0_clock(chipyardPRCI_5_auto_out_member_allClocks_subsystem_fbus_0_clock),
+ .auto_out_member_allClocks_subsystem_fbus_0_reset(chipyardPRCI_5_auto_out_member_allClocks_subsystem_fbus_0_reset),
+ .auto_out_member_allClocks_subsystem_pbus_0_clock(chipyardPRCI_5_auto_out_member_allClocks_subsystem_pbus_0_clock),
+ .auto_out_member_allClocks_subsystem_pbus_0_reset(chipyardPRCI_5_auto_out_member_allClocks_subsystem_pbus_0_reset),
+ .auto_out_member_allClocks_subsystem_sbus_0_clock(chipyardPRCI_5_auto_out_member_allClocks_subsystem_sbus_0_clock),
+ .auto_out_member_allClocks_subsystem_sbus_0_reset(chipyardPRCI_5_auto_out_member_allClocks_subsystem_sbus_0_reset)
+ );
+ DebugTransportModuleJTAG dtm ( // @[Periphery.scala 161:21]
+ .io_jtag_clock(dtm_io_jtag_clock),
+ .io_jtag_reset(dtm_io_jtag_reset),
+ .io_dmi_req_ready(dtm_io_dmi_req_ready),
+ .io_dmi_req_valid(dtm_io_dmi_req_valid),
+ .io_dmi_req_bits_addr(dtm_io_dmi_req_bits_addr),
+ .io_dmi_req_bits_data(dtm_io_dmi_req_bits_data),
+ .io_dmi_req_bits_op(dtm_io_dmi_req_bits_op),
+ .io_dmi_resp_ready(dtm_io_dmi_resp_ready),
+ .io_dmi_resp_valid(dtm_io_dmi_resp_valid),
+ .io_dmi_resp_bits_data(dtm_io_dmi_resp_bits_data),
+ .io_dmi_resp_bits_resp(dtm_io_dmi_resp_bits_resp),
+ .io_jtag_TMS(dtm_io_jtag_TMS),
+ .io_jtag_TDI(dtm_io_jtag_TDI),
+ .io_jtag_TDO_data(dtm_io_jtag_TDO_data)
+ );
+ assign auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_clock =
+ chipyardPRCI_1_auto_out_4_member_chipyardPRCI_implicit_clock_clock; // @[LazyModule.scala 311:12]
+ assign auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_reset =
+ chipyardPRCI_1_auto_out_4_member_chipyardPRCI_implicit_clock_reset; // @[LazyModule.scala 311:12]
+ assign auto_subsystem_cbus_fixedClockNode_out_clock = subsystem_cbus_auto_fixedClockNode_out_4_clock; // @[LazyModule.scala 311:12]
+ assign auto_subsystem_cbus_fixedClockNode_out_reset = subsystem_cbus_auto_fixedClockNode_out_4_reset; // @[LazyModule.scala 311:12]
+ assign serial_tl_clock = domain_clock; // @[SerialAdapter.scala 408:22]
+ assign serial_tl_bits_in_ready = domain_serial_tl_in_ready; // @[SerialAdapter.scala 407:21]
+ assign serial_tl_bits_out_valid = domain_serial_tl_out_valid; // @[SerialAdapter.scala 407:21]
+ assign serial_tl_bits_out_bits = domain_serial_tl_out_bits; // @[SerialAdapter.scala 407:21]
+ assign debug_systemjtag_jtag_TDO_data = dtm_io_jtag_TDO_data; // @[Periphery.scala 162:17]
+ assign debug_dmactive = debug_1_io_ctrl_dmactive; // @[Periphery.scala 147:20]
+ assign uart_0_txd = uartClockDomainWrapper_auto_uart_0_io_out_txd; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign uart_1_txd = uartClockDomainWrapper_1_auto_uart_1_io_out_txd; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_0_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_0_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_0_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_1_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_1_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_1_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_2_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_2_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_2_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_3_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_3_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpio_0_pins_3_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_sck = qspiClockDomainWrapper_auto_qspi_0_io_out_sck; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_dq_0_o = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_dq_0_oe = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_dq_1_o = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_dq_1_oe = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_dq_2_o = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_dq_2_oe = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_dq_3_o = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_dq_3_oe = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_0_cs_0 = qspiClockDomainWrapper_auto_qspi_0_io_out_cs_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_sck = qspiClockDomainWrapper_1_auto_qspi_1_io_out_sck; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_dq_0_o = qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_dq_0_oe = qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_dq_1_o = qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_dq_1_oe = qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_dq_2_o = qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_dq_2_oe = qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_dq_3_o = qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_dq_3_oe = qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspi_1_cs_0 = qspiClockDomainWrapper_1_auto_qspi_1_io_out_cs_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign ibus_auto_int_bus_int_in_4_0 = intsink_8_auto_out_0; // @[LazyModule.scala 296:16]
+ assign ibus_auto_int_bus_int_in_3_0 = intsink_7_auto_out_0; // @[LazyModule.scala 296:16]
+ assign ibus_auto_int_bus_int_in_2_0 = intsink_6_auto_out_0; // @[LazyModule.scala 296:16]
+ assign ibus_auto_int_bus_int_in_2_1 = intsink_6_auto_out_1; // @[LazyModule.scala 296:16]
+ assign ibus_auto_int_bus_int_in_2_2 = intsink_6_auto_out_2; // @[LazyModule.scala 296:16]
+ assign ibus_auto_int_bus_int_in_2_3 = intsink_6_auto_out_3; // @[LazyModule.scala 296:16]
+ assign ibus_auto_int_bus_int_in_1_0 = intsink_5_auto_out_0; // @[LazyModule.scala 296:16]
+ assign ibus_auto_int_bus_int_in_0_0 = intsink_4_auto_out_0; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_valid =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt =
+ tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_ready =
+ tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_valid =
+ subsystem_fbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_opcode =
+ subsystem_fbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_param =
+ subsystem_fbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_size =
+ subsystem_fbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_source =
+ subsystem_fbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_address =
+ subsystem_fbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_mask =
+ subsystem_fbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_data =
+ subsystem_fbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_bits_corrupt =
+ subsystem_fbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_ready =
+ subsystem_fbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready =
+ subsystem_cbus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid =
+ subsystem_cbus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode =
+ subsystem_cbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param =
+ subsystem_cbus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size =
+ subsystem_cbus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source =
+ subsystem_cbus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink =
+ subsystem_cbus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied =
+ subsystem_cbus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data =
+ subsystem_cbus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt =
+ subsystem_cbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock =
+ chipyardPRCI_2_auto_chipyard_prci_out_0_member_subsystem_sbus_0_clock; // @[LazyModule.scala 296:16]
+ assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset =
+ chipyardPRCI_2_auto_chipyard_prci_out_0_member_subsystem_sbus_0_reset; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_ready =
+ qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_valid =
+ qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_size =
+ qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_source =
+ qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_bits_data =
+ qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_ready =
+ qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_valid =
+ qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_opcode =
+ qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_size =
+ qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_source =
+ qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_bits_data =
+ qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready =
+ qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid =
+ qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size =
+ qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source =
+ qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data =
+ qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready =
+ qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid =
+ qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode =
+ qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size =
+ qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source =
+ qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data =
+ qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready =
+ gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid =
+ gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode =
+ gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size =
+ gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source =
+ gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data =
+ gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_ready =
+ uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_valid =
+ uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode =
+ uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size =
+ uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source =
+ uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data =
+ uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_ready =
+ uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_valid =
+ uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode =
+ uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size =
+ uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source =
+ uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data =
+ uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_ready =
+ domain_auto_tlserial_manager_crossing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_valid =
+ domain_auto_tlserial_manager_crossing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_opcode =
+ domain_auto_tlserial_manager_crossing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_param =
+ domain_auto_tlserial_manager_crossing_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_size =
+ domain_auto_tlserial_manager_crossing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_source =
+ domain_auto_tlserial_manager_crossing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_sink =
+ domain_auto_tlserial_manager_crossing_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_denied =
+ domain_auto_tlserial_manager_crossing_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_data =
+ domain_auto_tlserial_manager_crossing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_bits_corrupt =
+ domain_auto_tlserial_manager_crossing_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock =
+ chipyardPRCI_2_auto_chipyard_prci_out_1_member_subsystem_pbus_0_clock; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset =
+ chipyardPRCI_2_auto_chipyard_prci_out_1_member_subsystem_pbus_0_reset; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_valid =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_bits_opcode =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_bits_param =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_bits_size =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_bits_source =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_bits_address =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_bits_mask =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_bits_data =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_a_bits_corrupt =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign subsystem_pbus_auto_bus_xing_in_d_ready =
+ subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_valid =
+ domain_auto_serdesser_client_out_a_valid; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_opcode =
+ domain_auto_serdesser_client_out_a_bits_opcode; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_param =
+ domain_auto_serdesser_client_out_a_bits_param; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_size =
+ domain_auto_serdesser_client_out_a_bits_size; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_source =
+ domain_auto_serdesser_client_out_a_bits_source; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_address =
+ domain_auto_serdesser_client_out_a_bits_address; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_mask =
+ domain_auto_serdesser_client_out_a_bits_mask; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_data =
+ domain_auto_serdesser_client_out_a_bits_data; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_bits_corrupt =
+ domain_auto_serdesser_client_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_ready =
+ domain_auto_serdesser_client_out_d_ready; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock =
+ chipyardPRCI_2_auto_chipyard_prci_out_2_member_subsystem_fbus_0_clock; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset =
+ chipyardPRCI_2_auto_chipyard_prci_out_2_member_subsystem_fbus_0_reset; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_a_ready =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_a_ready; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_d_valid =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_valid; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_d_bits_opcode =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_d_bits_param =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_d_bits_size =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_d_bits_sink =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_d_bits_denied =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_d_bits_data =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign subsystem_fbus_auto_bus_xing_out_d_bits_corrupt =
+ subsystem_sbus_auto_coupler_from_bus_named_subsystem_fbus_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_ready =
+ chipyardPRCI_auto_chipyardPRCI_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_valid =
+ chipyardPRCI_auto_chipyardPRCI_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_opcode =
+ chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_size =
+ chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_source =
+ chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_bits_data =
+ chipyardPRCI_auto_chipyardPRCI_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_ready =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_valid =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_opcode =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_size =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_source =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_bits_data =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready = bootROMDomainWrapper_auto_bootrom_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid = bootROMDomainWrapper_auto_bootrom_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size =
+ bootROMDomainWrapper_auto_bootrom_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source =
+ bootROMDomainWrapper_auto_bootrom_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data =
+ bootROMDomainWrapper_auto_bootrom_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt =
+ tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_ready = debug_1_auto_dmInner_dmInner_tl_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_valid = debug_1_auto_dmInner_dmInner_tl_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode =
+ debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size =
+ debug_1_auto_dmInner_dmInner_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source =
+ debug_1_auto_dmInner_dmInner_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data =
+ debug_1_auto_dmInner_dmInner_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_ready = clint_auto_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_valid = clint_auto_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode = clint_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size = clint_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source = clint_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data = clint_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_ready = plicDomainWrapper_auto_plic_in_a_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_valid = plicDomainWrapper_auto_plic_in_d_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode = plicDomainWrapper_auto_plic_in_d_bits_opcode
+ ; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size = plicDomainWrapper_auto_plic_in_d_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source = plicDomainWrapper_auto_plic_in_d_bits_source
+ ; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data = plicDomainWrapper_auto_plic_in_d_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready =
+ subsystem_pbus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid =
+ subsystem_pbus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode =
+ subsystem_pbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param =
+ subsystem_pbus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size =
+ subsystem_pbus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source =
+ subsystem_pbus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink =
+ subsystem_pbus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied =
+ subsystem_pbus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data =
+ subsystem_pbus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt =
+ subsystem_pbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock =
+ chipyardPRCI_2_auto_chipyard_prci_out_3_member_subsystem_cbus_0_clock; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset =
+ chipyardPRCI_2_auto_chipyard_prci_out_3_member_subsystem_cbus_0_reset; // @[LazyModule.scala 296:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_valid =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_bits_opcode =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_bits_param =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_bits_size =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_bits_source =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_bits_address =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_bits_mask =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_bits_data =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_a_bits_corrupt =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_auto_bus_xing_in_d_ready =
+ subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign subsystem_cbus_custom_boot = custom_boot; // @[CustomBootPin.scala 81:16]
+ assign tile_prci_domain_auto_intsink_in_sync_0 = debug_1_auto_dmOuter_intsource_out_sync_0; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tile_reset_domain_tile_hartid_in = tileHartIdNexusNode_auto_out; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_int_in_clock_xing_in_1_sync_0 = intsource_1_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_int_in_clock_xing_in_0_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_int_in_clock_xing_in_0_sync_1 = intsource_auto_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_valid =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_opcode =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_param =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_size =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_source =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_address =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_mask =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_data =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_slave_clock_xing_in_d_ready =
+ subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_a_ready =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_ready; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_valid =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_valid; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_opcode =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_param =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_size =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_source =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_sink =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_denied =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_data =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_corrupt =
+ subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign tile_prci_domain_auto_tap_clock_in_clock = subsystem_sbus_auto_fixedClockNode_out_1_clock; // @[LazyModule.scala 298:16]
+ assign tile_prci_domain_auto_tap_clock_in_reset = subsystem_sbus_auto_fixedClockNode_out_1_reset; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_int_in_0 = ibus_auto_int_bus_int_out_0; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_int_in_1 = ibus_auto_int_bus_int_out_1; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_int_in_2 = ibus_auto_int_bus_int_out_2; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_int_in_3 = ibus_auto_int_bus_int_out_3; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_int_in_4 = ibus_auto_int_bus_int_out_4; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_int_in_5 = ibus_auto_int_bus_int_out_5; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_int_in_6 = ibus_auto_int_bus_int_out_6; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_int_in_7 = ibus_auto_int_bus_int_out_7; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_valid = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_bits_opcode = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode
+ ; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_bits_param = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_bits_size = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_bits_source = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source
+ ; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_bits_address =
+ subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_bits_mask = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_bits_data = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_a_bits_corrupt =
+ subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_plic_in_d_ready = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_clock_in_clock = subsystem_cbus_auto_fixedClockNode_out_0_clock; // @[LazyModule.scala 298:16]
+ assign plicDomainWrapper_auto_clock_in_reset = subsystem_cbus_auto_fixedClockNode_out_0_reset; // @[LazyModule.scala 298:16]
+ assign clint_clock = subsystem_cbus_clock; // @[CLINT.scala 115:26]
+ assign clint_reset = subsystem_cbus_reset; // @[CLINT.scala 116:26]
+ assign clint_auto_in_a_valid = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_a_bits_opcode = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_a_bits_param = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_a_bits_size = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_a_bits_source = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_a_bits_address = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_a_bits_mask = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_a_bits_data = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_a_bits_corrupt = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign clint_auto_in_d_ready = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready; // @[LazyModule.scala 298:16]
+ assign clint_io_rtcTick = int_rtc_tick_value == 7'h63; // @[Counter.scala 74:24]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_valid = subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode =
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_param =
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_size =
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_source =
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_address =
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask =
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_data =
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt =
+ subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign debug_1_auto_dmInner_dmInner_tl_in_d_ready = subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready; // @[LazyModule.scala 298:16]
+ assign debug_1_io_debug_clock = debug_clock; // @[Periphery.scala 144:38]
+ assign debug_1_io_debug_reset = debug_reset; // @[Periphery.scala 143:38]
+ assign debug_1_io_ctrl_dmactiveAck = debug_dmactiveAck; // @[Periphery.scala 148:43]
+ assign debug_1_io_dmi_dmi_req_valid = dtm_io_dmi_req_valid; // @[Periphery.scala 174:40]
+ assign debug_1_io_dmi_dmi_req_bits_addr = dtm_io_dmi_req_bits_addr; // @[Periphery.scala 174:40]
+ assign debug_1_io_dmi_dmi_req_bits_data = dtm_io_dmi_req_bits_data; // @[Periphery.scala 174:40]
+ assign debug_1_io_dmi_dmi_req_bits_op = dtm_io_dmi_req_bits_op; // @[Periphery.scala 174:40]
+ assign debug_1_io_dmi_dmi_resp_ready = dtm_io_dmi_resp_ready; // @[Periphery.scala 174:40]
+ assign debug_1_io_dmi_dmiClock = debug_systemjtag_jtag_TCK; // @[Periphery.scala 175:45]
+ assign debug_1_io_dmi_dmiReset = debug_systemjtag_reset; // @[Periphery.scala 176:45]
+ assign debug_1_io_hartIsInReset_0 = resetctrl_hartIsInReset_0; // @[Periphery.scala 113:40]
+ assign intsource_clock = clock;
+ assign intsource_reset = reset;
+ assign intsource_auto_in_0 = clint_auto_int_out_0; // @[LazyModule.scala 298:16]
+ assign intsource_auto_in_1 = clint_auto_int_out_1; // @[LazyModule.scala 298:16]
+ assign intsource_1_clock = clock;
+ assign intsource_1_reset = reset;
+ assign intsource_1_auto_in_0 = plicDomainWrapper_auto_plic_int_out_0; // @[LazyModule.scala 298:16]
+ assign intsink_1_auto_in_sync_0 = tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign intsink_2_auto_in_sync_0 = tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign intsink_3_auto_in_sync_0 = tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_a_valid = subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_a_bits_opcode =
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_a_bits_param =
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_a_bits_size =
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_a_bits_source =
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_a_bits_address =
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_a_bits_mask =
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_a_bits_corrupt =
+ subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_bootrom_in_d_ready = subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_clock_in_clock = subsystem_cbus_auto_fixedClockNode_out_2_clock; // @[LazyModule.scala 298:16]
+ assign bootROMDomainWrapper_auto_clock_in_reset = subsystem_cbus_auto_fixedClockNode_out_2_reset; // @[LazyModule.scala 298:16]
+ assign domain_auto_serdesser_client_out_a_ready =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_a_ready; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_valid =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_valid; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_bits_opcode =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_opcode; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_bits_param =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_param; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_bits_size =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_size; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_bits_source =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_source; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_bits_sink =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_sink; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_bits_denied =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_denied; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_bits_data =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_data; // @[LazyModule.scala 296:16]
+ assign domain_auto_serdesser_client_out_d_bits_corrupt =
+ subsystem_fbus_auto_coupler_from_port_named_serial_tl_ctrl_buffer_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_valid =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_bits_opcode =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_bits_param =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_bits_size =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_bits_source =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_bits_address =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_bits_mask =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_bits_data =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_a_bits_corrupt =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign domain_auto_tlserial_manager_crossing_in_d_ready =
+ subsystem_pbus_auto_coupler_to_port_named_serial_tl_mem_tlserial_manager_crossing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign domain_auto_clock_in_clock = subsystem_fbus_auto_fixedClockNode_out_clock; // @[LazyModule.scala 298:16]
+ assign domain_auto_clock_in_reset = subsystem_fbus_auto_fixedClockNode_out_reset; // @[LazyModule.scala 298:16]
+ assign domain_serial_tl_in_valid = serial_tl_bits_in_valid; // @[SerialAdapter.scala 407:21]
+ assign domain_serial_tl_in_bits = serial_tl_bits_in_bits; // @[SerialAdapter.scala 407:21]
+ assign domain_serial_tl_out_ready = serial_tl_bits_out_ready; // @[SerialAdapter.scala 407:21]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_valid =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_opcode =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_param =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_size =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_source =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_address =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_mask =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_data =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_corrupt =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_control_xing_in_d_ready =
+ subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_uart_0_io_out_rxd = uart_0_rxd; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign uartClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_0_clock; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_0_reset; // @[LazyModule.scala 298:16]
+ assign intsink_4_auto_in_sync_0 = uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_valid =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_opcode =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_param =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_size =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_source =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_address =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_mask =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_data =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_corrupt =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_ready =
+ subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_uart_1_io_out_rxd = uart_1_rxd; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign uartClockDomainWrapper_1_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_1_clock; // @[LazyModule.scala 298:16]
+ assign uartClockDomainWrapper_1_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_1_reset; // @[LazyModule.scala 298:16]
+ assign intsink_5_auto_in_sync_0 = uartClockDomainWrapper_1_auto_uart_1_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_valid =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_opcode =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_param =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_size =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_source =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_address =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_mask =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_data =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_corrupt =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_ready =
+ subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_i_ival = gpio_0_pins_0_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_i_ival = gpio_0_pins_1_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_i_ival = gpio_0_pins_2_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_i_ival = gpio_0_pins_3_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign gpioClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_2_clock; // @[LazyModule.scala 298:16]
+ assign gpioClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_2_reset; // @[LazyModule.scala 298:16]
+ assign intsink_6_auto_in_sync_0 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign intsink_6_auto_in_sync_1 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign intsink_6_auto_in_sync_2 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign intsink_6_auto_in_sync_3 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_valid =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_opcode =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_param =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_size =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_source =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_address =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_mask =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_corrupt =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_ready =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_valid =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_opcode =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_param =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_size =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_source =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_address =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_mask =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_data =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_corrupt =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_ready =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_i = qspi_0_dq_0_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_i = qspi_0_dq_1_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_i = qspi_0_dq_2_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_i = qspi_0_dq_3_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign qspiClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_3_clock; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_3_reset; // @[LazyModule.scala 298:16]
+ assign intsink_7_auto_in_sync_0 = qspiClockDomainWrapper_auto_qspi_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_valid =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_opcode =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_param =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_size =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_source =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_address =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_mask =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_a_bits_corrupt =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_mem_xing_in_d_ready =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_mem_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_valid =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_opcode =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_param =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_size =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_source =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_address =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_mask =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_data =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_a_bits_corrupt =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_control_xing_in_d_ready =
+ subsystem_pbus_auto_coupler_to_device_named_qspi_1_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_0_i = qspi_1_dq_0_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_1_i = qspi_1_dq_1_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_2_i = qspi_1_dq_2_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign qspiClockDomainWrapper_1_auto_qspi_1_io_out_dq_3_i = qspi_1_dq_3_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
+ assign qspiClockDomainWrapper_1_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_4_clock; // @[LazyModule.scala 298:16]
+ assign qspiClockDomainWrapper_1_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_4_reset; // @[LazyModule.scala 298:16]
+ assign intsink_8_auto_in_sync_0 = qspiClockDomainWrapper_1_auto_qspi_1_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset =
+ auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 309:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_valid =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_valid; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_opcode =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_param =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_size =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_source =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_address =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_mask =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_data =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_a_bits_corrupt =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_tl_in_d_ready =
+ subsystem_cbus_auto_coupler_to_slave_named_tileresetsetter_buffer_out_d_ready; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_valid =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_valid; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_opcode =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_opcode; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_param =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_param; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_size =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_size; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_source =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_source; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_address =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_address; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_mask =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_mask; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_data =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_data; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_a_bits_corrupt =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_chipyardPRCI_chipyard_prci_in_d_ready =
+ subsystem_cbus_auto_coupler_to_slave_named_clockgater_buffer_out_d_ready; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_clock_in_clock = subsystem_cbus_auto_fixedClockNode_out_3_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_clock_in_reset = subsystem_cbus_auto_fixedClockNode_out_3_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_implicit_clock_clock =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_implicit_clock_reset =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_subsystem_cbus_0_clock =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_subsystem_cbus_0_reset =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_subsystem_fbus_0_clock =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_subsystem_fbus_0_reset =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_subsystem_pbus_0_clock =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_subsystem_pbus_0_reset =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_subsystem_sbus_0_clock =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_1_auto_in_member_allClocks_subsystem_sbus_0_reset =
+ chipyardPRCI_3_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_2_auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_clock =
+ chipyardPRCI_1_auto_out_3_member_subsystem_cbus_subsystem_cbus_0_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_2_auto_chipyard_prci_in_3_member_subsystem_cbus_subsystem_cbus_0_reset =
+ chipyardPRCI_1_auto_out_3_member_subsystem_cbus_subsystem_cbus_0_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_2_auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_clock =
+ chipyardPRCI_1_auto_out_2_member_subsystem_fbus_subsystem_fbus_0_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_2_auto_chipyard_prci_in_2_member_subsystem_fbus_subsystem_fbus_0_reset =
+ chipyardPRCI_1_auto_out_2_member_subsystem_fbus_subsystem_fbus_0_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_2_auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_clock =
+ chipyardPRCI_1_auto_out_1_member_subsystem_pbus_subsystem_pbus_0_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_2_auto_chipyard_prci_in_1_member_subsystem_pbus_subsystem_pbus_0_reset =
+ chipyardPRCI_1_auto_out_1_member_subsystem_pbus_subsystem_pbus_0_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_2_auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_clock =
+ chipyardPRCI_1_auto_out_0_member_subsystem_sbus_subsystem_sbus_0_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_2_auto_chipyard_prci_in_0_member_subsystem_sbus_subsystem_sbus_0_reset =
+ chipyardPRCI_1_auto_out_0_member_subsystem_sbus_subsystem_sbus_0_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_implicit_clock_clock =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_implicit_clock_reset =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_3_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset =
+ chipyardPRCI_4_auto_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_implicit_clock_clock =
+ chipyardPRCI_5_auto_out_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_implicit_clock_reset =
+ chipyardPRCI_5_auto_out_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_clock =
+ chipyardPRCI_5_auto_out_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_cbus_0_reset =
+ chipyardPRCI_5_auto_out_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_clock =
+ chipyardPRCI_5_auto_out_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_fbus_0_reset =
+ chipyardPRCI_5_auto_out_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_clock =
+ chipyardPRCI_5_auto_out_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_pbus_0_reset =
+ chipyardPRCI_5_auto_out_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_clock =
+ chipyardPRCI_5_auto_out_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_4_auto_chipyard_prci_in_member_allClocks_subsystem_sbus_0_reset =
+ chipyardPRCI_5_auto_out_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 296:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_implicit_clock_clock =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_implicit_clock_reset =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_subsystem_cbus_0_clock =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_subsystem_cbus_0_reset =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_subsystem_fbus_0_clock =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_subsystem_fbus_0_reset =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_subsystem_pbus_0_clock =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_subsystem_pbus_0_reset =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_subsystem_sbus_0_clock =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_5_auto_in_member_allClocks_subsystem_sbus_0_reset =
+ chipyardPRCI_auto_chipyardPRCI_chipyard_prci_out_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 298:16]
+ assign dtm_io_jtag_clock = debug_systemjtag_jtag_TCK; // @[Periphery.scala 166:24]
+ assign dtm_io_jtag_reset = debug_systemjtag_reset; // @[Periphery.scala 167:24]
+ assign dtm_io_dmi_req_ready = debug_1_io_dmi_dmi_req_ready; // @[Periphery.scala 174:40]
+ assign dtm_io_dmi_resp_valid = debug_1_io_dmi_dmi_resp_valid; // @[Periphery.scala 174:40]
+ assign dtm_io_dmi_resp_bits_data = debug_1_io_dmi_dmi_resp_bits_data; // @[Periphery.scala 174:40]
+ assign dtm_io_dmi_resp_bits_resp = debug_1_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala 174:40]
+ assign dtm_io_jtag_TMS = debug_systemjtag_jtag_TMS; // @[Periphery.scala 162:17]
+ assign dtm_io_jtag_TDI = debug_systemjtag_jtag_TDI; // @[Periphery.scala 162:17]
+ always @(posedge subsystem_pbus_clock) begin
+ if (subsystem_pbus_reset) begin // @[Counter.scala 62:40]
+ int_rtc_tick_value <= 7'h0; // @[Counter.scala 62:40]
+ end else if (int_rtc_tick_wrap_wrap) begin // @[Counter.scala 88:20]
+ int_rtc_tick_value <= 7'h0; // @[Counter.scala 88:28]
+ end else begin
+ int_rtc_tick_value <= _int_rtc_tick_wrap_value_T_1; // @[Counter.scala 78:15]
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ int_rtc_tick_value = _RAND_0[6:0];
+`endif // RANDOMIZE_REG_INIT
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module ClockGroup_4(
+ input auto_in_member_chipyardPRCI_implicit_clock_clock,
+ input auto_in_member_chipyardPRCI_implicit_clock_reset,
+ output auto_out_clock,
+ output auto_out_reset
+);
+ assign auto_out_clock = auto_in_member_chipyardPRCI_implicit_clock_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_out_reset = auto_in_member_chipyardPRCI_implicit_clock_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module DividerOnlyClockGenerator(
+ input auto_divider_only_clock_gen_in_clock,
+ input auto_divider_only_clock_gen_in_reset,
+ output auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_clock,
+ output auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_reset,
+ output auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_clock,
+ output auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_reset,
+ output auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_clock,
+ output auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_reset,
+ output auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_clock,
+ output auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_reset,
+ output auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_clock,
+ output auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_reset
+);
+ wire bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_out; // @[DividerOnlyClockGenerator.scala 133:27]
+ wire bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_in; // @[DividerOnlyClockGenerator.scala 133:27]
+ ClockDividerN #(.DIV(1)) bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1 ( // @[DividerOnlyClockGenerator.scala 133:27]
+ .clk_out(bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_out),
+ .clk_in(bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_in)
+ );
+ assign auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_clock =
+ bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_out; // @[Nodes.scala 1207:84 DividerOnlyClockGenerator.scala 142:19]
+ assign auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_reset = auto_divider_only_clock_gen_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_clock =
+ bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_out; // @[Nodes.scala 1207:84 DividerOnlyClockGenerator.scala 142:19]
+ assign auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_reset = auto_divider_only_clock_gen_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_clock =
+ bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_out; // @[Nodes.scala 1207:84 DividerOnlyClockGenerator.scala 142:19]
+ assign auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_reset = auto_divider_only_clock_gen_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_clock =
+ bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_out; // @[Nodes.scala 1207:84 DividerOnlyClockGenerator.scala 142:19]
+ assign auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_reset = auto_divider_only_clock_gen_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_clock =
+ bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_out; // @[Nodes.scala 1207:84 DividerOnlyClockGenerator.scala 142:19]
+ assign auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_reset = auto_divider_only_clock_gen_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+ assign bundleOut_0_member_allClocks_subsystem_sbus_0_clock_ClockDivideBy1_clk_in =
+ auto_divider_only_clock_gen_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
+endmodule
+module ResetSynchronizerShiftReg_w1_d3_i0(
+ input clock,
+ input reset,
+ input io_d,
+ output io_q
+);
+ wire output_chain_clock; // @[ShiftReg.scala 45:23]
+ wire output_chain_reset; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_d; // @[ShiftReg.scala 45:23]
+ wire output_chain_io_q; // @[ShiftReg.scala 45:23]
+ AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
+ .clock(output_chain_clock),
+ .reset(output_chain_reset),
+ .io_d(output_chain_io_d),
+ .io_q(output_chain_io_q)
+ );
+ assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
+ assign output_chain_clock = clock;
+ assign output_chain_reset = reset;
+ assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 147:39]
+endmodule
+module ChipTop(
+`ifdef USE_POWER_PINS //added for Openlane check
+ inout vccd1, // User area 1 1.8V power
+ inout vssd1, // User area 1 digital ground
+`endif
+ output [37:0] io_oeb, // Caravel OEB pins
+ input jtag_TCK,
+ input jtag_TMS,
+ input jtag_TDI,
+ output jtag_TDO,
+ output serial_tl_clock,
+ output serial_tl_bits_in_ready,
+ input serial_tl_bits_in_valid,
+ input [31:0] serial_tl_bits_in_bits,
+ input serial_tl_bits_out_ready,
+ output serial_tl_bits_out_valid,
+ output [31:0] serial_tl_bits_out_bits,
+ input custom_boot,
+ input clock_clock,
+ input reset,
+ inout gpio_0_0,
+ inout gpio_0_1,
+ inout gpio_0_2,
+ inout gpio_0_3,
+ output spi_0_sck,
+ output spi_0_cs_0,
+ inout spi_0_dq_0,
+ inout spi_0_dq_1,
+ inout spi_0_dq_2,
+ inout spi_0_dq_3,
+ output spi_1_sck,
+ output spi_1_cs_0,
+ inout spi_1_dq_0,
+ inout spi_1_dq_1,
+ inout spi_1_dq_2,
+ inout spi_1_dq_3,
+ output uart_0_txd,
+ input uart_0_rxd,
+ output uart_1_txd,
+ input uart_1_rxd
+);
+`ifdef RANDOMIZE_REG_INIT
+ reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+ wire system_clock; // @[ChipTop.scala 28:35]
+ wire system_reset; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_clock; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_reset; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock; // @[ChipTop.scala 28:35]
+ wire system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset; // @[ChipTop.scala 28:35]
+ wire system_auto_subsystem_cbus_fixedClockNode_out_clock; // @[ChipTop.scala 28:35]
+ wire system_auto_subsystem_cbus_fixedClockNode_out_reset; // @[ChipTop.scala 28:35]
+ wire system_custom_boot; // @[ChipTop.scala 28:35]
+ wire system_serial_tl_clock; // @[ChipTop.scala 28:35]
+ wire system_serial_tl_bits_in_ready; // @[ChipTop.scala 28:35]
+ wire system_serial_tl_bits_in_valid; // @[ChipTop.scala 28:35]
+ wire [31:0] system_serial_tl_bits_in_bits; // @[ChipTop.scala 28:35]
+ wire system_serial_tl_bits_out_ready; // @[ChipTop.scala 28:35]
+ wire system_serial_tl_bits_out_valid; // @[ChipTop.scala 28:35]
+ wire [31:0] system_serial_tl_bits_out_bits; // @[ChipTop.scala 28:35]
+ wire system_resetctrl_hartIsInReset_0; // @[ChipTop.scala 28:35]
+ wire system_debug_clock; // @[ChipTop.scala 28:35]
+ wire system_debug_reset; // @[ChipTop.scala 28:35]
+ wire system_debug_systemjtag_jtag_TCK; // @[ChipTop.scala 28:35]
+ wire system_debug_systemjtag_jtag_TMS; // @[ChipTop.scala 28:35]
+ wire system_debug_systemjtag_jtag_TDI; // @[ChipTop.scala 28:35]
+ wire system_debug_systemjtag_jtag_TDO_data; // @[ChipTop.scala 28:35]
+ wire system_debug_systemjtag_reset; // @[ChipTop.scala 28:35]
+ wire system_debug_dmactive; // @[ChipTop.scala 28:35]
+ wire system_debug_dmactiveAck; // @[ChipTop.scala 28:35]
+ wire system_uart_0_txd; // @[ChipTop.scala 28:35]
+ wire system_uart_0_rxd; // @[ChipTop.scala 28:35]
+ wire system_uart_1_txd; // @[ChipTop.scala 28:35]
+ wire system_uart_1_rxd; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_0_i_ival; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_0_o_oval; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_0_o_oe; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_0_o_ie; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_1_i_ival; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_1_o_oval; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_1_o_oe; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_1_o_ie; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_2_i_ival; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_2_o_oval; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_2_o_oe; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_2_o_ie; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_3_i_ival; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_3_o_oval; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_3_o_oe; // @[ChipTop.scala 28:35]
+ wire system_gpio_0_pins_3_o_ie; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_sck; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_0_i; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_0_o; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_0_oe; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_1_i; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_1_o; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_1_oe; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_2_i; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_2_o; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_2_oe; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_3_i; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_3_o; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_dq_3_oe; // @[ChipTop.scala 28:35]
+ wire system_qspi_0_cs_0; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_sck; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_0_i; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_0_o; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_0_oe; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_1_i; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_1_o; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_1_oe; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_2_i; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_2_o; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_2_oe; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_3_i; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_3_o; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_dq_3_oe; // @[ChipTop.scala 28:35]
+ wire system_qspi_1_cs_0; // @[ChipTop.scala 28:35]
+ wire chipyardPRCI_auto_in_member_chipyardPRCI_implicit_clock_clock; // @[ClockGroup.scala 32:69]
+ wire chipyardPRCI_auto_in_member_chipyardPRCI_implicit_clock_reset; // @[ClockGroup.scala 32:69]
+ wire chipyardPRCI_auto_out_clock; // @[ClockGroup.scala 32:69]
+ wire chipyardPRCI_auto_out_reset; // @[ClockGroup.scala 32:69]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_in_clock; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_in_reset; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_clock; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_reset; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_clock; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_reset; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_clock; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_reset; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_clock; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_reset; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_clock; // @[IOBinders.scala 409:41]
+ wire dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_reset; // @[IOBinders.scala 409:41]
+ wire system_debug_systemjtag_reset_catcher_clock; // @[ResetCatchAndSync.scala 39:28]
+ wire system_debug_systemjtag_reset_catcher_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire system_debug_systemjtag_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala 39:28]
+ wire debug_reset_syncd_debug_reset_sync_clock; // @[ShiftReg.scala 45:23]
+ wire debug_reset_syncd_debug_reset_sync_reset; // @[ShiftReg.scala 45:23]
+ wire debug_reset_syncd_debug_reset_sync_io_d; // @[ShiftReg.scala 45:23]
+ wire debug_reset_syncd_debug_reset_sync_io_q; // @[ShiftReg.scala 45:23]
+ wire dmactiveAck_dmactiveAck_clock; // @[ShiftReg.scala 45:23]
+ wire dmactiveAck_dmactiveAck_reset; // @[ShiftReg.scala 45:23]
+ wire dmactiveAck_dmactiveAck_io_d; // @[ShiftReg.scala 45:23]
+ wire dmactiveAck_dmactiveAck_io_q; // @[ShiftReg.scala 45:23]
+ wire gated_clock_debug_clock_gate_in; // @[ClockGate.scala 24:20]
+ wire gated_clock_debug_clock_gate_test_en; // @[ClockGate.scala 24:20]
+ wire gated_clock_debug_clock_gate_en; // @[ClockGate.scala 24:20]
+ wire gated_clock_debug_clock_gate_out; // @[ClockGate.scala 24:20]
+ wire iocell_jtag_TDO_pad; // @[IOCell.scala 112:24]
+ wire iocell_jtag_TDO_o; // @[IOCell.scala 112:24]
+ wire iocell_jtag_TDO_oe; // @[IOCell.scala 112:24]
+ wire iocell_jtag_TDI_pad; // @[IOCell.scala 111:23]
+ wire iocell_jtag_TDI_i; // @[IOCell.scala 111:23]
+ wire iocell_jtag_TDI_ie; // @[IOCell.scala 111:23]
+ wire iocell_jtag_TMS_pad; // @[IOCell.scala 111:23]
+ wire iocell_jtag_TMS_i; // @[IOCell.scala 111:23]
+ wire iocell_jtag_TMS_ie; // @[IOCell.scala 111:23]
+ wire iocell_jtag_TCK_pad; // @[IOCell.scala 111:23]
+ wire iocell_jtag_TCK_i; // @[IOCell.scala 111:23]
+ wire iocell_jtag_TCK_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_out_bits_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_1_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_1_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_1_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_2_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_2_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_2_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_3_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_3_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_3_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_4_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_4_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_4_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_5_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_5_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_5_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_6_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_6_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_6_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_7_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_7_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_7_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_8_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_8_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_8_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_9_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_9_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_9_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_10_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_10_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_10_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_11_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_11_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_11_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_12_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_12_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_12_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_13_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_13_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_13_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_14_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_14_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_14_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_15_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_15_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_15_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_16_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_16_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_16_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_17_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_17_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_17_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_18_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_18_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_18_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_19_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_19_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_19_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_20_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_20_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_20_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_21_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_21_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_21_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_22_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_22_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_22_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_23_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_23_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_23_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_24_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_24_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_24_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_25_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_25_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_25_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_26_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_26_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_26_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_27_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_27_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_27_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_28_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_28_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_28_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_29_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_29_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_29_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_30_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_30_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_30_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_31_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_31_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_bits_31_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_valid_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_valid_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_valid_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_out_ready_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_out_ready_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_out_ready_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_1_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_1_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_1_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_2_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_2_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_2_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_3_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_3_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_3_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_4_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_4_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_4_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_5_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_5_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_5_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_6_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_6_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_6_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_7_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_7_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_7_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_8_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_8_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_8_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_9_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_9_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_9_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_10_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_10_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_10_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_11_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_11_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_11_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_12_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_12_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_12_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_13_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_13_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_13_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_14_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_14_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_14_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_15_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_15_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_15_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_16_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_16_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_16_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_17_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_17_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_17_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_18_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_18_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_18_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_19_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_19_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_19_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_20_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_20_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_20_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_21_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_21_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_21_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_22_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_22_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_22_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_23_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_23_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_23_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_24_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_24_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_24_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_25_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_25_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_25_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_26_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_26_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_26_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_27_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_27_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_27_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_28_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_28_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_28_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_29_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_29_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_29_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_30_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_30_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_30_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_31_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_31_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_bits_31_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_valid_pad; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_valid_i; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_valid_ie; // @[IOCell.scala 111:23]
+ wire iocell_serial_tl_bits_in_ready_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_in_ready_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_bits_in_ready_oe; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_clock_pad; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_clock_o; // @[IOCell.scala 112:24]
+ wire iocell_serial_tl_clock_oe; // @[IOCell.scala 112:24]
+ wire iocell_custom_boot_pad; // @[IOCell.scala 111:23]
+ wire iocell_custom_boot_i; // @[IOCell.scala 111:23]
+ wire iocell_custom_boot_ie; // @[IOCell.scala 111:23]
+ wire iocell_clock_clock_pad; // @[IOCell.scala 111:23]
+ wire iocell_clock_clock_i; // @[IOCell.scala 111:23]
+ wire iocell_clock_clock_ie; // @[IOCell.scala 111:23]
+ wire iocell_reset_pad; // @[IOCell.scala 111:23]
+ wire iocell_reset_i; // @[IOCell.scala 111:23]
+ wire iocell_reset_ie; // @[IOCell.scala 111:23]
+ wire iocell_gpio_0_0_i; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_0_ie; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_0_o; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_0_oe; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_1_i; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_1_ie; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_1_o; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_1_oe; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_2_i; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_2_ie; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_2_o; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_2_oe; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_3_i; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_3_ie; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_3_o; // @[IOCell.scala 110:22]
+ wire iocell_gpio_0_3_oe; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_sck_pad; // @[IOCell.scala 112:24]
+ wire iocell_spi_0_sck_o; // @[IOCell.scala 112:24]
+ wire iocell_spi_0_sck_oe; // @[IOCell.scala 112:24]
+ wire iocell_spi_0_cs_0_pad; // @[IOCell.scala 112:24]
+ wire iocell_spi_0_cs_0_o; // @[IOCell.scala 112:24]
+ wire iocell_spi_0_cs_0_oe; // @[IOCell.scala 112:24]
+ wire iocell_spi_0_dq_0_i; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_0_ie; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_0_o; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_0_oe; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_1_i; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_1_ie; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_1_o; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_1_oe; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_2_i; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_2_ie; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_2_o; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_2_oe; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_3_i; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_3_ie; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_3_o; // @[IOCell.scala 110:22]
+ wire iocell_spi_0_dq_3_oe; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_sck_pad; // @[IOCell.scala 112:24]
+ wire iocell_spi_1_sck_o; // @[IOCell.scala 112:24]
+ wire iocell_spi_1_sck_oe; // @[IOCell.scala 112:24]
+ wire iocell_spi_1_cs_0_pad; // @[IOCell.scala 112:24]
+ wire iocell_spi_1_cs_0_o; // @[IOCell.scala 112:24]
+ wire iocell_spi_1_cs_0_oe; // @[IOCell.scala 112:24]
+ wire iocell_spi_1_dq_0_i; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_0_ie; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_0_o; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_0_oe; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_1_i; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_1_ie; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_1_o; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_1_oe; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_2_i; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_2_ie; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_2_o; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_2_oe; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_3_i; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_3_ie; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_3_o; // @[IOCell.scala 110:22]
+ wire iocell_spi_1_dq_3_oe; // @[IOCell.scala 110:22]
+ wire iocell_uart_0_rxd_pad; // @[IOCell.scala 111:23]
+ wire iocell_uart_0_rxd_i; // @[IOCell.scala 111:23]
+ wire iocell_uart_0_rxd_ie; // @[IOCell.scala 111:23]
+ wire iocell_uart_0_txd_pad; // @[IOCell.scala 112:24]
+ wire iocell_uart_0_txd_o; // @[IOCell.scala 112:24]
+ wire iocell_uart_0_txd_oe; // @[IOCell.scala 112:24]
+ wire iocell_uart_1_rxd_pad; // @[IOCell.scala 111:23]
+ wire iocell_uart_1_rxd_i; // @[IOCell.scala 111:23]
+ wire iocell_uart_1_rxd_ie; // @[IOCell.scala 111:23]
+ wire iocell_uart_1_txd_pad; // @[IOCell.scala 112:24]
+ wire iocell_uart_1_txd_o; // @[IOCell.scala 112:24]
+ wire iocell_uart_1_txd_oe; // @[IOCell.scala 112:24]
+ wire _debug_reset_syncd_WIRE = debug_reset_syncd_debug_reset_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
+ wire _T = ~_debug_reset_syncd_WIRE; // @[Periphery.scala 297:38]
+ wire bundleIn_0_clock = system_auto_subsystem_cbus_fixedClockNode_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ reg clock_en; // @[Periphery.scala 299:29]
+ wire [7:0] serial_tl_bits_out_bits_lo_lo = {iocell_serial_tl_bits_out_bits_7_pad,iocell_serial_tl_bits_out_bits_6_pad,
+ iocell_serial_tl_bits_out_bits_5_pad,iocell_serial_tl_bits_out_bits_4_pad,iocell_serial_tl_bits_out_bits_3_pad,
+ iocell_serial_tl_bits_out_bits_2_pad,iocell_serial_tl_bits_out_bits_1_pad,iocell_serial_tl_bits_out_bits_pad}; // @[Cat.scala 31:58]
+ wire [15:0] serial_tl_bits_out_bits_lo = {iocell_serial_tl_bits_out_bits_15_pad,iocell_serial_tl_bits_out_bits_14_pad,
+ iocell_serial_tl_bits_out_bits_13_pad,iocell_serial_tl_bits_out_bits_12_pad,iocell_serial_tl_bits_out_bits_11_pad,
+ iocell_serial_tl_bits_out_bits_10_pad,iocell_serial_tl_bits_out_bits_9_pad,iocell_serial_tl_bits_out_bits_8_pad,
+ serial_tl_bits_out_bits_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] serial_tl_bits_out_bits_hi_lo = {iocell_serial_tl_bits_out_bits_23_pad,
+ iocell_serial_tl_bits_out_bits_22_pad,iocell_serial_tl_bits_out_bits_21_pad,iocell_serial_tl_bits_out_bits_20_pad,
+ iocell_serial_tl_bits_out_bits_19_pad,iocell_serial_tl_bits_out_bits_18_pad,iocell_serial_tl_bits_out_bits_17_pad,
+ iocell_serial_tl_bits_out_bits_16_pad}; // @[Cat.scala 31:58]
+ wire [15:0] serial_tl_bits_out_bits_hi = {iocell_serial_tl_bits_out_bits_31_pad,iocell_serial_tl_bits_out_bits_30_pad,
+ iocell_serial_tl_bits_out_bits_29_pad,iocell_serial_tl_bits_out_bits_28_pad,iocell_serial_tl_bits_out_bits_27_pad,
+ iocell_serial_tl_bits_out_bits_26_pad,iocell_serial_tl_bits_out_bits_25_pad,iocell_serial_tl_bits_out_bits_24_pad,
+ serial_tl_bits_out_bits_hi_lo}; // @[Cat.scala 31:58]
+ wire [7:0] system_serial_tl_bits_in_bits_lo_lo = {iocell_serial_tl_bits_in_bits_7_i,iocell_serial_tl_bits_in_bits_6_i,
+ iocell_serial_tl_bits_in_bits_5_i,iocell_serial_tl_bits_in_bits_4_i,iocell_serial_tl_bits_in_bits_3_i,
+ iocell_serial_tl_bits_in_bits_2_i,iocell_serial_tl_bits_in_bits_1_i,iocell_serial_tl_bits_in_bits_i}; // @[Cat.scala 31:58]
+ wire [15:0] system_serial_tl_bits_in_bits_lo = {iocell_serial_tl_bits_in_bits_15_i,iocell_serial_tl_bits_in_bits_14_i,
+ iocell_serial_tl_bits_in_bits_13_i,iocell_serial_tl_bits_in_bits_12_i,iocell_serial_tl_bits_in_bits_11_i,
+ iocell_serial_tl_bits_in_bits_10_i,iocell_serial_tl_bits_in_bits_9_i,iocell_serial_tl_bits_in_bits_8_i,
+ system_serial_tl_bits_in_bits_lo_lo}; // @[Cat.scala 31:58]
+ wire [7:0] system_serial_tl_bits_in_bits_hi_lo = {iocell_serial_tl_bits_in_bits_23_i,
+ iocell_serial_tl_bits_in_bits_22_i,iocell_serial_tl_bits_in_bits_21_i,iocell_serial_tl_bits_in_bits_20_i,
+ iocell_serial_tl_bits_in_bits_19_i,iocell_serial_tl_bits_in_bits_18_i,iocell_serial_tl_bits_in_bits_17_i,
+ iocell_serial_tl_bits_in_bits_16_i}; // @[Cat.scala 31:58]
+ wire [15:0] system_serial_tl_bits_in_bits_hi = {iocell_serial_tl_bits_in_bits_31_i,iocell_serial_tl_bits_in_bits_30_i,
+ iocell_serial_tl_bits_in_bits_29_i,iocell_serial_tl_bits_in_bits_28_i,iocell_serial_tl_bits_in_bits_27_i,
+ iocell_serial_tl_bits_in_bits_26_i,iocell_serial_tl_bits_in_bits_25_i,iocell_serial_tl_bits_in_bits_24_i,
+ system_serial_tl_bits_in_bits_hi_lo}; // @[Cat.scala 31:58]
+
+ // for input and output only pins is safe to have output enabled
+
+ assign io_oeb[18:15] = 1'b0; // JTAG
+ assign io_oeb[12:11] = 1'b0; // custom_boot and reset
+ assign io_oeb[20:19] = 1'b0; // SPI0
+ assign io_oeb[26:25] = 1'b0; // SPI1
+ assign io_oeb[14:13] = 1'b0; // UART0
+ assign io_oeb[33:32] = 1'b0; // UART1
+
+ // for bidirectional pins assign OEB from IOCELL signal
+ assign io_oeb[34] = !iocell_gpio_0_0_oe;
+ assign io_oeb[35] = !iocell_gpio_0_1_oe;
+ assign io_oeb[36] = !iocell_gpio_0_2_oe;
+ assign io_oeb[37] = !iocell_gpio_0_3_oe;
+
+ assign io_oeb[21] = !iocell_spi_0_dq_0_oe;
+ assign io_oeb[22] = !iocell_spi_0_dq_1_oe;
+ assign io_oeb[23] = !iocell_spi_0_dq_2_oe;
+ assign io_oeb[24] = !iocell_spi_0_dq_3_oe;
+
+ assign io_oeb[27] = !iocell_spi_1_dq_0_oe;
+ assign io_oeb[28] = !iocell_spi_1_dq_1_oe;
+ assign io_oeb[29] = !iocell_spi_1_dq_2_oe;
+ assign io_oeb[30] = !iocell_spi_1_dq_3_oe;
+
+ DigitalTop system ( // @[ChipTop.scala 28:35]
+ .clock(system_clock),
+ .reset(system_reset),
+ .auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_clock(
+ system_auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_clock),
+ .auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_reset(
+ system_auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_reset),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock),
+ .auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset(
+ system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset),
+ .auto_subsystem_cbus_fixedClockNode_out_clock(system_auto_subsystem_cbus_fixedClockNode_out_clock),
+ .auto_subsystem_cbus_fixedClockNode_out_reset(system_auto_subsystem_cbus_fixedClockNode_out_reset),
+ .custom_boot(system_custom_boot),
+ .serial_tl_clock(system_serial_tl_clock),
+ .serial_tl_bits_in_ready(system_serial_tl_bits_in_ready),
+ .serial_tl_bits_in_valid(system_serial_tl_bits_in_valid),
+ .serial_tl_bits_in_bits(system_serial_tl_bits_in_bits),
+ .serial_tl_bits_out_ready(system_serial_tl_bits_out_ready),
+ .serial_tl_bits_out_valid(system_serial_tl_bits_out_valid),
+ .serial_tl_bits_out_bits(system_serial_tl_bits_out_bits),
+ .resetctrl_hartIsInReset_0(system_resetctrl_hartIsInReset_0),
+ .debug_clock(system_debug_clock),
+ .debug_reset(system_debug_reset),
+ .debug_systemjtag_jtag_TCK(system_debug_systemjtag_jtag_TCK),
+ .debug_systemjtag_jtag_TMS(system_debug_systemjtag_jtag_TMS),
+ .debug_systemjtag_jtag_TDI(system_debug_systemjtag_jtag_TDI),
+ .debug_systemjtag_jtag_TDO_data(system_debug_systemjtag_jtag_TDO_data),
+ .debug_systemjtag_reset(system_debug_systemjtag_reset),
+ .debug_dmactive(system_debug_dmactive),
+ .debug_dmactiveAck(system_debug_dmactiveAck),
+ .uart_0_txd(system_uart_0_txd),
+ .uart_0_rxd(system_uart_0_rxd),
+ .uart_1_txd(system_uart_1_txd),
+ .uart_1_rxd(system_uart_1_rxd),
+ .gpio_0_pins_0_i_ival(system_gpio_0_pins_0_i_ival),
+ .gpio_0_pins_0_o_oval(system_gpio_0_pins_0_o_oval),
+ .gpio_0_pins_0_o_oe(system_gpio_0_pins_0_o_oe),
+ .gpio_0_pins_0_o_ie(system_gpio_0_pins_0_o_ie),
+ .gpio_0_pins_1_i_ival(system_gpio_0_pins_1_i_ival),
+ .gpio_0_pins_1_o_oval(system_gpio_0_pins_1_o_oval),
+ .gpio_0_pins_1_o_oe(system_gpio_0_pins_1_o_oe),
+ .gpio_0_pins_1_o_ie(system_gpio_0_pins_1_o_ie),
+ .gpio_0_pins_2_i_ival(system_gpio_0_pins_2_i_ival),
+ .gpio_0_pins_2_o_oval(system_gpio_0_pins_2_o_oval),
+ .gpio_0_pins_2_o_oe(system_gpio_0_pins_2_o_oe),
+ .gpio_0_pins_2_o_ie(system_gpio_0_pins_2_o_ie),
+ .gpio_0_pins_3_i_ival(system_gpio_0_pins_3_i_ival),
+ .gpio_0_pins_3_o_oval(system_gpio_0_pins_3_o_oval),
+ .gpio_0_pins_3_o_oe(system_gpio_0_pins_3_o_oe),
+ .gpio_0_pins_3_o_ie(system_gpio_0_pins_3_o_ie),
+ .qspi_0_sck(system_qspi_0_sck),
+ .qspi_0_dq_0_i(system_qspi_0_dq_0_i),
+ .qspi_0_dq_0_o(system_qspi_0_dq_0_o),
+ .qspi_0_dq_0_oe(system_qspi_0_dq_0_oe),
+ .qspi_0_dq_1_i(system_qspi_0_dq_1_i),
+ .qspi_0_dq_1_o(system_qspi_0_dq_1_o),
+ .qspi_0_dq_1_oe(system_qspi_0_dq_1_oe),
+ .qspi_0_dq_2_i(system_qspi_0_dq_2_i),
+ .qspi_0_dq_2_o(system_qspi_0_dq_2_o),
+ .qspi_0_dq_2_oe(system_qspi_0_dq_2_oe),
+ .qspi_0_dq_3_i(system_qspi_0_dq_3_i),
+ .qspi_0_dq_3_o(system_qspi_0_dq_3_o),
+ .qspi_0_dq_3_oe(system_qspi_0_dq_3_oe),
+ .qspi_0_cs_0(system_qspi_0_cs_0),
+ .qspi_1_sck(system_qspi_1_sck),
+ .qspi_1_dq_0_i(system_qspi_1_dq_0_i),
+ .qspi_1_dq_0_o(system_qspi_1_dq_0_o),
+ .qspi_1_dq_0_oe(system_qspi_1_dq_0_oe),
+ .qspi_1_dq_1_i(system_qspi_1_dq_1_i),
+ .qspi_1_dq_1_o(system_qspi_1_dq_1_o),
+ .qspi_1_dq_1_oe(system_qspi_1_dq_1_oe),
+ .qspi_1_dq_2_i(system_qspi_1_dq_2_i),
+ .qspi_1_dq_2_o(system_qspi_1_dq_2_o),
+ .qspi_1_dq_2_oe(system_qspi_1_dq_2_oe),
+ .qspi_1_dq_3_i(system_qspi_1_dq_3_i),
+ .qspi_1_dq_3_o(system_qspi_1_dq_3_o),
+ .qspi_1_dq_3_oe(system_qspi_1_dq_3_oe),
+ .qspi_1_cs_0(system_qspi_1_cs_0)
+ );
+ ClockGroup_4 chipyardPRCI ( // @[ClockGroup.scala 32:69]
+ .auto_in_member_chipyardPRCI_implicit_clock_clock(chipyardPRCI_auto_in_member_chipyardPRCI_implicit_clock_clock),
+ .auto_in_member_chipyardPRCI_implicit_clock_reset(chipyardPRCI_auto_in_member_chipyardPRCI_implicit_clock_reset),
+ .auto_out_clock(chipyardPRCI_auto_out_clock),
+ .auto_out_reset(chipyardPRCI_auto_out_reset)
+ );
+ DividerOnlyClockGenerator dividerOnlyClockGen ( // @[IOBinders.scala 409:41]
+ .auto_divider_only_clock_gen_in_clock(dividerOnlyClockGen_auto_divider_only_clock_gen_in_clock),
+ .auto_divider_only_clock_gen_in_reset(dividerOnlyClockGen_auto_divider_only_clock_gen_in_reset),
+ .auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_clock(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_clock),
+ .auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_reset(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_reset),
+ .auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_clock(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_clock),
+ .auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_reset(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_reset),
+ .auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_clock(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_clock),
+ .auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_reset(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_reset),
+ .auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_clock(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_clock),
+ .auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_reset(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_reset),
+ .auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_clock(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_clock),
+ .auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_reset(
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_reset)
+ );
+ ResetCatchAndSync_d3 system_debug_systemjtag_reset_catcher ( // @[ResetCatchAndSync.scala 39:28]
+ .clock(system_debug_systemjtag_reset_catcher_clock),
+ .reset(system_debug_systemjtag_reset_catcher_reset),
+ .io_sync_reset(system_debug_systemjtag_reset_catcher_io_sync_reset)
+ );
+ AsyncResetSynchronizerShiftReg_w1_d3_i0 debug_reset_syncd_debug_reset_sync ( // @[ShiftReg.scala 45:23]
+ .clock(debug_reset_syncd_debug_reset_sync_clock),
+ .reset(debug_reset_syncd_debug_reset_sync_reset),
+ .io_d(debug_reset_syncd_debug_reset_sync_io_d),
+ .io_q(debug_reset_syncd_debug_reset_sync_io_q)
+ );
+ ResetSynchronizerShiftReg_w1_d3_i0 dmactiveAck_dmactiveAck ( // @[ShiftReg.scala 45:23]
+ .clock(dmactiveAck_dmactiveAck_clock),
+ .reset(dmactiveAck_dmactiveAck_reset),
+ .io_d(dmactiveAck_dmactiveAck_io_d),
+ .io_q(dmactiveAck_dmactiveAck_io_q)
+ );
+ EICG_wrapper gated_clock_debug_clock_gate ( // @[ClockGate.scala 24:20]
+ .in(gated_clock_debug_clock_gate_in),
+ .test_en(gated_clock_debug_clock_gate_test_en),
+ .en(gated_clock_debug_clock_gate_en),
+ .out(gated_clock_debug_clock_gate_out)
+ );
+ GenericDigitalOutIOCell iocell_jtag_TDO ( // @[IOCell.scala 112:24]
+ .pad(iocell_jtag_TDO_pad),
+ .o(iocell_jtag_TDO_o),
+ .oe(iocell_jtag_TDO_oe)
+ );
+ GenericDigitalInIOCell iocell_jtag_TDI ( // @[IOCell.scala 111:23]
+ .pad(iocell_jtag_TDI_pad),
+ .i(iocell_jtag_TDI_i),
+ .ie(iocell_jtag_TDI_ie)
+ );
+ GenericDigitalInIOCell iocell_jtag_TMS ( // @[IOCell.scala 111:23]
+ .pad(iocell_jtag_TMS_pad),
+ .i(iocell_jtag_TMS_i),
+ .ie(iocell_jtag_TMS_ie)
+ );
+ GenericDigitalInIOCell iocell_jtag_TCK ( // @[IOCell.scala 111:23]
+ .pad(iocell_jtag_TCK_pad),
+ .i(iocell_jtag_TCK_i),
+ .ie(iocell_jtag_TCK_ie)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_pad),
+ .o(iocell_serial_tl_bits_out_bits_o),
+ .oe(iocell_serial_tl_bits_out_bits_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_1 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_1_pad),
+ .o(iocell_serial_tl_bits_out_bits_1_o),
+ .oe(iocell_serial_tl_bits_out_bits_1_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_2 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_2_pad),
+ .o(iocell_serial_tl_bits_out_bits_2_o),
+ .oe(iocell_serial_tl_bits_out_bits_2_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_3 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_3_pad),
+ .o(iocell_serial_tl_bits_out_bits_3_o),
+ .oe(iocell_serial_tl_bits_out_bits_3_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_4 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_4_pad),
+ .o(iocell_serial_tl_bits_out_bits_4_o),
+ .oe(iocell_serial_tl_bits_out_bits_4_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_5 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_5_pad),
+ .o(iocell_serial_tl_bits_out_bits_5_o),
+ .oe(iocell_serial_tl_bits_out_bits_5_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_6 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_6_pad),
+ .o(iocell_serial_tl_bits_out_bits_6_o),
+ .oe(iocell_serial_tl_bits_out_bits_6_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_7 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_7_pad),
+ .o(iocell_serial_tl_bits_out_bits_7_o),
+ .oe(iocell_serial_tl_bits_out_bits_7_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_8 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_8_pad),
+ .o(iocell_serial_tl_bits_out_bits_8_o),
+ .oe(iocell_serial_tl_bits_out_bits_8_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_9 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_9_pad),
+ .o(iocell_serial_tl_bits_out_bits_9_o),
+ .oe(iocell_serial_tl_bits_out_bits_9_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_10 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_10_pad),
+ .o(iocell_serial_tl_bits_out_bits_10_o),
+ .oe(iocell_serial_tl_bits_out_bits_10_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_11 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_11_pad),
+ .o(iocell_serial_tl_bits_out_bits_11_o),
+ .oe(iocell_serial_tl_bits_out_bits_11_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_12 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_12_pad),
+ .o(iocell_serial_tl_bits_out_bits_12_o),
+ .oe(iocell_serial_tl_bits_out_bits_12_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_13 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_13_pad),
+ .o(iocell_serial_tl_bits_out_bits_13_o),
+ .oe(iocell_serial_tl_bits_out_bits_13_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_14 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_14_pad),
+ .o(iocell_serial_tl_bits_out_bits_14_o),
+ .oe(iocell_serial_tl_bits_out_bits_14_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_15 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_15_pad),
+ .o(iocell_serial_tl_bits_out_bits_15_o),
+ .oe(iocell_serial_tl_bits_out_bits_15_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_16 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_16_pad),
+ .o(iocell_serial_tl_bits_out_bits_16_o),
+ .oe(iocell_serial_tl_bits_out_bits_16_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_17 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_17_pad),
+ .o(iocell_serial_tl_bits_out_bits_17_o),
+ .oe(iocell_serial_tl_bits_out_bits_17_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_18 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_18_pad),
+ .o(iocell_serial_tl_bits_out_bits_18_o),
+ .oe(iocell_serial_tl_bits_out_bits_18_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_19 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_19_pad),
+ .o(iocell_serial_tl_bits_out_bits_19_o),
+ .oe(iocell_serial_tl_bits_out_bits_19_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_20 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_20_pad),
+ .o(iocell_serial_tl_bits_out_bits_20_o),
+ .oe(iocell_serial_tl_bits_out_bits_20_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_21 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_21_pad),
+ .o(iocell_serial_tl_bits_out_bits_21_o),
+ .oe(iocell_serial_tl_bits_out_bits_21_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_22 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_22_pad),
+ .o(iocell_serial_tl_bits_out_bits_22_o),
+ .oe(iocell_serial_tl_bits_out_bits_22_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_23 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_23_pad),
+ .o(iocell_serial_tl_bits_out_bits_23_o),
+ .oe(iocell_serial_tl_bits_out_bits_23_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_24 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_24_pad),
+ .o(iocell_serial_tl_bits_out_bits_24_o),
+ .oe(iocell_serial_tl_bits_out_bits_24_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_25 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_25_pad),
+ .o(iocell_serial_tl_bits_out_bits_25_o),
+ .oe(iocell_serial_tl_bits_out_bits_25_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_26 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_26_pad),
+ .o(iocell_serial_tl_bits_out_bits_26_o),
+ .oe(iocell_serial_tl_bits_out_bits_26_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_27 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_27_pad),
+ .o(iocell_serial_tl_bits_out_bits_27_o),
+ .oe(iocell_serial_tl_bits_out_bits_27_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_28 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_28_pad),
+ .o(iocell_serial_tl_bits_out_bits_28_o),
+ .oe(iocell_serial_tl_bits_out_bits_28_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_29 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_29_pad),
+ .o(iocell_serial_tl_bits_out_bits_29_o),
+ .oe(iocell_serial_tl_bits_out_bits_29_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_30 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_30_pad),
+ .o(iocell_serial_tl_bits_out_bits_30_o),
+ .oe(iocell_serial_tl_bits_out_bits_30_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_bits_31 ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_bits_31_pad),
+ .o(iocell_serial_tl_bits_out_bits_31_o),
+ .oe(iocell_serial_tl_bits_out_bits_31_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_out_valid ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_out_valid_pad),
+ .o(iocell_serial_tl_bits_out_valid_o),
+ .oe(iocell_serial_tl_bits_out_valid_oe)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_out_ready ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_out_ready_pad),
+ .i(iocell_serial_tl_bits_out_ready_i),
+ .ie(iocell_serial_tl_bits_out_ready_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_pad),
+ .i(iocell_serial_tl_bits_in_bits_i),
+ .ie(iocell_serial_tl_bits_in_bits_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_1 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_1_pad),
+ .i(iocell_serial_tl_bits_in_bits_1_i),
+ .ie(iocell_serial_tl_bits_in_bits_1_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_2 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_2_pad),
+ .i(iocell_serial_tl_bits_in_bits_2_i),
+ .ie(iocell_serial_tl_bits_in_bits_2_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_3 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_3_pad),
+ .i(iocell_serial_tl_bits_in_bits_3_i),
+ .ie(iocell_serial_tl_bits_in_bits_3_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_4 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_4_pad),
+ .i(iocell_serial_tl_bits_in_bits_4_i),
+ .ie(iocell_serial_tl_bits_in_bits_4_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_5 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_5_pad),
+ .i(iocell_serial_tl_bits_in_bits_5_i),
+ .ie(iocell_serial_tl_bits_in_bits_5_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_6 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_6_pad),
+ .i(iocell_serial_tl_bits_in_bits_6_i),
+ .ie(iocell_serial_tl_bits_in_bits_6_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_7 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_7_pad),
+ .i(iocell_serial_tl_bits_in_bits_7_i),
+ .ie(iocell_serial_tl_bits_in_bits_7_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_8 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_8_pad),
+ .i(iocell_serial_tl_bits_in_bits_8_i),
+ .ie(iocell_serial_tl_bits_in_bits_8_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_9 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_9_pad),
+ .i(iocell_serial_tl_bits_in_bits_9_i),
+ .ie(iocell_serial_tl_bits_in_bits_9_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_10 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_10_pad),
+ .i(iocell_serial_tl_bits_in_bits_10_i),
+ .ie(iocell_serial_tl_bits_in_bits_10_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_11 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_11_pad),
+ .i(iocell_serial_tl_bits_in_bits_11_i),
+ .ie(iocell_serial_tl_bits_in_bits_11_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_12 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_12_pad),
+ .i(iocell_serial_tl_bits_in_bits_12_i),
+ .ie(iocell_serial_tl_bits_in_bits_12_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_13 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_13_pad),
+ .i(iocell_serial_tl_bits_in_bits_13_i),
+ .ie(iocell_serial_tl_bits_in_bits_13_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_14 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_14_pad),
+ .i(iocell_serial_tl_bits_in_bits_14_i),
+ .ie(iocell_serial_tl_bits_in_bits_14_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_15 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_15_pad),
+ .i(iocell_serial_tl_bits_in_bits_15_i),
+ .ie(iocell_serial_tl_bits_in_bits_15_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_16 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_16_pad),
+ .i(iocell_serial_tl_bits_in_bits_16_i),
+ .ie(iocell_serial_tl_bits_in_bits_16_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_17 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_17_pad),
+ .i(iocell_serial_tl_bits_in_bits_17_i),
+ .ie(iocell_serial_tl_bits_in_bits_17_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_18 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_18_pad),
+ .i(iocell_serial_tl_bits_in_bits_18_i),
+ .ie(iocell_serial_tl_bits_in_bits_18_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_19 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_19_pad),
+ .i(iocell_serial_tl_bits_in_bits_19_i),
+ .ie(iocell_serial_tl_bits_in_bits_19_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_20 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_20_pad),
+ .i(iocell_serial_tl_bits_in_bits_20_i),
+ .ie(iocell_serial_tl_bits_in_bits_20_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_21 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_21_pad),
+ .i(iocell_serial_tl_bits_in_bits_21_i),
+ .ie(iocell_serial_tl_bits_in_bits_21_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_22 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_22_pad),
+ .i(iocell_serial_tl_bits_in_bits_22_i),
+ .ie(iocell_serial_tl_bits_in_bits_22_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_23 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_23_pad),
+ .i(iocell_serial_tl_bits_in_bits_23_i),
+ .ie(iocell_serial_tl_bits_in_bits_23_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_24 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_24_pad),
+ .i(iocell_serial_tl_bits_in_bits_24_i),
+ .ie(iocell_serial_tl_bits_in_bits_24_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_25 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_25_pad),
+ .i(iocell_serial_tl_bits_in_bits_25_i),
+ .ie(iocell_serial_tl_bits_in_bits_25_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_26 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_26_pad),
+ .i(iocell_serial_tl_bits_in_bits_26_i),
+ .ie(iocell_serial_tl_bits_in_bits_26_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_27 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_27_pad),
+ .i(iocell_serial_tl_bits_in_bits_27_i),
+ .ie(iocell_serial_tl_bits_in_bits_27_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_28 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_28_pad),
+ .i(iocell_serial_tl_bits_in_bits_28_i),
+ .ie(iocell_serial_tl_bits_in_bits_28_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_29 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_29_pad),
+ .i(iocell_serial_tl_bits_in_bits_29_i),
+ .ie(iocell_serial_tl_bits_in_bits_29_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_30 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_30_pad),
+ .i(iocell_serial_tl_bits_in_bits_30_i),
+ .ie(iocell_serial_tl_bits_in_bits_30_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_bits_31 ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_bits_31_pad),
+ .i(iocell_serial_tl_bits_in_bits_31_i),
+ .ie(iocell_serial_tl_bits_in_bits_31_ie)
+ );
+ GenericDigitalInIOCell iocell_serial_tl_bits_in_valid ( // @[IOCell.scala 111:23]
+ .pad(iocell_serial_tl_bits_in_valid_pad),
+ .i(iocell_serial_tl_bits_in_valid_i),
+ .ie(iocell_serial_tl_bits_in_valid_ie)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_bits_in_ready ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_bits_in_ready_pad),
+ .o(iocell_serial_tl_bits_in_ready_o),
+ .oe(iocell_serial_tl_bits_in_ready_oe)
+ );
+ GenericDigitalOutIOCell iocell_serial_tl_clock ( // @[IOCell.scala 112:24]
+ .pad(iocell_serial_tl_clock_pad),
+ .o(iocell_serial_tl_clock_o),
+ .oe(iocell_serial_tl_clock_oe)
+ );
+ GenericDigitalInIOCell iocell_custom_boot ( // @[IOCell.scala 111:23]
+ .pad(iocell_custom_boot_pad),
+ .i(iocell_custom_boot_i),
+ .ie(iocell_custom_boot_ie)
+ );
+ GenericDigitalInIOCell iocell_clock_clock ( // @[IOCell.scala 111:23]
+ .pad(iocell_clock_clock_pad),
+ .i(iocell_clock_clock_i),
+ .ie(iocell_clock_clock_ie)
+ );
+ GenericDigitalInIOCell iocell_reset ( // @[IOCell.scala 111:23]
+ .pad(iocell_reset_pad),
+ .i(iocell_reset_i),
+ .ie(iocell_reset_ie)
+ );
+ GenericDigitalGPIOCell iocell_gpio_0_0 ( // @[IOCell.scala 110:22]
+ .pad(gpio_0_0),
+ .i(iocell_gpio_0_0_i),
+ .ie(iocell_gpio_0_0_ie),
+ .o(iocell_gpio_0_0_o),
+ .oe(iocell_gpio_0_0_oe)
+ );
+ GenericDigitalGPIOCell iocell_gpio_0_1 ( // @[IOCell.scala 110:22]
+ .pad(gpio_0_1),
+ .i(iocell_gpio_0_1_i),
+ .ie(iocell_gpio_0_1_ie),
+ .o(iocell_gpio_0_1_o),
+ .oe(iocell_gpio_0_1_oe)
+ );
+ GenericDigitalGPIOCell iocell_gpio_0_2 ( // @[IOCell.scala 110:22]
+ .pad(gpio_0_2),
+ .i(iocell_gpio_0_2_i),
+ .ie(iocell_gpio_0_2_ie),
+ .o(iocell_gpio_0_2_o),
+ .oe(iocell_gpio_0_2_oe)
+ );
+ GenericDigitalGPIOCell iocell_gpio_0_3 ( // @[IOCell.scala 110:22]
+ .pad(gpio_0_3),
+ .i(iocell_gpio_0_3_i),
+ .ie(iocell_gpio_0_3_ie),
+ .o(iocell_gpio_0_3_o),
+ .oe(iocell_gpio_0_3_oe)
+ );
+ GenericDigitalOutIOCell iocell_spi_0_sck ( // @[IOCell.scala 112:24]
+ .pad(iocell_spi_0_sck_pad),
+ .o(iocell_spi_0_sck_o),
+ .oe(iocell_spi_0_sck_oe)
+ );
+ GenericDigitalOutIOCell iocell_spi_0_cs_0 ( // @[IOCell.scala 112:24]
+ .pad(iocell_spi_0_cs_0_pad),
+ .o(iocell_spi_0_cs_0_o),
+ .oe(iocell_spi_0_cs_0_oe)
+ );
+ GenericDigitalGPIOCell iocell_spi_0_dq_0 ( // @[IOCell.scala 110:22]
+ .pad(spi_0_dq_0),
+ .i(iocell_spi_0_dq_0_i),
+ .ie(iocell_spi_0_dq_0_ie),
+ .o(iocell_spi_0_dq_0_o),
+ .oe(iocell_spi_0_dq_0_oe)
+ );
+ GenericDigitalGPIOCell iocell_spi_0_dq_1 ( // @[IOCell.scala 110:22]
+ .pad(spi_0_dq_1),
+ .i(iocell_spi_0_dq_1_i),
+ .ie(iocell_spi_0_dq_1_ie),
+ .o(iocell_spi_0_dq_1_o),
+ .oe(iocell_spi_0_dq_1_oe)
+ );
+ GenericDigitalGPIOCell iocell_spi_0_dq_2 ( // @[IOCell.scala 110:22]
+ .pad(spi_0_dq_2),
+ .i(iocell_spi_0_dq_2_i),
+ .ie(iocell_spi_0_dq_2_ie),
+ .o(iocell_spi_0_dq_2_o),
+ .oe(iocell_spi_0_dq_2_oe)
+ );
+ GenericDigitalGPIOCell iocell_spi_0_dq_3 ( // @[IOCell.scala 110:22]
+ .pad(spi_0_dq_3),
+ .i(iocell_spi_0_dq_3_i),
+ .ie(iocell_spi_0_dq_3_ie),
+ .o(iocell_spi_0_dq_3_o),
+ .oe(iocell_spi_0_dq_3_oe)
+ );
+ GenericDigitalOutIOCell iocell_spi_1_sck ( // @[IOCell.scala 112:24]
+ .pad(iocell_spi_1_sck_pad),
+ .o(iocell_spi_1_sck_o),
+ .oe(iocell_spi_1_sck_oe)
+ );
+ GenericDigitalOutIOCell iocell_spi_1_cs_0 ( // @[IOCell.scala 112:24]
+ .pad(iocell_spi_1_cs_0_pad),
+ .o(iocell_spi_1_cs_0_o),
+ .oe(iocell_spi_1_cs_0_oe)
+ );
+ GenericDigitalGPIOCell iocell_spi_1_dq_0 ( // @[IOCell.scala 110:22]
+ .pad(spi_1_dq_0),
+ .i(iocell_spi_1_dq_0_i),
+ .ie(iocell_spi_1_dq_0_ie),
+ .o(iocell_spi_1_dq_0_o),
+ .oe(iocell_spi_1_dq_0_oe)
+ );
+ GenericDigitalGPIOCell iocell_spi_1_dq_1 ( // @[IOCell.scala 110:22]
+ .pad(spi_1_dq_1),
+ .i(iocell_spi_1_dq_1_i),
+ .ie(iocell_spi_1_dq_1_ie),
+ .o(iocell_spi_1_dq_1_o),
+ .oe(iocell_spi_1_dq_1_oe)
+ );
+ GenericDigitalGPIOCell iocell_spi_1_dq_2 ( // @[IOCell.scala 110:22]
+ .pad(spi_1_dq_2),
+ .i(iocell_spi_1_dq_2_i),
+ .ie(iocell_spi_1_dq_2_ie),
+ .o(iocell_spi_1_dq_2_o),
+ .oe(iocell_spi_1_dq_2_oe)
+ );
+ GenericDigitalGPIOCell iocell_spi_1_dq_3 ( // @[IOCell.scala 110:22]
+ .pad(spi_1_dq_3),
+ .i(iocell_spi_1_dq_3_i),
+ .ie(iocell_spi_1_dq_3_ie),
+ .o(iocell_spi_1_dq_3_o),
+ .oe(iocell_spi_1_dq_3_oe)
+ );
+ GenericDigitalInIOCell iocell_uart_0_rxd ( // @[IOCell.scala 111:23]
+ .pad(iocell_uart_0_rxd_pad),
+ .i(iocell_uart_0_rxd_i),
+ .ie(iocell_uart_0_rxd_ie)
+ );
+ GenericDigitalOutIOCell iocell_uart_0_txd ( // @[IOCell.scala 112:24]
+ .pad(iocell_uart_0_txd_pad),
+ .o(iocell_uart_0_txd_o),
+ .oe(iocell_uart_0_txd_oe)
+ );
+ GenericDigitalInIOCell iocell_uart_1_rxd ( // @[IOCell.scala 111:23]
+ .pad(iocell_uart_1_rxd_pad),
+ .i(iocell_uart_1_rxd_i),
+ .ie(iocell_uart_1_rxd_ie)
+ );
+ GenericDigitalOutIOCell iocell_uart_1_txd ( // @[IOCell.scala 112:24]
+ .pad(iocell_uart_1_txd_pad),
+ .o(iocell_uart_1_txd_o),
+ .oe(iocell_uart_1_txd_oe)
+ );
+ assign jtag_TDO = iocell_jtag_TDO_pad; // @[IOCell.scala 239:25]
+ assign serial_tl_clock = iocell_serial_tl_clock_pad; // @[IOCell.scala 179:61]
+ assign serial_tl_bits_in_ready = iocell_serial_tl_bits_in_ready_pad; // @[IOCell.scala 239:25]
+ assign serial_tl_bits_out_valid = iocell_serial_tl_bits_out_valid_pad; // @[IOCell.scala 239:25]
+ assign serial_tl_bits_out_bits = {serial_tl_bits_out_bits_hi,serial_tl_bits_out_bits_lo}; // @[Cat.scala 31:58]
+ assign spi_0_sck = iocell_spi_0_sck_pad; // @[IOCell.scala 239:25]
+ assign spi_0_cs_0 = iocell_spi_0_cs_0_pad; // @[IOCell.scala 239:25]
+ assign spi_1_sck = iocell_spi_1_sck_pad; // @[IOCell.scala 239:25]
+ assign spi_1_cs_0 = iocell_spi_1_cs_0_pad; // @[IOCell.scala 239:25]
+ assign uart_0_txd = iocell_uart_0_txd_pad; // @[IOCell.scala 239:25]
+ assign uart_1_txd = iocell_uart_1_txd_pad; // @[IOCell.scala 239:25]
+ assign system_clock = chipyardPRCI_auto_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign system_reset = chipyardPRCI_auto_out_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_clock =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_clock; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_implicit_clock_reset =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_implicit_clock_reset; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_clock =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_clock; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_cbus_0_reset =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_cbus_0_reset; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_clock =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_clock; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_fbus_0_reset =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_fbus_0_reset; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_clock =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_clock; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_pbus_0_reset =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_pbus_0_reset; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_clock =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_clock; // @[LazyModule.scala 296:16]
+ assign system_auto_chipyardPRCI_chipyardPRCI_clock_in_member_allClocks_subsystem_sbus_0_reset =
+ dividerOnlyClockGen_auto_divider_only_clock_gen_out_member_allClocks_subsystem_sbus_0_reset; // @[LazyModule.scala 296:16]
+ assign system_custom_boot = iocell_custom_boot_i; // @[IOCell.scala 224:26]
+ assign system_serial_tl_bits_in_valid = iocell_serial_tl_bits_in_valid_i; // @[IOCell.scala 224:26]
+ assign system_serial_tl_bits_in_bits = {system_serial_tl_bits_in_bits_hi,system_serial_tl_bits_in_bits_lo}; // @[Cat.scala 31:58]
+ assign system_serial_tl_bits_out_ready = iocell_serial_tl_bits_out_ready_i; // @[IOCell.scala 224:26]
+ assign system_resetctrl_hartIsInReset_0 = system_auto_subsystem_cbus_fixedClockNode_out_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign system_debug_clock = gated_clock_debug_clock_gate_out; // @[Periphery.scala 303:19]
+ assign system_debug_reset = ~_debug_reset_syncd_WIRE; // @[Periphery.scala 291:40]
+ assign system_debug_systemjtag_jtag_TCK = iocell_jtag_TCK_i; // @[IOCell.scala 179:61]
+ assign system_debug_systemjtag_jtag_TMS = iocell_jtag_TMS_i; // @[IOBinders.scala 249:31 IOCell.scala 224:26]
+ assign system_debug_systemjtag_jtag_TDI = iocell_jtag_TDI_i; // @[IOBinders.scala 249:31 IOCell.scala 224:26]
+ assign system_debug_systemjtag_reset = system_debug_systemjtag_reset_catcher_io_sync_reset; // @[IOBinders.scala 235:21]
+ assign system_debug_dmactiveAck = dmactiveAck_dmactiveAck_io_q; // @[ShiftReg.scala 48:{24,24}]
+ assign system_uart_0_rxd = iocell_uart_0_rxd_i; // @[IOCell.scala 224:26]
+ assign system_uart_1_rxd = iocell_uart_1_rxd_i; // @[IOCell.scala 224:26]
+ assign system_gpio_0_pins_0_i_ival = iocell_gpio_0_0_i; // @[IOBinders.scala 142:20]
+ assign system_gpio_0_pins_1_i_ival = iocell_gpio_0_1_i; // @[IOBinders.scala 142:20]
+ assign system_gpio_0_pins_2_i_ival = iocell_gpio_0_2_i; // @[IOBinders.scala 142:20]
+ assign system_gpio_0_pins_3_i_ival = iocell_gpio_0_3_i; // @[IOBinders.scala 142:20]
+ assign system_qspi_0_dq_0_i = iocell_spi_0_dq_0_i; // @[IOBinders.scala 181:15]
+ assign system_qspi_0_dq_1_i = iocell_spi_0_dq_1_i; // @[IOBinders.scala 181:15]
+ assign system_qspi_0_dq_2_i = iocell_spi_0_dq_2_i; // @[IOBinders.scala 181:15]
+ assign system_qspi_0_dq_3_i = iocell_spi_0_dq_3_i; // @[IOBinders.scala 181:15]
+ assign system_qspi_1_dq_0_i = iocell_spi_1_dq_0_i; // @[IOBinders.scala 181:15]
+ assign system_qspi_1_dq_1_i = iocell_spi_1_dq_1_i; // @[IOBinders.scala 181:15]
+ assign system_qspi_1_dq_2_i = iocell_spi_1_dq_2_i; // @[IOBinders.scala 181:15]
+ assign system_qspi_1_dq_3_i = iocell_spi_1_dq_3_i; // @[IOBinders.scala 181:15]
+ assign chipyardPRCI_auto_in_member_chipyardPRCI_implicit_clock_clock =
+ system_auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_clock; // @[LazyModule.scala 298:16]
+ assign chipyardPRCI_auto_in_member_chipyardPRCI_implicit_clock_reset =
+ system_auto_chipyardPRCI_out_member_chipyardPRCI_implicit_clock_reset; // @[LazyModule.scala 298:16]
+ assign dividerOnlyClockGen_auto_divider_only_clock_gen_in_clock = iocell_clock_clock_i; // @[IOCell.scala 179:61]
+ assign dividerOnlyClockGen_auto_divider_only_clock_gen_in_reset = iocell_reset_i; // @[IOCell.scala 180:64]
+ assign system_debug_systemjtag_reset_catcher_clock = system_debug_systemjtag_jtag_TCK;
+ assign system_debug_systemjtag_reset_catcher_reset = system_auto_subsystem_cbus_fixedClockNode_out_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign debug_reset_syncd_debug_reset_sync_clock = system_auto_subsystem_cbus_fixedClockNode_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign debug_reset_syncd_debug_reset_sync_reset = system_debug_systemjtag_reset; // @[Periphery.scala 282:38]
+ assign debug_reset_syncd_debug_reset_sync_io_d = 1'h1; // @[ShiftReg.scala 47:16]
+ assign dmactiveAck_dmactiveAck_clock = system_auto_subsystem_cbus_fixedClockNode_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign dmactiveAck_dmactiveAck_reset = ~_debug_reset_syncd_WIRE; // @[Periphery.scala 297:38]
+ assign dmactiveAck_dmactiveAck_io_d = system_debug_dmactive; // @[ShiftReg.scala 47:16]
+ assign gated_clock_debug_clock_gate_in = system_auto_subsystem_cbus_fixedClockNode_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
+ assign gated_clock_debug_clock_gate_test_en = 1'h0; // @[ClockGate.scala 27:19]
+ assign gated_clock_debug_clock_gate_en = clock_en; // @[ClockGate.scala 28:14]
+ assign iocell_jtag_TDO_o = system_debug_systemjtag_jtag_TDO_data; // @[IOBinders.scala 249:31 253:25]
+ assign iocell_jtag_TDO_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_jtag_TDI_pad = jtag_TDI; // @[IOCell.scala 213:39]
+ assign iocell_jtag_TDI_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_jtag_TMS_pad = jtag_TMS; // @[IOCell.scala 213:39]
+ assign iocell_jtag_TMS_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_jtag_TCK_pad = jtag_TCK; // @[IOCell.scala 179:44]
+ assign iocell_jtag_TCK_ie = 1'h1; // @[IOCell.scala 164:24]
+ assign iocell_serial_tl_bits_out_bits_o = system_serial_tl_bits_out_bits[0]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_1_o = system_serial_tl_bits_out_bits[1]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_1_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_2_o = system_serial_tl_bits_out_bits[2]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_2_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_3_o = system_serial_tl_bits_out_bits[3]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_3_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_4_o = system_serial_tl_bits_out_bits[4]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_4_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_5_o = system_serial_tl_bits_out_bits[5]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_5_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_6_o = system_serial_tl_bits_out_bits[6]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_6_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_7_o = system_serial_tl_bits_out_bits[7]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_7_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_8_o = system_serial_tl_bits_out_bits[8]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_8_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_9_o = system_serial_tl_bits_out_bits[9]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_9_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_10_o = system_serial_tl_bits_out_bits[10]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_10_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_11_o = system_serial_tl_bits_out_bits[11]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_11_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_12_o = system_serial_tl_bits_out_bits[12]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_12_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_13_o = system_serial_tl_bits_out_bits[13]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_13_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_14_o = system_serial_tl_bits_out_bits[14]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_14_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_15_o = system_serial_tl_bits_out_bits[15]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_15_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_16_o = system_serial_tl_bits_out_bits[16]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_16_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_17_o = system_serial_tl_bits_out_bits[17]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_17_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_18_o = system_serial_tl_bits_out_bits[18]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_18_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_19_o = system_serial_tl_bits_out_bits[19]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_19_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_20_o = system_serial_tl_bits_out_bits[20]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_20_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_21_o = system_serial_tl_bits_out_bits[21]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_21_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_22_o = system_serial_tl_bits_out_bits[22]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_22_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_23_o = system_serial_tl_bits_out_bits[23]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_23_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_24_o = system_serial_tl_bits_out_bits[24]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_24_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_25_o = system_serial_tl_bits_out_bits[25]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_25_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_26_o = system_serial_tl_bits_out_bits[26]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_26_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_27_o = system_serial_tl_bits_out_bits[27]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_27_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_28_o = system_serial_tl_bits_out_bits[28]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_28_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_29_o = system_serial_tl_bits_out_bits[29]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_29_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_30_o = system_serial_tl_bits_out_bits[30]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_30_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_bits_31_o = system_serial_tl_bits_out_bits[31]; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_bits_31_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_valid_o = system_serial_tl_bits_out_valid; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_out_valid_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_bits_out_ready_pad = serial_tl_bits_out_ready; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_out_ready_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_pad = serial_tl_bits_in_bits[0]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_1_pad = serial_tl_bits_in_bits[1]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_1_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_2_pad = serial_tl_bits_in_bits[2]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_2_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_3_pad = serial_tl_bits_in_bits[3]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_3_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_4_pad = serial_tl_bits_in_bits[4]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_4_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_5_pad = serial_tl_bits_in_bits[5]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_5_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_6_pad = serial_tl_bits_in_bits[6]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_6_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_7_pad = serial_tl_bits_in_bits[7]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_7_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_8_pad = serial_tl_bits_in_bits[8]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_8_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_9_pad = serial_tl_bits_in_bits[9]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_9_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_10_pad = serial_tl_bits_in_bits[10]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_10_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_11_pad = serial_tl_bits_in_bits[11]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_11_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_12_pad = serial_tl_bits_in_bits[12]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_12_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_13_pad = serial_tl_bits_in_bits[13]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_13_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_14_pad = serial_tl_bits_in_bits[14]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_14_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_15_pad = serial_tl_bits_in_bits[15]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_15_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_16_pad = serial_tl_bits_in_bits[16]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_16_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_17_pad = serial_tl_bits_in_bits[17]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_17_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_18_pad = serial_tl_bits_in_bits[18]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_18_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_19_pad = serial_tl_bits_in_bits[19]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_19_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_20_pad = serial_tl_bits_in_bits[20]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_20_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_21_pad = serial_tl_bits_in_bits[21]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_21_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_22_pad = serial_tl_bits_in_bits[22]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_22_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_23_pad = serial_tl_bits_in_bits[23]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_23_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_24_pad = serial_tl_bits_in_bits[24]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_24_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_25_pad = serial_tl_bits_in_bits[25]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_25_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_26_pad = serial_tl_bits_in_bits[26]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_26_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_27_pad = serial_tl_bits_in_bits[27]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_27_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_28_pad = serial_tl_bits_in_bits[28]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_28_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_29_pad = serial_tl_bits_in_bits[29]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_29_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_30_pad = serial_tl_bits_in_bits[30]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_30_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_bits_31_pad = serial_tl_bits_in_bits[31]; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_bits_31_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_valid_pad = serial_tl_bits_in_valid; // @[IOCell.scala 213:39]
+ assign iocell_serial_tl_bits_in_valid_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_serial_tl_bits_in_ready_o = system_serial_tl_bits_in_ready; // @[IOCell.scala 228:40]
+ assign iocell_serial_tl_bits_in_ready_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_serial_tl_clock_o = system_serial_tl_clock; // @[IOCell.scala 179:44]
+ assign iocell_serial_tl_clock_oe = 1'h1; // @[IOCell.scala 172:24]
+ assign iocell_custom_boot_pad = custom_boot; // @[IOCell.scala 213:39]
+ assign iocell_custom_boot_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_clock_clock_pad = clock_clock; // @[IOCell.scala 179:44]
+ assign iocell_clock_clock_ie = 1'h1; // @[IOCell.scala 164:24]
+ assign iocell_reset_pad = reset; // @[IOCell.scala 180:54]
+ assign iocell_reset_ie = 1'h1; // @[IOCell.scala 164:24]
+ assign iocell_gpio_0_0_ie = system_gpio_0_pins_0_o_ie; // @[IOBinders.scala 141:22]
+ assign iocell_gpio_0_0_o = system_gpio_0_pins_0_o_oval; // @[IOBinders.scala 139:21]
+ assign iocell_gpio_0_0_oe = system_gpio_0_pins_0_o_oe; // @[IOBinders.scala 140:22]
+ assign iocell_gpio_0_1_ie = system_gpio_0_pins_1_o_ie; // @[IOBinders.scala 141:22]
+ assign iocell_gpio_0_1_o = system_gpio_0_pins_1_o_oval; // @[IOBinders.scala 139:21]
+ assign iocell_gpio_0_1_oe = system_gpio_0_pins_1_o_oe; // @[IOBinders.scala 140:22]
+ assign iocell_gpio_0_2_ie = system_gpio_0_pins_2_o_ie; // @[IOBinders.scala 141:22]
+ assign iocell_gpio_0_2_o = system_gpio_0_pins_2_o_oval; // @[IOBinders.scala 139:21]
+ assign iocell_gpio_0_2_oe = system_gpio_0_pins_2_o_oe; // @[IOBinders.scala 140:22]
+ assign iocell_gpio_0_3_ie = system_gpio_0_pins_3_o_ie; // @[IOBinders.scala 141:22]
+ assign iocell_gpio_0_3_o = system_gpio_0_pins_3_o_oval; // @[IOBinders.scala 139:21]
+ assign iocell_gpio_0_3_oe = system_gpio_0_pins_3_o_oe; // @[IOBinders.scala 140:22]
+ assign iocell_spi_0_sck_o = system_qspi_0_sck; // @[IOCell.scala 228:40]
+ assign iocell_spi_0_sck_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_spi_0_cs_0_o = system_qspi_0_cs_0; // @[IOCell.scala 228:40]
+ assign iocell_spi_0_cs_0_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_spi_0_dq_0_ie = 1'h1; // @[IOBinders.scala 180:22]
+ assign iocell_spi_0_dq_0_o = system_qspi_0_dq_0_o; // @[IOBinders.scala 178:21]
+ assign iocell_spi_0_dq_0_oe = system_qspi_0_dq_0_oe; // @[IOBinders.scala 179:22]
+ assign iocell_spi_0_dq_1_ie = 1'h1; // @[IOBinders.scala 180:22]
+ assign iocell_spi_0_dq_1_o = system_qspi_0_dq_1_o; // @[IOBinders.scala 178:21]
+ assign iocell_spi_0_dq_1_oe = system_qspi_0_dq_1_oe; // @[IOBinders.scala 179:22]
+ assign iocell_spi_0_dq_2_ie = 1'h1; // @[IOBinders.scala 180:22]
+ assign iocell_spi_0_dq_2_o = system_qspi_0_dq_2_o; // @[IOBinders.scala 178:21]
+ assign iocell_spi_0_dq_2_oe = system_qspi_0_dq_2_oe; // @[IOBinders.scala 179:22]
+ assign iocell_spi_0_dq_3_ie = 1'h1; // @[IOBinders.scala 180:22]
+ assign iocell_spi_0_dq_3_o = system_qspi_0_dq_3_o; // @[IOBinders.scala 178:21]
+ assign iocell_spi_0_dq_3_oe = system_qspi_0_dq_3_oe; // @[IOBinders.scala 179:22]
+ assign iocell_spi_1_sck_o = system_qspi_1_sck; // @[IOCell.scala 228:40]
+ assign iocell_spi_1_sck_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_spi_1_cs_0_o = system_qspi_1_cs_0; // @[IOCell.scala 228:40]
+ assign iocell_spi_1_cs_0_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_spi_1_dq_0_ie = 1'h1; // @[IOBinders.scala 180:22]
+ assign iocell_spi_1_dq_0_o = system_qspi_1_dq_0_o; // @[IOBinders.scala 178:21]
+ assign iocell_spi_1_dq_0_oe = system_qspi_1_dq_0_oe; // @[IOBinders.scala 179:22]
+ assign iocell_spi_1_dq_1_ie = 1'h1; // @[IOBinders.scala 180:22]
+ assign iocell_spi_1_dq_1_o = system_qspi_1_dq_1_o; // @[IOBinders.scala 178:21]
+ assign iocell_spi_1_dq_1_oe = system_qspi_1_dq_1_oe; // @[IOBinders.scala 179:22]
+ assign iocell_spi_1_dq_2_ie = 1'h1; // @[IOBinders.scala 180:22]
+ assign iocell_spi_1_dq_2_o = system_qspi_1_dq_2_o; // @[IOBinders.scala 178:21]
+ assign iocell_spi_1_dq_2_oe = system_qspi_1_dq_2_oe; // @[IOBinders.scala 179:22]
+ assign iocell_spi_1_dq_3_ie = 1'h1; // @[IOBinders.scala 180:22]
+ assign iocell_spi_1_dq_3_o = system_qspi_1_dq_3_o; // @[IOBinders.scala 178:21]
+ assign iocell_spi_1_dq_3_oe = system_qspi_1_dq_3_oe; // @[IOBinders.scala 179:22]
+ assign iocell_uart_0_rxd_pad = uart_0_rxd; // @[IOCell.scala 213:39]
+ assign iocell_uart_0_rxd_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_uart_0_txd_o = system_uart_0_txd; // @[IOCell.scala 228:40]
+ assign iocell_uart_0_txd_oe = 1'h1; // @[IOCell.scala 235:30]
+ assign iocell_uart_1_rxd_pad = uart_1_rxd; // @[IOCell.scala 213:39]
+ assign iocell_uart_1_rxd_ie = 1'h1; // @[IOCell.scala 220:30]
+ assign iocell_uart_1_txd_o = system_uart_1_txd; // @[IOCell.scala 228:40]
+ assign iocell_uart_1_txd_oe = 1'h1; // @[IOCell.scala 235:30]
+ always @(posedge bundleIn_0_clock or posedge _T) begin
+ if (_T) begin // @[ShiftReg.scala 48:{24,24}]
+ clock_en <= 1'h1;
+ end else begin
+ clock_en <= dmactiveAck_dmactiveAck_io_q;
+ end
+ end
+// Register and memory initialization
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+ integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+ `ifdef RANDOMIZE
+ `ifdef INIT_RANDOM
+ `INIT_RANDOM
+ `endif
+ `ifndef VERILATOR
+ `ifdef RANDOMIZE_DELAY
+ #`RANDOMIZE_DELAY begin end
+ `else
+ #0.002 begin end
+ `endif
+ `endif
+`ifdef RANDOMIZE_REG_INIT
+ _RAND_0 = {1{`RANDOM}};
+ clock_en = _RAND_0[0:0];
+`endif // RANDOMIZE_REG_INIT
+ if (_T) begin
+ clock_en = 1'h1;
+ end
+ `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+endmodule
+module data_arrays_0(
+ input [10:0] RW0_addr,
+ input RW0_en,
+ input RW0_clk,
+ input RW0_wmode,
+ input [7:0] RW0_wdata_0,
+ input [7:0] RW0_wdata_1,
+ input [7:0] RW0_wdata_2,
+ input [7:0] RW0_wdata_3,
+ input [7:0] RW0_wdata_4,
+ input [7:0] RW0_wdata_5,
+ input [7:0] RW0_wdata_6,
+ input [7:0] RW0_wdata_7,
+ output [7:0] RW0_rdata_0,
+ output [7:0] RW0_rdata_1,
+ output [7:0] RW0_rdata_2,
+ output [7:0] RW0_rdata_3,
+ output [7:0] RW0_rdata_4,
+ output [7:0] RW0_rdata_5,
+ output [7:0] RW0_rdata_6,
+ output [7:0] RW0_rdata_7,
+ input RW0_wmask_0,
+ input RW0_wmask_1,
+ input RW0_wmask_2,
+ input RW0_wmask_3,
+ input RW0_wmask_4,
+ input RW0_wmask_5,
+ input RW0_wmask_6,
+ input RW0_wmask_7
+);
+ wire [10:0] data_arrays_0_ext_RW0_addr;
+ wire data_arrays_0_ext_RW0_en;
+ wire data_arrays_0_ext_RW0_clk;
+ wire data_arrays_0_ext_RW0_wmode;
+ wire [63:0] data_arrays_0_ext_RW0_wdata;
+ wire [63:0] data_arrays_0_ext_RW0_rdata;
+ wire [7:0] data_arrays_0_ext_RW0_wmask;
+ wire [31:0] _GEN_4 = {RW0_wdata_7,RW0_wdata_6,RW0_wdata_5,RW0_wdata_4};
+ wire [31:0] _GEN_5 = {RW0_wdata_3,RW0_wdata_2,RW0_wdata_1,RW0_wdata_0};
+ wire [3:0] _GEN_10 = {RW0_wmask_7,RW0_wmask_6,RW0_wmask_5,RW0_wmask_4};
+ wire [3:0] _GEN_11 = {RW0_wmask_3,RW0_wmask_2,RW0_wmask_1,RW0_wmask_0};
+ data_arrays_0_ext data_arrays_0_ext (
+ .RW0_addr(data_arrays_0_ext_RW0_addr),
+ .RW0_en(data_arrays_0_ext_RW0_en),
+ .RW0_clk(data_arrays_0_ext_RW0_clk),
+ .RW0_wmode(data_arrays_0_ext_RW0_wmode),
+ .RW0_wdata(data_arrays_0_ext_RW0_wdata),
+ .RW0_rdata(data_arrays_0_ext_RW0_rdata),
+ .RW0_wmask(data_arrays_0_ext_RW0_wmask)
+ );
+ assign data_arrays_0_ext_RW0_clk = RW0_clk;
+ assign data_arrays_0_ext_RW0_en = RW0_en;
+ assign data_arrays_0_ext_RW0_addr = RW0_addr;
+ assign RW0_rdata_0 = data_arrays_0_ext_RW0_rdata[7:0];
+ assign RW0_rdata_1 = data_arrays_0_ext_RW0_rdata[15:8];
+ assign RW0_rdata_2 = data_arrays_0_ext_RW0_rdata[23:16];
+ assign RW0_rdata_3 = data_arrays_0_ext_RW0_rdata[31:24];
+ assign RW0_rdata_4 = data_arrays_0_ext_RW0_rdata[39:32];
+ assign RW0_rdata_5 = data_arrays_0_ext_RW0_rdata[47:40];
+ assign RW0_rdata_6 = data_arrays_0_ext_RW0_rdata[55:48];
+ assign RW0_rdata_7 = data_arrays_0_ext_RW0_rdata[63:56];
+ assign data_arrays_0_ext_RW0_wmode = RW0_wmode;
+ assign data_arrays_0_ext_RW0_wdata = {_GEN_4,_GEN_5};
+ assign data_arrays_0_ext_RW0_wmask = {_GEN_10,_GEN_11};
+endmodule
+module tag_array(
+ input [5:0] RW0_addr,
+ input RW0_en,
+ input RW0_clk,
+ input RW0_wmode,
+ input [20:0] RW0_wdata_0,
+ output [20:0] RW0_rdata_0
+);
+ wire [5:0] tag_array_ext_RW0_addr;
+ wire tag_array_ext_RW0_en;
+ wire tag_array_ext_RW0_clk;
+ wire tag_array_ext_RW0_wmode;
+ wire [20:0] tag_array_ext_RW0_wdata;
+ wire [20:0] tag_array_ext_RW0_rdata;
+ wire tag_array_ext_RW0_wmask;
+ tag_array_ext tag_array_ext (
+ .RW0_addr(tag_array_ext_RW0_addr),
+ .RW0_en(tag_array_ext_RW0_en),
+ .RW0_clk(tag_array_ext_RW0_clk),
+ .RW0_wmode(tag_array_ext_RW0_wmode),
+ .RW0_wdata(tag_array_ext_RW0_wdata),
+ .RW0_rdata(tag_array_ext_RW0_rdata),
+ .RW0_wmask(tag_array_ext_RW0_wmask)
+ );
+ assign tag_array_ext_RW0_clk = RW0_clk;
+ assign tag_array_ext_RW0_en = RW0_en;
+ assign tag_array_ext_RW0_addr = RW0_addr;
+ assign RW0_rdata_0 = tag_array_ext_RW0_rdata;
+ assign tag_array_ext_RW0_wmode = RW0_wmode;
+ assign tag_array_ext_RW0_wdata = RW0_wdata_0;
+ assign tag_array_ext_RW0_wmask = 1'h1;
+endmodule
+module data_arrays_0_0(
+ input [8:0] RW0_addr,
+ input RW0_en,
+ input RW0_clk,
+ input RW0_wmode,
+ input [31:0] RW0_wdata_0,
+ output [31:0] RW0_rdata_0
+);
+ wire [8:0] data_arrays_0_0_ext_RW0_addr;
+ wire data_arrays_0_0_ext_RW0_en;
+ wire data_arrays_0_0_ext_RW0_clk;
+ wire data_arrays_0_0_ext_RW0_wmode;
+ wire [31:0] data_arrays_0_0_ext_RW0_wdata;
+ wire [31:0] data_arrays_0_0_ext_RW0_rdata;
+ wire data_arrays_0_0_ext_RW0_wmask;
+ data_arrays_0_0_ext data_arrays_0_0_ext (
+ .RW0_addr(data_arrays_0_0_ext_RW0_addr),
+ .RW0_en(data_arrays_0_0_ext_RW0_en),
+ .RW0_clk(data_arrays_0_0_ext_RW0_clk),
+ .RW0_wmode(data_arrays_0_0_ext_RW0_wmode),
+ .RW0_wdata(data_arrays_0_0_ext_RW0_wdata),
+ .RW0_rdata(data_arrays_0_0_ext_RW0_rdata),
+ .RW0_wmask(data_arrays_0_0_ext_RW0_wmask)
+ );
+ assign data_arrays_0_0_ext_RW0_clk = RW0_clk;
+ assign data_arrays_0_0_ext_RW0_en = RW0_en;
+ assign data_arrays_0_0_ext_RW0_addr = RW0_addr;
+ assign RW0_rdata_0 = data_arrays_0_0_ext_RW0_rdata;
+ assign data_arrays_0_0_ext_RW0_wmode = RW0_wmode;
+ assign data_arrays_0_0_ext_RW0_wdata = RW0_wdata_0;
+ assign data_arrays_0_0_ext_RW0_wmask = 1'h1;
+endmodule
diff --git a/verilog/rtl/rocketAlpha/plusarg_reader.v b/verilog/rtl/rocketAlpha/plusarg_reader.v
new file mode 100644
index 0000000..c1e0311
--- /dev/null
+++ b/verilog/rtl/rocketAlpha/plusarg_reader.v
@@ -0,0 +1,26 @@
+// See LICENSE.SiFive for license details.
+
+//VCS coverage exclude_file
+
+// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),
+// but Incisive demands them. These default values should never be used.
+module plusarg_reader #(
+ parameter FORMAT="borked=%d",
+ parameter WIDTH=1,
+ parameter [WIDTH-1:0] DEFAULT=0
+) (
+ output [WIDTH-1:0] out
+);
+
+`ifdef SYNTHESIS
+assign out = DEFAULT;
+`else
+reg [WIDTH-1:0] myplus;
+assign out = myplus;
+
+initial begin
+ if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
+end
+`endif
+
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..78a23cc 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -81,43 +81,42 @@
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
-
-user_proj_example mprj (
+user_project_wrapper1 Inst_user_project_wrapper1 (
`ifdef USE_POWER_PINS
- .vccd1(vccd1), // User area 1 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
+ .vdda1(vdda1), // User area 1 3.3V supply
+ .vdda2(vdda2), // User area 2 3.3V supply
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V supply
+ .vccd2(vccd2), // User area 2 1.8v supply
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
`endif
-
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
+ .wbs_cyc_i(wbs_cyc_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
+ .wbs_adr_i(wbs_adr_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
.la_data_in(la_data_in),
.la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
+ .la_oenb(la_oenb),
+ .io_in(io_in),
.io_out(io_out),
.io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
+ .analog_io(analog_io),
+ .user_clock2(user_clock2),
+ .user_irq(user_irq)
);
+`ifndef VERBOSE
+ `define VERBOSE 0
+`endif
+
endmodule // user_project_wrapper
`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper1.v b/verilog/rtl/user_project_wrapper1.v
new file mode 100644
index 0000000..542c451
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper1.v
@@ -0,0 +1,182 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper1 #(
+ parameter BITS = 32
+) (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+ wire gpio_0_0;
+ wire gpio_0_1;
+ wire gpio_0_2;
+ wire gpio_0_3;
+
+ wire spi_0_dq_0;
+ wire spi_0_dq_1;
+ wire spi_0_dq_2;
+ wire spi_0_dq_3;
+
+ wire spi_1_dq_0;
+ wire spi_1_dq_1;
+ wire spi_1_dq_2;
+ wire spi_1_dq_3;
+
+ assign io_in[34] = gpio_0_0;
+ assign io_out[34] = gpio_0_0;
+ assign io_in[35] = gpio_0_1;
+ assign io_out[35] = gpio_0_1;
+ assign io_in[36] = gpio_0_2;
+ assign io_out[36] = gpio_0_2;
+ assign io_in[37] = gpio_0_3;
+ assign io_out[37] = gpio_0_3;
+
+ assign io_in[21] = spi_0_dq_0;
+ assign io_out[21] = spi_0_dq_0;
+ assign io_in[22] = spi_0_dq_1;
+ assign io_out[22] = spi_0_dq_1;
+ assign io_in[23] = spi_0_dq_2;
+ assign io_out[23] = spi_0_dq_2;
+ assign io_in[24] = spi_0_dq_3;
+ assign io_out[24] = spi_0_dq_3;
+
+ assign io_in[27] = spi_1_dq_0;
+ assign io_out[27] = spi_1_dq_0;
+ assign io_in[28] = spi_1_dq_1;
+ assign io_out[28] = spi_1_dq_1;
+ assign io_in[29] = spi_1_dq_2;
+ assign io_out[29] = spi_1_dq_2;
+ assign io_in[30] = spi_1_dq_3;
+ assign io_out[30] = spi_1_dq_3;
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+ChipTop Inst_ChipTop (
+`ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+`endif
+ .io_oeb(io_oeb),
+ .jtag_TCK(io_in[15]), // In
+ .jtag_TMS(io_in[16]), // In
+ .jtag_TDI(io_in[17]), // In
+ .jtag_TDO(io_out[18]), // Out
+
+ // Unconnected or connect to LA pins
+ .serial_tl_clock(la_data_out[1]), // Out
+ .serial_tl_bits_in_ready(la_data_out[2]), // Out
+ .serial_tl_bits_in_valid(la_data_in[2]), // In
+ .serial_tl_bits_in_bits(la_data_in[41:10]), // In 32bits
+ .serial_tl_bits_out_ready(la_data_in[3]), // In
+ .serial_tl_bits_out_valid(la_data_out[3]), // Out
+ .serial_tl_bits_out_bits(la_data_out[81:50]), // Out 32bits
+
+ .custom_boot(io_in[11]), // In
+ .clock_clock(wb_clk_i), // In
+ .reset(io_in[12]), // In
+
+ .gpio_0_0(gpio_0_0), // InOut
+ .gpio_0_1(gpio_0_1), // InOut
+ .gpio_0_2(gpio_0_2), // InOut
+ .gpio_0_3(gpio_0_3), // InOut
+
+ // SPI 0 - FLASH
+ .spi_0_sck(io_out[19]), // Out
+ .spi_0_cs_0(io_out[20]), // Out
+ .spi_0_dq_0(spi_0_dq_0), // InOut
+ .spi_0_dq_1(spi_0_dq_1), // InOut
+ .spi_0_dq_2(spi_0_dq_2), // InOut
+ .spi_0_dq_3(spi_0_dq_3), // InOut
+
+ // SPI 1 - FLASH
+ .spi_1_sck(io_out[25]), // Out
+ .spi_1_cs_0(io_out[26]), // Out
+ .spi_1_dq_0(spi_1_dq_0), // InOut
+ .spi_1_dq_1(spi_1_dq_1), // InOut
+ .spi_1_dq_2(spi_1_dq_2), // InOut
+ .spi_1_dq_3(spi_1_dq_3), // InOut
+
+ .uart_0_txd(io_out[13]), // Out
+ .uart_0_rxd(io_in[14]), // In
+
+ .uart_1_txd(io_out[32]), // Out
+ .uart_1_rxd(io_in[33]) // In
+);
+
+`ifndef VERBOSE
+ `define VERBOSE 0
+`endif
+
+endmodule // user_project_wrapper
+
+`default_nettype wire
