Update RTL design files
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 26081e9..e803d4f 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -39,8 +39,8 @@
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
- inout vccd1, // User area 1 1.8V supply
- inout vssd1, // User area 1 digital ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
@@ -83,6 +83,8 @@
wire [3:0] wstrb;
wire [31:0] la_write;
+ wire can_tx, can_rx;
+
// WB MI A
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
@@ -90,76 +92,59 @@
assign wdata = wbs_dat_i;
// IO
- assign io_out = count;
- assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+ // assign io_out = count;
+ // assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+
+ assign io_oeb[(`MPRJ_IO_PADS-1):2] = {(`MPRJ_IO_PADS-3){1'b0}};
+ assign io_out[(`MPRJ_IO_PADS-1):2] = {(`MPRJ_IO_PADS-3){1'b1}};
+
+ assign io_out[0] = can_tx;
+ assign io_oeb[0] = 1'b0;
+
+ assign can_rx = io_in[1];
+ assign io_oeb[1] = 1'b1;
// IRQ
- assign irq = 3'b000; // Unused
+ assign irq = 3'b000; // Unused
// LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+ assign la_data_out[127:96] = {(BITS){1'b0}};
+ assign la_data_out[63:32] = {(BITS){1'b0}};
+ assign la_data_out[31:0] = {(BITS){1'b0}};
- counter #(
+ // assign la_data_out = {{(127-BITS){1'b0}}, count};
+ // Assuming LA probes [63:32] are for controlling the count register
+ // assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
+ // Assuming LA probes [65:64] are for controlling the count clk & reset
+ // assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+ // assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+
+ assign clk = wb_clk_i;
+ assign rst = wb_rst_i;
+
+ yonga_can_top #(
.BITS(BITS)
- ) counter(
+ ) yonga_can_top(
.clk(clk),
- .reset(rst),
+ .rst(rst),
+
.ready(wbs_ack_o),
.valid(valid),
+
.rdata(rdata),
.wdata(wbs_dat_i),
.wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
+
+ .device_reg_wr_en(la_data_in[5]),
+ .device_addr(la_data_in[4:0]),
+ .device_reg_wr_data(la_data_in[63:32]),
+ .device_reg_rd_data(la_data_out[95:64]),
+
+ .can_tx(can_tx),
+ .can_rx(can_rx),
+
.count(count)
);
endmodule
-
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
-);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
- end
- end
-
-endmodule
`default_nettype wire
diff --git a/verilog/rtl/yonga_can_controller.v b/verilog/rtl/yonga_can_controller.v
new file mode 100644
index 0000000..a14bbc5
--- /dev/null
+++ b/verilog/rtl/yonga_can_controller.v
@@ -0,0 +1,253 @@
+// MIT License
+
+// Copyright (c) [2022] [Yonga Technology Microelectronics R&D]
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+
+// DESCRIPTION
+
+// The yonga_can_controller module manages the operations in CAN peripheral
+
+module yonga_can_controller(
+ input wire i_controller_clk,
+ input wire i_controller_rst,
+
+ input wire i_pulse_gen_synced,
+ input wire i_packetizer_rdy,
+ input wire i_ack_slot,
+ output reg o_packetizer_en,
+ output reg o_pulse_gen_en,
+
+ input wire i_packetizer_message_bit,
+ input wire i_message_bit,
+ output reg o_message_bit,
+
+ input wire i_drive_pulse,
+ input wire i_sample_pulse,
+
+ input wire i_config_enable,
+ input wire i_sys_ctrl_sts_send,
+ output reg [2:0] o_sts_code
+);
+
+ parameter STATE_RESET = 0, STATE_SYNC = 1, STATE_CHECK_IDLE = 2, STATE_DRIVE_DATA = 3, STATE_SAMPLE_DATA = 4, STATE_IFS = 5, STATE_ERROR = 6, STATE_EN_PACKETIZER = 7;
+ reg done_tx;
+ reg [2:0] state_reg;
+ reg bit_transmitted;
+ reg [5:0] bitcounter_reg;
+ reg prev_bit_reg;
+ reg [3:0] consecutive_ones_reg;
+ reg [3:0] zeros_reg;
+ reg is_extended, is_standart;
+ reg is_idle;
+
+ always @(posedge i_controller_clk) begin
+ if(i_controller_rst) begin
+ state_reg <= STATE_RESET;
+ o_packetizer_en <= 1'b0;
+ o_pulse_gen_en <= 1'b0;
+ o_sts_code <= 3'b0;
+ o_message_bit <= 1'b1;
+ done_tx <= 1'b0;
+ bitcounter_reg <= 6'd0;
+ consecutive_ones_reg <= 4'd0;
+ is_standart <= 1'b1;
+ is_extended <= 1'b0;
+ zeros_reg <= 4'd0;
+ prev_bit_reg <= 1'b0;
+ is_idle <= 1'b0;
+ end
+ else begin
+ case(state_reg)
+
+ STATE_RESET: begin
+ o_sts_code <= 3'b0;
+ o_message_bit <= 1'b1;
+ done_tx <= 1'b0;
+ bitcounter_reg <= 6'd0;
+ is_standart <= 1'b1;
+ is_extended <= 1'b0;
+ if((i_config_enable == 0) && (i_sys_ctrl_sts_send == 1)) begin
+ state_reg <= STATE_SYNC;
+ o_pulse_gen_en <= 1'b1;
+ end
+ end
+
+ STATE_SYNC: begin
+ if(i_pulse_gen_synced) begin
+ state_reg <= STATE_CHECK_IDLE;
+ end
+ end
+
+ STATE_CHECK_IDLE: begin
+ o_sts_code <= 3'b0;
+ if(i_sample_pulse) begin
+ if(~is_idle) begin
+ prev_bit_reg <= i_message_bit;
+ if(prev_bit_reg) begin
+ if(i_message_bit) begin
+ consecutive_ones_reg <= consecutive_ones_reg + 1;
+ end
+ else begin
+ consecutive_ones_reg <= 4'd0;
+ end
+ if(consecutive_ones_reg == 4'd9) begin
+ consecutive_ones_reg = 4'd0;
+ state_reg <= STATE_EN_PACKETIZER;
+ is_idle <= 1'b0;
+ end
+ end
+ end
+ else begin
+ state_reg <= STATE_EN_PACKETIZER;
+ is_idle <= 1'b0;
+ end
+ end
+ end
+
+ STATE_EN_PACKETIZER: begin
+ o_packetizer_en <= 1'b1;
+ if(i_drive_pulse == 1) begin
+ state_reg <= STATE_DRIVE_DATA;
+ end
+ end
+
+ STATE_DRIVE_DATA: begin
+ if(i_drive_pulse == 1) begin
+
+ state_reg <= STATE_SAMPLE_DATA;
+
+ if(bitcounter_reg == 13 && i_packetizer_message_bit == 0) begin
+
+ is_standart <= 1'b1;
+ is_extended <= 1'b0;
+
+ end
+ else if(bitcounter_reg == 13 && i_packetizer_message_bit == 1) begin
+
+ is_standart <= 1'b0;
+ is_extended <= 1'b1;
+
+ end
+
+ bit_transmitted <= i_packetizer_message_bit;
+ o_message_bit <= i_packetizer_message_bit;
+
+ end
+ end
+
+ STATE_SAMPLE_DATA: begin
+ if(i_sample_pulse == 1) begin
+ bitcounter_reg <= bitcounter_reg + 1;
+ prev_bit_reg <= i_message_bit;
+ if(prev_bit_reg) begin
+ if(i_message_bit) begin
+ consecutive_ones_reg <= consecutive_ones_reg + 1;
+ end
+ else begin
+ consecutive_ones_reg <= 4'd0;
+ end
+ end
+ if(bit_transmitted == i_message_bit) begin
+ if(i_ack_slot) begin
+ o_sts_code <= 3'h3;
+ bitcounter_reg <= 0;
+ o_packetizer_en <= 0;
+ state_reg <= STATE_IFS;
+ end
+ else if(i_packetizer_rdy) begin // EOF flag
+ o_packetizer_en <= 0;
+ bitcounter_reg <= 0;
+ state_reg <= STATE_IFS;
+ end
+ else begin
+ state_reg <= STATE_DRIVE_DATA;
+ end
+ end
+ else begin
+ if(i_ack_slot == 1) begin
+ o_sts_code <= 3'h1;
+ state_reg <= STATE_DRIVE_DATA;
+ end
+ else begin
+ if(is_standart) begin
+
+ if(bitcounter_reg < 6'd14) begin // Why 14? SOF + 11 bit standart arbitration field + RTR.
+ o_sts_code <= 3'h2;
+ o_packetizer_en <= 0;
+ state_reg <= STATE_CHECK_IDLE; // Sampled data and transmitted data does not match. Arbitration is lost to another node. STANDART FORMAT
+ bitcounter_reg <= 6'd0;
+ end
+ else begin
+ o_sts_code <= 3'h2;
+ o_packetizer_en <= 0;
+ bitcounter_reg <= 6'd0; // Sampled data and data on bus does not match. Bit error occured. Push eror frame to bus.
+ state_reg <= STATE_ERROR;
+ end
+ end
+
+ if(is_extended) begin
+
+ if(bitcounter_reg < 6'd34) begin // Why 34? SOF + 32 bit extended arbitration field.
+ o_sts_code <= 3'h2;
+ o_packetizer_en <= 0;
+ state_reg <= STATE_CHECK_IDLE; // Sampled data and transmitted data does not match. Arbitration is lost to another node. EXTENDED FORMAT
+ bitcounter_reg <= 6'd0;
+ end
+ else begin
+
+ o_sts_code <= 3'h2;
+ o_packetizer_en <= 0;
+ state_reg <= STATE_ERROR; // Sampled data and data on bus does not match. Bit error occured. Push eror frame to bus.
+ bitcounter_reg <= 6'd0;
+
+ end
+ end
+ end
+ end
+ end
+ end
+
+ STATE_IFS: begin
+ if(i_drive_pulse == 1'b1) begin
+ if(bitcounter_reg == 6'd2) begin
+ bitcounter_reg <= 6'd0;
+ o_message_bit <= 1;
+ is_idle <= 1'b1;
+ consecutive_ones_reg <= consecutive_ones_reg + 1;
+ done_tx <= 1'b1;
+ state_reg <= STATE_RESET;
+ end
+ else begin
+ state_reg <= STATE_IFS;
+ consecutive_ones_reg <= consecutive_ones_reg + 1;
+ o_message_bit <= 1;
+ bitcounter_reg <= bitcounter_reg + 1;
+ end
+ end
+ end
+ STATE_ERROR: begin
+ state_reg <= STATE_ERROR;
+ // FILL HERE
+
+ end
+ endcase
+ end
+ end
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/yonga_can_packetizer.v b/verilog/rtl/yonga_can_packetizer.v
new file mode 100644
index 0000000..7e19b32
--- /dev/null
+++ b/verilog/rtl/yonga_can_packetizer.v
@@ -0,0 +1,2265 @@
+// MIT License
+
+// Copyright (c) [2022] [Yonga Technology Microelectronics R&D]
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+
+// DESCRIPTION
+
+// The yonga_can_packetizer module forms a CAN frame in accordance with CAN 2.0B standard
+
+module yonga_can_packetizer(
+ input wire i_packetizer_clk,
+ input wire i_packetizer_rst,
+
+ input wire i_packetizer_en,
+ input wire i_drive_pulse,
+ input wire [11-1:0] i_packetizer_message_sid,
+ input wire i_packetizer_message_ide,
+ input wire i_packetizer_message_r0,
+ input wire i_packetizer_message_r1,
+ input wire i_packetizer_message_srr,
+ input wire [18-1:0] i_packetizer_message_eid,
+
+ input wire i_packetizer_message_rtr,
+ input wire [4-1:0] i_packetizer_message_dlc,
+
+ input wire [8-1:0] i_packetizer_message_data_byte_0,
+ input wire [8-1:0] i_packetizer_message_data_byte_1,
+ input wire [8-1:0] i_packetizer_message_data_byte_2,
+ input wire [8-1:0] i_packetizer_message_data_byte_3,
+ input wire [8-1:0] i_packetizer_message_data_byte_4,
+ input wire [8-1:0] i_packetizer_message_data_byte_5,
+ input wire [8-1:0] i_packetizer_message_data_byte_6,
+ input wire [8-1:0] i_packetizer_message_data_byte_7,
+
+ output wire o_packetizer_rdy,
+ input wire i_packetizer_req,
+
+ output reg o_packetizer_message_bit,
+ input wire i_packetizer_message_bit,
+ output reg o_ack_slot
+ );
+
+ // state registers
+ parameter STATE_IDLE = 0, STATE_SOF = 1 , STATE_SID = 2, STATE_RTR = 3, STATE_SRR = 4, STATE_IDE = 5, STATE_EID = 6,STATE_CTRL = 7,
+ STATE_DATA = 8, STATE_CRC = 9, STATE_ACK = 10, STATE_EOF = 11, STATE_IFS = 12;
+
+ reg [3:0] state_reg;
+ reg [3:0] state_reg_previous;
+ // data registers
+ reg [11-1:0] message_sid;
+ reg message_ide;
+ reg message_r0;
+ reg [18-1:0] message_eid;
+ reg message_rtr;
+ reg message_srr;
+ reg [6-1:0] message_control;
+ reg [4-1:0] message_dlc;
+ reg [64-1:0] message_data;
+
+ // control and status registers
+ reg prev_bit_reg;
+ reg [7-1:0] bit_counter_reg;
+ reg stuff_bit_exception_reg;
+ reg [4-1:0] num_of_consec_ones_reg;
+ reg [4-1:0] num_of_consec_zeros_reg;
+ reg packetizer_rdy_reg;
+ wire stuff_bit_exception_negedge;
+ reg stuff_bit_exception_prev;
+
+ // CRC register
+ reg [14:0] crc_reg;
+ wire next_bit;
+ wire crc_valid;
+ reg crc_enable;
+ reg prev_drive;
+ wire negedge_drive;
+
+ assign next_bit = state_reg != STATE_CRC ? o_packetizer_message_bit : 1'b0;
+ assign crc_valid = crc_enable & ~stuff_bit_exception_negedge;
+ assign negedge_drive = prev_drive & ~i_drive_pulse;
+ assign stuff_bit_exception_negedge = stuff_bit_exception_prev & ~stuff_bit_exception_reg;
+ always@(posedge i_packetizer_clk)
+ begin
+ prev_drive <= i_drive_pulse;
+ if(i_packetizer_rst == 1'b1)
+ begin
+ prev_bit_reg <= 1'b0;
+ stuff_bit_exception_reg <= 1'b0;
+ num_of_consec_ones_reg <= 4'b0;
+ num_of_consec_zeros_reg <= 4'b0;
+ bit_counter_reg <= 7'b0;
+ packetizer_rdy_reg <= 1'b0;
+ state_reg <= STATE_IDLE;
+ crc_reg <= 15'b0;
+ o_ack_slot <= 1'b0;
+ crc_enable <= 1'b0;
+
+ end
+ else
+ begin
+ stuff_bit_exception_prev <= stuff_bit_exception_reg;
+ state_reg_previous <= state_reg;
+ if(prev_drive) begin
+ if(crc_valid)
+ begin
+ //crc_next = next_bit ^ crc_reg[14];
+ crc_reg <= crc_reg << 1'b1;
+ if(next_bit ^ crc_reg[14])
+ begin
+ crc_reg <= (crc_reg<<1'b1) ^ 16'hC599;
+ end
+ //crc_reg = crc_reg & 16'h7FFF;
+ end
+ end
+ if(i_drive_pulse) begin
+ case(state_reg)
+ STATE_IDLE:
+ begin
+ packetizer_rdy_reg <= 1'b0;
+ o_packetizer_message_bit <= 1'b1;
+ message_sid <= i_packetizer_message_sid;
+ message_ide <= i_packetizer_message_ide;
+ message_eid <= i_packetizer_message_eid;
+ message_rtr <= i_packetizer_message_rtr;
+ message_srr <= i_packetizer_message_srr;
+
+ message_data <= {i_packetizer_message_data_byte_7,i_packetizer_message_data_byte_6, i_packetizer_message_data_byte_5, i_packetizer_message_data_byte_4, i_packetizer_message_data_byte_3, i_packetizer_message_data_byte_2, i_packetizer_message_data_byte_1, i_packetizer_message_data_byte_0};
+ if(i_packetizer_message_ide==1)
+ begin
+ message_control <= {i_packetizer_message_r1, i_packetizer_message_r0, i_packetizer_message_dlc};
+ end
+ else
+ begin
+ message_control <= {i_packetizer_message_ide, i_packetizer_message_r0, i_packetizer_message_dlc};
+ end
+ crc_reg <= 15'b0;
+
+ if(i_packetizer_message_dlc >= 4'd8 )
+ begin
+ message_dlc <= 4'd8;
+ end
+ else
+ begin
+ message_dlc <= i_packetizer_message_dlc;
+ end
+ //if(i_packetizer_en)
+ //begin
+ state_reg <= STATE_SOF;
+ crc_enable <= 1'b0;
+
+ //prev_bit_reg <= 1'b0;
+
+ //end
+ end
+
+ STATE_SOF :
+ begin
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else begin
+ o_packetizer_message_bit <= 1'b0;
+ // start counting bit levels - this is needed to inject stuff bits into bitstream
+ prev_bit_reg <= 1'b0;
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+ crc_enable <= 1'b1;
+ state_reg <= STATE_SID;
+
+ end
+
+ end
+
+ STATE_SID :
+ begin
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_sid[10];
+ crc_enable <= 1'b1;
+ prev_bit_reg <= ~message_sid[10];
+
+ // shift message_sid register left by 1-bit
+ message_sid <= message_sid << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd10)
+ begin
+ bit_counter_reg <= 7'd0;
+ if(message_ide==1)
+ state_reg <= STATE_SRR;
+ else
+ state_reg <= STATE_RTR;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_SID;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_sid[10])
+ begin
+ if(message_sid[10] == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_sid[10];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_sid[10];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_sid[10] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+ //message_sid <= message_sid << 1'b1;
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_sid <= message_sid << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd10)
+ begin
+ bit_counter_reg <= 7'd0;
+ if(message_ide==1)
+ state_reg <= STATE_SRR;
+ else
+ state_reg <= STATE_RTR;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_SID;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_sid[10];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_sid[10];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_sid[10] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_sid <= message_sid << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd10)
+ begin
+ bit_counter_reg <= 7'd0;
+ if(message_ide==1)
+ state_reg <= STATE_SRR;
+ else
+ state_reg <= STATE_RTR;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_SID;
+ end
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_sid[10];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_sid <= message_sid << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_sid[10];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd10)
+ begin
+ bit_counter_reg <= 7'd0;
+ if(message_ide==1)
+ state_reg <= STATE_SRR;
+ else
+ state_reg <= STATE_RTR;
+ end
+ else begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_SID;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+ end
+
+ STATE_RTR :
+ begin
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_rtr;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= ~message_rtr;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_CTRL;
+ end
+ else
+ begin
+ if(prev_bit_reg == message_rtr)
+ begin
+ if(message_rtr == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_rtr;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_rtr;
+
+ if(num_of_consec_ones_reg == 4'd3 && message_rtr == 1'b1)
+ begin
+ stuff_bit_exception_reg <= 1'b1;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_CTRL;
+ end
+
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_rtr;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_rtr;
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_rtr == 1'b0)
+ begin
+ stuff_bit_exception_reg <= 1'b1;
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_CTRL;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_rtr;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_rtr;
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_CTRL;
+ end
+ end
+ end
+
+ STATE_SRR :
+ begin
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_srr;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= ~message_srr;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_IDE;
+ end
+ else
+ begin
+ if(prev_bit_reg == message_srr)
+ begin
+ if(message_srr == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_srr;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_srr;
+
+ if(num_of_consec_ones_reg == 4'd3 && message_srr == 1'b1)
+ begin
+ stuff_bit_exception_reg <= 1'b1;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_IDE;
+ end
+
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_srr;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_srr;
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_srr == 1'b0)
+ begin
+ stuff_bit_exception_reg <= 1'b1;
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_IDE;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_srr;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_srr;
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_IDE;
+ end
+ end
+ end
+ STATE_IDE :
+ begin
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_ide;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= ~message_ide;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_EID;
+ end
+ else
+ begin
+ if(prev_bit_reg == message_ide)
+ begin
+ if(message_ide == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_ide;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_ide;
+
+ if(num_of_consec_ones_reg == 4'd3 && message_ide == 1'b1)
+ begin
+ stuff_bit_exception_reg <= 1'b1;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_EID;
+ end
+
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_ide;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_ide;
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_ide == 1'b0)
+ begin
+ stuff_bit_exception_reg <= 1'b1;
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_EID;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_ide;
+ crc_enable <= 1'b1;
+ prev_bit_reg <= message_ide;
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_EID;
+ end
+ end
+ end
+
+ STATE_EID :
+ begin
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_eid[17];
+ crc_enable <= 1'b1;
+ prev_bit_reg <= ~message_eid[17];
+
+ // shift message_eid register left by 1-bit
+ message_eid <= message_eid << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd17)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_RTR;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_EID;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_eid[17])
+ begin
+ if(message_eid[17] == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_eid[17];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_eid[17];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_eid[17] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+ //message_sid <= message_sid << 1'b1;
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_eid register left by 1-bit
+ message_eid <= message_eid << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd17)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_RTR;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_EID;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_eid[17];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_eid[17];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_eid[17] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_eid register left by 1-bit
+ message_eid <= message_eid << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd17)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_RTR;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_EID;
+ end
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_eid[17];
+ crc_enable <= 1'b1;
+ // shift message_eid register left by 1-bit
+ message_eid <= message_eid << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_eid[17];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd17)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_RTR;
+ end
+ else begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_EID;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+ end
+
+ STATE_CTRL:
+ begin
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_control[5];
+ crc_enable <= 1'b1;
+ // shift message control register left by 1-bit
+ message_control <= message_control << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ prev_bit_reg <= ~message_control[5];
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd5)
+ begin
+ bit_counter_reg <= 7'd0;
+ if(message_rtr)
+ begin
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_CTRL;
+ //end
+ end
+ end
+
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_control[5])
+ begin
+ if(message_control[5] == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_control[5];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_control[5];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_control[5] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_control register left by 1-bit
+ message_control <= message_control << 1'b1;
+
+ // check if the current bit sent is the last bit of message_control field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd5)
+ begin
+ bit_counter_reg <= 7'd0;
+ if(message_rtr)
+ begin
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ state_reg <= STATE_DATA;
+ end
+ end
+ else begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_CTRL;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_control[5];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_control[5];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_control[5] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_control <= message_control << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd5)
+ begin
+ bit_counter_reg <= 7'd0;
+ if(message_rtr)
+ begin
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_CTRL;
+ end
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_control[5];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_control <= message_control << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_control[5];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd5)
+ begin
+ bit_counter_reg <= 7'd0;
+ if(message_rtr)
+ begin
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_CTRL;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+ end
+
+ STATE_DATA:
+ begin
+ if(message_dlc == 'd0)
+ begin
+ //message_data <= null;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else
+ state_reg <= STATE_CRC;
+ end
+
+
+ else if(message_dlc == 'd1)
+ begin
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_data[7];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+
+ prev_bit_reg <= ~message_data[7];
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd7)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_data[7])
+ begin
+ if(message_data[7] == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_data[7];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[7];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_data[7] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd7)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[7];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[7];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_data[7] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd7)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[7];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[7];
+
+ // check if the current bit sent is the last bit of SID field
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd7)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+ end
+
+
+ else if(message_dlc == 'd2)
+ begin
+
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_data[15];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ prev_bit_reg <= ~message_data[15];
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd15)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_data[15])
+ begin
+ if(message_data[15] == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_data[15];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[15];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_data[15] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if (bit_counter_reg == 7'd16)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[15];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[15];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_data[15] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd15)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[15];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[15];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd15)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+
+ end
+
+
+ else if(message_dlc == 'd3)
+ begin
+
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_data[23];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+
+ prev_bit_reg <= ~message_data[23];
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd23)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_data[23])
+ begin
+ if(message_data[23] == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_data[23];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[23];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_data[23] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd23)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[23];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[23];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_data[23] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd23)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[23];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[23];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd23)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+
+ end
+
+
+ else if(message_dlc == 'd4)
+ begin
+
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_data[31];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+
+ prev_bit_reg <= ~message_data[31];
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd31)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_data[31])
+ begin
+ if(message_data[31] == 1'b1)
+ begin
+ // push next SID bit into FIFO
+ o_packetizer_message_bit <= message_data[31];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[31];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_data[31] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd31)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[31];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[31];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_data[31] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd31)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ end
+ else
+ begin
+ // push next SID bit into FIFO
+ o_packetizer_message_bit <= message_data[31];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[31];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd31)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+
+ end
+
+
+ else if(message_dlc == 'd5)
+ begin
+
+ if(stuff_bit_exception_reg)
+ begin
+ // push stuff bit into FIFO
+ o_packetizer_message_bit <= ~message_data[39];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ prev_bit_reg <= ~message_data[39];
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd39)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_data[39])
+ begin
+ if(message_data[39] == 1'b1)
+ begin
+ // push next SID bit into FIFO
+ o_packetizer_message_bit <= message_data[39];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[39];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_data[39] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd39)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[39];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[39];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_data[39] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd39)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ end
+ else
+ begin
+ // push next SID bit into FIFO
+ o_packetizer_message_bit <= message_data[39];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[39];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd39)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+
+ end
+
+
+ else if(message_dlc == 'd6)
+ begin
+
+ if(stuff_bit_exception_reg)
+ begin
+ // push stuff bit into FIFO
+ o_packetizer_message_bit <= ~message_data[47];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ prev_bit_reg <= ~message_data[47];
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd47)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_data[47])
+ begin
+ if(message_data[47] == 1'b1)
+ begin
+ // push next SID bit into FIFO
+ o_packetizer_message_bit <= message_data[47];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[47];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_data[47] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd47)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[47];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[47];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_data[47] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd47)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ end
+ else
+ begin
+ // push next SID bit into FIFO
+ o_packetizer_message_bit <= message_data[47];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[47];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd47)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+
+ end
+
+
+ else if(message_dlc == 'd7)
+ begin
+
+ if(stuff_bit_exception_reg)
+ begin
+ // push stuff bit into FIFO
+ o_packetizer_message_bit <= ~message_data[55];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ prev_bit_reg <= ~message_data[55];
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd55)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_data[55])
+ begin
+ if(message_data[55] == 1'b1)
+ begin
+ // push next SID bit into FIFO
+ o_packetizer_message_bit <= message_data[55];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[55];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_data[55] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd55)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[55];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[55];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_data[55] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd55)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ end
+ else
+ begin
+ // push next SID bit into FIFO
+ o_packetizer_message_bit <= message_data[55];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[55];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd55)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+
+ end
+
+
+ else
+ begin
+
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~message_data[63];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ prev_bit_reg <= ~message_data[63];
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd63)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ else
+ begin
+ // check possible stuff condition
+ if(prev_bit_reg == message_data[63])
+ begin
+ if(message_data[63] == 1'b1)
+ begin
+ o_packetizer_message_bit <= message_data[63];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[63];
+
+ if(num_of_consec_ones_reg == 4'd3 && message_data[63] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd63)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[63];
+ crc_enable <= 1'b1;
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[63];
+
+ if(num_of_consec_zeros_reg == 4'd3 && message_data[63] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd63)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= message_data[63];
+ crc_enable <= 1'b1;
+ // shift message_sid register left by 1-bit
+ message_data <= message_data << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= message_data[63];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd63)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_CRC;
+ end
+ else
+ begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_DATA;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+ end
+ end
+
+ STATE_CRC :
+ begin
+ crc_enable <= 1'b0;
+
+ if(stuff_bit_exception_reg)
+ begin
+ o_packetizer_message_bit <= ~crc_reg[14];
+ prev_bit_reg <= ~crc_reg[14];
+
+ // shift crc_reg register left by 1-bit
+ crc_reg <= crc_reg << 1'b1;
+
+ // reset stuff_bit_exception_reg
+ stuff_bit_exception_reg <= 1'b0;
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd14)
+ begin
+ //o_packetizer_message_bit <= 1'b1;
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_ACK;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_CRC;
+ end
+ end
+ else
+ begin
+ if(bit_counter_reg == 7'd14)
+ begin
+ o_packetizer_message_bit <= 1'b1;
+ end
+ // check possible stuff condition
+ if(prev_bit_reg == crc_reg[14])
+ begin
+ if(crc_reg[14] == 1'b1)
+ begin
+ o_packetizer_message_bit <= crc_reg[14];
+ // set next value of prev_bit_reg
+ prev_bit_reg <= crc_reg[14];
+
+ if(num_of_consec_ones_reg == 4'd3 && crc_reg[14] == 1'b1)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+ //message_sid <= message_sid << 1'b1;
+ // reset num_of_consec_ones_reg
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_ones_reg
+ num_of_consec_ones_reg <= num_of_consec_ones_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ crc_reg <= crc_reg << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd14)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_ACK;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_CRC;
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= crc_reg[14];
+ // set next value of prev_bit_reg
+ prev_bit_reg <= crc_reg[14];
+
+ if(num_of_consec_zeros_reg == 4'd3 && crc_reg[14] == 1'b0)
+ begin
+ // stuff condition occurs
+ stuff_bit_exception_reg <= 1'b1;
+
+ // reset num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= 4'd0;
+ end
+ else
+ begin
+ // increment num_of_consec_zeros_reg
+ num_of_consec_zeros_reg <= num_of_consec_zeros_reg + 1'b1;
+
+ // shift message_sid register left by 1-bit
+ crc_reg <= crc_reg << 1'b1;
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd14)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_ACK;
+ end
+ else
+ begin
+ // increment bit counter
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_CRC;
+ end
+ end
+ end
+ end
+ else
+ begin
+ o_packetizer_message_bit <= crc_reg[14];
+ // shift message_sid register left by 1-bit
+ crc_reg <= crc_reg << 1'b1;
+
+ // set next value of prev_bit_reg
+ prev_bit_reg <= crc_reg[14];
+
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd14)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_ACK;
+ end
+ else begin
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ state_reg <= STATE_CRC;
+ end
+
+ // reset stuff condition detect counters
+ num_of_consec_zeros_reg <= 4'd0;
+ num_of_consec_ones_reg <= 4'd0;
+ end
+ end
+ end
+ STATE_ACK :
+ begin
+ if(bit_counter_reg == 7'd0)
+ begin
+ o_packetizer_message_bit <= 1'b1;
+
+ end
+ else
+ begin
+ o_packetizer_message_bit <= 1'b1;
+ end
+ // check if the current bit sent is the last bit of SID field
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd1)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_EOF;
+ o_ack_slot <= 1'b1;
+ end
+ else
+ begin
+ state_reg <= STATE_ACK;
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ end
+ end
+
+ STATE_EOF :
+ begin
+ o_ack_slot <= 1'b0;
+ o_packetizer_message_bit <= 1'b1;
+
+ if(i_packetizer_en == 0)
+ state_reg <= STATE_IDLE;
+ else if(bit_counter_reg == 7'd6)
+ begin
+ bit_counter_reg <= 7'd0;
+ state_reg <= STATE_IDLE;
+ packetizer_rdy_reg <= 1'b1;
+ end
+ else
+ begin
+ state_reg <= STATE_EOF;
+ bit_counter_reg <= bit_counter_reg + 1'b1;
+ end
+ end
+
+ endcase
+ end
+ end
+ end
+
+ assign o_packetizer_rdy = packetizer_rdy_reg;
+endmodule
diff --git a/verilog/rtl/yonga_can_pulse_gen.v b/verilog/rtl/yonga_can_pulse_gen.v
new file mode 100644
index 0000000..f807780
--- /dev/null
+++ b/verilog/rtl/yonga_can_pulse_gen.v
@@ -0,0 +1,128 @@
+`timescale 1ns / 1ps
+// MIT License
+
+// Copyright (c) [2022] [Yonga Technology Microelectronics R&D]
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+
+// DESCRIPTION
+
+// The yonga_can_pulse_gen module generates appropriate bit synchronization signals
+// with respect to a particular bit rate
+
+`define NUM_OF_QUANTUM_BITS 9
+
+module yonga_can_pulse_gen(
+ input wire i_pulse_gen_clk,
+ input wire i_pulse_gen_rst,
+
+ input wire i_pulse_gen_config_en,
+
+ input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_prescaler_val,
+ input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_phase_seg1_time_quanta_val,
+ input wire [`NUM_OF_QUANTUM_BITS-1:0] i_pulse_gen_phase_seg2_time_quanta_val,
+
+ output wire o_pulse_gen_synced,
+
+ output wire o_pulse_gen_drive_pulse,
+ output wire o_pulse_gen_sample_pulse
+ );
+
+ // typedef enum {STATE_RESET, STATE_SYNC_SEG, STATE_PROP_SEG, STATE_PHASE_SEG1, STATE_PHASE_SEG2} state_t;
+ parameter STATE_RESET = 0, STATE_SYNC_SEG = 1, STATE_PROP_SEG = 2, STATE_PHASE_SEG1 = 3, STATE_PHASE_SEG2 = 4;
+
+ // state register
+ // reg [NUM_OF_STATE_BITS-1:0] state_reg;
+ reg [3:0] state_reg;
+
+ // timing registers
+ reg [`NUM_OF_QUANTUM_BITS-1:0] nom_time_qtm_reg;
+ reg [`NUM_OF_QUANTUM_BITS-1:0] qtm_counter_reg;
+ reg [`NUM_OF_QUANTUM_BITS-1:0] phase_seg1_counter_reg;
+ reg [`NUM_OF_QUANTUM_BITS-1:0] phase_seg2_counter_reg;
+
+ // status registers
+ reg sync_reg;
+ reg drive_pulse_reg;
+ reg sample_pulse_reg;
+
+ always@(posedge i_pulse_gen_clk) begin
+ if(i_pulse_gen_rst == 1'b1) begin
+ nom_time_qtm_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ phase_seg1_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ phase_seg2_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ sync_reg <= 1'b0;
+ drive_pulse_reg <= 1'b0;
+ sample_pulse_reg <= 1'b0;
+ state_reg <= STATE_RESET;
+ end
+ else begin
+ case(state_reg)
+ STATE_RESET: begin
+ if(i_pulse_gen_config_en) begin
+ nom_time_qtm_reg <= i_pulse_gen_prescaler_val; // assume that MINIMUM TIME QUANTUM equals 1
+ state_reg <= STATE_SYNC_SEG;
+ end
+ end
+ STATE_SYNC_SEG: begin
+ qtm_counter_reg <= qtm_counter_reg + 1'b1;
+ if(qtm_counter_reg == nom_time_qtm_reg) begin
+ qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ drive_pulse_reg <= 1'b1;
+ state_reg <= STATE_PHASE_SEG1;
+ end
+ end
+ // STATE_PROP_SEG: begin
+ // end
+ STATE_PHASE_SEG1: begin
+ drive_pulse_reg <= 1'b0;
+ qtm_counter_reg <= qtm_counter_reg + 1'b1;
+ if(qtm_counter_reg == nom_time_qtm_reg) begin
+ qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ phase_seg1_counter_reg <= phase_seg1_counter_reg + 1'b1;
+ if(phase_seg1_counter_reg == i_pulse_gen_phase_seg1_time_quanta_val) begin
+ phase_seg1_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ sample_pulse_reg <= 1'b1;
+ state_reg <= STATE_PHASE_SEG2;
+ end
+ end
+ end
+ STATE_PHASE_SEG2: begin
+ sample_pulse_reg <= 1'b0;
+ qtm_counter_reg <= qtm_counter_reg + 1'b1;
+ if(qtm_counter_reg == nom_time_qtm_reg) begin
+ qtm_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ phase_seg2_counter_reg <= phase_seg2_counter_reg + 1'b1;
+ if(phase_seg2_counter_reg == i_pulse_gen_phase_seg2_time_quanta_val) begin
+ phase_seg2_counter_reg <= {`NUM_OF_QUANTUM_BITS{1'b0}};
+ sync_reg <= 1'b1;
+ state_reg <= STATE_SYNC_SEG;
+ end
+ end
+ end
+ endcase
+ end
+ end
+
+ assign o_pulse_gen_synced = sync_reg;
+ assign o_pulse_gen_drive_pulse = drive_pulse_reg;
+ assign o_pulse_gen_sample_pulse = sample_pulse_reg;
+
+endmodule
diff --git a/verilog/rtl/yonga_can_top.v b/verilog/rtl/yonga_can_top.v
new file mode 100644
index 0000000..b22d945
--- /dev/null
+++ b/verilog/rtl/yonga_can_top.v
@@ -0,0 +1,229 @@
+// MIT License
+
+// Copyright (c) [2022] [Yonga Technology Microelectronics R&D]
+
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+
+// The above copyright notice and this permission notice shall be included in all
+// copies or substantial portions of the Software.
+
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+
+// DESCRIPTION
+
+// The yonga_can_top module includes the register access logic and
+// top-level logic of CAN peripheral
+
+`default_nettype none
+
+module yonga_can_top #(
+ parameter BITS = 32
+)(
+ input wire clk,
+ input wire rst,
+ output reg ready,
+ input wire valid,
+
+ output reg [BITS-1:0] rdata,
+ input wire [BITS-1:0] wdata,
+ input wire [3:0] wstrb,
+
+ input wire device_reg_wr_en,
+ input wire [4:0] device_addr,
+ input wire [BITS-1:0] device_reg_wr_data,
+ output reg [BITS-1:0] device_reg_rd_data,
+
+ output wire can_tx,
+ input wire can_rx,
+
+ output reg [BITS-1:0] count
+);
+// reg ready;
+// reg [BITS-1:0] device_reg_rd_data;
+// reg [BITS-1:0] count;
+// reg [BITS-1:0] rdata;
+
+ reg [BITS-1:0] BAUD_RATE_CFG_REG;
+ reg [BITS-1:0] MSG_ID_REG;
+ reg [BITS-1:0] MSG_CFG_REG;
+ reg [BITS-1:0] DATA_REG1_REG;
+ reg [BITS-1:0] DATA_REG2_REG;
+ reg [BITS-1:0] SYS_CFG_REG;
+ reg [BITS-1:0] SYS_CTRL_STS_REG;
+ wire [2:0] sts_code;
+ // CPU controls the peripheral via pseudo memory-mapped registers
+ always @(posedge clk) begin
+ if (rst) begin
+ BAUD_RATE_CFG_REG <= 32'h0;
+ MSG_ID_REG <= 32'h0;
+ MSG_CFG_REG <= 32'h0;
+ DATA_REG1_REG <= 32'h0;
+ DATA_REG2_REG <= 32'h0;
+ SYS_CFG_REG <= 32'h0;
+ SYS_CTRL_STS_REG <= 32'h0;
+
+ count <= 0;
+ ready <= 0;
+ rdata <= 32'h0;
+ end
+ else begin
+ ready <= 1'b0;
+ SYS_CTRL_STS_REG[0] <= 1'b0; // SEND bit is self-clearing
+ if (valid && !ready) begin
+ ready <= 1'b1;
+ rdata <= 32'h0;
+ if(wdata[0] && device_addr[4:0] == 5'h0) begin
+ device_reg_rd_data <= BAUD_RATE_CFG_REG;
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[0]) BAUD_RATE_CFG_REG[7:0] <= device_reg_wr_data[7:0];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[1]) BAUD_RATE_CFG_REG[15:8] <= device_reg_wr_data[15:8];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[2]) BAUD_RATE_CFG_REG[23:16] <= device_reg_wr_data[23:16];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[3]) BAUD_RATE_CFG_REG[31:24] <= device_reg_wr_data[31:24];
+ end
+ else if(wdata[0] && device_addr[4:0] == 5'h4) begin
+ device_reg_rd_data <= MSG_ID_REG;
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[0]) MSG_ID_REG[7:0] <= device_reg_wr_data[7:0];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[1]) MSG_ID_REG[15:8] <= device_reg_wr_data[15:8];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[2]) MSG_ID_REG[23:16] <= device_reg_wr_data[23:16];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[3]) MSG_ID_REG[31:24] <= device_reg_wr_data[31:24];
+ end
+ else if(wdata[0] && device_addr[4:0] == 5'h8) begin
+ device_reg_rd_data <= MSG_CFG_REG;
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[0]) MSG_CFG_REG[7:0] <= device_reg_wr_data[7:0];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[1]) MSG_CFG_REG[15:8] <= device_reg_wr_data[15:8];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[2]) MSG_CFG_REG[23:16] <= device_reg_wr_data[23:16];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[3]) MSG_CFG_REG[31:24] <= device_reg_wr_data[31:24];
+ end
+ else if(wdata[0] && device_addr[4:0] == 5'hC) begin
+ device_reg_rd_data <= DATA_REG1_REG;
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[0]) DATA_REG1_REG[7:0] <= device_reg_wr_data[7:0];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[1]) DATA_REG1_REG[15:8] <= device_reg_wr_data[15:8];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[2]) DATA_REG1_REG[23:16] <= device_reg_wr_data[23:16];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[3]) DATA_REG1_REG[31:24] <= device_reg_wr_data[31:24];
+ end
+ else if(wdata[0] && device_addr[4:0] == 5'h10) begin
+ device_reg_rd_data <= DATA_REG2_REG;
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[0]) DATA_REG2_REG[7:0] <= device_reg_wr_data[7:0];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[1]) DATA_REG2_REG[15:8] <= device_reg_wr_data[15:8];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[2]) DATA_REG2_REG[23:16] <= device_reg_wr_data[23:16];
+ if (SYS_CFG_REG[1] && device_reg_wr_en && wstrb[3]) DATA_REG2_REG[31:24] <= device_reg_wr_data[31:24];
+ end
+ else if(wdata[0] && device_addr[4:0] == 5'h14) begin
+ device_reg_rd_data <= SYS_CFG_REG;
+ if (device_reg_wr_en && wstrb[0]) SYS_CFG_REG[7:0] <= device_reg_wr_data[7:0];
+ if (device_reg_wr_en && wstrb[1]) SYS_CFG_REG[15:8] <= device_reg_wr_data[15:8];
+ if (device_reg_wr_en && wstrb[2]) SYS_CFG_REG[23:16] <= device_reg_wr_data[23:16];
+ if (device_reg_wr_en && wstrb[3]) SYS_CFG_REG[31:24] <= device_reg_wr_data[31:24];
+ end
+ else if(wdata[0] && device_addr[4:0] == 5'h18) begin
+ device_reg_rd_data <= SYS_CTRL_STS_REG;
+ if (device_reg_wr_en && wstrb[0]) SYS_CTRL_STS_REG[7:0] <= device_reg_wr_data[7:0];
+ if (device_reg_wr_en && wstrb[1]) SYS_CTRL_STS_REG[15:8] <= device_reg_wr_data[15:8];
+ if (device_reg_wr_en && wstrb[2]) SYS_CTRL_STS_REG[23:16] <= device_reg_wr_data[23:16];
+ if (device_reg_wr_en && wstrb[3]) SYS_CTRL_STS_REG[31:24] <= device_reg_wr_data[31:24];
+ end
+ end
+ if (sts_code != 3'b0) begin
+ SYS_CTRL_STS_REG[3:1] <= sts_code;
+ end
+ end
+ end
+
+ wire ack_slot_flag;
+
+ wire pulse_gen_en, pulse_gen_synced, pulse_gen_drive_pulse, pulse_gen_sample_pulse;
+ wire packetizer_en, packetizer_rdy, packetizer_message_bit;
+
+ // use can_tx for receive channel in loopback mode
+ wire can_rx_mux;
+ assign can_rx_mux = (SYS_CFG_REG[0] == 1'b1) ? ((ack_slot_flag == 1'b1) ? ~can_tx : can_tx) : can_rx;
+
+ // instantiate yonga_can_pulse_gen
+ yonga_can_pulse_gen inst_yonga_can_pulse_gen(
+ .i_pulse_gen_clk(clk),
+ .i_pulse_gen_rst(rst),
+
+ .i_pulse_gen_config_en(pulse_gen_en),
+
+ .i_pulse_gen_prescaler_val(BAUD_RATE_CFG_REG[26:18]),
+ .i_pulse_gen_phase_seg1_time_quanta_val(BAUD_RATE_CFG_REG[17:9]),
+ .i_pulse_gen_phase_seg2_time_quanta_val(BAUD_RATE_CFG_REG[8:0]),
+
+ .o_pulse_gen_synced(pulse_gen_synced),
+
+ .o_pulse_gen_drive_pulse(pulse_gen_drive_pulse),
+ .o_pulse_gen_sample_pulse(pulse_gen_sample_pulse)
+ );
+
+ // instantiate yonga_can_controller
+ yonga_can_controller inst_yonga_can_controller(
+ .i_controller_clk(clk),
+ .i_controller_rst(rst),
+
+ .i_pulse_gen_synced(pulse_gen_synced),
+ .i_packetizer_rdy(packetizer_rdy),
+ .i_ack_slot(ack_slot_flag),
+
+ .o_packetizer_en(packetizer_en),
+ .o_pulse_gen_en(pulse_gen_en),
+
+ .i_packetizer_message_bit(packetizer_message_bit),
+
+ .i_message_bit(can_rx_mux),
+ .o_message_bit(can_tx),
+
+ .i_drive_pulse(pulse_gen_drive_pulse),
+ .i_sample_pulse(pulse_gen_sample_pulse),
+
+ .i_config_enable(SYS_CFG_REG[1]),
+ .i_sys_ctrl_sts_send(SYS_CTRL_STS_REG[0]),
+ .o_sts_code(sts_code)
+
+ );
+
+ // instantiate yonga_can_controller
+ yonga_can_packetizer inst_yonga_can_packetizer(
+ .i_packetizer_clk(clk),
+ .i_packetizer_rst(rst),
+ .i_packetizer_en(packetizer_en),
+ .i_drive_pulse(pulse_gen_drive_pulse),
+
+ .i_packetizer_message_sid(MSG_ID_REG[29:19]),
+ .i_packetizer_message_ide(MSG_ID_REG[18]),
+ .i_packetizer_message_r0(1'b0),
+ .i_packetizer_message_r1(1'b0),
+ .i_packetizer_message_srr(1'b1),
+ .i_packetizer_message_eid(MSG_ID_REG[17:0]),
+
+ .i_packetizer_message_rtr(MSG_CFG_REG[4]),
+ .i_packetizer_message_dlc(MSG_CFG_REG[3:0]),
+
+ .i_packetizer_message_data_byte_0(DATA_REG1_REG[7:0]),
+ .i_packetizer_message_data_byte_1(DATA_REG1_REG[15:8]),
+ .i_packetizer_message_data_byte_2(DATA_REG1_REG[23:16]),
+ .i_packetizer_message_data_byte_3(DATA_REG1_REG[31:24]),
+ .i_packetizer_message_data_byte_4(DATA_REG2_REG[7:0]),
+ .i_packetizer_message_data_byte_5(DATA_REG2_REG[15:8]),
+ .i_packetizer_message_data_byte_6(DATA_REG2_REG[23:16]),
+ .i_packetizer_message_data_byte_7(DATA_REG2_REG[31:24]),
+
+ .o_packetizer_rdy(packetizer_rdy),
+ .i_packetizer_req(/* NOT USED */),
+ .o_packetizer_message_bit(packetizer_message_bit),
+ .i_packetizer_message_bit(/* NOT USED */),
+ .o_ack_slot(ack_slot_flag)
+
+ );
+
+endmodule
+`default_nettype wire
\ No newline at end of file
