Update verilog/dv/can_test_1
diff --git a/verilog/dv/can_test_1/can_test1.c b/verilog/dv/can_test_1/can_test_1.c
similarity index 98%
rename from verilog/dv/can_test_1/can_test1.c
rename to verilog/dv/can_test_1/can_test_1.c
index caf3e92..a4ac0e0 100644
--- a/verilog/dv/can_test_1/can_test1.c
+++ b/verilog/dv/can_test_1/can_test_1.c
@@ -19,6 +19,8 @@
#include <defs.h>
#include <stub.c>
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
#include "YONGA_CAN_IP_regs.h"
/*
diff --git a/verilog/dv/can_test_1/can_test1_tb.v b/verilog/dv/can_test_1/can_test_1_tb.v
similarity index 95%
rename from verilog/dv/can_test_1/can_test1_tb.v
rename to verilog/dv/can_test_1/can_test_1_tb.v
index 3ae4b20..f99be82 100644
--- a/verilog/dv/can_test_1/can_test1_tb.v
+++ b/verilog/dv/can_test_1/can_test_1_tb.v
@@ -17,7 +17,7 @@
`timescale 1 ns / 1 ps
-module can_test1_tb;
+module can_test_1_tb;
reg clock;
reg RSTB;
reg CSB;
@@ -44,8 +44,8 @@
end
initial begin
- $dumpfile("can_test1.vcd");
- $dumpvars(0, can_test1_tb);
+ $dumpfile("can_test_1.vcd");
+ $dumpvars(0, can_test_1_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (200) begin
@@ -121,7 +121,7 @@
);
spiflash #(
- .FILENAME("can_test1.hex")
+ .FILENAME("can_test_1.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
