| commit | 45713ae38da32395dc6695c43efce094080baa74 | [log] [tgz] |
|---|---|---|
| author | abdullahyildiz <abdullahyildiz@github.com> | Tue Nov 22 16:03:30 2022 +0300 |
| committer | abdullahyildiz <abdullahyildiz@github.com> | Tue Nov 22 16:03:30 2022 +0300 |
| tree | ee53343f2212c7342b75985aba9b11f1b5ab0141 | |
| parent | 83771d251d748d3368acc813b545a05bd7c97bd2 [diff] |
Update verilog/dv/Makefile
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 43a4149..76873b7 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -20,7 +20,7 @@ .SILENT: clean all -PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus +PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus can_test_1 can_test_2 all: ${PATTERNS}