fix path to macro.cfg

openlane/user_project_wrapper/config.json

diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index bd4e2e4..53d5c1e 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -5,7 +5,7 @@
     "CLOCK_PORT": "user_clock2",
     "CLOCK_NET": "mprj.clk",
     "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
-    "MACRO_PLACEMENT_CFG": "/home/jeffdi/caravel_user_project_gf/openlane/user_proj_example/macro.cfg",
+    "MACRO_PLACEMENT_CFG": "/home/jeffdi/caravel_user_project_gf/openlane/user_project_wrapper/macro.cfg",
     "VERILOG_FILES_BLACKBOX": "/home/jeffdi/caravel-gf180mcu/verilog/rtl/defines.v /home/jeffdi/caravel_user_project_gf/verilog/rtl/user_proj_example.v",
     "EXTRA_LEFS": "/home/jeffdi/caravel_user_project_gf/lef/user_proj_example.lef",
     "EXTRA_GDS_FILES": "/home/jeffdi/caravel_user_project_gf/gds/user_proj_example.gds",
@@ -80,6 +80,6 @@
         "FP_PDN_CHECK_NODES": 0,
         "MAGIC_WRITE_FULL_LEF": 0,
         "FP_PDN_ENABLE_RAILS": 0,
-        "GLB_RT_OBS": "Metal1 0 0 ref::$DIE_AREA, Metal2 0 0 ref::$DIE_AREA, Metal3 0 0 ref::$DIE_AREA, Metal4 0 0 ref::$DIE_AREA, Metal5 0 0 ref::$DIE_AREA"
+        "GRT_OBS": "Metal1 0 0 ref::$DIE_AREA, Metal2 0 0 ref::$DIE_AREA, Metal3 0 0 ref::$DIE_AREA, Metal4 0 0 ref::$DIE_AREA, Metal5 0 0 ref::$DIE_AREA"
    }
 }
\ No newline at end of file