commit c2805a3380c2e965e3faa8b6d34cd854d059d30a
author Anton Blanchard <anton@linux.ibm.com> Mon Nov 28 14:07:56 2022 +1100
committer Anton Blanchard <anton@ozlabs.org> Mon Nov 28 14:07:56 2022 +1100
tree 47831994fdbf04d74c486c78d6eb2be9910456a4
parent df2ae0f8e803b8b6d00040fd4de63eb9e32184cb

Fix typo

openlane/Microwatt_FP_DFFRFile/base.sdc

diff --git a/openlane/Microwatt_FP_DFFRFile/base.sdc b/openlane/Microwatt_FP_DFFRFile/base.sdc
index 7c1aa5d..15085f2 100644
--- a/openlane/Microwatt_FP_DFFRFile/base.sdc
+++ b/openlane/Microwatt_FP_DFFRFile/base.sdc
@@ -22,7 +22,7 @@
 puts "\[INFO\]: Setting load to: $cap_load"
 set_load  $cap_load [all_outputs]
 
-puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+puts "\[INFO\]: Setting clock uncertainty to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
 set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks $::env(CLOCK_PORT)]
 
 puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"