Fix gate level sim
make gpio_defaults writes a modified caravel.v to the
caravel_user_project verilog/gl directory so we need to use that and not
the version in the caravel repo. We also need the gate level
implementations of the various gpio_defaults_block modules (only a few
are created and referenced in the caravel repo).
diff --git a/verilog/dv/microwatt/make.rules b/verilog/dv/microwatt/make.rules
index ec00c93..1f52e2a 100644
--- a/verilog/dv/microwatt/make.rules
+++ b/verilog/dv/microwatt/make.rules
@@ -29,7 +29,7 @@
else
iverilog $(SIM_DEFINES) -DGL \
-l$(USER_PROJECT_VERILOG)/rtl/user_defines.v \
- -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.caravel_user_project \
$< -o $@
endif
diff --git a/verilog/includes/includes.gl.caravel b/verilog/includes/includes.gl.caravel
new file mode 100644
index 0000000..343456e
--- /dev/null
+++ b/verilog/includes/includes.gl.caravel
@@ -0,0 +1,100 @@
+###########################################################
+## DFFRAM - either behavioral or GL
+###########################################################
+
+## DFFRAM Full GL
+#-v $(VERILOG_PATH)/gl/DFFRAM.v
+-v $(VERILOG_PATH)/gl/RAM128.v
+-v $(VERILOG_PATH)/gl/RAM256.v
+
+###########################################################
+# Mgmt Core Wrapper
+###########################################################
+-v $(VERILOG_PATH)/rtl/defines.v
+#-v $(VERILOG_PATH)/gl/mgmt_core.v
+-v $(VERILOG_PATH)/gl/mgmt_core_wrapper.v
+
+# Caravel
+
+###########################################################
+## Must stay in RTL regardless of the type of simulation
+###########################################################
+-v $(CARAVEL_PATH)/rtl/pads.v
+-v $(CARAVEL_PATH)/rtl/defines.v
+-v $(CARAVEL_PATH)/rtl/user_defines.v
+-v $(CARAVEL_PATH)/rtl/mprj_io.v
+-v $(CARAVEL_PATH)/rtl/simple_por.v
+
+###########################################################
+## These blocks only needed for RTL sims
+## Not needed for GL and will be a part of another block
+###########################################################
+-v $(CARAVEL_PATH)/rtl/digital_pll_controller.v
+-v $(CARAVEL_PATH)/rtl/ring_osc2x13.v
+-v $(CARAVEL_PATH)/rtl/clock_div.v
+-v $(CARAVEL_PATH)/rtl/housekeeping_spi.v
+
+###########################################################
+## These blocks are either synthesized or STD cell based
+## Manually designed blocks
+###########################################################
+-v $(CARAVEL_PATH)/gl/mprj_logic_high.v
+-v $(CARAVEL_PATH)/gl/mprj2_logic_high.v
+-v $(CARAVEL_PATH)/gl/gpio_control_block.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block.v
+-v $(CARAVEL_PATH)/gl/gpio_logic_high.v
+-v $(CARAVEL_PATH)/gl/xres_buf.v
+-v $(CARAVEL_PATH)/gl/spare_logic_block.v
+-v $(CARAVEL_PATH)/gl/housekeeping.v
+-v $(CARAVEL_PATH)/gl/caravel_clocking.v
+-v $(CARAVEL_PATH)/rtl/digital_pll.v
+-v $(CARAVEL_PATH)/rtl/debug_regs.v
+#-v $(CARAVEL_PATH)/gl/__user_project_wrapper.v
+-v $(CARAVEL_PATH)/gl/user_id_programming.v
+-v $(CARAVEL_PATH)/gl/buff_flash_clkrst.v
+-v $(CARAVEL_PATH)/gl/gpio_signal_buffering_alt.v
+-v $(CARAVEL_PATH)/gl/gpio_signal_buffering.v
+#-v $(CARAVEL_PATH)/gl/caravel.v
+-v $(USER_PROJECT_VERILOG)/gl/caravel.v
+-v $(CARAVEL_PATH)/gl/caravan.v
+
+###########################################################
+## These blocks are manually designed
+###########################################################
+-v $(CARAVEL_PATH)/gl/constant_block.v
+-v $(CARAVEL_PATH)/gl/chip_io_alt.v
+-v $(CARAVEL_PATH)/gl/chip_io.v
+-v $(CARAVEL_PATH)/gl/mgmt_protect.v
+-v $(CARAVEL_PATH)/gl/mgmt_protect_hv.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_0403.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_0801.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_1803.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_0402.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_0800.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_0c00.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_1800.v
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_1808.v
+
+###########################################################
+# STD CELLS - they need to be below the defines.v files
+###########################################################
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
+#-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v
+
+
+## STD CELLS - they need to be below the defines.v files
+##v $(VERILOG_PATH)/cvc-pdk/sky130_ef_io.v
+#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_io.v
+#-v $(VERILOG_PATH)/cvc-pdk/primitives_hd.v
+#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_sc_hd.v
+#-v $(VERILOG_PATH)/cvc-pdk/primitives_hvl.v
+#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_sc_hvl.v
+ -v $(VERILOG_PATH)/cvc-pdk/sky130_sram_2kbyte_1rw1r_32x512_8.v
+
+
+
