Switch to using config.json
diff --git a/openlane/Microwatt_FP_DFFRFile/config.json b/openlane/Microwatt_FP_DFFRFile/config.json
new file mode 100644
index 0000000..d50de31
--- /dev/null
+++ b/openlane/Microwatt_FP_DFFRFile/config.json
@@ -0,0 +1,49 @@
+{
+ "DESIGN_NAME": "Microwatt_FP_DFFRFile",
+ "VERILOG_FILES": ["dir::../../verilog/rtl/Microwatt_FP_DFFRFile.v"],
+
+ "CLOCK_PERIOD": 10,
+ "CLOCK_PORT": "CLK",
+ "CLOCK_NET": "CLK",
+ "BASE_SDC_FILE": "dir::base.sdc",
+
+ "FP_SIZING": "absolute",
+ "DIE_AREA": "0 0 700 700",
+
+ "DESIGN_IS_CORE": 0,
+ "FP_PDN_CORE_RING": 0,
+ "RT_MAX_LAYER": "met4",
+
+ "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+
+ "IO_PCT": "0.3",
+
+ "VDD_NETS": ["VPWR"],
+ "GND_NETS": ["VGND"],
+
+ "FP_PDN_VWIDTH": 3.1,
+ "FP_PDN_HWIDTH": 3.1,
+ "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_VWIDTH)",
+ "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_VWIDTH)",
+ "FP_PDN_VPITCH": 180,
+ "FP_PDN_HPITCH": 180,
+ "FP_PDN_VOFFSET": 5,
+ "FP_PDN_HOFFSET": 5,
+
+ "SYNTH_STRATEGY": "DELAY 4",
+ "SYNTH_MAX_FANOUT": "10",
+
+ "PL_TARGET_DENSITY": "0.68",
+
+ "CTS_CLK_BUFFER_LIST": ["sky130_fd_sc_hd__clkbuf_8", "sky130_fd_sc_hd__clkbuf_4", "sky130_fd_sc_hd__clkbuf_2"],
+ "CTS_DISABLE_POST_PROCESSING": "1",
+ "CTS_DISTANCE_BETWEEN_BUFFERS": "250",
+
+ "RUN_KLAYOUT": "0",
+
+ "GPL_CELL_PADDING": "2",
+ "DPL_CELL_PADDING": "0",
+ "DIODE_PADDING": "0",
+
+ "ROUTING_CORES": "24"
+}
diff --git a/openlane/Microwatt_FP_DFFRFile/config.tcl b/openlane/Microwatt_FP_DFFRFile/config.tcl
deleted file mode 100644
index 902d44b..0000000
--- a/openlane/Microwatt_FP_DFFRFile/config.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-set script_dir $::env(DESIGN_DIR)
-
-set ::env(DESIGN_NAME) Microwatt_FP_DFFRFile
-
-set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/Microwatt_FP_DFFRFile.v"
-
-set ::env(CLOCK_PORT) "CLK"
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_NET) $::env(CLOCK_PORT)
-set ::env(BASE_SDC_FILE) $script_dir/base.sdc
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 700 700"
-
-# Settings for macros
-set ::env(DESIGN_IS_CORE) 0
-set ::env(FP_PDN_CORE_RING) 0
-set ::env(RT_MAX_LAYER) "met4"
-
-# Macro pin out
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-# Macro input/output delay - must match liberty file
-set ::env(IO_PCT) 0.3
-
-# Handle PDN
-set ::env(VDD_NETS) [list {VPWR} ]
-set ::env(GND_NETS) [list {VGND} ]
-
-# Make PDN match top level
-set ::env(FP_PDN_VWIDTH) 3.1
-set ::env(FP_PDN_HWIDTH) 3.1
-set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_VWIDTH)]
-set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_HWIDTH)]
-
-# PDN Pitch
-set ::env(FP_PDN_VPITCH) 180
-set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
-
-# PDN Offset
-set ::env(FP_PDN_VOFFSET) 5
-set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
-
-# Synthesis tuning
-set ::env(SYNTH_STRATEGY) {DELAY 4}
-set ::env(SYNTH_MAX_FANOUT) {10}
-
-# Placement tuning
-set ::env(PL_TARGET_DENSITY) 0.68
-
-# CTS tuning
-set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2};
-set ::env(CTS_DISABLE_POST_PROCESSING) 1
-set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) 250
-
-# Speed up tape out a bit
-set ::env(RUN_KLAYOUT) 0
-
-if {[catch {exec nproc} result] == 0} {
- set ::env(ROUTING_CORES) $result
-} else {
- set ::env(ROUTING_CORES) 4
-}
-
-set ::env(GPL_CELL_PADDING) 2
-set ::env(DPL_CELL_PADDING) 0
-set ::env(DIODE_PADDING) 0
diff --git a/openlane/multiply_add_64x64/config.json b/openlane/multiply_add_64x64/config.json
new file mode 100644
index 0000000..2cf75d6
--- /dev/null
+++ b/openlane/multiply_add_64x64/config.json
@@ -0,0 +1,52 @@
+{
+ "DESIGN_NAME": "multiply_add_64x64",
+ "VERILOG_FILES": ["dir::src/multiply_add_64x64.v"],
+
+ "CLOCK_PERIOD": 10,
+ "CLOCK_PORT": "clk",
+ "CLOCK_NET": "clk",
+
+ "FP_SIZING": "absolute",
+ "DIE_AREA": "0 0 500 500",
+
+ "DESIGN_IS_CORE": 0,
+ "FP_PDN_CORE_RING": 0,
+ "RT_MAX_LAYER": "met4",
+
+ "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+
+ "IO_PCT": "0.4",
+
+ "SYNTH_READ_BLACKBOX_LIB": "1",
+
+ "VDD_NETS": ["VPWR"],
+ "GND_NETS": ["VGND"],
+
+ "FP_PDN_VWIDTH": 3.1,
+ "FP_PDN_HWIDTH": 3.1,
+ "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_VWIDTH)",
+ "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_VWIDTH)",
+ "FP_PDN_VPITCH": 180,
+ "FP_PDN_HPITCH": 180,
+ "FP_PDN_VOFFSET": 5,
+ "FP_PDN_HOFFSET": 5,
+
+ "SYNTH_STRATEGY": "DELAY 4",
+ "SYNTH_MAX_FANOUT": "10",
+
+ "PL_TARGET_DENSITY": "0.74",
+
+ "GRT_ADJUSTMENT": "0.2",
+
+ "CTS_CLK_BUFFER_LIST": ["sky130_fd_sc_hd__clkbuf_8", "sky130_fd_sc_hd__clkbuf_4", "sky130_fd_sc_hd__clkbuf_2"],
+ "CTS_DISABLE_POST_PROCESSING": "1",
+ "CTS_DISTANCE_BETWEEN_BUFFERS": "250",
+
+ "RUN_KLAYOUT": "0",
+
+ "GPL_CELL_PADDING": "2",
+ "DPL_CELL_PADDING": "0",
+ "DIODE_PADDING": "0",
+
+ "ROUTING_CORES": "24"
+}
diff --git a/openlane/multiply_add_64x64/config.tcl b/openlane/multiply_add_64x64/config.tcl
deleted file mode 100644
index 9cabd1c..0000000
--- a/openlane/multiply_add_64x64/config.tcl
+++ /dev/null
@@ -1,70 +0,0 @@
-set script_dir $::env(DESIGN_DIR)
-
-set ::env(DESIGN_NAME) multiply_add_64x64
-
-set ::env(VERILOG_FILES) "\
- $script_dir/src/multiply_add_64x64.v"
-
-set ::env(CLOCK_PORT) "clk"
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_NET) $::env(CLOCK_PORT)
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 500 500"
-
-# Settings for macros
-set ::env(DESIGN_IS_CORE) 0
-set ::env(FP_PDN_CORE_RING) 0
-set ::env(RT_MAX_LAYER) "met4"
-
-# Macro pin out
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-# Macro input/output delay - must match liberty file
-set ::env(IO_PCT) 0.4
-
-# Because the macro uses standard cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-
-# Handle PDN
-set ::env(VDD_NETS) [list {VPWR} ]
-set ::env(GND_NETS) [list {VGND} ]
-
-# Make PDN match top level
-set ::env(FP_PDN_VWIDTH) 3.1
-set ::env(FP_PDN_HWIDTH) 3.1
-set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_VWIDTH)]
-set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_HWIDTH)]
-
-# PDN Pitch
-set ::env(FP_PDN_VPITCH) 180
-set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
-
-# PDN Offset
-set ::env(FP_PDN_VOFFSET) 5
-set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
-
-# Synthesis tuning
-set ::env(SYNTH_STRATEGY) {DELAY 4}
-set ::env(SYNTH_MAX_FANOUT) {10}
-
-# Placement tuning
-set ::env(PL_TARGET_DENSITY) 0.52
-
-# CTS tuning
-set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2};
-set ::env(CTS_DISABLE_POST_PROCESSING) 1
-set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) 250
-
-# Speed up tape out a bit
-set ::env(RUN_KLAYOUT) 0
-
-if {[catch {exec nproc} result] == 0} {
- set ::env(ROUTING_CORES) $result
-} else {
- set ::env(ROUTING_CORES) 4
-}
-
-set ::env(GPL_CELL_PADDING) 2
-set ::env(DPL_CELL_PADDING) 0
-set ::env(DIODE_PADDING) 0
