Reduce timeout on minimal test so it fails faster

verilog/dv/microwatt/minimal/minimal_tb.v

diff --git a/verilog/dv/microwatt/minimal/minimal_tb.v b/verilog/dv/microwatt/minimal/minimal_tb.v
index d00f86f..d83870e 100644
--- a/verilog/dv/microwatt/minimal/minimal_tb.v
+++ b/verilog/dv/microwatt/minimal/minimal_tb.v
@@ -69,7 +69,7 @@
 
 		// Set the timeout at around 10x what the test should finish
 		// in
-		repeat (200000) begin
+		repeat (20000) begin
 			@(posedge clock);
 		end