Fix power plumbing through execute unit

verilog/rtl/microwatt.v

diff --git a/verilog/rtl/microwatt.v b/verilog/rtl/microwatt.v
index 9ff6a30..eab3507 100644
--- a/verilog/rtl/microwatt.v
+++ b/verilog/rtl/microwatt.v
@@ -62649,7 +62649,12 @@
 endmodule
 
 module execute1_0_276e8824c88e117571aa19e570895b56ecbd3507
-  (input  clk,
+(
+`ifdef USE_POWER_PINS
+   inout vccd1,
+   inout vssd1,
+`endif
+   input  clk,
    input  rst,
    input  flush_in,
    input  e_in_valid,
@@ -97011,6 +97016,10 @@
   assign n1164_o = ctrl_debug[273:256];
   /* core.vhdl:363:5  */
   execute1_0_276e8824c88e117571aa19e570895b56ecbd3507 execute1_0 (
+`ifdef USE_POWER_PINS
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+`endif
     .clk(clk),
     .rst(rst_ex1),
     .flush_in(flush),