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foss-eda-tools / third_party / shuttle / sky130 / mpw-007 / slot-002 / f296936f23edac8e05ba47469c7f05445330c19f / verilog / dv
  1. 2d40ac0 Fix la_test2 gl sim by manarabdelaty · 3 years, 6 months ago
  2. ee54cee Update Makefile to work with efabless style by manarabdelaty · 3 years, 7 months ago
  3. f02cd32 Update Makefile PDK_PATH by manarabdelaty · 3 years, 7 months ago
  4. a2ff3b4 [DATA] Update views by manarabdelaty · 4 years ago
  5. ef957a6 Updated the documentation to reflect the changes made to the source by Tim Edwards · 4 years ago
  6. c89cfac Update to coincide with the most recent commit to the caravel by Tim Edwards · 4 years ago
  7. 340cc4a Update full chip simulation to run from root by manarabdelaty · 4 years ago
  8. 4bbff2e Update README.md by Manar · 4 years ago
  9. b41301c Added top level makefile by manarabdelaty · 4 years ago
  10. 22f3cd0 Submodule caravel-lite by manarabdelaty · 4 years ago
  11. c0f458a Update DV Makefile by manarabdelaty · 4 years ago
  12. eac56e8 Rename CARAVEL_MASTER -> CARAVEL_ROOT by manarabdelaty · 4 years ago
  13. 8dbabc1 Update DV Makefiles by manarabdelaty · 4 years ago
  14. 8e8bf63 Update la_test2 Makefile by manarabdelaty · 4 years ago
  15. 496112a Add CARAVEL_PATH for the testbenches by manarabdelaty · 4 years ago
  16. f989c64 Corrected the user_project_wrapper verilog to have the correct by Tim Edwards · 4 years ago
  17. a7929f3 Added mprj_stimulus test by manarabdelaty · 4 years ago
  18. d184bf6 Update wb_port dv makefile by manarabdelaty · 4 years ago
  19. a63e2e6 Makefile and RTL updates to run GL sim by manarabdelaty · 4 years ago
  20. 10b3a10 Update README.md by Manar · 4 years ago
  21. 69bd326 Updated DV tests by manarabdelaty · 4 years ago
  22. d4ec2f0 Example of a full run of user_project_wrapper by Ahmed Ghazy · 4 years ago