litex integration iteration - only wb_port not working
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index e14258d..be842fc 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -28,10 +28,9 @@
all: ${PATTERNS}
- echo "bla"
- # for i in ${PATTERNS}; do \
- # ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
- # done
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
$(DV_PATTERNS): verify-% :
