yaml

local.yaml

diff --git a/local.yaml b/local.yaml
new file mode 100644
index 0000000..9886a6e
--- /dev/null
+++ b/local.yaml
@@ -0,0 +1,18 @@
+project_directory: "/home/runner/work/"
+
+caravel:
+    root:           /home/runner/work/zero_to_asic_mpw7/zero_to_asic_mpw7
+    gl_dir:         /home/runner/work/zero_to_asic_mpw7/zero_to_asic_mpw7/verilog/gl
+    test_dir:       /home/runner/work/zero_to_asic_mpw7/zero_to_asic_mpw7/verilog/dv
+    rtl_dir:        /home/runner/work/zero_to_asic_mpw7/zero_to_asic_mpw7/verilog/rtl
+    includes_dir:   /home/runner/work/zero_to_asic_mpw7/zero_to_asic_mpw7/verilog/includes/
+    mgmt_root:      /home/runner/work/zero_to_asic_mpw7/zero_to_asic_mpw7/mgmt_core_wrapper/
+    config:         config.tcl
+
+env: # used for simulation
+    GCC_PATH:       /home/runner/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14/bin/
+    GCC_PREFIX:     riscv64-unknown-elf
+    PDK_PATH:       /home/runner/pdk/sky130B
+    PDK_ROOT:       /home/runner/pdk
+    OPENLANE:       /home/runner/openlane
+    PDK:            sky130B

projects.yaml

diff --git a/projects.yaml b/projects.yaml
new file mode 100644
index 0000000..11dd87e
--- /dev/null
+++ b/projects.yaml
@@ -0,0 +1,65 @@
+interfaces:
+    required:
+        power: {vccd1: 1, vssd1: 1}
+        clock: {wb_clk_i: 1}
+        active: {active: 1}
+
+    optional:
+        gpio:       {io_in: 38, io_out: 38, io_oeb: 38}
+        la1:        {la1_data_in: 32, la1_data_out: 32, la1_oenb: 32}
+        la2:        {la2_data_in: 32, la2_data_out: 32, la2_oenb: 32}
+        la3:        {la3_data_in: 32, la3_data_out: 32, la3_oenb: 32}
+        irq:        {user_irq: 3}
+        clk2 :      {user_clock2: 1}
+        wishbone:   {wb_rst_i: 1, wbs_stb_i: 1, wbs_cyc_i: 1, wbs_we_i: 1, wbs_sel_i: 4, wbs_dat_i: 32, wbs_adr_i: 32, wbs_ack_o: 1, wbs_dat_o: 32}
+        openram:    {rambus_wb_clk_o: 1, rambus_wb_rst_o: 1, rambus_wb_stb_o: 1, rambus_wb_cyc_o: 1,  rambus_wb_we_o: 1, rambus_wb_sel_o: 4, rambus_wb_dat_o: 32, rambus_wb_adr_o: 10, rambus_wb_ack_i: 1, rambus_wb_dat_i: 32}
+
+openram_support:
+    wb_uprj_bus:    {
+                        wbs_stb_i   : wbs_uprj_stb_i,
+                        wbs_cyc_i   : wbs_uprj_cyc_i,
+                        wbs_we_i    : wbs_uprj_we_i,
+                        wbs_sel_i   : wbs_uprj_sel_i,
+                        wbs_dat_i   : wbs_uprj_dat_i,
+                        wbs_adr_i   : wbs_uprj_adr_i,
+                        wbs_ack_o   : wbs_uprj_ack_o,
+                        wbs_dat_o   : wbs_uprj_dat_o,
+                    }
+    projects:
+
+        wb_bridge:
+            repo:   'https://github.com/embelon/wb_bridge'
+            commit: '4a766fceed9bc52a1ab11621afade3cba1e44eeb'
+            pos:    '1550 480 N'
+            
+        wb_openram_wrapper:
+            repo:   'https://github.com/embelon/wb_openram_wrapper'
+            commit: '9b6c79a6015c46b923d6aed2d5cf9306003d4b3b'
+            pos:    '1085 480 N'
+
+        openram:
+            repo:   'https://github.com/mattvenn/openram_z2a'
+            commit: '1ef59a0d03fc21cdadabec0a3f07ff4e05598f70'
+            pos:    '344 475.5 N'
+
+configuration:
+    macro_snap: 0.23 # half of met2 pin/track space
+    user_area_width: 2920
+    user_area_height: 3520
+    gds:
+        # https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html?highlight=72#gds-layers-information
+        metal5_id:  72 
+        layers: [ 'li', 'met1', 'met2', 'met3', 'met4', 'met5']
+
+docs:
+    pic_dir:        pics
+    index:          index.md
+    px_per_um:      0.53 # for the image markup
+    macro_border:   25 # px
+
+projects:
+    function_generator:
+        repo:   'https://github.com/mattvenn/wrapped_function_generator'
+        commit: '701095fd880ad3bb80d6cec1d214a04e5676a65d'
+        pos:    '350 1200 N'
+