| commit | 151693a46cb0acb1c6d1d442e7a18df409802537 | [log] [tgz] |
|---|---|---|
| author | matt venn <matt@mattvenn.net> | Tue Aug 30 21:26:50 2022 +0200 |
| committer | matt venn <matt@mattvenn.net> | Tue Aug 30 21:26:50 2022 +0200 |
| tree | f1181e519f3dc033621dd13c405dd3226b971647 | |
| parent | 702392054dc8a9506cc83b351b3e3fdb59c0fb24 [diff] |
silife
This ASIC was designed by members of the Zero to ASIC course.
This submission was configured and built by the multi project tools at commit 8be9641236aa5c055f6195d3d903eb63e4f1336e.
The configuration files are projects.yaml & local.yaml. See the CI for how the build works.
# clone all repos, and include support for shared OpenRAM ./multi_tool.py --clone-repos --clone-shared-repos --create-openlane-config --copy-gds --copy-project --openram # run all the tests ./multi_tool.py --test-all --force-delete # build user project wrapper submission cd $CARAVEL_ROOT; make user_project_wrapper # create docs ./multi_tool.py --generate-doc --annotate-image
