wip
diff --git a/configure.py b/configure.py index 742dd09..63a36c2 100755 --- a/configure.py +++ b/configure.py
@@ -325,6 +325,7 @@ with open('verilog/includes/includes.rtl.caravel_user_project', 'w') as fh: fh.write('-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v\n') fh.write('-v $(USER_PROJECT_VERILOG)/rtl/scan_controller/scan_controller.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/scan_controller/cells.v\n') for verilog in verilog_files: fh.write('-v $(USER_PROJECT_VERILOG)/rtl/{}\n'.format(verilog))
diff --git a/verilog/dv/scan_controller/Makefile b/verilog/dv/scan_controller/Makefile index 4686307..2350a6b 100644 --- a/verilog/dv/scan_controller/Makefile +++ b/verilog/dv/scan_controller/Makefile
@@ -11,7 +11,7 @@ test_scan_controller: rm -rf sim_build/ mkdir sim_build/ - iverilog -DMPRJ_IO_PADS=38 -DCOCOTB -o sim_build/sim.vvp -s test_scan_controller_tb -g2012 test_scan_controller_tb.v -I $(PDK_ROOT)/sky130A/ -f../../includes/includes.rtl.caravel_user_project + iverilog -DUSE_POWER_PINS -DMPRJ_IO_PADS=38 -DCOCOTB -o sim_build/sim.vvp -s test_scan_controller_tb -g2012 test_scan_controller_tb.v -I $(PDK_ROOT)/sky130A/ -f../../includes/includes.rtl.caravel_user_project MODULE=test_scan_controller vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp ! grep failure results.xml
diff --git a/verilog/dv/scan_controller/test_scan_controller.gtkw b/verilog/dv/scan_controller/test_scan_controller.gtkw new file mode 100644 index 0000000..387d96d --- /dev/null +++ b/verilog/dv/scan_controller/test_scan_controller.gtkw
@@ -0,0 +1,27 @@ +[*] +[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI +[*] Fri Aug 26 12:41:18 2022 +[*] +[dumpfile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller/test_scan_controller.vcd" +[dumpfile_mtime] "Fri Aug 26 12:41:01 2022" +[dumpfile_size] 7201446 +[savefile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller/test_scan_controller.gtkw" +[timestart] 0 +[size] 1848 1016 +[pos] -1 -1 +*-28.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] test_scan_controller_tb. +[sst_width] 233 +[signals_width] 174 +[sst_expanded] 1 +[sst_vpaned_height] 289 +@22 +test_scan_controller_tb.user_project_wrapper.active_select[8:0] +test_scan_controller_tb.user_project_wrapper.inputs[7:0] +test_scan_controller_tb.user_project_wrapper.outputs[7:0] +@28 +test_scan_controller_tb.user_project_wrapper.ready +test_scan_controller_tb.clk +test_scan_controller_tb.reset +[pattern_trace] 1 +[pattern_trace] 0
diff --git a/verilog/dv/scan_controller/test_scan_controller.py b/verilog/dv/scan_controller/test_scan_controller.py index a2d55ed..2bbba67 100644 --- a/verilog/dv/scan_controller/test_scan_controller.py +++ b/verilog/dv/scan_controller/test_scan_controller.py
@@ -26,14 +26,12 @@ cocotb.fork(clock.start()) dut.reset = 1 - dut.active_select = 0 - await ClockCycles(dut.clk, 1) + dut.active_select = 12 # 7 seg seconds + await ClockCycles(dut.clk, 10) dut.reset = 0 dut.inputs = 0x00 - await RisingEdge(dut.ready); - await RisingEdge(dut.ready); - assert dut.outputs == 0x00 + for i in range(10): + print("clock {}".format(i)) + await RisingEdge(dut.ready); - # wait one clock cycle to sync - await single_cycle(dut)
diff --git a/verilog/dv/scan_controller/test_scan_controller_tb.v b/verilog/dv/scan_controller/test_scan_controller_tb.v index b7d67c2..5befe1e 100644 --- a/verilog/dv/scan_controller/test_scan_controller_tb.v +++ b/verilog/dv/scan_controller/test_scan_controller_tb.v
@@ -26,14 +26,14 @@ `ifdef COCOTB initial begin $dumpfile ("test_scan_controller.vcd"); - $dumpvars (0, test_scan_controller); + $dumpvars (0, test_scan_controller_tb); #1; end `endif user_project_wrapper user_project_wrapper( .wb_clk_i (clk), - .wb_rst_i (rst), + .wb_rst_i (reset), .io_in (io_in), .io_out (io_out), .io_oeb (io_oeb));
diff --git a/verilog/rtl/cells.v b/verilog/rtl/cells.v new file mode 100644 index 0000000..fb6db62 --- /dev/null +++ b/verilog/rtl/cells.v
@@ -0,0 +1,96 @@ +`define default_netname none + +module buffer_cell ( + input wire in, + output wire out + ); + assign out = in; +endmodule + +module and_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a & b; +endmodule + +module or_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a | b; +endmodule + +module xor_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a ^ b; +endmodule + +module nand_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = !(a&b); +endmodule + +module not_cell ( + input wire in, + output wire out + ); + + assign out = !in; +endmodule + +module mux_cell ( + input wire a, + input wire b, + input wire sel, + output wire out + ); + + assign out = sel ? b : a; +endmodule + +module dff_cell ( + input wire clk, + input wire d, + output reg q, + output wire notq + ); + + assign notq = !q; + always @(posedge clk) + q <= d; + +endmodule + +module dffsr_cell ( + input wire clk, + input wire d, + input wire s, + input wire r, + output reg q, + output wire notq + ); + + assign notq = !q; + + always @(posedge clk or posedge s or posedge r) begin + if (r) + q <= '0; + else if (s) + q <= '1; + else + q <= d; + end +endmodule