fix verilog error

verilog/rtl/scan_controller/scan_controller.v

diff --git a/verilog/rtl/scan_controller/scan_controller.v b/verilog/rtl/scan_controller/scan_controller.v
index d9f8f96..1591991 100644
--- a/verilog/rtl/scan_controller/scan_controller.v
+++ b/verilog/rtl/scan_controller/scan_controller.v
@@ -53,7 +53,7 @@
     assign scan_latch_en    = driver_sel == 2'b00 ? ext_scan_latch_en : driver_sel == 2'b01 ? int_scan_latch_en : la_scan_latch_en;
 
     wire int_scan_data_in   = scan_data_in;
-    wire la_scan_data_out   = scan_data_in;
+    assign la_scan_data_out = scan_data_in;
     assign outputs          = driver_sel == 2'b01 ? outputs_r : {7'b0, ext_scan_data_out};
 
     `ifdef FORMAL