ready signal and reset for clock div
1 file changed
tree: c68e2e91e7c7f81b99eac870df7a7c9a78e00279
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spef/
  11. spi/
  12. verilog/
  13. .gitignore
  14. configure.py
  15. INFO.md
  16. integrate_new_projects.sh
  17. LICENSE
  18. lint.sh
  19. Makefile
  20. missing_power_rings.gds
  21. post_build.sh
  22. powerring.lyp
  23. project_urls.py
  24. project_urls_test.py
  25. projects.pkl
  26. README.md
  27. README_init.md
  28. requirements.txt
  29. tinytapeout.png
  30. upw_post.v
  31. upw_pre.v
README.md

tinytapeout

TinyTapeout

  • See https://tinytapeout.com for more information on the project and how to get involved.
  • See INFO for how the project is built and technical project notes.

GDS layout of all projects

tiny tapeout

Project Index