)]}'
{
  "commit": "4ed41af6ae695e1fd2acf10c03dfd6b020a9d066",
  "tree": "c68e2e91e7c7f81b99eac870df7a7c9a78e00279",
  "parents": [
    "e91bdedbf75a1da30d41bcb8be7eb4ae1bf74b1f"
  ],
  "author": {
    "name": "matt venn",
    "email": "matt@mattvenn.net",
    "time": "Wed Aug 31 22:13:47 2022 +0200"
  },
  "committer": {
    "name": "Matt Venn",
    "email": "matt@mattvenn.net",
    "time": "Thu Sep 01 12:44:37 2022 +0200"
  },
  "message": "ready signal and reset for clock div\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e1d75a896fa1402291b436b04377f0133fcebc80",
      "old_mode": 33188,
      "old_path": "verilog/rtl/scan_controller/scan_controller.v",
      "new_id": "df298c9892a3339333399b57a48cca69f9767a2b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/scan_controller/scan_controller.v"
    }
  ]
}