wip testing
diff --git a/configure.py b/configure.py index 637ca8f..172d777 100755 --- a/configure.py +++ b/configure.py
@@ -6,7 +6,6 @@ from signal import signal, SIGPIPE, SIG_DFL signal(SIGPIPE, SIG_DFL) -filler_project_url = 'https://github.com/mattvenn/wokwi_filler' tmp_dir = '/tmp/tt' DEFAULT_NUM_PROJECTS = 498 @@ -15,8 +14,9 @@ projects_db = "projects.pkl" - def __init__(self, update_cache=False): + def __init__(self, update_cache=False, test=False): self.default_project = 0 + self.test = test if update_cache: self.update_cache() else: @@ -88,13 +88,23 @@ def get_wokwi_ids(self): return self.wokwi_ids + + def get_giturl(self, id): + try: + return self.get_project_urls()[id] + except IndexError: + return self.get_project_urls()[self.default_project] @classmethod def build_wokwi_url(Project, wokwi_id): return "https://wokwi.com/projects/{}".format(wokwi_id) def get_project_urls(self): - from project_urls import project_urls + if self.test: + from project_urls_test import project_urls, filler_project_url + else: + from project_urls import project_urls, filler_project_url + return [filler_project_url] + project_urls # the latest artifact isn't necessarily the one related to the latest commit, as github @@ -290,8 +300,8 @@ .slow_clk (io_out[10]), .set_clk_div (io_in[11]), - .scan_clk_in (clk[0]), - .scan_clk_out (clk[NUM_MACROS]), + .scan_clk_out (clk[0]), + .scan_clk_in (clk[NUM_MACROS]), .scan_data_out (data[0]), .scan_data_in (data[NUM_MACROS]), .scan_select (scan[0]), @@ -310,6 +320,7 @@ """ lesson_template = """ + // {giturl} {name} #(.NUM_IOS(8)) {instance} ( .clk_in (clk [{id}]), .data_in (data [{id}]), @@ -334,7 +345,7 @@ for i in range(self.num_projects): logging.debug("instance {} {}".format(i, self.projects.get_macro_name(i))) # instantiate template - instance = lesson_template.format(instance=self.projects.get_macro_instance(i), name=self.projects.get_macro_name(i), id=i, next_id=i + 1) + instance = lesson_template.format(giturl=self.projects.get_giturl(i), instance=self.projects.get_macro_instance(i), name=self.projects.get_macro_name(i), id=i, next_id=i + 1) fh.write(instance) fh.write(post) @@ -378,6 +389,7 @@ parser.add_argument('--update-projects', help='fetch the project data', action='store_const', const=True) parser.add_argument('--update-caravel', help='configure caravel for build', action='store_const', const=True) parser.add_argument('--limit-num-projects', help='only configure for the first n projects', type=int, default=DEFAULT_NUM_PROJECTS) + parser.add_argument('--test', help='use test projects', action='store_const', const=True) parser.add_argument('--debug', help="debug logging", action="store_const", dest="loglevel", const=logging.DEBUG, default=logging.INFO) args = parser.parse_args() @@ -398,7 +410,7 @@ ch.setFormatter(log_format) log.addHandler(ch) - projects = Projects(update_cache=args.update_projects) + projects = Projects(update_cache=args.update_projects, test=args.test) caravel = CaravelConfig(projects, num_projects=args.limit_num_projects) if args.update_caravel:
diff --git a/project_urls.py b/project_urls.py index 2f538cf..21a1f2a 100644 --- a/project_urls.py +++ b/project_urls.py
@@ -1,4 +1,4 @@ -# name must be valid verilog module name set in scan_wrapper.v +filler_project_url = 'https://github.com/mattvenn/wokwi_filler' project_urls = [ 'https://github.com/mattvenn/wokwi-verilog-gds-test', 'https://github.com/mattvenn/animation_tinytapeout_demo',
diff --git a/project_urls_test.py b/project_urls_test.py new file mode 100644 index 0000000..a10723a --- /dev/null +++ b/project_urls_test.py
@@ -0,0 +1,5 @@ +filler_project_url = 'https://github.com/mattvenn/tinytapeout-test-straight' +project_urls = [ + 'https://github.com/mattvenn/tinytapeout-7seg-seconds-counter', + 'https://github.com/mattvenn/tinytapeout-test-invert', + ]
diff --git a/verilog/dv/scan_controller/test_scan_controller.gtkw b/verilog/dv/scan_controller/test_scan_controller.gtkw index f4509d8..c90cbc9 100644 --- a/verilog/dv/scan_controller/test_scan_controller.gtkw +++ b/verilog/dv/scan_controller/test_scan_controller.gtkw
@@ -1,19 +1,18 @@ [*] [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI -[*] Sat Aug 27 16:09:50 2022 +[*] Wed Aug 31 19:31:00 2022 [*] [dumpfile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller/test_scan_controller.vcd" -[dumpfile_mtime] "Sat Aug 27 16:09:19 2022" -[dumpfile_size] 86352838 +[dumpfile_mtime] "Wed Aug 31 19:30:43 2022" +[dumpfile_size] 14402588 [savefile] "/home/matt/work/asic-workshop/shuttle7/tinytapeout-mpw7/verilog/dv/scan_controller/test_scan_controller.gtkw" [timestart] 0 [size] 1848 1016 [pos] -1 -1 -*-27.000000 91200000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-30.000000 3209000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] test_scan_controller_tb. [treeopen] test_scan_controller_tb.user_project_wrapper. [treeopen] test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0. -[treeopen] test_scan_controller_tb.user_project_wrapper.scan_wrapper_340805072482992722_12. [sst_width] 507 [signals_width] 265 [sst_expanded] 1 @@ -21,76 +20,19 @@ @28 test_scan_controller_tb.clk test_scan_controller_tb.reset -@24 -test_scan_controller_tb.user_project_wrapper.active_select[8:0] -@c00022 -test_scan_controller_tb.user_project_wrapper.inputs[7:0] -@28 -(0)test_scan_controller_tb.user_project_wrapper.inputs[7:0] -(1)test_scan_controller_tb.user_project_wrapper.inputs[7:0] -(2)test_scan_controller_tb.user_project_wrapper.inputs[7:0] -(3)test_scan_controller_tb.user_project_wrapper.inputs[7:0] -(4)test_scan_controller_tb.user_project_wrapper.inputs[7:0] -(5)test_scan_controller_tb.user_project_wrapper.inputs[7:0] -(6)test_scan_controller_tb.user_project_wrapper.inputs[7:0] -(7)test_scan_controller_tb.user_project_wrapper.inputs[7:0] -@1401200 --group_end -@c00022 -test_scan_controller_tb.user_project_wrapper.outputs[7:0] -@28 -(0)test_scan_controller_tb.user_project_wrapper.outputs[7:0] -(1)test_scan_controller_tb.user_project_wrapper.outputs[7:0] -(2)test_scan_controller_tb.user_project_wrapper.outputs[7:0] -(3)test_scan_controller_tb.user_project_wrapper.outputs[7:0] -(4)test_scan_controller_tb.user_project_wrapper.outputs[7:0] -(5)test_scan_controller_tb.user_project_wrapper.outputs[7:0] -(6)test_scan_controller_tb.user_project_wrapper.outputs[7:0] -(7)test_scan_controller_tb.user_project_wrapper.outputs[7:0] -@1401200 --group_end -@28 -test_scan_controller_tb.user_project_wrapper.ready -@800200 --scan controller -@28 -test_scan_controller_tb.user_project_wrapper.scan_controller.scan_clk -test_scan_controller_tb.user_project_wrapper.scan_controller.state[2:0] -@22 -test_scan_controller_tb.user_project_wrapper.scan_controller.current_design[8:0] -@1000200 --scan controller -@c00200 --module 0 -@28 -test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.data_in -test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.data_out -@800022 -test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -@28 -(0)test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -(1)test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -(2)test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -(3)test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -(4)test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -(5)test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -(6)test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -(7)test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_data_in[7:0] -test_scan_controller_tb.user_project_wrapper.scan_wrapper_339501025136214612_0.scan_select_in -@1001200 --group_end -@1401200 --module 0 -@800200 --scan chain -@28 -test_scan_controller_tb.user_project_wrapper.scan_controller.clk -test_scan_controller_tb.user_project_wrapper.scan_controller.scan_clk +test_scan_controller_tb.user_project_wrapper.scan_controller.scan_clk_in +test_scan_controller_tb.user_project_wrapper.scan_controller.scan_clk_out test_scan_controller_tb.user_project_wrapper.scan_controller.scan_data_in test_scan_controller_tb.user_project_wrapper.scan_controller.scan_data_out -test_scan_controller_tb.user_project_wrapper.scan_controller.scan_latch_enable +test_scan_controller_tb.user_project_wrapper.scan_controller.scan_latch_en test_scan_controller_tb.user_project_wrapper.scan_controller.scan_select -@1000200 --scan chain +@22 +test_scan_controller_tb.user_project_wrapper.scan_controller.inputs[7:0] +test_scan_controller_tb.user_project_wrapper.scan_controller.outputs[7:0] +test_scan_controller_tb.user_project_wrapper.scan_controller.active_select[8:0] +@28 +test_scan_controller_tb.user_project_wrapper.scan_controller.ready +@29 +test_scan_controller_tb.user_project_wrapper.scan_controller.proj_done [pattern_trace] 1 [pattern_trace] 0
diff --git a/verilog/dv/scan_controller/test_scan_controller.py b/verilog/dv/scan_controller/test_scan_controller.py index fd64c35..b4e0577 100644 --- a/verilog/dv/scan_controller/test_scan_controller.py +++ b/verilog/dv/scan_controller/test_scan_controller.py
@@ -39,14 +39,13 @@ dut.reset.value = 1 dut.set_clk_div.value = 0 - dut.driver_sel.value = 0b01 # internal controller - dut.active_select.value = 12 # 7 seg seconds + dut.driver_sel.value = 0b10 # internal controller + dut.active_select.value = 1 # 7 seg seconds await ClockCycles(dut.clk, 10) dut.reset.value = 0 dut.inputs.value = 0 dut.set_clk_div.value = 1 # lock in the new clock divider value await ClockCycles(dut.clk, 1) -# dut.set_clk_div.value = 0 dut.inputs.value = 0 # reset: set bit 1 high, wait for one cycle of slow_clk, then set bit 1 low @@ -60,7 +59,40 @@ await FallingEdge(dut.slow_clk) for i in range(10): print("clock {:2} 7seg {}".format(i, decode_seg(dut.seven_seg.value))) - #assert decode_seg(dut.seven_seg.value) == i - #await single_cycle(dut) + assert decode_seg(dut.seven_seg.value) == i await FallingEdge(dut.slow_clk) + print("straight test") + dut.set_clk_div.value = 0 # no clock div + dut.active_select.value = 0 # straight + await FallingEdge(dut.ready) + for i in range(11): + dut.inputs.value = i + await FallingEdge(dut.ready) + print(i, int(dut.outputs)) + if i > 0: + assert i == int(dut.outputs) + 1 + + print("invert test") + dut.active_select.value = 2 # invert + dut.inputs.value = 0 + await FallingEdge(dut.ready) + await FallingEdge(dut.ready) + for i in range(11): + dut.inputs.value = i + await FallingEdge(dut.ready) + print(i, int(dut.outputs)) + if i > 0: + assert 256 - i == int(dut.outputs) + + for design in range(10): # next 10 designs are all straight + print("straight test at pos {}".format(design)) + dut.active_select.value = 3 + design + await FallingEdge(dut.ready) + for i in range(11): + dut.inputs.value = i + await FallingEdge(dut.ready) + print(i, int(dut.outputs)) + if i > 0: + assert i == int(dut.outputs) + 1 +
diff --git a/verilog/rtl/scan_controller/scan_controller.v b/verilog/rtl/scan_controller/scan_controller.v index 93ec4b0..e1d75a8 100644 --- a/verilog/rtl/scan_controller/scan_controller.v +++ b/verilog/rtl/scan_controller/scan_controller.v
@@ -38,6 +38,7 @@ // Signals // ------- + assign ready = active && state == ST_IDLE; // Reset reg [2:0] rst_shift;