back to all segs

verilog/dv/scan_controller/test_scan_controller.py

diff --git a/verilog/dv/scan_controller/test_scan_controller.py b/verilog/dv/scan_controller/test_scan_controller.py
index 3cfe4da..b4e0577 100644
--- a/verilog/dv/scan_controller/test_scan_controller.py
+++ b/verilog/dv/scan_controller/test_scan_controller.py
@@ -57,7 +57,7 @@
     # sync to falling edge of slow clk
     # this is because the design won't see the clock until it's sampled by the scan chain.
     await FallingEdge(dut.slow_clk)
-    for i in range(2):
+    for i in range(10):
         print("clock {:2} 7seg {}".format(i, decode_seg(dut.seven_seg.value)))
         assert decode_seg(dut.seven_seg.value) == i
         await FallingEdge(dut.slow_clk)