tapeout checklist fom density fix
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index e636eb4..f08a011 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz index ee8bc66..72e6b02 100644 --- a/lef/user_project_wrapper.lef.gz +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 7c6a411..a766a77 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -135,10 +135,10 @@ met2 950 130 1633.1 546.54,\ met3 950 130 1633.1 546.54,\ - li1 150 650 833.1 1066.54,\ - met1 150 650 833.1 1066.54,\ - met2 150 650 833.1 1066.54,\ - met3 150 650 833.1 1066.54,\ + li1 150 750 833.1 1166.54,\ + met1 150 750 833.1 1166.54,\ + met2 150 750 833.1 1166.54,\ + met3 150 750 833.1 1166.54,\ met5 0 0 2920 3520" set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index c4ee99f..cf294f1 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -8,9 +8,9 @@ u_riscv_top.i_core_top_3 1200 2475 FN u_riscv_top.u_connect 725 1400 N u_riscv_top.u_intf 950 650 N -u_icache_2kb 150 130 N -u_dcache_2kb 950 130 N -u_tsram0_2kb 150 650 N +u_dcache_2kb 150 130 N +u_icache_2kb 950 130 N +u_tsram0_2kb 150 750 N u_intercon 1850 650 N
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 50ba5e6..fd0ffe5 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h8m41s0ms,0h4m26s0ms,-2.0,-1,-1,-1,590.45,14,0,0,0,0,0,0,-1,0,0,-1,-1,1558516,14240,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.83,9.11,1.58,2.6,0.0,391,4307,391,4307,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h2m10s0ms,0h4m30s0ms,-2.0,-1,-1,-1,590.02,14,0,0,0,0,0,0,-1,0,0,-1,-1,1528399,14110,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.57,9.14,1.71,2.11,0.0,391,4307,391,4307,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/spef/user_project_wrapper.spef.gz b/spef/user_project_wrapper.spef.gz index 208e4eb..0d24c2a 100644 --- a/spef/user_project_wrapper.spef.gz +++ b/spef/user_project_wrapper.spef.gz Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz index e29cd5b..377b416 100644 --- a/spi/lvs/user_project_wrapper.spice.gz +++ b/spi/lvs/user_project_wrapper.spice.gz Binary files differ
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v index fdbbf92..f2c62cb 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -47,10 +47,12 @@ initial begin $dumpfile("simx.vcd"); $dumpvars(1, wb_port_tb); - //$dumpvars(0, wb_port_tb.uut.soc); - //$dumpvars(1, wb_port_tb.uut.mprj); + $dumpvars(1, wb_port_tb.uut); + $dumpvars(1, wb_port_tb.uut.mgmt_buffers); + $dumpvars(1, wb_port_tb.uut.soc); + $dumpvars(1, wb_port_tb.uut.mprj); $dumpvars(1, wb_port_tb.uut.mprj.u_wb_host); - $dumpvars(2, wb_port_tb.uut.mprj.u_pinmux); + //$dumpvars(2, wb_port_tb.uut.mprj.u_pinmux); end `endif