first version riscduino dual core
diff --git a/.gitmodules b/.gitmodules
index 7c54d50..453828c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +1,6 @@
-[submodule "verilog/rtl/yifive/ycr1c"]
- path = verilog/rtl/yifive/ycr1c
- url = https://github.com/dineshannayya/ycr1c.git
[submodule "verilog/rtl/qspim"]
path = verilog/rtl/qspim
url = https://github.com/dineshannayya/qspim.git
+[submodule "verilog/rtl/yifive/ycr2c"]
+ path = verilog/rtl/yifive/ycr2c
+ url = https://github.com/dineshannayya/ycr2c.git
diff --git a/Makefile b/Makefile
index 2067627..cd5722b 100644
--- a/Makefile
+++ b/Makefile
@@ -18,6 +18,7 @@
PRECHECK_ROOT?=${HOME}/mpw_precheck
SIM ?= RTL
DUMP ?= OFF
+RISC_CORE ?=0
# Install lite version of caravel, (1): caravel-lite, (0): caravel
CARAVEL_LITE?=1
@@ -57,7 +58,7 @@
.PHONY: verify
verify:
cd ./verilog/dv/ && \
- export SIM=${SIM} DUMP=${DUMP} && \
+ export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && \
$(MAKE) -j$(THREADS)
# Install DV setup
@@ -69,7 +70,7 @@
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
TARGET_PATH=$(shell pwd)
PDK_PATH=${PDK_ROOT}/sky130A
-VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make"
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make"
$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_PATH}:${PDK_PATH} \
-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index c8c838c..2aab7ff 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -30,7 +30,7 @@
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 48e54f0..126b3c1 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -178,7 +178,7 @@
// Remove All Reset
- reg_mprj_wbhost_reg0 = 0x1F;
+ reg_mprj_globl_reg2 = 0x21F;
// Enable UART Multi Functional Ports
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 0461ba3..2c853fa 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -4,6 +4,7 @@
SIM ?= RTL
DUMP ?= OFF
+RISC_CORE ?=0
# PARAMETERS
@@ -47,7 +48,7 @@
VECT_IRQ ?= 0
IPIC ?= 0
TCM ?= 0
- SIM_CFG_DEF = YCR1_CFG_$(CFG)
+ SIM_CFG_DEF = YCR_CFG_$(CFG)
endif
endif
endif
@@ -136,7 +137,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = $(root_dir)/../model
UPRJ_BEHAVIOURAL_AGENTS = $(root_dir)/../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -283,6 +284,7 @@
printf "" > $(test_results); \
iverilog-vpi ../../../vpi/system/system.c; \
vvp -M. -msystem $(top_module).vvp \
+ +risc_core_id=$(RISC_CORE) \
+test_info=$(test_info) \
+test_results=$(test_results) \
| tee $(sim_results) ;\
@@ -303,6 +305,7 @@
printf "" > $(test_results); \
iverilog-vpi ../../../vpi/system/system.c; \
vvp -M. -msystem $(top_module).vvp \
+ +risc_core_id=$(RISC_CORE) \
+test_info=$(test_info) \
+test_results=$(test_results) \
| tee $(sim_results) ;\
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv
index 25c14a5..9a798ff 100644
--- a/verilog/dv/riscv_regress/riscv_runtests.sv
+++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -34,7 +34,7 @@
logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o_r; // DMEM address
logic core2dmem_cmd_o_r;
- `define RISC_CORE i_top.i_core_top
+ `define RISC_CORE i_top.i_core_top_0
always@(posedge `RISC_CORE.clk) begin
if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
@@ -55,7 +55,7 @@
**/
/***
logic [31:0] test_count;
- `define RISC_CORE u_top.u_riscv_top.i_core_top
+ `define RISC_CORE u_top.u_riscv_top.i_core_top_0
`define RISC_EXU u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu
initial begin
@@ -71,6 +71,10 @@
end
***/
+wire [31:0] pc_curr_ff = (d_risc_id == 0) ? u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_exu.pc_curr_ff : u_top.u_riscv_top.i_core_top_1.i_pipe_top.i_pipe_exu.pc_curr_ff;
+wire [31:0] exu2pipe_pc_curr_o = (d_risc_id == 0) ? u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o : u_top.u_riscv_top.i_core_top_1.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o;
+wire [31:0] mprf_int_10 = (d_risc_id == 0) ? u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_mprf.mprf_int[10] : u_top.u_riscv_top.i_core_top_1.i_pipe_top.i_pipe_mprf.mprf_int[10];
+
always @(posedge clk) begin
bit test_pass;
int unsigned f_test;
@@ -78,11 +82,11 @@
if (test_running) begin
test_pass = 1;
rst_init <= 1'b0;
- if(u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu.pc_curr_ff === 32'hxxxx_xxxx) begin
+ if(pc_curr_ff === 32'hxxxx_xxxx) begin
$display("ERROR: CURRENT PC Counter State is Known");
$finish;
end
- if ((u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o == YCR1_SIM_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
+ if ((exu2pipe_pc_curr_o == YCR1_SIM_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
`ifdef VERILATOR
logic [255:0] full_filename;
@@ -103,9 +107,9 @@
// Flush the content of dcache for signature validation at app
// memory
- force u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush = 1'b1;
- wait(u_top.u_riscv_top.u_intf.u_dcache.force_flush_done == 1'b1);
- release u_top.u_riscv_top.u_intf.u_dcache.cfg_force_flush;
+ force u_top.u_riscv_top.u_mintf.u_intf.u_dcache.cfg_force_flush = 1'b1;
+ wait(u_top.u_riscv_top.u_mintf.u_intf.u_dcache.force_flush_done == 1'b1);
+ release u_top.u_riscv_top.u_mintf.u_intf.u_dcache.cfg_force_flush;
repeat (2000) @(posedge clock); // wait data to flush in pipe
$display("STATUS: Checking Complaince Test Status .... ");
test_running <= 1'b0;
@@ -203,10 +207,10 @@
`endif // SIGNATURE_OUT
end else begin // Non compliance mode
test_running <= 1'b0;
- if(u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] != 0)
- $display("ERROR: mprf_int[10]: %x not zero",u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10]);
+ if(mprf_int_10 != 0)
+ $display("ERROR: mprf_int[10]: %x not zero",mprf_int_10);
- test_pass = (u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] == 0);
+ test_pass = (mprf_int_10 == 0);
tests_total += 1;
tests_passed += test_pass;
`ifndef SIGNATURE_OUT
@@ -236,7 +240,10 @@
if (f_test != 0) begin
// Launch new test
`ifdef YCR1_TRACE_LOG_EN
- u_top.u_riscv_top.i_core_top.i_pipe_top.i_tracelog.test_name = test_file;
+ if(d_risc_id == 0)
+ u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_tracelog.test_name = test_file;
+ else
+ u_top.u_riscv_top.i_core_top_1.i_pipe_top.i_tracelog.test_name = test_file;
`endif // SCR1_TRACE_LOG_EN
//i_memory_tb.test_file = test_file;
//i_memory_tb.test_file_init = 1'b1;
diff --git a/verilog/dv/riscv_regress/run_iverilog b/verilog/dv/riscv_regress/run_iverilog
index fbd8e05..6245dbc 100755
--- a/verilog/dv/riscv_regress/run_iverilog
+++ b/verilog/dv/riscv_regress/run_iverilog
@@ -18,7 +18,7 @@
-I ../../../../../verilog/rtl \
-I ../../../../../verilog \
-I ../../../agents \
--I ../../../../../verilog/rtl/yifive/ycr1c/src/includes \
+-I ../../../../../verilog/rtl/yifive/ycr2c/src/includes \
-I ../../../../../verilog/rtl/sdram_ctrl/src/defs \
-I ../../../../../verilog/rtl/i2cm/src/includes \
-I ../../../../../verilog/rtl/usb1_host/src/includes \
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
index d7b3d63..19f8703 100644
--- a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
+++ b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
@@ -11,9 +11,9 @@
#define MCAUSE_TMR_IRQ (1 << 31 | IRQ_M_TIMER)
// IPIC
-#define IRQ_LINES_ADDR 0x10020018 // simulation
-#define TRIG_EXT_IRQ_ADDR 0x10020018 // external irq is triggered when tb memory is set to non-zero // Bit [15:0]
-#define TRIG_SW_IRQ_ADDR 0x10020018 // software irq is triggered when tb memory is set to non-zero // Bit [16]
+#define IRQ_LINES_ADDR 0x10020020 // simulation
+#define TRIG_EXT_IRQ_ADDR 0x10020020 // external irq is triggered when tb memory is set to non-zero // Bit [15:0]
+#define TRIG_SW_IRQ_ADDR 0x10020020 // software irq is triggered when tb memory is set to non-zero // Bit [16]
#define IPIC_EOI 0xBF4 // end of interrupt
#define IPIC_SOI 0xBF5 // start of interrupt
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 2bc1cfb..c23fe35 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -78,6 +78,9 @@
`include "mt48lc8m8a2.v"
`include "is62wvs1288.v"
+
+`define ADDR_SPACE_PINMUX 32'h3002_0000
+
localparam [31:0] YCR1_SIM_EXIT_ADDR = 32'h0000_00F8;
localparam [31:0] YCR1_SIM_PRINT_ADDR = 32'hF000_0000;
localparam [31:0] YCR1_SIM_EXT_IRQ_ADDR = 32'hF000_0100;
@@ -157,6 +160,7 @@
logic [7:0] tem_mem[0:4095];
logic [31:0] mem_data;
+ integer d_risc_id;
parameter P_FSM_C = 4'b0000; // Command Phase Only
@@ -220,6 +224,8 @@
wbd_ext_we_i ='h0; // write
wbd_ext_dat_i ='h0; // data output
wbd_ext_sel_i ='h0; // byte enable
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
end
`ifdef WFDUMP
@@ -230,7 +236,6 @@
$dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top);
$dumpvars(0, user_risc_regress_tb.u_top.u_qspi_master);
$dumpvars(0, user_risc_regress_tb.u_top.u_intercon);
- $dumpvars(0, user_risc_regress_tb.u_top.u_mbist);
end
`endif
@@ -289,7 +294,13 @@
repeat (2) @(posedge clock);
#1;
// Remove WB and SPI Reset, Keep SDARM and CORE under Reset
- wb_user_core_write('h3080_0000,'h5);
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
+ end else begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
+ end
// CS#2 Switch to QSPI Mode
wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile
index ec6f963..9be6ff7 100644
--- a/verilog/dv/uart_master/Makefile
+++ b/verilog/dv/uart_master/Makefile
@@ -31,7 +31,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index e9e1108..e534f3b 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 5788ed8..6f0b848 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 826774d..b56a263 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -127,7 +127,7 @@
`ifdef WFDUMP
initial begin
- $dumpfile("tb_top.vcd");
+ $dumpfile("simx.vcd");
$dumpvars(0, tb_top);
end
`endif
@@ -151,11 +151,14 @@
repeat (10) @(posedge clock);
#1;
// Enable I2M Block & WB Reset and Enable I2CM Mux Select
- wb_user_core_write('h3080_0000,'hA1);
+ wb_user_core_write('h3080_0000,'h01);
// Enable I2C Multi Functional Ports
wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h200);
+ // Remove i2m reset
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h010);
+
repeat (100) @(posedge clock);
@(posedge clock);
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 1057c10..46c4437 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -47,6 +47,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
DUMP?=OFF
+RISC_CORE?=0
.SUFFIXES:
@@ -92,7 +93,7 @@
endif
%.vcd: %.vvp
- vvp $<
+ vvp $< +risc_core_id=$(RISC_CORE)
%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index fff2408..11360d2 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -78,6 +78,7 @@
`include "uprj_netlists.v"
`include "mt48lc8m8a2.v"
+`define ADDR_SPACE_PINMUX 32'h3002_0000
module user_risc_boot_tb;
reg clock;
reg wb_rst_i;
@@ -105,6 +106,7 @@
wire [7:0] mprj_io_0;
reg test_fail;
reg [31:0] read_data;
+ integer d_risc_id;
@@ -133,6 +135,8 @@
initial begin
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
@@ -143,7 +147,13 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- wb_user_core_write('h3080_0000,'hF);
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
+ end else begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
+ end
// Repeat cycles of 1000 clock edges as needed to complete testbench
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index e0934e1..bedef96 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index cb37454..97b7c9f 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -101,6 +101,8 @@
`define QSPIM_IMEM_RDATA 32'h1000002C
`define QSPIM_SPI_STATUS 32'h10000030
+ `define ADDR_SPACE_PINMUX 32'h3002_0000
+
module user_spi_tb;
reg clock;
reg wb_rst_i;
@@ -221,8 +223,8 @@
repeat (2) @(posedge clock);
#1;
- // Remove WB and SPI Reset, Keep SDARM and CORE under Reset
- wb_user_core_write('h3080_0000,'h5);
+ // Remove only WB and SPI Reset
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h2);
wb_user_core_write('h3080_0004,'h0); // Change the Bank Sel 0
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 387f35d..320f113 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
@@ -47,6 +47,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
DUMP?=OFF
+RISC_CORE?=0
.SUFFIXES:
@@ -92,7 +93,7 @@
endif
%.vcd: %.vvp
- vvp $<
+ vvp $< +risc_core_id=$(RISC_CORE)
%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index dba2b77..9e150f4 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -129,6 +129,8 @@
reg [7:0] uart_write_data [0:39];
reg uart_fifo_enable ; // fifo mode disable
+ integer d_risc_id;
+
integer i,j;
// External clock is used by default. Make this artificially fast for the
@@ -171,6 +173,8 @@
uart_timeout = 500;// wait time limit
uart_fifo_enable = 0; // fifo mode disable
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Uart Test Started");
@@ -184,7 +188,13 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- wb_user_core_write('h3080_0000,'h1F);
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F);
+ end else begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h21F);
+ end
repeat (100) @(posedge clock); // wait for Processor Get Ready
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index b52caef..4e61e77 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile
@@ -29,7 +29,7 @@
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../model
UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index a19be6a..8844da3 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -30,7 +30,7 @@
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
UPRJ_BEHAVIOURAL_MODELS = ../
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr2c/src/includes
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 5015bb6..c1c1a56 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -50,6 +50,15 @@
input logic mclk,
input logic h_reset_n,
+ // Global Reset control
+ output logic [1:0] cpu_core_rst_n ,
+ output logic cpu_intf_rst_n ,
+ output logic qspim_rst_n ,
+ output logic sspim_rst_n ,
+ output logic uart_rst_n ,
+ output logic i2cm_rst_n ,
+ output logic usb_rst_n ,
+
// Reg Bus Interface Signal
input logic reg_cs,
input logic reg_wr,
@@ -264,6 +273,14 @@
.mclk (mclk ),
.h_reset_n (h_reset_n ),
+ .cpu_core_rst_n (cpu_core_rst_n ),
+ .cpu_intf_rst_n (cpu_intf_rst_n ),
+ .qspim_rst_n (qspim_rst_n ),
+ .sspim_rst_n (sspim_rst_n ),
+ .uart_rst_n (uart_rst_n ),
+ .i2cm_rst_n (i2cm_rst_n ),
+ .usb_rst_n (usb_rst_n ),
+
// Reg read/write Interface Inputs
.reg_cs (reg_cs ),
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 211bd40..1e7ad9f 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -42,6 +42,15 @@
input logic mclk,
input logic h_reset_n,
+ // Global Reset control
+ output logic [1:0] cpu_core_rst_n ,
+ output logic cpu_intf_rst_n ,
+ output logic qspim_rst_n ,
+ output logic sspim_rst_n ,
+ output logic uart_rst_n ,
+ output logic i2cm_rst_n ,
+ output logic usb_rst_n ,
+
// Reg Bus Interface Signal
input logic reg_cs,
input logic reg_wr,
@@ -134,13 +143,13 @@
logic [31:0] reg_out;
logic [31:0] reg_0; // Chip ID
logic [31:0] reg_1; // Risc Fuse Id
-logic [31:0] reg_2; // GPIO Read Data
-logic [31:0] reg_3; // GPIO Output Data
-logic [31:0] reg_4; // GPIO Dir Sel
-logic [31:0] reg_5; // GPIO Type
-logic [31:0] reg_6; // Interrupt
-logic [31:0] reg_7; //
-logic [31:0] reg_8; //
+logic [31:0] reg_2; // Global config-1
+logic [31:0] reg_3; // Global config-2
+logic [31:0] reg_4; // GPIO Read Data
+logic [31:0] reg_5; // GPIO Output Data
+logic [31:0] reg_6; // GPIO Dir Sel
+logic [31:0] reg_7; // GPIO Type
+logic [31:0] reg_8; // Interrupt
logic [31:0] reg_9; // GPIO Interrupt Status
logic [31:0] reg_10; // GPIO Interrupt Status
logic [31:0] reg_11; // GPIO Interrupt Mask
@@ -269,11 +278,12 @@
//-----------------------------------------------------------------------
// Chip ID
-wire [15:0] manu_id = 16'h8949; // Asci value of YI
-wire [7:0] chip_id = 8'h02;
-wire [7:0] chip_rev = 8'h01;
+wire [15:0] manu_id = 16'h8268; // Asci value of RD
+wire [3:0] total_core = 4'h02;
+wire [3:0] chip_id = 4'h03;
+wire [7:0] chip_rev = 8'h01;
-assign reg_0 = {manu_id,chip_id,chip_rev};
+assign reg_0 = {manu_id,total_core,chip_id,chip_rev};
//-----------------------------------------------------------------------
@@ -294,34 +304,36 @@
assign fuse_mhartid = reg_1;
-//-----------------------------------------------------------------------
-// Logic for gpio_data_in
-//-----------------------------------------------------------------------
-logic [31:0] gpio_in_data_s;
-logic [31:0] gpio_in_data_ss;
-// Double Sync the gpio pin data for edge detection
-always @ (posedge mclk or negedge h_reset_n)
-begin
- if (h_reset_n == 1'b0) begin
- reg_2 <= 'h0 ;
- gpio_in_data_s <= 32'd0;
- gpio_in_data_ss <= 32'd0;
- end
- else begin
- gpio_in_data_s <= gpio_in_data;
- gpio_in_data_ss <= gpio_in_data_s;
- reg_2 <= gpio_in_data_ss;
- end
-end
+//------------------------------------------
+// reg-2: GLBL_CFG_1
+//------------------------------------------
+wire [31:0] cfg_glb_ctrl = reg_2;
+ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n));
+ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n));
+ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n));
+ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n));
+ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n));
+ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n));
-assign cfg_gpio_data_in = reg_2[31:0]; // to be used for edge interrupt detect
-assign gpio_prev_indata = gpio_in_data_ss;
+ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
+ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_data
-//-----------------------------------------------------------------------
-assign cfg_gpio_out_data = reg_3[31:0]; // data to the GPIO control blk
+gen_32b_reg #(32'h0) u_reg_2 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_2 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_2 )
+ );
+
+//----------------------------------------------
+// reg-3: GLBL_CFG_1
+//------------------------------------------
gen_32b_reg #(32'h0) u_reg_3 (
//List of Inputs
@@ -334,26 +346,36 @@
//List of Outs
.data_out (reg_3 )
);
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_dir_sel
-//-----------------------------------------------------------------------
-assign cfg_gpio_dir_sel = reg_4[31:0]; // data to the GPIO O/P pins
-gen_32b_reg #(32'h0) u_reg_4 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_4 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_4 )
- );
+assign cfg_pulse_1us = reg_3[9:0];
//-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_type
+// Logic for gpio_data_in
//-----------------------------------------------------------------------
-assign cfg_gpio_out_type = reg_5[31:0]; // to be used for read
+logic [31:0] gpio_in_data_s;
+logic [31:0] gpio_in_data_ss;
+// Double Sync the gpio pin data for edge detection
+always @ (posedge mclk or negedge h_reset_n)
+begin
+ if (h_reset_n == 1'b0) begin
+ reg_4 <= 'h0 ;
+ gpio_in_data_s <= 32'd0;
+ gpio_in_data_ss <= 32'd0;
+ end
+ else begin
+ gpio_in_data_s <= gpio_in_data;
+ gpio_in_data_ss <= gpio_in_data_s;
+ reg_4 <= gpio_in_data_ss;
+ end
+end
+
+
+assign cfg_gpio_data_in = reg_4[31:0]; // to be used for edge interrupt detect
+assign gpio_prev_indata = gpio_in_data_ss;
+
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_out_data
+//-----------------------------------------------------------------------
+assign cfg_gpio_out_data = reg_5[31:0]; // data to the GPIO control blk
gen_32b_reg #(32'h0) u_reg_5 (
//List of Inputs
@@ -366,69 +388,87 @@
//List of Outs
.data_out (reg_5 )
);
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_dir_sel
+//-----------------------------------------------------------------------
+assign cfg_gpio_dir_sel = reg_6[31:0]; // data to the GPIO O/P pins
+
+gen_32b_reg #(32'h0) u_reg_6 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_6 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_6 )
+ );
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_out_type
+//-----------------------------------------------------------------------
+assign cfg_gpio_out_type = reg_7[31:0]; // to be used for read
+
+gen_32b_reg #(32'h0) u_reg_7 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_7 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_7 )
+ );
//-----------------------------------------------------------------------
-// reg-6
+// reg-8
//-----------------------------------------------------------------
-assign irq_lines = reg_6[15:0];
-assign soft_irq = reg_6[16];
-assign user_irq = reg_6[19:17];
+assign irq_lines = reg_8[15:0];
+assign soft_irq = reg_8[16];
+assign user_irq = reg_8[19:17];
-generic_register #(8,0 ) u_reg6_be0 (
- .we ({8{sw_wr_en_6 &
+generic_register #(8,0 ) u_reg8_be0 (
+ .we ({8{sw_wr_en_8 &
wr_be[0] }} ),
.data_in (sw_reg_wdata[7:0] ),
.reset_n (h_reset_n ),
.clk (mclk ),
//List of Outs
- .data_out (reg_6[7:0] )
+ .data_out (reg_8[7:0] )
);
-generic_register #(3,0 ) u_reg6_be1_1 (
- .we ({3{sw_wr_en_6 &
+generic_register #(3,0 ) u_reg8_be1_1 (
+ .we ({3{sw_wr_en_8 &
wr_be[1] }} ),
.data_in (sw_reg_wdata[10:8] ),
.reset_n (h_reset_n ),
.clk (mclk ),
//List of Outs
- .data_out (reg_6[10:8] )
+ .data_out (reg_8[10:8] )
);
-assign reg_6[15:11] = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr};
+assign reg_8[15:11] = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr};
-generic_register #(4,0 ) u_reg6_be2 (
- .we ({4{sw_wr_en_6 &
+generic_register #(4,0 ) u_reg8_be2 (
+ .we ({4{sw_wr_en_8 &
wr_be[2] }} ),
.data_in (sw_reg_wdata[19:16]),
.reset_n (h_reset_n ),
.clk (mclk ),
//List of Outs
- .data_out (reg_6[19:16] )
+ .data_out (reg_8[19:16] )
);
-assign reg_6[31:20] = '0;
+assign reg_8[31:20] = '0;
-// Register-7
-gen_32b_reg #(32'h0) u_reg_7 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_7 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_7 )
- );
-
-assign cfg_pulse_1us = reg_7[9:0];
//-----------------------------------------------------------------------
// Logic for cfg_int_status
@@ -721,7 +761,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h1402_2022) u_reg_23 (
+gen_32b_reg #(32'h2202_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -736,7 +776,7 @@
//-----------------------------------------
// Software Reg-3: Poject Revison 3.3 = 0003400
// ----------------------------------------
-gen_32b_reg #(32'h0003_4000) u_reg_24 (
+gen_32b_reg #(32'h0003_5000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 4271db8..938ce8d 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -104,48 +104,49 @@
`include "wb_interconnect/src/wb_arb.sv"
`include "wb_interconnect/src/wb_interconnect.sv"
-
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_hdu.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_tdu.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_ipic.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_csr.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_exu.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_ialu.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_idu.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_ifu.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_lsu.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_mprf.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_mul.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_div.sv"
- `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_top.sv"
- `include "yifive/ycr1c/src/core/primitives/ycr1_reset_cells.sv"
- `include "yifive/ycr1c/src/core/primitives/ycr1_cg.sv"
- `include "yifive/ycr1c/src/core/ycr1_clk_ctrl.sv"
- `include "yifive/ycr1c/src/core/ycr1_tapc_shift_reg.sv"
- `include "yifive/ycr1c/src/core/ycr1_tapc.sv"
- `include "yifive/ycr1c/src/core/ycr1_tapc_synchronizer.sv"
- `include "yifive/ycr1c/src/core/ycr1_core_top.sv"
- `include "yifive/ycr1c/src/core/ycr1_dm.sv"
- `include "yifive/ycr1c/src/core/ycr1_dmi.sv"
- `include "yifive/ycr1c/src/core/ycr1_scu.sv"
- `include "yifive/ycr1c/src/top/ycr1_imem_router.sv"
- `include "yifive/ycr1c/src/top/ycr1_dmem_router.sv"
- `include "yifive/ycr1c/src/top/ycr1_dp_memory.sv"
- `include "yifive/ycr1c/src/top/ycr1_tcm.sv"
- `include "yifive/ycr1c/src/top/ycr1_timer.sv"
- `include "yifive/ycr1c/src/top/ycr1_dmem_wb.sv"
- `include "yifive/ycr1c/src/top/ycr1_imem_wb.sv"
- `include "yifive/ycr1c/src/top/ycr1_intf.sv"
- `include "yifive/ycr1c/src/top/ycr1_top_wb.sv"
- `include "yifive/ycr1c/src/top/ycr1_icache_router.sv"
- `include "yifive/ycr1c/src/top/ycr1_dcache_router.sv"
- `include "yifive/ycr1c/src/cache/src/core/icache_top.sv"
- `include "yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv"
- `include "yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv"
- `include "yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv"
- `include "yifive/ycr1c/src/cache/src/core/dcache_top.sv"
- `include "yifive/ycr1c/src/lib/ycr1_async_wbb.sv"
- `include "yifive/ycr1c/src/lib/ycr1_arb.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_ipic.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv"
+ `include "yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv"
+ `include "yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv"
+ `include "yifive/ycr2c/src/core/primitives/ycr_cg.sv"
+ `include "yifive/ycr2c/src/core/ycr_clk_ctrl.sv"
+ `include "yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv"
+ `include "yifive/ycr2c/src/core/ycr_tapc.sv"
+ `include "yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv"
+ `include "yifive/ycr2c/src/core/ycr_core_top.sv"
+ `include "yifive/ycr2c/src/core/ycr_dm.sv"
+ `include "yifive/ycr2c/src/core/ycr_dmi.sv"
+ `include "yifive/ycr2c/src/core/ycr_scu.sv"
+ `include "yifive/ycr2c/src/top/ycr_imem_router.sv"
+ `include "yifive/ycr2c/src/top/ycr_dmem_router.sv"
+ `include "yifive/ycr2c/src/top/ycr_dp_memory.sv"
+ `include "yifive/ycr2c/src/top/ycr_tcm.sv"
+ `include "yifive/ycr2c/src/top/ycr_timer.sv"
+ `include "yifive/ycr2c/src/top/ycr_dmem_wb.sv"
+ `include "yifive/ycr2c/src/top/ycr_imem_wb.sv"
+ `include "yifive/ycr2c/src/top/ycr2_mcore_router.sv"
+ `include "yifive/ycr2c/src/top/ycr2_intf.sv"
+ `include "yifive/ycr2c/src/top/ycr2_mintf.sv"
+ `include "yifive/ycr2c/src/top/ycr2_top_wb.sv"
+ `include "yifive/ycr2c/src/top/ycr_icache_router.sv"
+ `include "yifive/ycr2c/src/top/ycr_dcache_router.sv"
+ `include "yifive/ycr2c/src/cache/src/core/icache_top.sv"
+ `include "yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv"
+ `include "yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv"
+ `include "yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv"
+ `include "yifive/ycr2c/src/cache/src/core/dcache_top.sv"
+ `include "yifive/ycr2c/src/lib/ycr_async_wbb.sv"
+ `include "yifive/ycr2c/src/lib/ycr_arb.sv"
`include "lib/sync_fifo.sv"
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f4ef426..f08cd4c 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -164,11 +164,15 @@
//// 3.4 Feb 14, 2022, Dinesh A ////
//// burst mode supported added in imem buffer inside ////
//// riscv core ////
-//// We have created seperate repo from this onwards ////
-//// SRAM based SOC is spin-out to ////
-//// dineshannayya/riscduino_sram.git ////
-//// This repo will remove mbist + SRAM and RISC SRAM will be ////
-//// replaced with DFRAM ////
+//// 3.5 Feb 22, 2022 Dinesh A ////
+//// A. To create more space in die, we have removed mbist ////
+//// controller and 4x 2KB RAM ////
+//// B. Risc core will have core with common icache,dcache ////
+//// TCM memory ////
+//// C. Individual block reset are moved to pinmux to ////
+//// support peripheral reset from Risc and WishBone ////
+//// Host. ////
+//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -394,7 +398,8 @@
//----------------------------------------------------
// CPU Configuration
//----------------------------------------------------
-wire cpu_rst_n ;
+wire cpu_intf_rst_n ;
+wire [1:0] cpu_core_rst_n ;
wire qspim_rst_n ;
wire sspim_rst_n ;
wire uart_rst_n ; // uart reset
@@ -585,13 +590,6 @@
.usb_clk (usb_clk ),
.wbd_int_rst_n (wbd_int_rst_n ),
- .cpu_rst_n (cpu_rst_n ),
- .qspim_rst_n (qspim_rst_n ),
- .sspim_rst_n (sspim_rst_n ), // spi reset
- .uart_rst_n (uart_rst_n ), // uart reset
- .i2cm_rst_n (i2c_rst_n ), // i2c reset
- .usb_rst_n (usb_rst_n ), // usb reset
- .bist_rst_n (bist_rst_n ), // BIST Reset
// Master Port
.wbm_rst_i (wb_rst_i ),
@@ -641,7 +639,7 @@
//------------------------------------------------------------------------------
// RISC V Core instance
//------------------------------------------------------------------------------
-ycr1_top_wb u_riscv_top (
+ycr2_top_wb u_riscv_top (
`ifdef USE_POWER_PINS
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
@@ -653,7 +651,8 @@
// Reset
.pwrup_rst_n (wbd_int_rst_n ),
.rst_n (wbd_int_rst_n ),
- .cpu_rst_n (cpu_rst_n ),
+ .cpu_intf_rst_n (cpu_intf_rst_n ),
+ .cpu_core_rst_n (cpu_core_rst_n ),
.riscv_debug (riscv_debug ),
// Clock
@@ -1124,6 +1123,15 @@
.mclk (wbd_clk_pinmux_skew ),
.h_reset_n (wbd_int_rst_n ),
+ // Reset Control
+ .cpu_core_rst_n (cpu_core_rst_n ),
+ .cpu_intf_rst_n (cpu_intf_rst_n ),
+ .qspim_rst_n (qspim_rst_n ),
+ .sspim_rst_n (sspim_rst_n ),
+ .uart_rst_n (uart_rst_n ),
+ .i2cm_rst_n (i2c_rst_n ),
+ .usb_rst_n (usb_rst_n ),
+
// Reg Bus Interface Signal
.reg_cs (wbd_glbl_stb_o ),
.reg_wr (wbd_glbl_we_o ),
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 470a421..55bf9fb 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -82,13 +82,6 @@
output logic usb_clk ,
// Global Reset control
output logic wbd_int_rst_n ,
- output logic cpu_rst_n ,
- output logic qspim_rst_n ,
- output logic sspim_rst_n ,
- output logic uart_rst_n ,
- output logic i2cm_rst_n ,
- output logic usb_rst_n ,
- output logic bist_rst_n ,
// Master Port
input logic wbm_rst_i , // Regular Reset signal
@@ -191,13 +184,6 @@
ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
-ctech_buf u_buf_cpu_rst (.A(cfg_glb_ctrl[1]),.X(cpu_rst_n));
-ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[2]),.X(qspim_rst_n));
-ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[3]),.X(sspim_rst_n));
-ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[4]),.X(uart_rst_n));
-ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[5]),.X(i2cm_rst_n));
-ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[6]),.X(usb_rst_n));
-ctech_buf u_buf_bist_rst (.A(cfg_glb_ctrl[7]),.X(bist_rst_n));
//--------------------------------------------------------------------------------
// Look like wishbone reset removed early than user Power up sequence
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c
deleted file mode 160000
index defc5ce..0000000
--- a/verilog/rtl/yifive/ycr1c
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit defc5ce7ce231aa0c5944a897a0144f9613944be
diff --git a/verilog/rtl/yifive/ycr2c b/verilog/rtl/yifive/ycr2c
new file mode 160000
index 0000000..d2ab5c6
--- /dev/null
+++ b/verilog/rtl/yifive/ycr2c
@@ -0,0 +1 @@
+Subproject commit d2ab5c6787943530e98b18dfc3a92bdbe97756e5
