commit	1ccb309996a743075a97234334608bb5f9989292	[log] [tgz]
author	Usman <usmanzain95@gmail.com>	Mon May 30 20:22:27 2022 +0500
committer	Usman <usmanzain95@gmail.com>	Mon May 30 20:22:27 2022 +0500
tree	73420b298967c2d826c17cfc51bc8716448fbcec
parent	a11292b5ad1ffdb085a7884807f9d9569dce13f5 [diff]

soc now rtl and openram added

openlane/user_project_wrapper/config.tcl[diff]
verilog/rtl/Caravel_Top.v[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project_wrapper.v[diff]

5 files changed

tree: 73420b298967c2d826c17cfc51bc8716448fbcec

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.