tree: b01864109742b348425d6e0b355fa11f5084347c [path history] [tgz]
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. mpw_precheck/
  9. openlane/
  10. sdc/
  11. sdf/
  12. signoff/
  13. spef/
  14. spi/
  15. tapeout/
  16. verilog/
  17. .gitignore
  19. Makefile

License UPRJ_CI


RISC-V SoC designed for the Efabless Open MPW Program. This project

Block diagram of Experiar SoC


  • Dual RV32I cores
  • Per core SRAM
  • JTAG interface
  • External flash controller
  • Shared video SRAM
  • Configurable VGA output
  • 3x UART ports + 1 internal to caravel
  • 1x SPI ports
  • 4x PWM counters with 4x separate outputs (2 are internal read only)

Memory Map

Memory map for Experiar SoC

Macro Layout

Build Status

  • CaravelHost: Success
  • ExperiarCore: Success
  • Flash: Success
  • Peripherals: Success
  • Video: Success
  • WishboneInterconnect: Success
  • user_project_wrapper: Success



verify-coreArch-rtl: Success

verify-corePC-rtl: Success

verify-coreMemory-rtl: Success

verify-flash-rtl: Success

verify-memory-rtl: Success

verify-peripheralsGPIO-rtl: Success

verify-peripheralsPWM-rtl: Success

verify-peripheralsSPI-rtl: Success

verify-peripheralsUART-rtl: Success

verify-video-rtl: Success (Not validating correct pixel data)


verify-corePC-gl: Success

verify-coreMemory-rtl: Not run

verify-flash-gl: Success

verify-memory-gl: Success

verify-peripheralsGPIO-gl: Success

verify-peripheralsPWM-gl: Success

verify-peripheralsSPI-gl: Success

verify-peripheralsUART-gl: Success

verify-video-gl: Success

Need to do

  • Make final version of art
  • Decide on probe values
  • Check for any remaining errors
  • Add stall signal if two wishbone masters read from the same location at the same time

Could do

  • Misaligned architecture instructions
  • Look into simulation with CVC
  • Write macro level simulations to get more coverage due to shorter simulations
  • Add JTAG test
  • Add interrupt test
  • Add uart pin swapping
  • Page based flash controller
  • Tile map rendering
  • Fetch next instruction a clock cycle earlier so instructions only take 2 cycles
  • Allow JTAG to read from wishbone bus

Reference work and inspiration

  • Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.
  • Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
  • Caravel Documentation: Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the github repository.
  • Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.