commit	f76defcbe5fcda02a6961deb864dfddfb3c99694	[log] [tgz]
author	Charlie <charlie.david.smith@hotmail.co.uk>	Sat May 07 21:39:36 2022 +0100
committer	Charlie <charlie.david.smith@hotmail.co.uk>	Sat May 07 21:39:36 2022 +0100
tree	06fdb330157f79451a8676bd39b176d94bd4382e
parent	2da27a2a3967b7acad66d7bbc83a25229ea7dbe7 [diff]

Updated memory map to include caravel UART device.

4 files changed

tree: 06fdb330157f79451a8676bd39b176d94bd4382e

README.md

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program.

Features

Block diagram of Experiar SoC

Dual RV32I cores
Per core SRAM
External flash controller
Larger shared block SRAM
VGA output using frame buffer in block SRAM
4x UART ports + 1 internal to caravel
2x SPI ports
4x PWM counters with 4x seperate outputs
DMA for UART peripheral

Memory Map

Memory map for Experiar SoC

ToDo

Flash controller
DMA
Block SRAM
VGA
Multi core controller
Fix all of the timeing errors
Test

Reference work and inspiration

Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.
Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
Caravel Documentation: Reference for caravel and configuration.