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tree: b4d777ee89c83bbdba260b9a3918daa3675dae7d [path history] [tgz]
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program. This project

Block diagram of Experiar SoC

Features

  • Dual RV32I cores
  • Per core SRAM
  • JTAG interface
  • External flash controller
  • Shared video SRAM
  • Configurable VGA output
  • 3x UART ports + 1 internal to caravel
  • 1x SPI ports
  • 4x PWM counters with 4x seperate outputs (2 are internal read only)

Memory Map

Memory map for Experiar SoC

Macro Layout

Experiar SoC Macro Layout

Build Status

  • CaravelHost: Success
  • ExperiarCore: Success (Seem to be missing much of the core from the gds)
  • Flash: Success
  • Peripherals: Success
  • Video: Success
  • WishboneInterconnect: Success
  • user_project_wrapper: Error at step 13
    • Running Global Routing Resizer Timing Optimizations: Routing congestion too high

Tests

verify-peripheral-rtl (-gl)

Status: Success (Partially implemented)

Runs a number of tests (currently just a very basic gpio test) from the management core to ensure the peripherals work correctly.

verify-memory-rtl (-gl)

Status: Not implemented

Tests the managment core has access to each sram region, and that data can be correctly writen and read.

verify-video-rtl (-gl)

Status: Not implemented

Tests that the managment core can initialise the VGA device, and that the signal coresponding to this is generated. This will not produce a valid VGA signal as the simulation time would be too long.

verify-core-rtl (-gl)

Status: Not implemented

Runs a number of tests on each core to ensure they function correctly, and can access all peripherals on the SoC.

ToDo

  • Get it to build
  • Flash controller
  • JTAG core managment controller
  • CSRs
  • Write more tests
  • Fix all of the errors

Reference work and inspiration

  • Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.
  • Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
  • Caravel Documentation: Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the github repository.
  • Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.