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foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-032 / 7e131524e5533a93e2c323c0d3b16da98598eb5a
commit7e131524e5533a93e2c323c0d3b16da98598eb5a[log] [tgz]
authorCharlie <charlie.david.smith@hotmail.co.uk>Tue May 24 23:56:27 2022 +0100
committerCharlie <charlie.david.smith@hotmail.co.uk>Tue May 24 23:56:27 2022 +0100
tree9a8f0d3f1a7b350640cba2d6c821f8d42b309d12
parente4118ea630d43e1c9b62058d6a0f223d74498a01 [diff]
Removed art from art module so that it doesn't cause DRC errors (this will be changed back when a fix for this is found). Also added set, clear, and toggle registers to gpio for easier control. This also makes it easier for both cores to write to gpio without clearing what the other core has set.
39 files changed
tree: 9a8f0d3f1a7b350640cba2d6c821f8d42b309d12
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

License UPRJ_CI

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program. This project

Block diagram of Experiar SoC

Features

  • Dual RV32I cores
  • Per core SRAM
  • JTAG interface
  • External flash controller
  • Shared video SRAM
  • Configurable VGA output
  • 3x UART ports + 1 internal to caravel
  • 1x SPI ports
  • 4x PWM counters with 4x separate outputs (2 are internal read only)

Memory Map

Memory map for Experiar SoC

Macro Layout

Build Status

  • CaravelHost: Success
  • ExperiarCore: Success
  • Flash: Success
  • Peripherals: Success
  • Video: Success
  • WishboneInterconnect: Success
  • user_project_wrapper: Success

Several macros have max slew violations.

Tests

RTL

verify-peripheralsGPIO-rtl: Success

verify-peripheralsUART-rtl: Failed

verify-peripheralsSPI-rtl: Not implemented

verify-peripheralsPWM-rtl: Not implemented

verify-memory-rtl: Not implemented

verify-video-rtl: Not implemented

verify-corePC-rtl: Success

verify-coreMem-rtl: Not implemented

verify-coreArch-rtl: Not implemented

GL

verify-peripheralsGPIO-gl: Not run

verify-peripheralsUART-gl: Not run

verify-peripheralsSPI-gl: Not implemented

verify-peripheralsPWM-gl: Not implemented

verify-memory-gl: Not implemented

verify-video-gl: Not implemented

verify-corePC-gl: Not run

verify-coreMem-gl: Not implemented

verify-coreArch-gl: Not implemented

Need to do

  • Write remaining tests (and fix everything until they pass)
  • Fix timing violations
  • Fix precheck errors

Could do

  • Add gpio registers for set, clear, and toggle which use the write data as a mask
  • Add uart pin swapping
  • Flash controller
  • JTAG core management controller
  • CSRs
  • More tests
  • Tile map rendering
  • Change peripheral bus design to have a read ready signal
  • Fetch next instruction a clock cycle earlier so instructions only take 2 cycles

Reference work and inspiration

  • Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.
  • Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
  • Caravel Documentation: Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the github repository.
  • Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.